JP2007109313A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic memory capable of performing data writing at high speed and with accuracy with reduced consumption current by simplifying circuit configuration. <P>SOLUTION: When the data is written, write current is supplied to a selection digit line (DL) by a digit line drive circuit (2), and magnetization direction of a free layer of a memory cell, coupled with the digit line by a current induction magnetic field, is set in the direction opposite to a fixed layer. Subsequently, by bit line current from a write drive circuit, a polarized spin electron in the same direction as the polarized spin of the fixed layer is injected into the free layer, and the writing is executed solely for data "1". This spin injection is executed in parallel to the memory cells to which the data "1" is written, the bit line write drive circuit is only required to constantly supply the data write current in one direction, and reduction for a layout space for the write drive circuit and high-speed writing can be realized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a magnetic memory device that uses an element utilizing a magnetoresistive effect for data storage. More specifically, the present invention relates to a spin injection magnetic memory device that utilizes a mechanism for controlling the magnetization direction of a magnetic material by carrier spin injection.

  As one of nonvolatile semiconductor memory devices, a magnetic memory device (MRAM: Magnetic Random Access Memory) that stores information in a nonvolatile manner using a magnetoresistive effect is known. In this MRAM, an MTJ (Magnetic Tunneling Junction: Magnetic Tunneling Junction) element or a TMR (Tunnel Magnetoresistance: Magnet Tunneling Resistance) element is used for the data storage part of the memory cell. The MTJ element or TMR element has a structure in which a nonmagnetic tunneling barrier layer is provided between two ferromagnetic layers. The resistance value of the element with respect to the current flowing through the ferromagnetic layer differs depending on whether the magnetization directions of these two ferromagnetic layers are the same or antiparallel. Binary information is stored depending on the amount of current flowing through the MTJ or TMR element.

  In the magnetoresistive element such as the MTJ element or the TMR element, the magnetization direction of one of the two ferromagnetic layers is fixedly set, and the magnetization direction of the other ferromagnetic layer is used as stored data. Set accordingly. Data is stored according to the parallel / antiparallel state of the magnetization direction of the fixed layer in which the magnetization direction is fixedly set and the free layer in which the magnetization direction is set according to the stored data.

  When the magnetization direction is set in the free layer, a current is passed through a write word line (digit line) and a write bit line arranged in the orthogonal direction. Memory cells are arranged at intersections of these write word lines (digit lines) and write bit lines. The magnetization direction of the free layer of the memory cell is set by the combined magnetic field of the magnetic fields induced by the currents of these write word lines and write bit lines. Therefore, a relatively large current is required to generate an effective magnetic field that causes magnetization reversal. In addition, the current-induced magnetic field may cause a disturbance in which the magnetization direction of the free layer of the magnetoresistive element of the adjacent memory cell is reversed, the distance between the cells cannot be reduced, and the memory cell size is reduced. Has become an obstacle to.

  The configurations intended to solve the problem of erroneous writing to the unselected memory cells are disclosed in Patent Document 1 (US Pat. No. 6,545,906) and Non-Patent Document 1 (“A 4-Mb 0.18-μm 1T1MTJ Toggle). MRAM with Balanced Three Input Sensing Scheme and Locally Mirroed Unidirectional Write Drivers, ”TW Andre et al., IEEE, Journal of Solid-State Circuits, Vol.40, No.1, January 2005, pp.301-309) ing.

  These Patent Document 1 and Non-Patent Document 1 disclose the same method as a data writing method of a memory cell. That is, the magnetoresistive element of the memory cell is arranged between the write word line and the write bit line so that the magnetic anisotropy axis of the memory cell is 45 °. This magnetoresistive element has a free layer, a tunnel barrier layer, and a fixed layer. When writing data, first, a current is supplied to the write word line, and the magnetization direction of the free layer is aligned with the direction of the magnetic field induced by the write word line current. Next, a current is supplied to the write bit line in a state where a current is supplied to the write word line, and the magnetization direction of the free layer is rotated to align with the magnetization direction of the fixed layer. Next, supply to the write word line current is stopped, and current is supplied only to the write bit line. In this state, the magnetization direction of the free layer is aligned with the direction of the induced magnetic field of the bit line current. Next, when the supply of the write bit line current is stopped, the magnetization direction of the free layer is aligned to the nearest stable state. With these series of current supply sequences, the magnetization direction of the free layer is rotated by 180 °.

  The free layer of the memory cell has a SAF (synthetic antiferromagnetic) structure, and two ferromagnetic layers are antiferromagnetically coupled by a spacer layer, and the semi-selected state depends on the magnetization direction of the free layer. In the state where one of the write word line and the write bit line is selected, the magnetization direction of the free layer is maintained stably, and the occurrence of write disturbance is suppressed.

  In order to set the magnetization direction of this free layer, a relatively large current is required because a current-induced magnetic field is used. Patent Document 2 (Japanese Patent Laid-Open No. 2003-17782) discloses a configuration intended to further reduce current consumption during data writing and reliably write data only to a selected memory cell. ing.

  In the memory cell shown in Patent Document 2, the magnetization direction of the free layer is set by carrier spin injection. In the configuration disclosed in Patent Document 2, two electrode layers formed to face the free layer surface are magnetized in an antiparallel direction, and current is supplied from one electrode to the other electrode. Thereby, electrons having a spin corresponding to the magnetization direction of the electrode are injected into the free layer according to the direction in which the current flows. The electron spin injected into the free layer interacts with the spontaneously polarized electron spin of the free layer to set the electron spin direction of the free layer and determine the polarization magnetization direction. Thereby, the magnetization direction of the free layer is set in a parallel direction or an antiparallel direction to the magnetization direction of the fixed layer.

  In the configuration disclosed in Patent Document 2, a current is passed only in the selected memory cell, and the magnetization direction of the free layer is set by injecting polarized spin electrons through this electrode. This eliminates the need to induce a magnetic field by current, reduces current consumption, and prevents erroneous writing from occurring in unselected memory cells.

  A configuration for writing data by this electron spin injection is shown in Patent Document 3 (Japanese Patent Laid-Open No. 2004-179483). In Patent Document 3, in order to reduce the number of memory cell wirings, a tunnel magnetoresistive element and a spin injection magnetization switching layer are stacked, and the spin injection magnetization switching layer is coupled to a word line via a PN diode. To do. Therefore, the magnetoresistive element and the PN diode of the memory cell are connected in series between the bit line and the word line. Data writing is performed by spin injection, and data reading is performed using the magnetoresistive effect.

Patent Document 4 discloses a principle configuration for setting the magnetization direction of the free layer by electron spin injection (US Pat. No. 5,695,864). In this Patent Document 4, the principle that the injected electrons exchange the spin momentum by the spin magnetic exchange action with the electrons of the free layer by electron spin injection, and by supplying this spin-polarized current to the free layer, It is disclosed that the magnetization direction of the free layer can be set.
US Pat. No. 6,545,906 JP 2003-17782 A JP 2004-179383 A US Pat. No. 5,695,864 “A 4-Mb 0.18-μm 1T1MTJ Toggle MRAM with Balanced Three Input Sensing Scheme and Locally Mirroed Unidirectional Write Drivers,” TW Andre et al., IEEE, Journal of Solid-State Circuits, Vol.40, No.1, January 2005 , pp.301-309

  In the case of the MRAM shown in Patent Document 1 and Non-Patent Document 1, current flows only in one direction through the write bit line and the write word line during data writing. Therefore, although the configuration of the circuit for supplying the write current can be simplified, it is necessary to sequentially supply current pulses to the write bit line and the write word line, and timing control becomes complicated. In addition, erroneous writing of a half-selected memory cell in which one of the write bit line and the write word line is in a selected state can be prevented by forming a free layer with the SAF structure. Data is written to the memory cell by the magnetic field induced by the current flowing through the bit line and the write word line, the write current is large, and the current consumption is relatively large. Therefore, when writing multiple bits of data in parallel, the current consumption increases, making it difficult to write multiple bits of data in parallel, and it is necessary to take measures such as writing each bit sequentially, depending on the write time. The problem that becomes longer.

  Also, the write current (write bit line current and write word line current) is supplied only to the memory cell to which data opposite to the stored data is written, and the memory cell is stored before the data is written. It is necessary to determine the coincidence / mismatch between the data and the write data, and it is necessary to read the data in the selected memory cell before the data is written, which increases the write time.

  In the memory cell structures disclosed in Patent Documents 2 to 4, the magnetization direction of the free layer of the magnetoresistive element is set by polarized electron spin injection. Therefore, the direction in which the injection current flows is set in accordance with the write data, and a write current supply circuit for flowing current to the memory cell in both directions is required. Accordingly, since the direction of the write current is set in accordance with the write data, the circuit configuration becomes complicated and the circuit area also increases, and accordingly, the wiring layout area increases and it is difficult to reduce the chip area. It is.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce current consumption during data writing and can simplify the configuration of a write circuit.

  Another object of the present invention is to provide a magnetic memory device having a write circuit configuration suitable for high integration.

  A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a matrix, each including a magnetoresistive effect element whose resistance value is set according to stored data, and a logic of write data during data writing. Regardless of the value, a unidirectional magnetic field induced current is applied so as to apply a unidirectional magnetic field to the memory cells in the selected region, and the storage data of the memory cells in the selected region is set to an initial value. An initial write current supply circuit and a memory cell memory by selectively flowing a current in a single direction according to a logical value of write data to a selected memory cell in the selected region at the time of data writing And a data write current supply circuit for setting data to a value different from the initial value.

  At the time of data writing, after writing an initial value to the memory cell, a current is supplied to the memory cell in a direction in which data having a logical value different from the initial value is written. Therefore, it is not necessary to flow current bidirectionally through the first and second signal lines arranged for the memory cell according to the write data, and according to the current supply and write data at the time of initial value data writing. The current supply at the time of writing is only required to flow in a fixed direction. For example, as shown in Patent Document 2, data is transmitted bidirectionally according to write data for the same signal line. A configuration for passing current is not required, the configuration of the writing circuit is simplified, the wiring layout is simplified, and the chip area can be reduced accordingly.

  Further, when the variable resistance element of the memory cell includes a carrier spin-induced magnetic material layer connected between the bit line and the digit line (write word line), the initial value data is simultaneously written to the plurality of memory cells. At the time of insertion, only the digit line current and the spin injection current are consumed, and the current consumption can be reduced as compared with the case of using the current-induced magnetic field.

  Also, when this carrier spin-induced magnetic layer is used as a variable magnetoresistive element, when data is written, initial value data and write data are written to the digit line and bit line, respectively. The writing circuit that is only required to be supplied (the other is grounded when one current is supplied) can greatly simplify the writing circuit.

  In addition, the memory cell magnetoresistive element is set to a high resistance state by a digit line current induced magnetic field, and data writing is performed by spin injection into the memory cell corresponding to the data in the low resistance state. It is only necessary to inject direction-polarized spin electrons, the amount of spin injection current can be reduced, and parallel writing of multi-bit data can be realized.

[Principle configuration]
FIG. 1 conceptually shows an overall configuration of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, the nonvolatile semiconductor memory device includes a memory cell array 1 in which memory cells MC are arranged in a matrix. In memory cell array 1, digit lines DL and word lines WL and SL are arranged in parallel corresponding to the rows of memory cells MC, and bit lines BL are arranged corresponding to the respective columns of memory cells MC. . FIG. 1 representatively shows a portion related to one memory cell MC.

  Memory cell MC includes a variable resistance element VR whose resistance value is set according to stored data, and an access transistor AT which connects variable resistance element VR to source line SL according to the signal potential of word line WL. Variable resistance element VR is formed of a magnetoresistance element such as a TMR element, for example, and one electrode is connected to bit line BL and the other electrode is connected to access transistor AT. In the variable resistance element VR, in the present invention, the magnetization direction of the free layer is set by the induced magnetic field of the digit line DL, and the magnetization direction of the free layer by spin injection by the write current supplied from the bit line BL. Is selectively inverted and its resistance value is set. When data is written to the bit line BL, a current flows only in one fixed direction. At the time of data reading, a bit line read current is supplied from a read circuit (not shown) including a sense circuit.

  This nonvolatile semiconductor memory device further drives digit line drive circuit 2 for supplying a write current to digit line DL of the selected row at the time of data writing, and drives word line WL of the selected row to the selected state at the time of data reading. A word line drive circuit 3 to perform, a column selection circuit 4 for selecting a bit line BL of a selected column in accordance with an address signal (not shown), a write data register 8 for temporarily holding write data at the time of data writing, When writing data, bit line write drive circuit 6 that selectively drives the bit line selected by column selection circuit 4 in accordance with the write data held in write data register 8, and the source arranged in the selected row Source line drive circuit 7 for driving line SL to a selected state is included.

  Digit line drive circuit 2 corresponds to the initial data write current supply circuit, and supplies a write current for inducing a magnetic field in one direction to digit line DL of the selected row in the data write mode. Bit line write drive circuit 6 supplies a write current to the bit line of the selected column only in one direction. Therefore, the bit line write drive circuit 6 applies only to the bit line for writing the data of the logic value different from the initialization value of the memory cell MC among the write data held in the write data register 8. A write current is supplied in the direction. Therefore, the bit line write drive circuit 6 is not required to drive the bit line current bidirectionally, and the circuit configuration is simplified.

  The write data register 8 may be any circuit that can hold the write data at the time of writing, and may be an input buffer circuit that latches the write data.

  FIG. 2 schematically shows a data write sequence of the nonvolatile semiconductor memory device shown in FIG. In FIG. 2, storage data of one row of memory cells MC0 to MCn is shown. At the time of data writing, first, in the initial phase, a current is supplied to the digit line DL of the selected row, and the data stored in the memory cells MC0 to MCn of the selected row is set to a state in which the initial value “0” is stored. Next or in parallel, the memory cell (MC1, MCi) storing the initial value “0” by supplying the bit line current IwrBL to the memory cell to which the data “1” is written according to the write data D Is determined to be a logical value “1” corresponding to the write data. No bit line write current is supplied to memory cells MC0, MC2, MCn−1 and MCn whose write data D is a logical value “0”.

  Here, the data “0” corresponds to the case where the magnetization directions of the free layer and the fixed layer are antiparallel in the variable resistance element (magnetoresistance element) VR, that is, the state where the resistance value is high.

  In bit line BL, a current flows only in the direction of writing data “1” at the time of data writing. Therefore, in this data writing, a digit line current flows in initial value data writing, and in writing according to write data, a memory in which data “1” corresponding to a low resistance value is written Data is written to the cell according to the spin injection method. Therefore, even when writing multi-bit data in parallel, the bit line current is small (in order to set a low resistance value, spin-polarized electrons in the same direction as the magnetization of the injection pinned layer are injected, so that the injection pin is fixed. Electrons can be efficiently injected through the layer, and magnetization reversal can be efficiently generated), and the easy axis of the magnetoresistive element is set in a direction parallel to the digit line current induced magnetic field. By taking measures such as this, the digit line current can be reduced, and the current consumption can be reduced.

  At the time of data writing by the bit line current, writing may be executed in units of predetermined bits, and data may be simultaneously written in parallel to one row of memory cells MC0 to MCn. Data may be written in the same bit width unit as the write data. The magnetization reversal is caused by spin injection, the amount of current is small, and the number of memory cells at the time of parallel writing may be determined according to the total current at the time of multi-bit data writing. Hereinafter, a specific circuit configuration will be described.

[Embodiment 1]
FIG. 3 schematically shows a planar layout of the memory cell of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 3 shows memory cells MC arranged in 2 rows and 2 columns. An active region AG is provided in common for two-bit memory cells adjacent in the column direction (bit line extending direction). A TMR element is arranged as a variable resistance element on the upper layer of the active region. An MTJ element or a GMR (giant magnetoresistive) element may be used as a variable resistance element. However, in the following embodiments, as the variable resistance element, magnetization reversal by an induced magnetic field is easy and an MR ratio (magnetoresistance) In the following description, a variable resistance element of a memory cell is shown as a magnetoresistive effect element TMR. In the magnetoresistive effect element TMR, the direction of the easy axis EAX is set to the column extending direction (major axis direction of the magnetoresistive effect element).

  Bit lines BL (BLo, BLe) are respectively provided for the memory cells MC aligned in the column direction. The bit lines BL (BLo, BLe) are connected to the magnetoresistive effect elements TMR of the memory cells MC in the corresponding column. Electrically connected.

  Digit lines DL (DLo, DLe) are arranged for memory cells MC aligned in the row direction so as to face the magnetoresistive effect element TMR, and word lines WL (under the digit lines DL are parallel to the digit lines DL). WLo, WLe). In addition, source line SL is arranged between digit lines DLo and DLe in parallel with digit line DL and word line so as to be shared by memory cells arranged in alignment with these two rows.

  The magnetoresistive effect element TMR corresponding to the memory cell MC is connected to the active region AG by the contacts CT1 and CT3 of the memory cell MC, and the active region of the memory cell is coupled to the source line SL by the contact CT2 at the center. These contacts CT1, CT2 and CT3 form an electrical connection to the access transistor (AT) of the memory cell.

  FIG. 4 schematically shows a cross-sectional structure taken along line 4A-4B shown in FIG. In FIG. 4, a bit line BLo is arranged to be electrically connected to the magnetoresistive effect element TMR. The magnetoresistive effect element TMR is electrically connected to the corresponding intermediate layer ILY (ILYo, ILYe). Intermediate layers ILYO and ILYe are electrically connected to impurity regions AG1 and AG3 formed on the surface of substrate region SUB via contacts CT1 and CT3, respectively. Impurity region AG2 is formed between impurity regions AG1 and AG3, and impurity region AG2 is electrically connected to source line SL via contact CT2. Impurity regions AG1-AG3 are impurity regions formed in active region AG shown in FIG.

  Word line WLo is provided on the surface of substrate region SUB between impurity regions AG1 and AG2, and word line WLe is provided on substrate region SUB between impurity regions AG2 and AG3. Aligned with the word lines WLo and WLe, digit lines DLo and DLe are arranged in the upper layer. Digit lines DLo and DLe are electrically isolated from intermediate layers ILYo and ILYe.

  When a current is passed through digit lines DLo and DLe in one direction, a magnetic field is induced, and the magnetization direction of magnetoresistive effect element TMR is set to an initial state by this digit line current induced magnetic field (at the time of initialization, bit line current Is not used).

  FIG. 5 is a diagram showing the cross-sectional structure of the magnetoresistive effect element TMR shown in FIG. 4 in more detail. In FIG. 5, the magnetoresistive effect element TMR is composed of a buffer layer 20 electrically connected to the lower intermediate layer ILY and a ferromagnetic layer formed on the buffer layer 20, and a magnetoresistive element (TMR element). A TMR pinned layer 21 functioning as a pinned layer, a tunnel barrier layer 22 formed of a nonmagnetic insulator layer formed on the TMR pinned layer 21, and a ferromagnetic formed on the tunnel barrier layer 22. A free layer 23 formed of a body layer, a nonmagnetic layer 24 formed on the free layer 23, and a spin injection pinned layer 25 formed of a ferromagnetic layer formed on the nonmagnetic layer 24 And a buffer layer 26 formed on the injection fixing layer 25. Buffer layer 26 is electrically connected to corresponding bit line BL.

  The magnetization directions of the fixed layers 21 and 25 are fixed. The easy axis of free layer 23 is parallel to the magnetic field induced by the corresponding digit line DL. The spin injection pinned layer 25 allows the spin of electrons injected into the free layer 23 to pass electrons having spins polarized in the same direction as the polarized spin of the pinned layer 25. By accumulating majority carrier (electron) spins in the free layer 23 via the injection fixed layer 25 (when the injection, the majority carrier spins are reflected and accumulated freely by the barrier layer 21), the electron spins of the free layer 23 are accumulated. The direction of magnetization of the free layer 23 is set to the same direction as that of the injection fixed layer by setting the same direction as the polarized spin of the injection fixed layer 25.

  When the magnetization direction is set to be antiparallel to the fixed layer, among the electrons (carriers) supplied via the buffer layer 20 and the TMR fixed layer 21, the polarization is opposite to the injection fixed layer 25. Electrons having a spin are reflected by the nonmagnetic layer 24, and majority carrier spins are emitted through the injection fixed layer 25 or reflected by the barrier layer 21 (the fixed layers 21 and 25 are in the same direction). In the free layer 23, electrons having a polarization spin opposite to that of the spin injection fixed layer 25 (hereinafter simply referred to as the injection fixed layer 25) are accumulated, and the magnetization direction of the free layer 22 is , Set in the opposite direction to the fixed layers 21 and 25.

  Therefore, in order to set the magnetization direction of the free layer 23 during spinning, it is necessary to flow a current in the opposite direction according to the set magnetization direction. Conventionally, the current is supplied to the magnetoresistive element according to this write data. Is set to one of the two directions. In particular, when the magnetization direction of the free layer 23 is set in the direction opposite to the magnetization direction of the injection fixed layer 25, it is necessary to inject minority carrier spins into the free layer 23 as will be described in detail below. Therefore, it is necessary to supply more current than when the same magnetization direction is set.

  The magnetization directions of the TMR fixed layer 21 and the injection layer fixed layer 25 are fixed in directions parallel to each other as shown in FIG. The current IwrBL supplied at the time of data writing using the bit line current is in the direction from the buffer layer 20 toward the buffer layer 26, and the electrons e flow from the buffer layer 26 toward the buffer layer 20. When the bit line write current IwrBL is supplied, electrons having the same spin as the polarized spin electrons of the injection fixed layer 25 are supplied to the free layer 23. Therefore, the magnetization direction of the free layer 23 is set in the same direction as that of the injection fixed layer 25. In this state, the magnetization direction of the free layer 23 becomes the same magnetization direction as that of the TMR fixed layer 21, and the resistance value of the magnetoresistive effect element TMR becomes small. Therefore, by performing spin injection using a small amount of current, the magnetization direction of the free layer 23 can be set to the same direction, and current consumption during data writing can be reduced (the spin injection current is Sufficiently smaller than the magnetic field induced current).

  That is, when the bit line current is passed in the direction opposite to the bit line write current IwrBL shown in FIG. 5, electrons e flow from the buffer layer 20 to the buffer layer 26. In this case, the magnetization direction of the free layer 23 is set to be opposite to the magnetization direction of the fixed layer 21 by the minority spins supplied through the TMR fixed layer 21. Therefore, it is necessary to supply a large amount of current. In the present invention, when the magnetization direction of the free layer 23 is set in the direction opposite to the fixed layers 21 and 25, a current is passed through the digit line DL, and the magnetization direction is set by the induced magnetic field. Is only the digit line current, and even when data is written to a plurality of bits (one row of memory cells) at a time, the current consumption is only the digit line current, compared to the case where the spin injection current is used. The current consumption can be greatly reduced.

  FIG. 6 is a diagram schematically showing a state at the time of initialization of the magnetoresistive effect element TMR (an initialization state at the time of data writing). When the storage data of the memory cell is initialized (when initial data is written), a current is passed through the corresponding digit line DL to induce a magnetic field H. In FIG. 6, a magnetic field H in the counterclockwise direction is induced by the current flowing through the digit line DL, and the free layer 23 whose easy axis is parallel to the magnetic field H is magnetized M1 parallel to the digit line current induced magnetic field H. The magnetoresistive effect element TMR is set in a high resistance state. In this case, no write current is required to flow between the buffer layer 20 and the buffer layer 26, and data “0” is written in the memory cell.

  FIG. 7 is a diagram showing a state in which data of logical value “1” opposite to this initialization data “0” is written according to the stored data. In this case, current is supplied from the buffer layer 20 toward the buffer layer 26 using the source line SL and the bit line BL so that the write current IwrBL flows in the magnetoresistive effect element TMR. As a result, electrons e having the same polarization spin as the injection fixed layer 25 are injected into the free layer 23, and the free layer 23 is set to have a magnetization M <b> 2 in the same direction as the fixed layers 25 and 21. This state is opposite to that at the time of initialization, is a low resistance state, and data “1” is written and stored.

  At the time of writing the data “1” by spin injection, the free layer 23 is set in the same magnetization direction as that of the injection fixed layer 25. Therefore, the magnetization M2 of the free layer 23 is set using electrons e of many spins among the polarized spins, and data “1” can be written at high speed and with low current consumption.

[Example of changing magnetoresistive effect element]
FIG. 8 is a diagram showing a modification of the structure of the magnetoresistive element TMR used in the memory cell. In the magnetoresistive effect element TMR shown in FIG. 8, a TMR fixed layer 21 and an injection fixed layer 25 each formed of a ferromagnetic layer are coupled to a lower electrode 31 and an upper electrode 30. A tunnel barrier layer 22 having a tunnel effect is formed between the fixed layer 21 and the free layer 23, and a non-function that functions as an electron spin reflection layer at the time of spin injection is formed between the free layer 23 and the fixed layer 25. A magnetic layer 24 is provided.

  The magnetoresistive effect element TMR shown in FIG. 8 is the same as the magnetoresistive effect element TMR shown in FIGS. 6 and 7 except that the buffer layers 20 and 26 are not provided. The same reference number is attached. Also in the structure of the magnetoresistive effect element TMR shown in FIG. 8, the magnetization direction of the free layer 23 can be set by spin injection, and the magnetization direction of the free layer 23 is set by the digit line current induced magnetic field. be able to. Therefore, as the magnetoresistive effect element TMR, a three-layer structure in which three ferromagnetic layers are provided as the fixed layers 21 and 25 and the free layer 23 can be used as a basic structure. Each of these fixed layers 21 and 25 and free layer 23 may be composed of a plurality of ferromagnetic layers. For example, each of the fixed layers 21 and 25 may be composed of a plurality of ferromagnetic layers that are antiferromagnetically coupled.

[Specific circuit configuration]
FIG. 9 schematically shows an array arrangement of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In FIG. 9, sub memory circuits MK0 to MK15 each having a memory cell of 64K bits are arranged. Each of sub memory circuits MK0-MK15 includes a 64K bit memory cell array and a peripheral circuit for writing / reading the memory cell array.

  Central control circuits 32 and 34 are arranged between sub memory circuits MK0-MK7 and sub memory circuits MK8-MK15. Central control circuits 32 and 34 control access to the addressed sub-memory circuit in accordance with address signal ADD from address bus 48 and write / read instruction signal R / W applied through control bus 46. An address bus 48 is disposed between the central control circuits 32 and 34. In FIG. 9, main word line MWL is arranged in common to sub memory circuits (for example, MK8 and MK9) arranged adjacent to each other on the same side of central control circuits 32 and 34, and main word line MWL is A state driven by the main word line driver 36 disposed in the central control circuit 34 is shown as an example.

  The main word line driver 36 drives the main word line MWL of the selected row to the selected state in accordance with the sub memory circuit designation address included in the address signal ADD and the address signal designating the row in the sub memory. In accordance with the sub memory circuit instruction bit included in address signal ADD on address bus 48, driver 38 transmits a sub memory circuit selection signal to each corresponding sub memory circuit (sub memory circuit MK0 in FIG. 9). Drive circuits 38 for transmitting the sub memory circuit designation addresses are also provided for sub memory circuits MK2-MK15, respectively.

  A read data bus Q for transmitting read data Q and a write data bus D for transmitting write data D are arranged between sub memory circuits MK2-MK7 and central control circuit 32. The read data bus 40 and the write data bus 42 are shared by the sub memory circuits MK0 to MK15.

  One sub memory circuit is designated by an address signal ADD from address bus 48, and data is written or read in the designated sub memory circuit. The main word line MWL is provided in common for the two sub memory circuits in order to allow data access to the two sub memory circuits in parallel in preparation for the expansion of the bit width of the internal write / read data. This is to make it possible to expand the configuration to be performed and to easily expand the sector range during data writing.

  FIG. 10 schematically shows a configuration of sub memory circuits MK0-MK15 shown in FIG. FIG. 10 representatively shows a configuration of one sub memory circuit MKi (i = 1-15).

  In FIG. 10, sub memory circuit MKi includes a local memory array 100 having memory cells each arranged in a matrix. Local memory array 100 is divided into two subarrays 100l and 100r each having the same number of rows and columns. In subarray 100l, word lines WLL0 to WLL255 are arranged, and in subarray 100r, word lines WLR0 to WLR255 are arranged.

  For source line SL and digit line DL, digit lines DL0-DL255 and source lines SL0-SL255 are arranged corresponding to memory cell rows in common to subarrays 100l and 100r, respectively. Corresponding to the memory cell columns, bit lines BL0 to BL127 are arranged in subarray 100l, and bit lines BL128 to BL255 are arranged in subarray 100r.

  In the local memory array 100, memory cells (indicated by magnetoresistive elements TMR) are arranged in 256 rows and 256 columns and have 64K-bit memory cells.

  In the magnetoresistive effect element TMR, the long axis direction is aligned with the extending direction of the bit line so that the magnetic field induced by the current flowing through the digit line DL is parallel to the easy axis of magnetization.

  Main word lines MWL0 to MWL255 are arranged for sub memory circuit MKi. Main word lines MWL0-MWL255 are arranged corresponding to the memory cell rows of subarrays 100l and 100r.

  A left word line drive circuit 103l, a left digit line drive circuit 102l and a left source line drive circuit 107 are provided outside the subarray 100l, and a right word line drive circuit 103r and a right digit drive circuit 102r are provided outside the subarray 100r. Is provided.

  Left word line drive circuit 103l is selected according to sub memory circuit selection signal BA designating sub memory circuit MKi, array selection signal AA designating one of sub arrays 100l and 100r, and signals on main word lines MWL0 to MWL 255 Drive the word line of the selected row of the subarray to the selected state.

  Left digit line drive circuit 102l stores data stored in the memory cell to the digit line of the selected row when data is written in accordance with write / read instruction signal R / WZ, signals of main word lines MWL0 to MWL255, and sub circuit selection signal BA. Supply current for initialization. A right digit line drive circuit 102r is provided opposite to the left digit line drive circuit 102l. This right digit line drive circuit 102r drives digit lines DL0-DL255 to a fixed potential. Therefore, the left digit line drive circuit 102l couples the selected digit line to the power source opposite to the fixed power source coupled to the right digit line drive circuit 102r, and the digit line write current flows as an initialization current.

  Left source line drive circuit 107 includes a source line driver provided for each of source lines SL0 to SL255, and a source line of a selected row according to a signal on main word lines MWL0 to MWL255 and a write / read instruction signal R / WZ. Drive. The source line driver included in the left source line drive circuit 107 drives the source line of the selected row at different voltage levels during data writing and data reading (debit line currents are different during data writing and reading). Reverse direction).

  The sub memory circuit MKi is further selected by the local column selection circuit 104 and the local column selection circuit 104 that selects the addressed column according to the sub memory circuit selection signal BA, the array selection signal AA, and the column address signal CA. A local write / read circuit 110 for writing / reading data to / from the column is included.

  When the sub memory circuit MKi is selected, the local column selection circuit 104 simultaneously selects, for example, a plurality of 32-bit columns in one of the sub arrays 100l and 100r.

  Local write / read circuit 110 receives 32-bit write data D0-D31 via internal write bus 42 and transmits 32-bit internal read data Q0-Q31 to internal read data bus 40. . When data is written to the memory cell by the bit line current, data may be written in units of 32 bits having the same bit width as the external data, or data may be written in units of 62 bits. Good.

  In correspondence with the components of the nonvolatile semiconductor memory device shown in FIG. 1, the local memory array 100 forms one row of the memory cell array 1, and the left word line drive circuit 103l and the right word line drive circuit 103r are word lines. A part of the drive circuit 3 is configured, and a part of the column selection circuit 4 is configured by the local column selection circuit 104. The source line drive circuit 107 constitutes a part of the source line drive circuit 7 shown in FIG. Local column selection circuit 104 forms part of column selection circuit 4 shown in FIG. 1, and local write / read circuit 110 is one of bit line write drive circuit 6 and write data register 5 shown in FIG. Parts.

  FIG. 11 shows an example of a specific configuration of local column selection circuit 104 and local write / read circuit 110 shown in FIG.

  In FIG. 11, in the local column selection circuit 104, a unit column group selection circuit CSU is provided corresponding to each set of four bit lines of bit lines BL0 to BL255. In this unit column group selection circuit CSU (CSU0-31), column selection lines CSL0-CSL3 are provided for subarrays 100l and 100r, respectively, in order to select one bit line from four corresponding bit lines. The column selection lines CSL0 to CSL3 are 2-bit signal lines as shown by the numeral 2 next to the diagonal lines of the column selection signal lines in FIG. 11, and each of the subarrays 100l and 100r is in accordance with the array address signal AA. Column selection lines CSL0 to CSL3 provided for one subarray are set to a valid state (selected state) in decoder 117.

  In order to perform the 4: 1 selection operation in the unit column group selection circuit CSU, a column selection line driver 119 for driving the column selection lines CSL0 to CSL3 according to the output signal of the decoder 117 is provided. Decoder 117 generates a selection signal for column selection signals CSL0-CSL3 in accordance with array address signal AA, column address signal CA, and sub memory selection signal BA. Specifically, decoder 117 selects one of subarrays 100l and 100r according to array address signal AA and selects one of column selection signals CSL0-CSL3 for the selected subarray according to column address signal CA when selecting a corresponding submemory circuit. A selection signal for making one selected is generated. Driver 119 drives column select lines CSL0-CSL3 to the selected state in accordance with the output signal of decoder 117.

  In the memory sub-circuit, a local data bus 115 is provided and transmits 32-bit write / read data having the same bit width as that of external data. Unit column group selection circuit CSU includes column selection gates CSG0 to CSG3 receiving the signals of column selection lines CSL0 to CSL3 at their gates. One column selection gate is turned on in unit column group selection circuit CSU in accordance with selection signals CSL0-CSL3, and one of the corresponding bit line groups is coupled to the corresponding bus line of 32-bit local data bus 115.

  Thirty-two unit column group selection circuits CSU0 to CSU31 are provided for each of subarrays 100l and 100r, and are coupled to different internal data bus lines. Since one of subarrays 100l and 100r is selected (word line WL is provided separately for subarrays 100l and 100r), 32-bit data is written / read to / from the selected subarray.

  For local data bus 115, write circuit 110W including write driver 120 for driving the bus lines of local data bus 115 in accordance with write data bits D0 to D31, and the bus lines of local data bus 115, respectively. And a local read circuit 110R including a sense amplifier 122 provided. Local write circuit 110W and local read circuit 110r correspond to local write / read circuit 110 shown in FIG. 10, and 32-bit data D0-D31 and Q0-Q31 are written data buses shown in FIG. 42 and the read data bus 40 are transferred.

  FIG. 12 is a diagram more specifically showing the configuration of the word line drive circuit, digit line drive circuit, source line drive circuit and internal write / read circuit shown in FIG.

  In FIG. 12, in the local memory array 100, a plurality of memory cells are arranged in a matrix. FIG. 12 representatively shows memory cells MC0 to MC255 arranged in a row. Each of memory cells MC0-MC255 includes a magnetoresistive element TMR and an access transistor AT connected in series between corresponding bit lines BL0-BL255 and corresponding source line SLn. Digit line DLn and source line SLn are provided in common to memory cells MC0-MC255. Word line WLLn is commonly connected to 128-bit memory cells MC0 to MC127 (not shown), and word lines are connected to 128-bit memory cells from memory cell MC128 (not shown) to memory cell MC255. WLRn are connected in common.

  The left digit line drive circuit 102l receives a write / read instruction signal R / WZ, a block selection signal, and a signal on the main word line MWLn, and outputs a digit line DLn according to an output signal of the digit line decoder 134. And a digit line driver 136 coupled to the ground node.

  Digit line decoder 134 is enabled when a corresponding array block (sub memory circuit) is designated, corresponding main word line MWLn is in a selected state, and the write mode is read / write instruction signal R / When specified by WZ, an active signal (H level signal) is generated.

  Digit line driver 136 includes an N channel MOS transistor (insulated gate field effect transistor) TN1 that couples digit line DLn to a ground node in response to an H level signal from digit line decoder 134.

  In right digit line drive circuit 102r, a wiring is simply provided as driver 140 for coupling digit line DLn to power supply node 142. This wiring is arranged for each digit line DL, and each digit line is coupled to a power supply line in right digit line drive circuit 102r.

  Therefore, in digit line DLn, write current IwrDL always flows from right digit line drive circuit 102r to left digit line drive circuit 102l by digit line driver 136.

  Source line drive circuit 107 provided for source line SLn includes a source line decoder 130 for receiving a signal on main word line MWLn, a write / read instruction signal R / WZ, and a sub memory circuit selection signal, and a source line decoder Source line driver 132 for driving source line SLn to a power supply voltage level or a ground voltage level according to an output signal 130 is included.

  When the sub memory circuit selection signal BA and the main word line MWLn are both selected and the read / write instruction signal R / WZ is at the L level and the write mode is designated, the source line decoder 130 is an L level signal. Is output, otherwise an H level signal is output.

  The source line driver 132 has a configuration of a CMOS inverter including a P channel MOS transistor TP1 and an N channel MOS transistor TN2. Therefore, when source line decoder 130 outputs an L level signal in the data write mode, power supply voltage is supplied to source line SLn. Otherwise, source line driver 132 grounds corresponding source line SLn. Maintain voltage level.

  Word line WLLn and WLRn are provided with word line drivers corresponding to the right word line drive circuit and the left word line drive circuit, respectively. In FIG. 12, in order to simplify the drawing, The configuration is not shown. At the time of data reading, the word line is driven to a selected state in accordance with a signal on main word line MWL and array selection signal AA.

  In bit lines BL0 to BL255, local column selection circuit 104 performs 2: 1 selection (sub memory circuit selection) and 4: 1 selection (selection within a unit bit line group) to select 32 bit lines. Then, the local data bus 115 is coupled to the 32-bit bus line. The local read circuit 110R includes sense amplifiers 122-0 to 122-31 provided for the 32-bit bus lines of the local data bus 115, and the local write circuit 110W includes the 32-bit of the local data bus 115. Write drive gates 120-0 to 120-31 provided for the respective bus lines.

  Sense amplifiers 122-0 to 122-31 each include a read current source for supplying a read current and a sense circuit for detecting a current of a corresponding local data bus line. As shown in FIG. 12, the read current source included in sense amplifiers 122-0 to 122-31 causes a bit line read current IrdBL to flow from the bit line to source line SLn via the selected memory cell as shown in FIG. . Read data bits Q0 to Q31 are generated by sense amplifiers 122-0 to 122-31, respectively.

  Write drive gates 120-0 to 120-31 include N-channel MOS transistors NT3 receiving write data bits D0-D31 corresponding to the respective gates. Therefore, each of these write drive gates 120-0 to 120-31 couples the bit line of the selected column to the ground node when the corresponding data bit Di is at H level ("1"), and When the embedded data bit is at L level (“0”), the non-conductive state is maintained and no bit line write current is supplied.

  Therefore, when a bit line current is caused to flow in accordance with write data, a write current IwrBL from the source line to the ground node via the selected memory cell always flows through bit lines BL0 to BL255. Although bit line read current IrdBL is set larger than bit line write current IwrBL, the bit line read current IrdBL is set to a current level at which the stored data of the memory cell is not inverted by the bit line read current IrdBL.

  Write current IwrBL and read current IrdBL are in opposite directions, and in particular, the direction in which bit line read current IrdBL flows is set such that the magnetization direction of the free layer of the magnetoresistive effect element of the memory cell is opposite to the magnetization direction of the fixed layer Direction. In this case, the magnetization reversal due to the spin injection current is performed by minority carrier spin (spin in the direction opposite to the polarization spin of the fixed layer), so that the magnetization reversal of the free layer is prevented (minority carrier spin). This is because a large current value is required to cause magnetization reversal by injection).

  FIG. 13 is a timing diagram representing an operation at the time of data writing / reading of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. A data write / read operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will now be described with reference to FIG. 13 and FIG.

  A write cycle and a read cycle for writing and reading data are respectively defined by an external clock signal CLK (an external processor operates in synchronization with the clock signal CLK).

  At time t0, a write cycle is started in accordance with the rise of clock signal CLK (read / write instruction signal R / WZ is set to L level). In this write cycle, first, at time t1, the MOS transistor TN1 of the digit line driver 136 becomes conductive, and the digit line write is performed on the digit line DLn from the right digit line driver 140 to the ground node via the left digit line driver 136. Current IwrDL flows. Thereby, in one row of memory cells MC0 to MC255 provided corresponding to digit line DLn, the free layer of magnetoresistive effect element TMR is magnetized in a direction parallel to the magnetic field induced by current IwrDL flowing through digit line DLn, That is, it is magnetized in a direction antiparallel to the magnetization of the fixed layer.

  Next, in the local column selection circuit 104, a column selection operation is performed, and the 32-bit bit line of the selected column is coupled to the local data bus 115. In this state, in write drive gates 120-0 to 120-31, among the write data bits D0-D31, the write drive gate for writing data “1” is rendered conductive, and the bit line of the selected column is grounded. Joined to a node

  In parallel or after this, at time t2, the word line WL (WLLn or WLRn) of the selected row is driven to the selected state, the access transistor AT of the selected memory cell is turned on, and the selected 32-bit memory cell In MC, a magnetoresistive effect element TMR is connected between a corresponding bit line and a source line. In the source line driver 132, the source line drive transistor TP1 is turned on according to the output signal (L level) of the source line decoder 130, and the power supply voltage is supplied to the source line SLn. As a result, the bit line write current IwrBL flows from the source line SLn to the bit line for writing data “1” to the corresponding bit line BL (32-bit bit line) via the memory cell. For the memory cell to which data “0” is written, the bit line is in a floating state, so that electron injection hardly occurs, and the state of the magnetoresistive element TMR of the memory cell does not change. As a result, electrons having spin polarization in the same direction as the spin-polarized electrons in the injection fixed layer of the magnetoresistive effect element in the memory cell are injected into the free layer, and the magnetization of the free layer is reversed from the initial state.

  When writing data of more bits than 32-bit data at the time of this data writing, the column selection signal is switched in the local column selection circuit 104 using the write data register shown in FIG. In the writing of up to 256 bits of data, the bit line write current IwrBL is supplied to the bit line to which the memory cell to which data “1” is written is selected.

  As the configuration of the write data register, a 32-bit width FIFO may be used, and a 32-bit write data is switched by switching the input unit and the output unit in units of 32 bits using a 256-bit width shift register. May be used so that the latch data is sequentially transferred to the write drive circuit in units of 32 bits at the time of writing.

  Thereby, data writing is completed in the selected sub memory circuit of the memory cell row selected by the main word line MWLn.

  At time t3, when a read cycle starts, digit line DLn is in a non-conducting state during digit data read, digit line driver 136 is fixed to power supply voltage VCC level by right digit line driver 140, and no current flows.

  At time t4, the word line WL is driven to the selected state, and the access transistor AT of the memory cell in the selected row is turned on. At this time, the source line decoder 130 outputs an H level signal on the source line corresponding to the selected row in the read mode, and the source line SLn is set to the ground voltage level by the MOS transistor TN2 of the source line driver 132. Maintained.

  At the time of reading, the local column selection circuit 104 performs a column selection operation in parallel with the word line selection, and the read current from the current source included in the sense amplifiers 122-0 to 122-31 is selected. Supplied to the bit line. By detecting the magnitude of the read current IrdBL by the sense amplifiers 122-0 to 122-31, it is determined whether the data stored in the memory cell is “0” or “1”. Data Q0-Q31 is generated.

  When data “0” is stored in the memory cell, the magnetoresistive element TMR is in a high resistance state and the bit line read current IrdBL is small, while the memory cell stores data “1”. In the case of storage, the resistance value of the magnetoresistive effect element TMR is small, a large current flows, and the stored data of the memory cell is binary-determined based on the magnitude of the bit line read current IrdBL. Thereby, internal data can be read in units of 32 bits.

  Internal data is written / read in units of 32 bits. In this case, input / output of external data may be performed in units of 32 bits, and in units of 8 bits, 16 bits, or 64 bits. It may be executed in bit units (by providing a register circuit inside, the bit width of the internal data and the bit width of the external data can be adjusted).

  Further, the selection timing of this word line WL may be the same timing as the timing at which the digit line DL is driven to the selected state and the digit line write current IwrDL is supplied in the data write cycle (both in FIG. 13). A directional arrow indicates a period during which this word line selection timing can be set).

  Main word line MWL is shared by two memory subcircuits, and digit line DL and word line WL are selected based on a signal on the main word line. As a result, it is not necessary to arrange a main word line and a row decode circuit for selecting a word line in each sub memory circuit, the area of the decoder circuit can be reduced, the wiring layout can be simplified, and high-speed operation can be achieved. It becomes possible.

  FIG. 14 shows an example of the configuration of digit line decoder 134 shown in FIG. In FIG. 14, digit line decoder 134 includes a three-input gate circuit 134a that receives read / write instruction signal R / WZ, a signal on main word line MWL, and a sub memory circuit selection signal BA. In 3-input gate circuit 134a, read / write instruction signal R / WZ is at L level, data writing is instructed, a signal on main word line MWL is at H level, and sub memory circuit selection signal BA When H indicates a selection state of H level, an H level signal is output. Therefore, at the time of data writing, one of the two sub memory circuits arranged corresponding to the selected main word line is designated by the block sub memory circuit selection signal BA, and the digit line driver 136 Corresponding digit line DL is coupled to the ground node, and a write digit line current flows.

  At the time of data reading and in a non-selected row, the output signal of 3-input gate circuit 134a is at L level, and digit line driver 136 is non-conductive. Therefore, digit line DL is maintained at power supply voltage VCC level by right digit line driver 140 shown in FIG.

  The sub memory circuit selection signal BA is generated by decoding the sub memory circuit designation address included in the address signal. The sub memory circuit designating address is generated by decoding the sub memory circuit block selected by the output signal of the driver 38 shown in FIG. 9, and the address designating one memory array in one sub memory circuit is decoded. A memory array selection signal AA is generated.

  FIG. 15 shows an example of the configuration of source line decoder 130 shown in FIG. In FIG. 15, source line decoder 130 includes a three-input gate circuit 130a having a different output signal logic from the digit line decoder. In 3-input gate circuit 130a, read / write instruction signal R / WZ is at L level to indicate data write, main word line MWL is at H level and in a selected state, and sub memory circuit selection signal BA corresponds. When a sub memory circuit is designated, an L level signal is output, and an H level signal is output otherwise.

  Source line driver 132 is formed of a CMOS inverter. Therefore, at the time of data writing, source line SL arranged corresponding to the selected row of the selected sub memory circuit is driven to the H level. Line SL is maintained at the L level. Thus, current can be supplied from the source line to the bit line via the memory cell when data is written by the bit line current, and current can be supplied from the bit line to the source line via the memory cell when data is read.

  FIG. 16 schematically shows a configuration of a word line driving unit for driving word lines WL (WLL, WLR). This word line WL is driven by a word line driver 145. A word line subdecode circuit 147 for generating a word line selection permission signal WA is provided in common to the word lines for the subarray of the submemory circuit. Word line subdecode circuit 147 has a two-input AND circuit 147a receiving array selection signal AA and submemory circuit selection signal BA, and an output timing of an output signal of two-input AND circuit 147a in accordance with read / write instruction signal R / WZ. And a timing adjustment circuit 147b for generating a word line selection permission signal WA. The word line driver 145 drives the corresponding word line WL to the selected state according to the signal on the main word line MWL and the word line selection permission signal WA.

  Timing adjustment circuit 147b delays the activation timing of the output signal of 2-input AND circuit 147a by a predetermined time in accordance with the digit line selection timing when read / write instruction signal R / WZ is at the L level. On the other hand, when read / write instruction signal R / WZ indicates data reading at H level, the output signal of 2-input AND circuit 147a is set at substantially the same timing as the digit line selection timing. Therefore, timing adjustment circuit 147b functions as a delay circuit when read / write instructing signal R / WZ is at L level and is buffered when read / write instructing signal R / WZ indicates data reading at H level. Functions as a circuit. For example, when the read / write instruction signal R / WZ is at the L level, the timing adjustment circuit 147b is a rising delay that delays the rising of the output signal of the AND circuit 147a and / or a falling delay circuit that delays the falling thereof. It may be constituted by.

  The main word line MWL performs the decoding operation of the sub memory circuit block designation address signal in the local row decoding circuit included in the central control band, and addresses according to the row address signal when the corresponding sub memory circuit block is in the selected state. The main word line MWL corresponding to the designated row is driven to the selected state.

  As shown in FIGS. 14 to 16, the circuit that drives digit line DL, word line WL, and source line SL receives a signal on main word line MWL as a circuit activation control signal. Therefore, it is not necessary to arrange a row decode circuit for each sub memory circuit, and it is required to arrange a local row decode circuit in common for the two sub memory circuits and drive the main word line MWL to a selected state. Just do. Therefore, in each of the sub memory circuits, the drive circuit for driving the digit line, the source line, and the word line is not disposed, and it is only necessary to supply the data read mode and the memory sub circuit selection signal, thereby simplifying the wiring layout. In addition, the layout area of the circuit related to row selection can be reduced.

  FIG. 17 schematically shows an example of the configuration of sense amplifier 122 shown in FIG. In FIG. 17, sense amplifier 122 selects a read current source 122a for supplying constant current Iread when data is read according to read / write instruction signal R / WZ, and according to read / write instruction signal R / WZ when data is read. Sense circuit that is activated and detects the magnitude of the difference between the read current Iread from read current source 122a and the bit line read current IrdBL flowing through the selected bit line, and generates internal read data Q 122b.

  The read current source 122a may be of any circuit configuration that supplies a constant current during data reading, and any constant current source circuit can be used. The sense circuit 122b may be a current sense type sense circuit that detects the magnitude of the difference between the read current Iread and the bit line read current IrdBL, and is generated by a current supplied from the read current source 122a. Any voltage sense type sensing circuit that compares the voltage of the bit line (local data bus line) with a predetermined voltage may be used. For example, the sense circuit 122b may be configured to compare the difference current Iread-IrdBL supplied from the read current source with a reference current.

  By using this read current source 122a, a read current can be supplied to the bit line in the direction opposite to that at the time of writing.

  As described above, according to the first embodiment of the present invention, the free layer of the magnetoresistive effect element of the memory cell is set in the direction opposite to the fixed layer by the digit line current induced magnetic field, and then the spin injection by the bit line current is performed. Is performed by electron injection in the same spin direction as that of the fixed layer. Therefore, the amount of current required for data writing can be reduced, and power consumption can be reduced. For example, when data is written using a current-induced magnetic field in a conventional MRAM, the data is rewritten in order to induce a magnetic field having a required magnitude in order to induce a current of about tens of mA in each digit line and bit line. is required. Therefore, when parallel writing of 32-bit data is performed, tens of mA (digit line current) and tens of mA (bit current of about 15 mA) × 32 = about 400 mA are consumed. However, according to the first embodiment, as the digit line current, since the magnetization direction of the free layer is set only using the digit line current, it is 2 to 3 times larger than the configuration using the conventional magnetic field. However, the spin injection current is about several mA (about 1 mA) per bit line, and only about 80 mA of current is consumed as a whole. The power consumption during writing can be greatly reduced.

  Even when spin injection is performed, there is no need to supply current to the bit line bidirectionally according to write data, the write current source and its wiring layout can be simplified, and the chip area is reduced. can do.

  The direction of flow of the spin injection current used for data writing is the direction in which the magnetization in the free layer is likely to be reversed (the direction in which spin-polarized electrons in the same direction as the polarized spin electrons in the fixed layer are injected into the free layer). Therefore, spin injection can be performed efficiently, and the spin injection current can be reduced as compared with magnetization reversal by spin injection in the reverse direction.

  In addition, the direction in which the bit line current flows is opposite between data writing and data reading, and the bit line read current supplied during data reading is less likely to cause magnetization reversal of the memory cell. Incorrect reading at the time of reading can be prevented, and the problem of reading disturbance can be avoided.

  Further, as shown in FIG. 18, a hierarchical structure of main word lines MWL, digit lines DL (DLa, DLb) and word lines WL (WLa, WLRa, WLLb, WLRb) is used. Therefore, row selection is performed based on the signal on main word line mWL, subarray selection signals AA0 and AA1, and memory subcircuit selection signals BA0 and BA1 to drive each signal line in the selected row to a selected state. The circuit configuration of the row selection system can be simplified (there is no need to arrange the row decoding circuit in each memory sub-circuit), and the activation / deactivation timing setting of each signal line is set as the main. This can be performed in accordance with the signal of the word line, and the timing adjustment becomes easy.

  In this sub memory circuit, the initial value of the data stored in the memory cell is written in units of digit lines DLa or DLb. Data write according to the write data is executed with the word line WL of one sub-array selected. When this word line is maintained in the selected state 2, as shown in FIG. 18, data unit WDmax having the same number of bits as the memory cell to which the word line is connected is written in parallel as the maximum parallel write data unit. Data may be written in, for example, the page mode using the minimum data unit, that is, the minimum data unit WDmin having the same bit width as the external write data (read data). Alternatively, the minimum unit data WDmin may be sequentially held by the register circuit, and data writing may be executed in the maximum parallel writing unit WDmax.

  Therefore, data can be continuously written to two word lines in one sub memory circuit, so that data can be written in page units for so-called sector erasure of the flash memory. High-speed writing can be realized (writing is faster than flash memory and higher-speed data writing can be realized).

  When data is continuously written to two word lines WLLa and WLRa in the same row shown in FIG. 18, the data stored in the memory cell is initialized on digit line DLa and then subarray selection signal AA0. By sequentially driving AA1 and AA1 to the selected state and sequentially performing column selection in units of necessary data, parallel writing of data by the bit line current can be performed with low current consumption.

[Embodiment 2]
FIG. 19 shows a structure of a main portion of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. The configuration of the nonvolatile semiconductor memory device shown in FIG. 19 is different from the nonvolatile semiconductor memory device shown in FIG. 12 in the following points. That is, in the left digit line drive circuit 102l, a line drive gate is provided by driving the digit line DLn in binary. Digit line drive gate 152 includes an N channel MOS transistor TN1 for coupling digit line DLn to a ground node when conducting, and a P channel MOS transistor TP5 for coupling digit line DLn to a power supply node when conducting. The conduction of MOS transistors TN1 and TP5 of digit line drive gate 152 is controlled by digit line decoder 150.

  In the right digit line drive circuit 102r, a digit line driver 140 is provided for the digit line DLn. Digit line driver 140 is provided with a digit line drive gate 162 for binary driving of the digit line. Digit line drive gate 162 includes an N channel MOS transistor TN10 coupling digit line DLn to the ground node when conductive, and a P channel MOS transistor TP10 coupling digit line DLn to the power supply node when conductive. The conduction of MOS transistor TN10 and MOS transistor TP10 of digit line drive gate 162 is controlled by digit line decoder 160. Therefore, in this digit line DLn, currents IwrDL and IwrDLA flow in both directions during data writing. The current IwrDLA is a current for generating an assist magnetic field when data is written by a bit line current, and the current value is smaller than the current IwrDL that generates the write magnetic field.

  Digit line decoders 150 and 160 control conduction of corresponding digit line drive gates 152 and 162 in accordance with the signal on corresponding main word line MWLn, sub memory selection signal BA and read / write instruction signal R / WZ.

  Each of write drive gates 120-0 to 120-31 of write circuit 110W is responsive to a signal on control signal line 170 to couple the bus line of corresponding local data bus 115 to the power supply node. TP7 and N channel MOS transistor TN3 which is selectively turned on in accordance with write data bits D0-D31. The signal potential of the control signal line 170 is adjusted by the initial assist control circuit 172. When MOS transistor TP7 is conductive in write drive gates 120-0 to 120-31, current IwrBLA flows from the bit line to the source line through the memory cell to the bit line. An assist magnetic field is generated with respect to the magnetic field at the time of initial data writing.

  The other configuration of the nonvolatile semiconductor memory device shown in FIG. 19 is the same as that of the nonvolatile semiconductor memory device shown in FIG. 12, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. .

  In digit line drivers 152 and 162, the current driving capabilities of MOS transistors TP5 and TN10 are made smaller than the current driving capabilities of MOS transistors TN1 and TP10. Therefore, digit line write current IwrDL is larger than digit line assist current IwrDLA. The difference between the current driving capability of the MOS transistors TP5 and TN10 and the current driving capability of the MOS transistors TN1 and TP10 may be adjusted by the size of each element (ratio of gate width to channel length), and the gate potential thereof. It may be set according to the level.

  Also in write drive gates 120- to 120-31, the current driving capability of MOS transistor TP7 is made smaller than the current driving capability of MOS transistor NT3. Also in this case, the current driving capabilities of the MOS transistors NT3 and TP7 may be adjusted according to their sizes, or may be adjusted according to the potential level of the control signal line 170.

  FIG. 20 is a signal waveform diagram representing operations at the time of data writing and reading of the nonvolatile semiconductor memory device shown in FIG. Hereinafter, data write and read operations of the nonvolatile semiconductor memory device shown in FIG. 19 will be described with reference to FIG.

  At time t0, the write cycle starts according to the rise of clock signal CLK. In this write cycle, first, digit line DLn is driven by digit line drive circuits 102l and 102r at time t1. That is, MOS transistor TP10 conducts at digit line drive gate 162, and MOS transistor TN1 conducts at left digit line drive gate 152. Thereby, a digit line write current IwrDL flows from digit line drive gate 162 toward digit line drive gate 152, and a magnetic field is induced by this current IwrDL, and in parallel, in magneto-resistive effect element in memory cells MC0-MC255. The magnetization direction of the TMR free layer is driven in the opposite direction to the fixed layer.

  In parallel with the supply of digit line write current IwrDL, assist control circuit 172 lowers assist control voltage CVA on signal line 170 to a low level. When this bit line write assist current IwrBLA is supplied, all the write data bits D0 to D31 are maintained at the L level. Accordingly, in write drive gates 120-0 to 120-31, MOS transistor TP7 is rendered conductive, and bit line write assist current IwrBLA for the selected column is supplied via local column selection circuit 104.

  This bit line write assist current IwrBLA assists the magnetization of the free layer by the digit line write current IwrDL. That is, when the bit line write assist current IwrBLA is supplied, the word line WL of the selected row is driven to the selected state in parallel with the previous column selection by the local column selection circuit 104. As a result, a minority spin carrier having a polarization spin opposite to the polarization spin of the injection fixed layer of the magnetoresistive effect element TMR is injected into the free layer by the bit line write assist current IwrBLA, and the magnetization of the free layer is changed. The process of setting in the direction opposite to the fixed layer is facilitated. This digit line write assist current IwrBLA is smaller than that required in the case of magnetic field induction, and assists magnetization reversal by the digit line write current induced magnetic field by minority carrier spin injection.

  At time t2, digit line decoders 150 and 160 invert the direction of current flowing through digit line DL. In other words, MOS transistor TP5 is rendered conductive at digit line drive gate 152, and MOS transistor TN10 is driven to be rendered conductive at digit line drive gate 162. In response, current IwrDLA flows from digit line drive gate 152 to digit line drive gate 162. This digit line write assist current IwrDLA has a smaller current value than digit line write current IwrDL, and this assist current IwrDLA causes all of the magnetization of the free layer of the magnetoresistive element of the memory cell connected to digit line DLn. Inversion in the direction opposite to the initial writing is prevented. The magnitude is such that a magnetic field is generated to assist the magnetization reversal of the free layer when data “1” is written.

  At time t2, the initial assist control circuit 172 sets the assist control voltage CVA on the control signal line 170 to the power supply voltage level, and the MOS transistors TP7 are all turned off in the write drive gates 120-0 to 120-31. Set to the conductive state. During the initial value data write period, write data bits D0-D31 are all fixed at the L level, and MOS transistor TN3 is in the non-conductive state, and the write data bit is changed according to the change in voltage level of control signal line 170. D0 to D31 are set to the valid state, and the bit line connected to the memory cell to which data “1” is written is coupled to the ground node.

  At this time, source line decoder 130 turns on MOS transistor TP1 of source line drive gate 132 to couple source line SLn to the power supply node. The selected word line WL is in a selected state, and the bit line to be written is connected to the ground node. The write current IwrBL flows from the source line SLn to the bit line through the memory cell, and the data “1” is passed. In the memory cell to be written, majority carrier spin having the same polarization spin as the injection fixed layer is injected, and the magnetization direction of the free layer is reversed. In this operation, the magnetization reversal of the free layer is promoted by the induced magnetic field of the digit line write assist current IwrDLA.

  At time t3, data writing is completed, and supply of digit line write assist current IwrDLA is stopped according to the output signals of digit line decoders 150 and 160, and digit line DLn is maintained at the power supply voltage level in the initial state. The Further, the word line WLLn (or WLRn) is driven to a non-selected state.

  In the above description, minority carrier spins are injected by the bit line write assist current. However, at the time of data writing, at the initial setting of the magnetization direction by the induced initial magnetic field by the digit line write current IwrDL, by inducing a small magnetic field by the bit line write assist current IwrBLA, The magnetoresistive effect element may be initially set by induction and a combined magnetic field with a digit line write current induced magnetic field.

  As described above, the bit line write assist current promotes the transition to the initial state of the free layer when writing the initial value of the memory cell, and the memory cell can be set to the initial state at high speed. Also, the digit line write current can be reduced (because the strength of the digit line induced magnetic field can be reduced).

  In addition, when data “1” is written, the digit line assist current IwrDLA can promote free layer magnetization reversal by spin injection, and similarly, the time required for data writing can be shortened. The line write current can be reduced.

  Even in this case, the amount of current required for data writing is about twice the maximum amount of current in the first embodiment (when the assist current is the same as the current at the time of writing). Compared to data writing by an induced magnetic field, the current consumption can be sufficiently reduced.

  At time t4, a read cycle for reading data starts in synchronization with the rise of clock signal CLK. In this read cycle, at time t5, the word line WL in the selected row is driven to the selected state. The local column selection circuit 104 performs a column selection operation to couple the bit line of the selected column to the corresponding bus line of the local data bus 115.

  At the time of data reading, source line SLn is maintained at the ground voltage level by MOS transistor TN2 of source line drive gate 132. Therefore, bit line current IrdBL flows through the bit line selected by local column selection circuit 109 by the read current from sense amplifiers 122-0 to 122-31, and data is read according to this current.

  When data reading is completed at time t6, word line WL is driven to a non-selected state. The local column selection circuit 104 completes the column selection operation, and the bit line and the local data bus 115 are separated. In addition, the sense amplifiers 122-0 to 122-31 also stop the sensing operation.

  The bit line read current IrdBL supplied from the sense amplifier is in the opposite direction to the bit line write current IwrBL, is equal to the supply current (Iread) from the constant current source of the maximum sense amplifier, and is supplied from the sense amplifier current source. The value of the current Iread is smaller than the value of the bit line write current IwrBL (inversion) that causes the reversal of the magnetization direction of the memory cell due to minority carrier spin injection, but the bit line write for performing majority carrier spin injection The current value is larger than the current IwrBL.

  The direction in which this bit line read current IrdBL flows is the direction in which fractional spin injection is performed in the magnetoresistive effect element, and the magnetization reversal of the free layer is unlikely to occur. Accurate reading can be performed while maintaining the relationship of the magnetization direction of the free layer.

  FIG. 21 shows an example of the configuration of digit line decoders 150 and 160 shown in FIG. In FIG. 21, the configuration of word line drive gates 152 and 162 for driving word lines WL and WLR is also shown.

  In FIG. 21, a timing adjustment circuit 175 for adjusting the activation timing of sub memory circuit selection signal BA in accordance with read / write instruction signal R / WZ is provided for the sub memory circuit in common. Output signal S0 of timing adjustment circuit 175 is applied in common to the digit line driver and word line driver provided for the corresponding sub memory circuit. The sub memory circuit selection signal BA specifies one of the two sub memory circuits sharing the main word line MWL.

  Left digit line decoder 150 includes a three-input gate circuit 172 which receives output signal S0 of timing adjustment circuit 175, read / write instruction signal R / WZ, and a signal on main word line MWL corresponding thereto. Three-input gate circuit 172 has an output signal S0 of timing adjustment circuit 175 at L level, read / write instruction signal R / WZ at L level, and a signal on main word line MWL at H level. The output signal S1 is set to H level, and the output signal S1 is set to L level otherwise. The output signal of left digit line decoder 150 is applied in common to the gates of MOS transistors TP5 and TN1 included in digit line drive gate 152.

  Right digit line driver 160 includes a three-input gate circuit 174 receiving output signal S0 of timing adjustment circuit 175, a corresponding signal on main word line MWL, and read / write instruction signal R / WZ. Three-input gate circuit 174 outputs an output signal S2 when signal S0 is at H level, a signal on main word line MWL is at H level, and read / write instruction signal R / WZ is at L level. Other than that, the output signal S2 is set to L level.

  Output signal S2 of right digit line decoder 160 is applied in common to the gates of MOS transistors TP10 and TN10 included in digit line drive gate 162. MOS transistor TN10 has a relatively small current driving capability, while MOS transistors TN1 and TP10 have a relatively large current driving capability.

  Word line driver 180 includes a two-input gate circuit 180a receiving a signal on a corresponding main word line MWL and subarray selection signal AA0. Word line driver 182 includes a two-input gate circuit 182a receiving subarray selection signal AA1 and a signal on main word line MWL. Subarray selection signals AA0 and AA1 respectively specify a subarray including word line WLL and a subarray including word line WLR in the submemory circuit.

  FIG. 22 is a timing chart showing the operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 21 will be described below with reference to FIG.

  At the time of data writing, read / write instruction signal R / WZ is set to L level. When the corresponding sub memory circuit is selected, sub memory circuit selection signal BA is driven to the H level of the selected state, and at this time, when word line WLL is selected, sub array selection signal AA0 is driven to the selected state. . In parallel with the activation of the sub memory circuit selection signal BA, the main word line MWL is driven to the selected H level according to a row address signal (not shown). In the write mode, timing adjustment circuit 175 delays activation of output signal S0 in accordance with read / write instruction signal R / WZ. In this state, main word line MWL is in the selected state, read / write instruction signal R / WZ is at L level, and signal S0 is at L level. Therefore, output signal S1 of digit line decoder 150 is at H level. Thus, in the digit line drive gate 152, the MOS transistor TN1 is turned on. On the other hand, in digit line decoder 174, since output signal S0 of timing adjustment circuit 175 is at L level, output signal S2 is at L level. Therefore, MOS transistor TN1 is rendered conductive in digit line drive gate 152, and MOS transistor TP10 is rendered conductive in digit line drive gate 162, and a current from digit line drive gate 162 to digit line drive gate 152 flows through digit line DL. .

  In this state, the signal on main word line MWL and subarray selection signal AA0 are in the selected state, the output signal of word line driver 180 is at H level, and word line WLL is selected at the same timing as digit line selection. Driven to state.

  When the output signal S0 of the timing adjustment circuit 175 becomes H level, the output signal S1 of the left digit line decoder 150 becomes L level, while the output signal S2 of the right digit line decoder 160 becomes H level. Accordingly, MOS transistor TP5 is turned on in digit line driver 152, and MOS transistor TN10 is turned on in digit line driver 162, and a current flows through digit line DL from digit line driver 152 to digit line driver 162. In this case, MOS transistors TP5 and TN10 have a small current driving capability and a small digit line current flows.

  On the other hand, even if the control signal S0 rises to the H level, the sub-array selection signal AA0 and the signal of the main word line MWL do not change, so that the word line driver 180 maintains the word line WLL in the selected state.

  On the other hand, at the time of data writing, when array selection signal AA1 is at the H level, word line WLR is driven to a selected state by word line driver 182. Digit line DL is provided in common to the two sub-arrays of the sub-memory circuit, and the same operation as the multi-operation described above is performed on the digit line. That is, initially, a relatively large current flows through the digit line DL from the digit line drive gate 152 to the digit line drive gate 162. When the source line voltage is switched, the digit line DL is switched from the digit line drive gate 152 to the digit line. A relatively small current flows to the drive gate 162. Thus, in any subarray, when data of logic “1” is written by the bit line write current, the digit line assist current can be supplied to the digit line DL.

  FIG. 23 is a diagram showing an example of the configuration of the initial assist control circuit 172 shown in FIG. In FIG. 23, the configuration of the write drive gate 120-i is also shown.

  Initial assist control circuit 172 activates the output signal of OR circuit 172 in the data write cycle in accordance with 2-input OR circuit 172d receiving sub memory circuit selection signals BA0 and BA1 and read / write instruction signal R / WZ. Timing adjustment circuit 172e for delaying the timing of the read signal, a gate circuit 172a receiving read / write instruction signal R / WZ and output signal SS0 from timing adjustment circuit 172e, an output signal of gate circuit 172a, and read / write In response to the instruction signal R / WZ, the OR circuit 172b for driving the control signal line 170, the write data bit Di and the output signal of the gate circuit 172a are received, and the gate of the MOS transistor TN3 of the write drive gate 120-i is applied. An AND circuit 172c for providing the output signal is included.

  OR circuit 172d outputs an H level signal when one of the two sub memory circuits of the corresponding memory block is selected and one of sub memory circuit selection signals BA0 and BA1 is selected. The timing adjustment circuit 172e performs the same operation as that of the timing adjustment circuit 175 shown in FIG. 21 at the time of data writing, delays activation of the output signal of the OR circuit 172e, and outputs the timing adjustment signal SS0. In the data read cycle, timing adjustment circuit 172e maintains its output signal SS0 at the L level. Therefore, timing adjusting circuit 172e functions as a rising delay circuit during the data write cycle, and is configured by a circuit that maintains the output signal at the L level during the data read cycle.

  Gate circuit 172a outputs a signal at H level when timing adjustment signal SS0 is at H level and read / write instruction signal R / WZ is at L level. Therefore, at the time of data reading, the output signal of gate circuit 172a is at L level, and the output signal of AND circuit 172c is at L level, and MOS transistor TN3 of write drive gate 120-i maintains the non-conductive state. When read / write instruction signal R / WZ is at H level, the output signal of OR circuit 172b is at H level, and MOS transistor TP7 coupled to control signal line 170 is turned off. Therefore, write drive gate 120-i is in an output high impedance state at the time of data reading, and has no effect on the data reading operation for local data bus line 115i.

  At the time of data writing, read / write instruction signal R / WZ is at L level, gate circuit 172a operates as a buffer circuit, and OR circuit 172b also operates as a buffer circuit. The timing adjustment signal SS0 is generated from a timing adjustment circuit 172e that adjusts the timing of the output signal of the OR circuit 172d in accordance with the read / write instruction signal R / WZ. This timing adjustment circuit 172e has a configuration similar to that of the timing adjustment circuit 175 shown in FIG. 21, and changes the timing adjustment signals S0 and SS0 at the same timing during data writing. Sub memory circuit selection signals BA0 and BA1 specify two sub memory circuits sharing the main word line, respectively. Therefore, when one of the sub memory circuits sharing the main word line is selected, one of the sub memory circuit selection signals BA0 and BA1 is driven to the selected state. At the time of data writing, the timing adjustment circuit 172e delays the output signal of the OR circuit by a predetermined time to generate the timing adjustment signal SS0.

  When timing adjustment signal SS0 is at the L level, timing adjustment signal S0 is also at the L level. As described above with reference to the operation of the digit line drive gate with reference to FIGS. In FIG. 2, the main word line is in a selected state and a write current for inducing magnetic field is supplied to the digit line. In this state, the output signal of gate circuit 172a is at L level, and MOS transistor TP7 is rendered conductive in write drive gate 120-i in accordance with the L level output signal from OR circuit 172b, and local data bus line 115i. In addition, a current is supplied with a relatively small current driving force. In response, an assist current is supplied to the bit line. At this time, the output signal of the AND circuit 172c is at L level, and the MOS transistor TN3 is in a non-conductive state.

  On the other hand, when the predetermined time elapses and the timing adjustment signal SS0 becomes H level, the output signal of the gate circuit 172a becomes H level and the output signal of the OR circuit 172b becomes H level. Accordingly, MOS transistor TP7 coupled to control signal line 170 is turned off, and supply of the bit line write assist current is stopped. On the other hand, AND circuit 170c operates as a buffer circuit, and its output signal is set to H level or L level in accordance with write data bit Di. Accordingly, MOS transistor TN3 in write drive gate 120-i is set to the conductive or nonconductive state. When data bit Di is "1", it is at H level, MOS transistor TN3 is rendered conductive, local data bus line 115i is coupled to the ground node, and the bit line write current is driven. The current driving capability of MOS transistor TN3 is relatively large (driving a current smaller than the driving current of the read current supply source included in the sense amplifier), and thus a write current for performing spin injection can be supplied. .

  Source line SL also needs to supply an assist current and write current to the bit line at the time of data writing. According to control signal S1 or S2, when driving bit line assist current, the ground voltage level, bit line write When driving a built-in current, the power supply voltage level is set. In the configuration of the source line driver shown in FIG. 15, the configuration of the source line drive circuit is realized by supplying control signal S2 to decoder 130 instead of read / write instruction signal R / WZ.

  Also in the second embodiment, the digit line write current supply and the bit line write assist current supply timing do not have to be the same, and the periods need only overlap. Further, the supply timing of the bit line write current and the digit line write assist current may be different as long as both supply periods overlap.

  As described above, according to the second embodiment of the present invention, when the digit line current and the bit line current are driven to set the magnetization of the free layer of the memory cell, the assist current is applied to the bit line and the digit line, respectively. The time required for setting the magnetization of the free layer of the magnetoresistive effect element of the memory cell can be shortened, and the digit line write current for magnetic field induction and the bit line write for majority carrier spin injection The current can be reduced.

  The nonvolatile semiconductor memory device according to the present invention can be applied to a magnetic memory that uses a magnetoresistive effect element as a memory element and can set the magnetization of a free layer by spin injection. The present invention can also be applied to a magnetic memory that is a component of a system LSI integrated on the same chip as a processing device such as a memory and other processors.

1 schematically shows an entire configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. It is a figure which shows typically the data write sequence in the non-volatile semiconductor memory device according to this invention. It is a figure which shows roughly the planar layout of the memory cell used in Embodiment 1 of this invention. It is a figure which shows schematically the cross-section along 4A-4B shown in FIG. It is a figure which shows roughly the cross-section of the magnetoresistive effect element shown in FIG. 3 and FIG. FIG. 6 is a diagram schematically showing an aspect at the time of initial data writing of the magnetoresistive effect element shown in FIG. 5. It is a figure which shows schematically the mode at the time of data writing of logic "1" at the time of data writing according to this invention. It is a figure which shows roughly the modification of the magnetoresistive effect element applicable in this invention. 1 schematically shows a whole chip layout of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 10 schematically shows a configuration of a sub memory circuit shown in FIG. 9. FIG. 11 schematically shows structures of a local column selection circuit and a local write / read circuit shown in FIG. 10. FIG. 11 is a diagram showing a specific configuration of the memory cell array, word line drive circuit, digit line drive circuit, and local write / read circuit shown in FIG. 10. FIG. 13 is a timing chart showing the operation of the configuration shown in FIG. 12. It is a figure which shows an example of a structure of the digit line decoding shown in FIG. It is a figure which shows an example of a structure of the source line decoding shown in FIG. It is a figure which shows an example of a structure of a word line driver. FIG. 13 is a diagram schematically showing a configuration of a sense amplifier shown in FIG. 12. It is a figure which shows schematically the relationship between the hierarchical structure of the row-related selection line in Embodiment 1 of this invention, and a parallel write data unit. It is a figure which shows the structure of the principal part of the non-volatile semiconductor memory device according to Embodiment 2 of this invention. FIG. 20 is a timing chart showing an operation of the nonvolatile semiconductor memory device shown in FIG. 19. FIG. 20 is a diagram showing a configuration of digit line decoding shown in FIG. 19 together with a word line driver. FIG. 22 is a signal waveform diagram showing an operation of the circuit shown in FIG. 21. FIG. 20 is a diagram illustrating an example of a configuration of an initial assist control circuit illustrated in FIG. 19.

Explanation of symbols

  1 memory cell array, 2 digit line drive circuit, 3 word line drive circuit, 4 column selection circuit, 8 write data register, 6 bit line write drive circuit, 7 source line drive circuit, MC memory cell, TMR magnetoresistance effect element , MK0-MK15 Sub memory circuit, 100 Local memory array, 100l, 100r Sub memory array, 102l Left digit line drive circuit, 102r Right digit line drive circuit, 103r Right word line drive circuit, 103l Left word line drive circuit, 107 Left Source line drive circuit, 104 Local column selection circuit, 110 Local write / read circuit, 140 Left source line driver, 134 digit line decoder, 136 Left digit line driver, 130 Source line decoder, 132 Source line driver Ba, 122-0～122-31 sense amplifier, 120-0～120-31 write drive gate, 150, 160 digit line decoder, 152, 162 digit line drive gate, 172 initial assist control circuit.

Claims (15)

A plurality of memory cells including magnetoresistive elements arranged in a matrix and each having a resistance value set according to stored data;
At the time of data writing, regardless of the logical value of the write data, an initial data write current for magnetic field induction is applied in a single direction so as to apply a magnetic field in a single direction to the memory cells in the selected region, An initial write current supply circuit for setting storage data of a memory cell in a selected region to an initial value, and at the time of the data write, the selected memory cell in the selected region depends on a logical value of the write data A non-volatile semiconductor comprising a data write current supply circuit for selectively supplying a current in a single direction to the memory cells in the selected region to set the memory data in a state different from the initial value Storage device. The magnetoresistive effect element has a laminated structure of a fixed layer in which the magnetization direction is fixedly set regardless of stored data, and a free layer in which the magnetization direction is set according to the stored data,
The nonvolatile semiconductor memory device according to claim 1, wherein the current-induced magnetic field sets the magnetization direction of the free layer of the memory cell in the selected region to be opposite to the magnetization direction of the fixed layer. The nonvolatile semiconductor memory device further includes:
A plurality of bit lines arranged corresponding to each of the memory cell columns, each connected to a magnetoresistive element of a memory cell in the corresponding column;
A plurality of digit lines disposed corresponding to each of the memory cell rows, each coupled to a magnetoresistive element of a memory cell in the corresponding row;
The selected region is defined by a selected digit line of the plurality of digit lines;
The initial write current supply circuit supplies, to the digit line of the selected row, a current that generates a magnetic field in which the magnetoresistive effect element of the corresponding memory cell is in a high resistance state.
2. The data write current supply circuit supplies a current to a bit line of a selected column so that a current that causes a selected memory cell to be in a low resistance state flows to a magnetoresistive effect element of the selected memory cell. Nonvolatile semiconductor memory device. The magnetoresistive effect element includes: a fixed layer for injection that sets a spin direction of injected electrons to a fixed direction; a fixed layer for injection whose spin direction is fixed; a free layer whose magnetization direction is set according to stored data; the free layer; A nonmagnetic material layer disposed between the injection pinned layer and a magnetic pinned layer disposed opposite to the injection pinned layer with respect to the free layer and having a magnetization direction fixed regardless of stored data Having a laminated structure,
The nonvolatile semiconductor memory device further includes:
A plurality of source lines each disposed corresponding to each memory cell row;
Each is arranged corresponding to each memory cell row, and when each is selected, a plurality of word lines are provided for transmitting a signal for coupling the magnetoresistive effect element of the memory cell in the corresponding row to the source line in the corresponding row. ,
4. The nonvolatile semiconductor memory device according to claim 3, wherein the magnetization direction of the free layer is set by a current flowing between the corresponding bit line and source line via the magnetoresistive effect element.   2. The nonvolatile semiconductor memory device according to claim 1, further comprising a read current supply circuit that supplies a read current to a selected memory cell in a direction opposite to a current supplied by the data write current supply circuit when reading data.   The current supplied by the read current supply circuit is larger than the data write current supplied by the data write current supply circuit at the time of data writing and the current that reverses the magnetization of the magnetoresistive effect element of the memory cell The nonvolatile semiconductor memory device according to claim 5, wherein the nonvolatile semiconductor memory device is smaller than the value. The nonvolatile semiconductor memory device further includes:
A plurality of bit lines arranged corresponding to each of the memory cell columns, each connected to a magnetoresistive element of a memory cell in the corresponding column;
A plurality of digit lines arranged corresponding to each of the memory cell rows, each magnetically coupled to a magnetoresistive effect element of a memory cell in the corresponding row;
A read current supply circuit is provided for flowing a current to the bit line of the selected column during data reading.
The selected region is defined by a selected digit line of the plurality of digit lines;
The write current supply circuit supplies a data write current to the bit line in a single direction in a direction opposite to the read current,
The initial write current supply circuit includes:
A digit line drive circuit for supplying the initial data write current to the digit line of the selected row;
2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a circuit that supplies an assist current in parallel to the current supplied by the write current supply circuit to the bit line in the selected region in the opposite direction. The data write current supply circuit includes:
A circuit for supplying a data write current in one direction in accordance with write data to a bit line of a selected column when supplying the data write current;
The nonvolatile semiconductor memory device according to claim 7, further comprising: a circuit that supplies a current in a direction opposite to the initial data write current at the time of initial data write to the digit line of the selected row when the data write current is supplied. .   9. The nonvolatile semiconductor memory device according to claim 8, wherein a current flowing through the digit line when the initial write current is supplied is larger than a current flowing through the digit line when the data write current is supplied.   9. The nonvolatile semiconductor memory device according to claim 8, wherein a data write current supplied from said data write current supply circuit is larger than an assist current supplied from said initial data write current supply circuit.   9. The non-volatile semiconductor memory device according to claim 8, wherein currents flowing through the bit lines by said initial write current supply circuit and said write current supply circuit are in opposite directions.   9. The nonvolatile semiconductor memory device according to claim 8, wherein currents supplied to the digit lines by said initial write current supply circuit and said data write current supply circuit are in opposite directions. A plurality of word lines arranged corresponding to each memory cell row and connected to the corresponding memory cells;
A plurality of digit lines arranged corresponding to each memory cell row and magnetically coupled to the magnetoresistive effect elements of the memory cells in the corresponding row, and connected to each digit line. Is greater than the number of memory cells connected to each of the word lines,
A plurality of bit lines arranged corresponding to each memory cell column and connected to the magnetoresistive elements of the memory cells in the corresponding column,
The initial write current supply circuit supplies a magnetic field induced current to the digit line,
The nonvolatile semiconductor memory device according to claim 1, wherein the data write current supply circuit supplies a data write current to the bit line. The number of memory cells in which stored data is initialized in parallel by the initial write current is larger than the number of memory cells in which stored data is set by the data write current,
The nonvolatile semiconductor memory device according to claim 1, wherein the data write current supply circuit supplies the data write current in units of a predetermined number of memory cells.   The nonvolatile semiconductor memory device according to claim 13, further comprising a read circuit that reads data in memory cells smaller than the predetermined number in parallel.

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