JP2007103763A - High withstand voltage power semiconductor device structure and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure that enables a high withstand voltage power semiconductor device to be manufactured inexpensively. <P>SOLUTION: This power semiconductor device (MOS transistor, diode) provides the main function via a first main electrode (emitter, anode area) and a second main electrode (cathode, collector area) corresponding to the first main electrode. In this semiconductor device, the first main electrode to be formed on the n<SP>-</SP>-type semiconductor layer and the n<SP>+</SP>-type separation area 14 to be circularly formed enclosing a cell area near that electrode within an n<SP>-</SP>-type semiconductor layer are formed in a portion to be formed as a unit device periphery after dicing from the top surface of the n<SP>-</SP>-type semiconductor layer until they reach at least a depth dimension of thickness dimension of the n<SP>-</SP>-type semiconductor layer, wherein the n<SP>+</SP>-type separation area 14 is not a channel stopper. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power semiconductor device structure with improved breakdown voltage, and to a device structure and a manufacturing method that can be manufactured at low cost.

  There is Patent Document 1 as a technical document regarding the breakdown voltage improvement of the IGBT element.

Patent Document 1 (paragraph 0002) has the following description. “As a means for increasing the withstand voltage at the end of the IGBT cell region (a region corresponding to one MOSFET), a guard ring structure is generally provided on the outer periphery of the cell region of the element. As a result, the electric field becomes stepped and the breakdown voltage is improved.The main cross-sectional view of a conventional IGBT element having a guard ring structure is shown in FIG.
(Paragraph 0003) has the following description. “In FIG. 3 (described in FIG. 2 of the present application), a voltage surge is applied between the drain electrode 1 and the source electrode 9, and the pn junction 2 composed of the third semiconductor layer 7 and the second semiconductor layer 3 is reversed. Consider a situation in which a depletion layer (not shown) spreads in the high resistance second semiconductor layer 3 in a biased state, where a cell region (hereinafter referred to as an A region) in which a plurality of third and fourth semiconductor layers are arranged. That is, in the adjacent third semiconductor layer and the second semiconductor layer region positioned therebetween, the depletion layers extend from the adjacent third semiconductor layer 7 toward the second semiconductor layer region positioned therebetween and overlap each other. As a result, electric field relaxation is achieved, and the maximum electric field value E _A is obtained at the pn junction at the bottom of the third semiconductor layer, while the electric field relaxation is performed at the end of the region A where the repeated arrangement of the third semiconductor layer ends. Terminated third semiconductor layer, no effect Co - Na -. Take part to the maximum electric field value at the second surface of the semiconductor layer of the third semiconductor vicinity E _B, generally the E _A <E _B So close to the E _A value decreases the E _B value, A region In order to improve the breakdown voltage of a region (hereinafter referred to as B region) from the end of the second semiconductor layer to the end of the second semiconductor layer, one or more fifth semiconductor layers are provided in the B region and the maximum electric field value E _B of the B region is increased. In order to reduce the size, a guarding structure is generally used, and in addition to the fifth semiconductor layer, it has a contact portion with a part of the fifth semiconductor layer and extends over the second semiconductor layer via an insulating film. In some cases, a so-called field plate may be provided. " (Note, 18 in FIG. 2 is a field plate, and 6 is a p-layer of the fifth semiconductor layer and is a field limiting ring FLR). However, here, the B region is a cell region (acting site of main function, A region from the end of (A region) to the end of the second semiconductor layer 3 (periphery of the diced chip), which is a guard ring region.

Japanese Patent Laid-Open No. 07-115189. "Insulated Gate Bipolar Transistor"

  However, in the conventional structure such as Patent Document 1, it is necessary to secure a dimension for carrying a voltage around the FLR, so that a large area is spent for a guard ring for improving a withstand voltage. An inexpensive power semiconductor device that has a large chip area that does not contribute to the operation of the main function of the apparatus, and the number of chips that can be diced from one wafer is reduced, so that the cost per chip is high and the target cost can be achieved. Could not be produced.

  It is an object of the present invention to make a semiconductor device structure and manufacturing method suitable for mass production so that a power semiconductor device having a high withstand voltage can be completed by a method that can be produced at low cost.

  It is a problem to find a structure of a power semiconductor device that can improve the withstand voltage even if the area (B region) spent for improving the withstand voltage is reduced among the chip dimensions.

  In order to solve the above problem, an n + type semiconductor substrate (first layer) having a collector electrode on the lower surface, an n − type second layer epitaxially grown on the substrate, and a second layer A power semiconductor device having a cell region formed immediately below the main electrode (emitter electrode) connected to the control electrode and the control electrode, and a current flowing through the collector electrode controlled according to a voltage input to the control electrode, or In order to solve the above problems, a first conductivity type (p-type) semiconductor substrate (first layer) having a collector electrode on the lower surface and a second conductivity type (n +) second layer epitaxially grown on the substrate And a cell region formed by a main electrode (emitter electrode) connected to the third layer of the n− layer formed on the second layer and a portion immediately below the control electrode, and input to the control electrode The current flowing through the collector electrode is controlled according to the voltage In the power semiconductor device to be controlled, n extends from the upper surface of the n-layer having the emitter electrode toward the lower surface and surrounds the cell region, at least to a depth of the thickness dimension of the n-layer (for example, 55 μm). A power semiconductor device structure with a collector wall structure characterized by providing a + -type isolation region.

  With respect to claim 2, an n + type semiconductor substrate (first layer), an n − type second layer epitaxially grown on the substrate, and a first main body connected to the n − type second layer In a power semiconductor device comprising an electrode and a second main electrode provided on the substrate, having a cell region formed in a second layer immediately below the first main electrode, and rectifying an alternating current applied between the electrodes, Alternatively, a first conductivity type (p-type) semiconductor substrate (first layer), a second conductivity type (n +) second layer epitaxially grown on the substrate, and an n− formed on the second layer. A first main electrode connected to the third layer of the layer and a second main electrode provided on the substrate, and having a cell region formed in the third layer immediately below the first main electrode, between the electrodes In a power semiconductor device that rectifies an applied alternating current, a cell region extends from the upper surface of the n − layer having the first main electrode toward the lower surface. A shape surrounding, has a structure of the power semiconductor devices of the vertical structure, characterized in that the n + -type isolation region is provided at least on the n- layer thickness.

According to a third aspect of the present invention, there is provided the structure of the power semiconductor device according to the first or second aspect, wherein the first layer is a semiconductor substrate formed by forming an n + type semiconductor in a p-type semiconductor layer.
According to claim 4, the n + type isolation region is formed in a region where the position where the n + type isolation region is provided becomes a peripheral portion in each element separated after the semiconductor wafer is diced. It was set as the structure of a power semiconductor device.
The power semiconductor device structure according to claim 4, wherein the area of the guard ring region is smaller than the area of the cell region.

Regarding claim 6,
An n + type separation is performed at least from the upper surface of the second layer at a position that forms the outer periphery of the element when diced, and the step A of forming an n− type second layer on the upper surface of the n + type semiconductor substrate (first layer). Forming step A2 at a depth of the second layer;
Forming a p-layer (third layer) in a predetermined shape on the second layer by impurity diffusion; and
Forming a first main electrode in connection with the third layer;
Performing a step I of forming a second main electrode on the lower surface of the semiconductor substrate (first layer);
In the process J of forming individual unit semiconductor elements by dicing,
A power semiconductor characterized in that it is diced so that an n + -type isolation region is positioned at least in the thickness dimension of the second layer (n− layer) in a shape surrounding a cell region which is a region immediately below the first type electrode A device manufacturing method was adopted.

Regarding claim 7,
Step A for forming an n-type second layer on the upper surface of a p-type or n + -type semiconductor substrate (first layer), and n + -type separation at the position that becomes the outer periphery of the element when diced A step A2 of forming at least the depth of the second layer from the upper surface;
Forming a gate oxide film in a predetermined shape on the emitter side plane; and
Forming a control electrode in a predetermined shape on the first insulating layer; and
A step D of depositing and forming a second insulating layer covering the control electrode;
Forming a p-layer (third layer) in a predetermined shape on the second layer by impurity diffusion; and
Forming an n layer (fourth layer) in the third layer by impurity diffusion; and
A step G of forming an emitter electrode by connecting the third layer and the fourth layer to both layers while short-circuiting;
Forming a hole in the second insulating layer to lead out the control electrode; and
Performing a step I of forming a collector electrode on the lower surface of the semiconductor substrate (first layer);
In the process J of forming individual unit semiconductor elements by dicing,
A power semiconductor device characterized in that it is diced so that an n + -type isolation region is positioned at least in the thickness dimension of the second layer (n-layer) in a shape surrounding a cell region which is an active region immediately below the emitter electrode It was set as the manufacturing method of this.

  According to the structure of the present invention, since the chip size of 0.95 mm square can be reduced to 0.82 mm square, the number of chips obtained by dicing from one wafer increases to 134% and is stable. Could be mass-produced. Therefore, 34% of the chips can be provided at low cost because the cost can be reduced by the increase in the production of the same wafer. Since the number of man-hours that used to form one or more field limiting rings (FLR) and field plates (metal films) can be eliminated from the conventional production man-hours, labor costs have been greatly increased. Reduced production costs have been reduced.

  An embodiment according to the present invention will be described with reference to a structural diagram shown in FIG. Reference numeral 4 denotes a semiconductor substrate (n + layer) on which a collector electrode 1 is provided. A second semiconductor layer (n− layer) is formed on the upper surface of the semiconductor substrate 4 by epitaxial growth or the like, and an emitter layer is formed thereon to provide an emitter electrode 9 and a control electrode (gate electrode) via a gate insulating film 11. 10 is formed, and an IGBT (Insulated Gate Bipolar Transistor) element that functions by the cell region 30 that is an active zone immediately below the emitter electrode 9 and the control electrode 10 is formed. In the conventional example of FIG. 3 in which the same part is indicated by the same reference numeral, the reverse breakdown voltage is borne by the FLR (field limiting ring) 6 of a p-type semiconductor formed in an annular shape so as to surround the cell region 30. This structure was abolished, and an n + type isolation region 14 for carrying a withstand voltage as shown in FIG. 1 was formed by an impurity diffusion method or the like. The semiconductor substrate 6 is not limited to an n + type semiconductor but may be a p-type semiconductor.

  The two main electrodes of the collector electrode 1 and the emitter electrode 9 and the control electrode 10 are derived by forming electrodes with a metal electrode material. An oxide film 13 that is an insulator is formed around the emitter electrode 9 so as to contribute to withstand voltage. A collector electrode 1 of a metal electrode is formed on a plane below the semiconductor substrate 4. Thus, the power device is completed, and dicing is performed at the site of the n + type isolation region 14 in FIG. 1 to complete the element of the power semiconductor device. As a result, the n + type isolation region 14 is formed at the peripheral portion of the power semiconductor device.

  As shown in FIG. 2 and FIG. 3 in the cross-sectional view of the conventional chip, the size of the conventional B region (guard ring region) was 175 μm in FIG. 3, but in the embodiment of the present invention in FIG. As shown in FIGS. 2 and 3, the conventional p-type semiconductor FLR (field limiting ring or guard ring) 6 is not required and is 110 μm. With the emitter electrode size of 600 μm, the size of the conventional chip of FIG. 3 was 950 μm square, whereas in FIG. 1, the finished product was 820 μm square and could be stably mass-produced. Therefore, since the number of chips that can be cut out from one wafer has increased to 134%, even if the manufacturing method is the same as the conventional manufacturing process, the cost has been reduced by an increase of 34%. FIG. 4 shows a manufacturing process flow chart of a power semiconductor according to an embodiment of the present invention, and FIG. 5 shows a manufacturing process flow chart of a conventional power semiconductor produced by the present inventors.

  Since the present invention succeeded in reducing the chip area that has become large for improving the breakdown voltage of the semiconductor device, the number of chips that can be taken from the same wafer increases, and the product cost per chip can be reduced. It contributes to energy and resource saving when producing semiconductor devices, and has a high industrial contribution.

Structure of power semiconductor according to one embodiment of the present invention Structure of conventional power semiconductor in Patent Document 1 Structure diagram of the conventional power semiconductor produced by the authors Manufacturing process flow diagram of power semiconductor according to an embodiment of the present invention Flow chart of manufacturing process of conventional power semiconductors made by the authors

Explanation of symbols

1 drain (collector) electrode 2 pn junction consisting of p + layer (third layer) and n- layer (second layer) 3 n- layer (second layer)
4 n + layer (first layer) semiconductor substrate 5 n + type isolation region 6 p layer field limiting ring (FLR) or guard ring 7 p + layer (third layer)
8 n + layer (fourth layer)
9 Emitter electrode (source electrode)
DESCRIPTION OF SYMBOLS 10 Gate electrode 11 Gate insulating film 12 Interlayer insulating film 13 Oxide film 14 n + type isolation region 18 Metal film (field plate)
30 cell area

Claims (7)

  an n + type semiconductor substrate (first layer), an n − type second layer formed on the upper surface of the first layer, a first main electrode (emitter electrode) connected to the upper surface of the second layer, and a second A control electrode connected to the upper surface of the layer via an insulating layer; a cell region formed immediately below the first main electrode (emitter electrode) and immediately below the control electrode; In a power semiconductor device having a collector wall structure provided with a main electrode (collector electrode), the thickness dimension of at least the second layer (n− layer) extends from the upper surface of the second layer toward the lower surface and surrounds the cell region. A structure of a power semiconductor device characterized in that an n + -type isolation region is provided in the structure.   an n + type semiconductor substrate (first layer), an n− type second layer formed on the upper surface of the first layer, a first main electrode formed on and connected to the second layer, and the semiconductor substrate In a power semiconductor device having a second main electrode provided on the lower surface and having a cell region formed immediately below the first main electrode, the shape extends from the upper surface of the second layer toward the lower surface and surrounds the cell region. A structure of a power semiconductor device having a vertical structure, wherein an n + type isolation region is provided at least in the thickness dimension of the second layer.   3. The structure of a power semiconductor device according to claim 1, wherein the first semiconductor layer is an n + type first layer formed by epitaxially growing an n + type semiconductor on the p type semiconductor upper surface.   The portion where the n + type isolation region is formed is a portion which becomes the periphery of the unit element after the semiconductor wafer is diced, and is a guard ring region having an area excluding the area of the cell region from the area of the single semiconductor chip. 4. The structure of a power semiconductor device according to claim 1, which is an n + type isolation region forming an area.   5. The structure of a power semiconductor according to claim 4, wherein the area of the guard ring region is formed to have a size equal to or not exceeding the area size of the cell region of the unit element. An n + type separation is performed at least from the upper surface of the second layer at a position that forms the outer periphery of the element when diced, and the step A of forming an n− type second layer on the upper surface of the n + type semiconductor substrate (first layer). Forming step A2 at a depth of the second layer;
Forming a p-layer (third layer) in a predetermined shape on the second layer by impurity diffusion; and
Forming a first main electrode in connection with the third layer; and
Performing a step I of forming a second main electrode on the lower surface of the semiconductor substrate (first layer);
In the process J of forming individual unit semiconductor elements by dicing,
A method for manufacturing a power semiconductor device, characterized in that dicing is performed so that an n + -type isolation region is positioned at a position that is an outer periphery of an element in a shape surrounding a cell region that is a region immediately below a first main electrode. Step A for forming an n-type second layer on the upper surface of a p-type or n + -type semiconductor substrate (first layer), and n + -type separation at the position that becomes the outer periphery of the element when diced A step A2 of forming at least the depth of the second layer from the upper surface;
Forming a gate oxide film in a predetermined shape on the emitter side plane; and
Forming a control electrode in a predetermined shape on the first insulating layer; and
A step D of depositing and forming a second insulating layer covering the control electrode;
Forming a p-layer (third layer) in a predetermined shape on the second layer by impurity diffusion; and
Forming an n layer (fourth layer) in the third layer by impurity diffusion; and
A step G of forming an emitter electrode by connecting the third layer and the fourth layer to both layers while short-circuiting;
Forming a hole in the second insulating layer to lead out the control electrode; and
Performing a step I of forming a collector electrode on the lower surface of the semiconductor substrate (first layer);
In the process J of forming individual unit semiconductor elements by dicing,
A method of manufacturing a power semiconductor device, characterized in that dicing is performed so that an n + -type isolation region is positioned at a position that is an outer periphery of an element in a shape surrounding a cell region that is an active region immediately below an emitter electrode.

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