JP2007103505A - Light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device with high light emission efficiency, allowing miniaturization. <P>SOLUTION: The light emitting device LE1 comprises a laminated chip varistor 11, a semiconductor light emitting element 1, and a reflecting layer 24. The laminated chip varistor 11 comprises a varistor element 21 composed of a varistor layer, and of a plurality of internal electrodes disposed to sandwich the varistor layer; and first external electrodes 22, 23 and second external electrodes 25 to 28 formed on the outer surface of the varistor element 21, and respectively connected with the corresponding internal electrodes among the plurality of the internal electrodes. The semiconductor light emitting element 1 is disposed on the laminated chip varistor 11 and is connected with the second external electrodes 25 to 28 so as to be connected in parallel with the laminated chip varistor 11. The reflecting layer 24 is disposed between the laminated chip varistor 11 and the semiconductor light emitting element 1, and reflects light emitted from the semiconductor light emitting element 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light emitting device.

As a conventional light-emitting device, a device including a semiconductor light-emitting element and a varistor connected in parallel to the semiconductor light-emitting element is known (for example, see Patent Document 1). In the light emitting device described in Patent Document 1, a light reflecting plate is disposed around the semiconductor light emitting element.
Japanese Patent Laid-Open No. 2001-15815

  In the light emitting device described in Patent Document 1, a space for arranging the light reflection plate must be secured around the semiconductor light emitting element. Therefore, it is difficult to reduce the size of the entire light emitting device. However, if the light reflector is not arranged in order to reduce the size, the light emission efficiency is lowered.

  Therefore, an object of the present invention is to provide a light-emitting device that has high luminous efficiency and can be reduced in size.

  A light-emitting device according to the present invention is formed on the outer surface of a laminate having a varistor layer and a plurality of internal electrodes arranged so as to sandwich the varistor layer, and among the plurality of internal electrodes A multilayer chip varistor having a plurality of external electrodes each connected to a corresponding internal electrode, and disposed on the multilayer chip varistor and connected to the plurality of external electrodes so as to be connected in parallel to the multilayer chip varistor And a reflective layer that is disposed between the stacked chip varistor and the semiconductor light emitting element and reflects light generated by the semiconductor light emitting element.

  In the light emitting device of the present invention, since the reflective layer is disposed between the multilayer chip varistor and the semiconductor light emitting element, light traveling toward the multilayer chip varistor generated by the semiconductor light emitting element can be reflected. Therefore, high luminous efficiency can be obtained. In addition, since the reflective layer is formed between the multilayer chip varistor and the semiconductor light emitting element, it is not necessary to secure a special space around the semiconductor light emitting element. Therefore, the entire light emitting device can be reduced in size.

  Moreover, it is preferable that a reflection layer contains glass and a metal. In this case, the reflective layer is a dispersion of metal in glass. Since glass is included, a reflective layer having electrical insulation can be obtained. Therefore, a short circuit between the external electrodes of the multilayer chip varistor via the reflective layer can be suppressed. Moreover, the reflection layer can be made excellent in heat resistance by including glass. Since the metal is included, the light generated by the semiconductor light emitting element can be reliably reflected. Moreover, since heat conductivity becomes favorable by containing a metal, the heat | fever from a semiconductor light-emitting device can be dissipated efficiently.

  Moreover, it is preferable that a reflection layer contains resin and a metal. In this case, the reflective layer has a metal dispersed in the resin. Since the reflective layer contains a resin, it has electrical insulation. Therefore, a short circuit between the external electrodes of the multilayer chip varistor via the reflective layer can be suppressed. In addition, the inclusion of the resin facilitates the formation of the reflective layer, and can improve the adhesion between the multilayer chip varistor or semiconductor light emitting element and the reflective layer. Further, since the metal is included, the light generated by the semiconductor light emitting element can be reliably reflected. By including the metal, the thermal conductivity is improved, so that the heat from the semiconductor light emitting element can be efficiently dissipated.

  Moreover, it is preferable that a reflection layer contains glass and a metal oxide. In this case, since glass is included, a reflective layer having electrical insulation and heat resistance can be obtained. Since the metal oxide is included, the light generated by the semiconductor light emitting element can be reliably reflected, and the electrical insulation of the reflective layer can be further enhanced. Further, since the metal oxide has good dispersibility in the glass, a reflective layer in which the metal oxide is uniformly dispersed and the characteristic variation is small can be easily formed. By including glass and a metal oxide, a reflective layer having a relatively small thermal expansion coefficient can be obtained. As a result, the reflective layer can be made less susceptible to distortion, cracking and cracking.

  Moreover, it is preferable that a reflection layer contains resin and a metal oxide. In this case, since the reflective layer contains a resin, it has electrical insulation. In addition, the inclusion of the resin facilitates the formation of the reflective layer, and can improve the adhesion between the multilayer chip varistor or semiconductor light emitting element and the reflective layer. Furthermore, since the reflective layer contains a metal oxide, the light generated by the semiconductor light emitting element can be reliably reflected, and the electrical insulation of the reflective layer can be further enhanced.

  The reflective layer preferably contains glass and metal powder, and the metal powder is preferably coated with a metal oxide. Since glass is included, a reflective layer having electrical insulation and heat resistance can be obtained. By using a metal powder coated with a metal oxide, the dispersibility of the metal powder in the glass can be improved, and the electrical insulation of the reflective layer can be further improved without reducing the reflection efficiency. it can.

  The reflective layer preferably contains a resin and a metal powder, and the metal powder is preferably coated with a metal oxide. Since the resin is included, a reflective layer having electrical insulation, easy formation, and good adhesion can be obtained. By using metal powder coated with metal oxide, the dispersibility of the metal powder in the resin can be improved, and the electrical insulation of the reflective layer can be further improved without reducing the reflection efficiency. it can.

  The reflective layer preferably has a thin film layer made of metal. In this case, the light generated by the semiconductor light emitting element with the metal can be reliably reflected. Since the thin film layer is used, the thickness of the reflective layer can be reduced. As a result, the light emitting device can be further downsized.

  The reflective layer preferably contains at least one of Ag, Al, Ti, and Ni as a metal. Since Ag, Al, Ti, and Ni have a higher reflectance than other general metals, the reflection efficiency of the reflective layer can be improved. Therefore, the luminous efficiency can be further increased.

  The reflective layer preferably contains at least one of silicone resin, polytetrafluoroethylene, polyethylene terephthalate, and xylene resin as a resin. When these materials are used, a reflective layer having high electrical insulation can be obtained with certainty. In addition, the ease of forming the reflective layer and the adhesion between the multilayer chip varistor or semiconductor light emitting element and the reflective layer can be reliably increased.

The reflective layer preferably contains at least one of Al ₂ O ₃ , TiO ₂ , SiO ₂ , and ZrO ₂ as a metal oxide. Since Al ₂ O ₃ , TiO ₂ , SiO ₂ , and ZrO ₂ have a higher reflectance than other general metal oxides, the reflection efficiency of the reflective layer can be further increased.

  The reflective layer is preferably formed on the surface of the multilayer chip varistor facing the semiconductor light emitting element. In this case, the reflective layer and the multilayer chip varistor can be integrally formed. Further, the reflective layer is preferably formed on the surface facing the multilayer chip varistor of the semiconductor light emitting device. In this case, the reflective layer and the semiconductor light emitting element can be integrally formed. As described above, when the multilayer chip varistor or the semiconductor light emitting element and the reflective layer are integrally formed, the assembly of the semiconductor light emitting device is facilitated.

  The semiconductor light emitting device is preferably flip-chip bonded or wire bonded on the multilayer chip varistor. In this case, the semiconductor light emitting device can be disposed on the multilayer chip varistor without providing a support member for supporting the semiconductor light emitting device. Therefore, further downsizing of the entire light emitting device can be achieved.

  According to the present invention, it is possible to provide a light emitting device that has high luminous efficiency and can be miniaturized.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  (First embodiment)

  With reference to FIGS. 1-5, the structure of light-emitting device LE1 which concerns on 1st Embodiment is demonstrated. FIG. 1 is a schematic top view showing the light emitting device LE1 according to the first embodiment. FIG. 2 is a schematic perspective view showing the multilayer chip varistor included in the light emitting device LE1 according to the first embodiment. FIG. 3 is a schematic top view showing the multilayer chip varistor included in the light emitting device LE1 according to the first embodiment. FIG. 4 is a diagram for explaining a cross-sectional configuration along the line IV-IV in FIG. 3. FIG. 5 is a diagram for explaining a cross-sectional configuration along the line VV in FIG. 3.

  The light emitting device LE1 includes the semiconductor light emitting element 1, the reflective layer 24, and the multilayer chip varistor 11, as shown in FIGS.

  First, the configuration of the multilayer chip varistor 11 will be described. As shown in FIG. 2, the multilayer chip varistor 11 includes a varistor element body 21 (laminate) having a substantially rectangular parallelepiped shape, first external electrodes 22 and 23, and second external electrodes 25, 26 and 27. , 28. The first external electrodes 22, 23 and the second external electrodes 25, 26, 27, 28 are formed on the main surface (outer surface) 21 a of the varistor element body 21, respectively. For example, the varistor element body 21 is set to have a length of about 1.0 mm, a width of about 0.5 mm, and a thickness of about 0.3 mm.

  As shown in FIG. 3, the varistor element body 21 includes a plurality of varistor layers that exhibit voltage nonlinear characteristics (hereinafter referred to as “varistor characteristics”), a plurality of first internal electrodes 31, and a plurality of first varistor layers. This is a laminate in which two internal electrodes 41 are laminated. The first internal electrodes 31 and the second internal electrodes 41 are alternately arranged in the varistor element body 21 along the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”). The first internal electrode 31 and the second internal electrode 41 are arranged so that at least one varistor layer is sandwiched between them. The main surface 21a of the varistor element body 21 extends in a direction parallel to the stacking direction and parallel to the direction in which the varistor layer extends. In the actual multilayer chip varistor 11, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized.

  The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, a region of the varistor layer that overlaps the first internal electrode 31 and the second internal electrode 41 contains ZnO as a main component and Pr.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 5 to 60 μm.

  As shown in FIG. 4, the first internal electrode 31 includes a first electrode portion 33 and a second electrode portion 35. The first electrode portion 33 has a substantially rectangular shape. The first electrode portion 33 overlaps the first electrode portion 43 of the second internal electrode 41 shown in FIG. 5 when viewed from the stacking direction. The second electrode portion 35 is drawn out from the first electrode portion 33 so as to be exposed on the main surface 21a of the varistor element body 21, and functions as a lead conductor. The second electrode portion 35 is physically and electrically connected to the first external electrode 22. The first electrode portion 33 is electrically connected to the first external electrode 22 through the second electrode portion 35. The second electrode portion 35 is formed integrally with the first electrode portion 33.

  As shown in FIG. 5, the second internal electrode 41 includes a first electrode portion 43 and a second electrode portion 45. The first electrode portion 43 has a substantially rectangular shape. The first electrode portion 43 overlaps the first electrode portion 33 of the first internal electrode 31 shown in FIG. 4 when viewed from the stacking direction. The second electrode portion 45 is drawn out from the first electrode portion 43 so as to be exposed on the main surface 21a of the varistor element body 21, and functions as a lead conductor. The second electrode portion 45 is physically and electrically connected to the first external electrode 23. The first electrode portion 43 is electrically connected to the first external electrode 23 through the second electrode portion 45. The second electrode portion 45 is formed integrally with the first electrode portion 43.

  The first and second internal electrodes 31 and 41 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st and 2nd internal electrodes 31 and 41, It is preferable to consist of Ag-Pd alloy. The thickness of the first and second internal electrodes 31 and 41 is, for example, about 0.5 to 5 μm.

  As described above, the first electrode portion 33 of the first internal electrode 31 and the first electrode portion 43 of the third internal electrode 41 are the first electrode portions 33 of the adjacent first internal electrodes 31. And overlap each other. Therefore, a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer functions as a region that develops varistor characteristics. In the multilayer chip varistor 11 having the above-described configuration, the first electrode portion 33, the first electrode portion 43, and a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer. One varistor portion is formed.

  As shown in FIG. 2, the first external electrodes 22 and 23 are arranged on the main surface 21a of the varistor element body 21 at a predetermined interval (for example, in a direction perpendicular to the stacking direction of the varistor layers and parallel to the main surface 21a). (Interval of 50 μm or more). The first external electrodes 22 and 23 have a rectangular shape (in this embodiment, a rectangular shape). The first external electrodes 22 and 23 contain Au, and are formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of a metal powder containing Au particles as a main component and an organic binder and an organic solvent is used.

  Second external electrodes 25, 26, 27, and 28 are formed on the first external electrodes 22 and 23. The second external electrode 25 and the second external electrode 26 are arranged on the main surface 21a with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the main surface 21a. The second external electrode 25 is physically and electrically connected to the first external electrode 22, and the second external electrode 26 is physically and electrically connected to the first external electrode 23. The second external electrodes 25 and 26 have a rectangular shape (in this embodiment, a square shape). The second external electrode 25 functions as an input terminal electrode of the multilayer chip varistor 11, and the second external electrode 26 functions as an output terminal electrode of the multilayer chip varistor 11.

  The second external electrodes 27 and 28 are arranged so as to be sandwiched between the pair of second external electrodes 25 and 26. The second external electrode 27 and the second external electrode 28 are arranged on the main surface 21a with a predetermined interval in a direction perpendicular to the varistor layer stacking direction and parallel to the main surface 21a. The second external electrode 27 is physically and electrically connected to the first external electrode 22, and the second external electrode 28 is physically and electrically connected to the first external electrode 23. Thus, the second external electrode 25 and the second external electrode 27 are electrically connected via the first external electrode 22, and the second external electrode 26 and the second external electrode 28 are connected to each other. Electrical connection is made via the first external electrode 23. The second external electrodes 27 and 28 have a rectangular shape (in this embodiment, a square shape). The second external electrodes 27 and 28 function as pad electrodes that are electrically connected to the semiconductor light emitting element 1 described later.

  The second external electrodes 25 to 28 are formed on the first external electrodes 22 and 23 by, for example, a plating method. The second external electrodes 25 to 28 are made of Au or Pt. When the plating method is used, the second external electrodes 25 to 28 are formed by vapor-depositing Au or Pt by a vacuum plating method (vacuum deposition method, sputtering method, ion plating method, or the like). The second external electrodes 25 to 28 may be configured as a Pt / Au laminated body.

  A reflective layer 24 is disposed between the multilayer chip varistor 11 having such a configuration and the semiconductor light emitting element 1 as shown in FIGS. 4 and 5. The reflective layer 24 is formed on the surface of the multilayer chip varistor 11 facing the semiconductor light emitting element 1, that is, on the main surface 21 a of the varistor element body 21. The reflection layer 24 formed at such a position reflects light traveling in the direction of the multilayer chip varistor 11 out of the light generated by the semiconductor light emitting element 1.

  More specifically, the reflection layer 24 is formed so as to cover the main surface 21a of the varistor element body 21, as shown in FIG. The reflective layer 24 is formed on the first external electrodes 22 and 23, and has openings 24a to 24d at portions where the second external electrodes 25 to 28 are disposed. The openings 24a to 24d are larger than the second external electrodes 25 to 28, and the second external electrodes 25 to 28 are disposed at the centers of the openings 24a to 24d, respectively. The first external electrode 22 is exposed from the openings 24a and 24c, and the first external electrode 23 is exposed from the openings 24b and 24d. The second external electrode 25 is connected to the first external electrode 22 exposed from the opening 24a, and the second external electrode 26 is connected to the first external electrode 23 exposed from the opening 24b. The second external electrode 27 is connected to the first external electrode 22 exposed from the opening 24c, and the second external electrode 28 is connected to the first external electrode 23 exposed from the opening 24d.

  The reflective layer 24 can be formed using various materials. For example, the reflective layer 24 includes glass and an additive. In this case, the reflective layer 24 is obtained by dispersing additives in glass. By including glass, the reflective layer 24 having electrical insulation can be obtained. By having electrical insulation, it is possible to prevent a short circuit between the first electrodes 22 and 23 via the reflective layer 24. Moreover, the reflection layer 24 can be made excellent in heat resistance by including glass.

  As an additive contained in the reflective layer 24, a metal can be used. The reflective layer 24 containing a metal can reliably reflect the light generated by the semiconductor light emitting element 1. Moreover, since the heat conductivity of the reflective layer 24 becomes favorable by using a metal, the heat from the semiconductor light emitting element 1 can be dissipated efficiently. As the metal, Ag, Al, Ti, Ni, etc., which have a higher reflectance than other general metals are suitable. In particular, when Ag or Al is used, the reflection efficiency of the reflection layer 24 can be further increased.

In addition, a metal oxide can also be used as an additive. The reflective layer 24 containing a metal oxide can reliably reflect the light generated by the semiconductor light emitting element 1. In addition, the electrical insulation of the reflective layer 24 can be further enhanced as compared with the case where a metal is used. Since the metal oxide has good dispersibility in the glass, the reflective layer 24 in which the metal oxide is uniformly dispersed and the characteristic variation is small can be easily formed. Since the reflective layer 24 contains glass and a metal oxide, the reflective layer 24 having a relatively small thermal expansion coefficient can be obtained, and distortion, cracks, and cracks can be suppressed. As the metal oxide, Al ₂ O ₃ , TiO ₂ , SiO ₂ , ZrO ₂ , and the like, which have a higher reflectance than other general metal oxides, are suitable. In particular, when Al ₂ O ₃ is used, the reflection efficiency of the reflective layer 24 can be further increased.

As another additive, a powder made of a metal coated with a metal oxide can also be used. The metal oxide is coated on the powder by a method such as barrel sputtering, plasma oxidation, or thermal oxidation. By coating with a metal oxide, the dispersibility of the powder made of metal in the glass can be improved. In addition, by using a metal powder coated with a metal oxide, it is possible to obtain a reflective layer 24 having both the characteristics of a metal having high reflection efficiency and the characteristics of a metal oxide having high electrical insulation. Therefore, it is possible to further increase the electrical insulation of the reflective layer 24 without reducing the reflection efficiency. Particularly, in the case of using a material obtained by coating the Al ₂ O ₃ as coated with Al ₂ O ₃ powder consisting of _Ag, or the powder of Al can further improve the reflection efficiency of the reflective layer 24.

  The reflective layer 24 may include a resin and an additive. In this case, the reflective layer 24 is obtained by dispersing additives in the resin. By including the resin, the reflective layer 24 can have electrical insulation. Further, the reflective layer 24 can be easily formed and the adhesion between the multilayer chip varistor 11 and the reflective layer 24 is improved. Further, the thermal stress applied to the multilayer chip varistor 11 can be reduced. As the resin, it is preferable to use at least one of silicone resin, polytetrafluoroethylene, polyethylene terephthalate, and xylene resin. When such a resin is used, the reflective layer 24 with high electrical insulation can be obtained with certainty. In addition, the ease of forming the reflective layer 24 and the adhesion between the multilayer chip varistor 11 and the reflective layer 24 can be reliably increased. As the additive, as in the case of glass, metal, metal oxide, or metal powder coated with metal oxide can be used.

  The reflective layer 24 may have a thin film layer made of metal. In this case, an insulating layer is formed under the metal-containing thin film layer for the purpose of preventing a short circuit between the first electrodes 22 and 23 via the reflective layer 24. The light generated by the semiconductor light emitting element 1 can be reliably reflected by the thin film layer containing metal. Further, by using the thin film layer, the thickness of the reflective layer 24 can be reduced. As the metal contained in the thin film layer, Ag, Al, Ti, Ni, etc., which have a higher reflectance than other general metals are suitable. In particular, when Ag or Al is used, the reflection efficiency of the reflection layer 24 can be further increased.

  As a result of examining the various reflective layers 24 as described above, the reflective layer 24 of the present embodiment includes glass and Ag. By using Ag, the reflection layer 24 can have excellent reflection characteristics particularly with respect to light having a wavelength of about 450 nm. As a result, the reflection efficiency of the reflective layer 24 can be sufficiently increased.

  The reflective layer 24 containing glass and Ag is formed on the main surface 21a of the varistor element body 21 by, for example, a printing method. When the printing method is used, a glass paste in which glass powder, Ag powder, an organic binder, and an organic solvent are mixed is prepared, and the glass paste is used as the first external electrodes 22 and 23 and the main surface 21a of the varistor element body 21. The reflective layer 24 is formed by printing on the substrate, drying, and firing.

  Next, a manufacturing process of the multilayer chip varistor 11 and the reflective layer 24 having the above-described configuration will be described with reference to FIGS. FIG. 6 is a flowchart for explaining a manufacturing process of the multilayer chip varistor and the reflective layer according to the first embodiment. 7 and 8 are diagrams for explaining a manufacturing process of the multilayer chip varistor and the reflective layer according to the first embodiment.

  First, after weighing ZnO, which is a main component constituting the varistor layer, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides so as to have a predetermined ratio. Each component is mixed to prepare a varistor material (step S100). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S101).

  Next, a plurality of electrode portions corresponding to the first and second internal electrodes 31 and 41 (a number corresponding to the number of divided chips described later) are formed on the green sheet (step S102). The electrode portions corresponding to the first and second internal electrodes 31 and 41 are made by using a conductive paste in which a metal powder mainly composed of Ag—Pd alloy particles, an organic binder, and an organic solvent is mixed for a printing method such as screen printing. It is formed by printing and drying.

  Next, each green sheet on which the electrode portion is formed and a green sheet on which the electrode portion is not formed are stacked in a predetermined order to form a sheet laminate (step S103). The sheet laminate thus obtained is cut into chips, and a plurality of divided green bodies GL1 (see FIG. 7) are obtained (step S104). In the obtained green body GL1, a green sheet GS1 in which an electrode portion EL1 corresponding to the first internal electrode 31 is formed, a green sheet GS2 in which an electrode portion EL2 corresponding to the second internal electrode 41 is formed, A green sheet GS3 on which the electrode portions EL1 and EL2 are not formed is sequentially laminated. A plurality of green sheets GS3 positioned between the green sheets GS1 and GS2 may be stacked or may not be stacked.

  Next, as shown in FIG. 8A, a conductive paste for the first external electrodes 22 and 23 is applied to the outer surface of the green body GL1 (FIG. 6, step S105). Here, a conductive paste is printed on the main surface of the green body GL1 so as to be in contact with the corresponding electrode portions EL1 and EL2 by a screen printing method, and then dried, whereby the first external electrodes 22 and 23 are applied. Corresponding electrode portions are formed. As the conductive paste for the first external electrodes 22, 23, as described above, a metal powder mainly composed of Au particles mixed with an organic binder and an organic solvent can be used.

  Next, as shown in FIG. 8B, a glass paste for the reflective layer 24 is applied on the first external electrodes 22 and 23 (FIG. 6, step S106). Here, a glass paste in which Ag powder, glass powder, an organic binder and an organic solvent are mixed is printed and applied by a printing method such as screen printing. At this time, since the glass paste is not printed and applied to the portions corresponding to the openings 24a to 24d, the first external electrodes 22 and 23 are exposed from the portions corresponding to the openings 24a to 24d. After printing and applying the glass paste, a layer corresponding to the reflective layer 24 is formed by drying.

  Next, the green body GL1 to which the glass paste is applied is subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to perform binder removal, and then further to 1000 to 1400 ° C. and 0.5 ° C. Baking is performed for about ˜8 hours (FIG. 6, step S107), and the varistor element body 21, the first external electrodes 22 and 23, and the reflective layer 24 are obtained. By this firing, the green sheets GS1 to GS3 in the green body GL1 become varistor layers. The electrode portion EL <b> 1 becomes the first internal electrode 31. The electrode portion EL <b> 2 becomes the second internal electrode 41. Note that alkali metal (for example, Li, Na, etc.) may be diffused from the surface of the varistor element body 21 after firing.

  After forming the varistor element body 21, the first external electrodes 22 and 23, and the reflective layer 24 in this manner, the second external electrodes 25 to 28 are formed on the first external electrodes 22 and 23. (Step S108). Here, the second external electrodes 25 to 28 are formed by vapor-depositing Au in the central portions of the openings 24 a to 24 d of the reflective layer 24 using a vacuum plating method. Through the above process, the multilayer chip varistor 11 in which the reflective layer 24 is formed is obtained.

  Next, the configuration of the semiconductor light emitting element 1 will be described with reference to FIGS. 4 and 5.

  The semiconductor light-emitting element 1 is a light-emitting diode (LED) of a GaN (gallium nitride) semiconductor, and includes a substrate 2 and a layer structure LS formed on the substrate 2. GaN-based semiconductor LEDs are well known and will be described briefly. The substrate 2 is an optically transparent and electrically insulating substrate made of sapphire. The layer structure LS includes an n-type (first conductivity type) semiconductor region 3, a light emitting layer 4, and a p-type (second conductivity type) semiconductor region 5 which are stacked. The semiconductor light emitting element 1 emits light according to a voltage applied between the n-type semiconductor region 3 and the p-type semiconductor region 5.

  The n-type semiconductor region 3 includes an n-type nitride semiconductor. In this embodiment, the n-type semiconductor region 3 is formed by epitaxially growing GaN on the substrate 2 and has an n-type conductivity by adding an n-type dopant such as Si. Further, the n-type semiconductor region 3 may have a composition such that the refractive index is smaller than that of the light emitting layer 4 and the band gap is increased. In this case, the n-type semiconductor region 3 serves as a lower cladding for the light emitting layer 4.

  The light emitting layer 4 is formed on the n-type semiconductor region 3, and carriers (electrons and holes) supplied from the n-type semiconductor region 3 and the p-type semiconductor region 5 are recombined to emit light in the light-emitting region. Is generated. The light emitting layer 4 can have, for example, a multiple quantum well (MQW) structure in which barrier layers and well layers are alternately stacked over a plurality of periods. In this case, the barrier layer and the well layer are made of InGaN, and the band gap of the barrier layer is configured to be larger than the band gap of the well layer by appropriately selecting the composition of In (indium). The light emitting region is generated in a region where carriers are injected in the light emitting layer 4.

  The p-type semiconductor region 5 includes a p-type nitride semiconductor. In the present embodiment, the p-type semiconductor region 5 is formed by epitaxially growing AlGaN on the light emitting layer 4 and has p-type conductivity by adding a p-type dopant such as Mg. The p-type semiconductor region 5 may have a composition that has a refractive index smaller than that of the light emitting layer 4 and a larger band gap. In this case, the p-type semiconductor region 5 serves as an upper cladding for the light emitting layer 4.

  A cathode electrode 6 is formed on the n-type semiconductor region 3. The cathode electrode 6 is made of a conductive material and realizes ohmic contact with the n-type semiconductor region 3. An anode electrode 7 is formed on the p-type semiconductor region 5. The anode electrode 7 is made of a conductive material, and has an ohmic contact with the p-type semiconductor region 5. Bump electrodes 8 are formed on the cathode electrode 6 and the anode electrode 7.

  In the semiconductor light emitting device 1 having the above-described configuration, when a predetermined voltage is applied between the anode electrode 7 (bump electrode 8) and the cathode electrode 6 (bump electrode 8) and a current flows, the light emitting region 4 emits light. Generate light. This light is reflected by the reflective layer 24.

  The semiconductor light emitting element 1 is flip-chip bonded to a pair of second external electrodes 27 and 28. That is, the cathode electrode 6 is electrically and physically connected to the second external electrode 28 via the bump electrode 8. As described above, by connecting via the bump electrodes 8, the semiconductor light emitting element 1 can be disposed on the multilayer chip varistor 11 without providing a support member for supporting the semiconductor light emitting element 1. The anode electrode 7 is electrically and physically connected to the second external electrode 27 through the bump electrode 8. Thereby, the varistor part comprised by the 1st electrode part 33, the 1st electrode part 43, and the area | region which overlaps with the 1st electrode parts 33 and 43 in a varistor layer is connected to the semiconductor light emitting element 1 in parallel. It will be. Therefore, the semiconductor light emitting element 1 can be protected from the ESD surge. Further, the heat generated in the semiconductor light emitting element 1 is mainly transmitted to the external electrodes 27 and 28 and the internal electrodes 31 and 41 to be dissipated. The heat radiation path of the heat generated in the semiconductor light emitting element 1 is expanded, and the heat generated in the semiconductor light emitting element 1 can be efficiently dissipated.

  When heat is generated in the semiconductor light emitting device 1, light is generated from the light emitting region of the light emitting layer 4. This light is emitted outward from the semiconductor light emitting element 1. Of the emitted light, the light toward the multilayer chip varistor 11 is reflected by the reflection layer 24 formed on the multilayer chip varistor 11. As a result, reflected light is generated. By generating the reflected light in this way, the light emission efficiency can be improved.

  As described above, according to the first embodiment, since the reflective layer 24 is provided, the light generated by the semiconductor light emitting element 1 can be reflected by the reflective layer 24. Since the reflective layer 24 is formed between the multilayer chip varistor 11 and the semiconductor light emitting device 1, it is not necessary to secure a special space for installing the reflective layer 24 around the semiconductor light emitting device 1. Therefore, the light emitting device LE1 can be reduced in size.

  By the way, in the device in which the semiconductor light emitting element is arranged on the multilayer chip varistor 11 like the light emitting device LE1 in the first embodiment, a part of the light generated by the semiconductor light emitting element is directed toward the multilayer chip varistor. It will go on. When light traveling in this direction is blocked by the multilayer chip varistor, the light emission efficiency is deteriorated. In the present embodiment, since the reflective layer is disposed between the multilayer chip varistor and the semiconductor light emitting element, light traveling in the direction of the multilayer chip varistor can be reliably reflected. Therefore, high luminous efficiency can be obtained.

  In the first embodiment, the reflective layer 24 is formed on the surface of the multilayer chip varistor 11 facing the semiconductor light emitting element 1, that is, on the main surface 21 a of the varistor element body 21. Thereby, the reflective layer 24 and the multilayer chip varistor 11 can be integrally formed. As a result, the semiconductor light-emitting device LE1 can be easily assembled since the semiconductor light-emitting element 1 has only to be disposed on the reflection layer 24 and the multilayer chip varistor 11 integrated.

  In the first embodiment, the reflective layer 24 includes glass and Ag. By including Ag, the reflection layer 24 can have excellent reflection characteristics particularly with respect to light having a wavelength of about 450 nm. As a result, the reflection efficiency of the reflective layer 24 can be further increased. Since glass is included, the reflective layer 24 can be made excellent in electrical insulation and heat resistance.

  In the first embodiment, the semiconductor light emitting element 1 is flip-chip bonded onto the multilayer chip varistor 11. In this case, the semiconductor light emitting element 1 can be disposed on the multilayer chip varistor 11 without providing a support member or the like for supporting the semiconductor light emitting element 1. As a result, further miniaturization becomes possible.

  The light emitting device LE1 is preferably installed on the heat sink 53 as shown in FIG. FIG. 9A is a schematic top view showing a state in which the light emitting device according to the first embodiment is installed. FIG. 9B is a diagram for explaining a cross-sectional configuration along the line IX-IX in FIG. The heat sink 53 has a recess. The recessed chip varistor 11 is accommodated in the recess. The heat sink 53 has external electrodes 55 and 56. The second external electrode 25 of the multilayer chip varistor 11 accommodated in the recess is connected to the external electrode 55 of the heat sink 53 by wire. The second external electrode 26 of the multilayer chip varistor 11 is wire-connected to the external electrode 56 of the heat sink 53. The second external electrodes 25 and 26 of the multilayer chip varistor 11 are electrically connected to an external circuit or the like via the external electrodes 55 and 56 of the heat sink 53. Thus, by installing the light emitting device LE1 on the heat sink 53, the heat generated in the semiconductor light emitting element 1 of the light emitting device LE1 can be dissipated to the heat sink 53 via the multilayer chip varistor 11.

  (Second Embodiment)

  With reference to FIG. 10, the structure of light-emitting device LE2 which concerns on 2nd Embodiment is demonstrated. FIG. 10 is a diagram for explaining a cross-sectional configuration of the light emitting device according to the second embodiment. The light emitting device LE2 according to the second embodiment is different from the light emitting device LE1 according to the first embodiment with respect to the position of the reflective layer, the configuration of the multilayer chip varistor, and the configuration of the light emitting element.

  As shown in FIG. 10, the light emitting device LE2 includes a semiconductor light emitting element 60 and a multilayer chip varistor 70. The semiconductor light emitting device 60 is wire bonded on the multilayer chip varistor 70.

  The multilayer chip varistor 11 includes a varistor element body 21, first external electrodes 22 and 23 formed on the varistor element body 21, and a second external electrode formed on the first external electrodes 22 and 23, respectively. External electrodes 25 to 28 are provided.

  The multilayer chip varistor 11 includes an insulating layer 71. The insulating layer 71 has the same shape as the reflective layer 24 in the light emitting device LE1 according to the first embodiment. That is, the insulating layer 71 is formed so as to cover the main surface 21 a of the varistor element body 21 provided in the multilayer chip varistor 11. The insulating layer 71 is formed on the first external electrodes 22 and 23, and has openings 71a to 71d at portions where the second external electrodes 25 to 28 are disposed. The first external electrode 22 is exposed from the openings 71a and 71c, and the first external electrode 23 is exposed from the openings 71b and 71d. The openings 71a to 71d are larger than the second external electrodes 25 to 28, and the second external electrodes 25 to 28 are disposed at the centers of the openings 71a to 71d.

  The semiconductor light emitting element 60 includes a substrate 2 and a layer structure LS formed on the substrate 2 in the same manner as the semiconductor light emitting element 1 of the light emitting device LE1 according to the first embodiment. The layer structure LS includes an n-type (first conductivity type) semiconductor region 3, a light emitting layer 4, and a p-type (second conductivity type) semiconductor region 5 which are stacked. A cathode electrode 6 is formed on the n-type semiconductor region 3. An anode electrode 7 is formed on the p-type semiconductor region 5.

  The semiconductor light emitting device 60 is different from the semiconductor light emitting device 1 of the light emitting device LE1 according to the first embodiment in that the semiconductor light emitting device 60 does not include the bump electrodes 7 and 8. The semiconductor light emitting device 60 that does not include the bump electrodes is wire-bonded to the pair of second external electrodes 27 and 28. That is, the cathode electrode 6 is electrically and physically connected to the second external electrode 28 via the wire 65. The anode electrode 7 is electrically and physically connected to the second external electrode 27 via a wire 66.

A reflective layer 61 is formed on the surface 60 a of the semiconductor light emitting device 60 that faces the multilayer chip varistor 70. The reflective layer 61 is formed so as to cover the main surface 60 a of the semiconductor light emitting element 60. The reflective layer 61 includes glass and Al ₂ O ₃ . The reflective layer 61 containing Al ₂ O ₃ that is a metal oxide can efficiently reflect the light generated by the semiconductor light emitting element 60. Moreover, it is excellent also in electrical insulation. Furthermore, since the thermal expansion coefficient is small as compared with the case containing metal, distortion, cracking, and cracking are less likely to occur. Therefore, the semiconductor light emitting element 60 can be protected by providing the reflective layer 61. Since Al ₂ O ₃ has good dispersibility in glass, the reflective layer 61 in which Al ₂ O ₃ is uniformly dispersed can be easily formed.

  According to the second embodiment having the above-described configuration, the reflective layer 61 is formed on the surface of the semiconductor light emitting device 60 facing the stacked chip varistor 70, that is, on the main surface 60 a of the semiconductor light emitting device 60. As a result, the light traveling toward the multilayer chip varistor 70 out of the light emitted from the semiconductor light emitting element 60 can be reliably reflected by the reflective layer 61. Therefore, high luminous efficiency can be obtained. In addition, by forming the reflective layer 61 at such a position, a special space for installing the reflective layer 61 around the semiconductor light emitting element 60 becomes unnecessary. Therefore, the light emitting device LE2 can be downsized. Furthermore, since the reflective layer 61 and the semiconductor light emitting element 60 are integrally formed, the light emitting device LE2 can be easily assembled.

  In the second embodiment, the semiconductor light emitting device 60 is wire-bonded on the multilayer chip varistor 70. In this case, since the semiconductor light emitting element 60 can be disposed on the multilayer chip varistor 70 without providing a support member for supporting the semiconductor light emitting element 60, the light emitting device LE2 can be further reduced in size. .

  The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to these embodiments.

  For example, in the above-described embodiment, the varistor element body 21 includes the plurality of internal electrodes 31 and 41, but is not limited thereto. For example, one each of the first internal electrode 31 and the second internal electrode 41 may be provided.

  Moreover, although the GaN-type semiconductor LED is used as the semiconductor light emitting elements 1 and 60, it is not limited to this. As the semiconductor light emitting devices 1 and 60, for example, a nitride semiconductor LED other than a GaN-based semiconductor (for example, an InGaNAs semiconductor LED), a compound semiconductor LED other than a nitride-based semiconductor, or a laser diode (LD) is used. Also good. The configuration of the multilayer chip varistors 11 and 70 is not limited to that of the above embodiment.

1 is a schematic top view showing a light emitting device LE1 according to a first embodiment. 1 is a schematic perspective view showing a multilayer chip varistor included in a light emitting device LE1 according to a first embodiment. 1 is a schematic top view showing a multilayer chip varistor according to a first embodiment. It is a figure for demonstrating the cross-sectional structure along the IV-IV line in FIG. It is a figure for demonstrating the cross-sectional structure along the VV line | wire in FIG. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor and reflective layer which concern on 1st Embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor and reflective layer which concern on 1st Embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor and reflective layer which concern on 1st Embodiment. It is a figure which shows the state which installed the light-emitting device which concerns on 1st Embodiment. It is a figure for demonstrating the cross-sectional structure of the light-emitting device which concerns on 2nd Embodiment.

Explanation of symbols

  LE1, LE2 ... light emitting device, 1,60 ... semiconductor light emitting element, 11,70 ... multilayer chip varistor, 21 ... varistor element body, 22,23 ... first external electrode, 25-28 ... 2nd external electrode, 24, 61 ... reflective layer, 31, 41 ... internal electrode.

Claims (14)

A multilayer body having a varistor layer and a plurality of internal electrodes arranged so as to sandwich the varistor layer, and formed on the outer surface of the multilayer body, and corresponding internal electrodes among the plurality of internal electrodes, respectively. A multilayer chip varistor having a plurality of external electrodes to be connected;
A semiconductor light emitting device disposed on the multilayer chip varistor and connected to the plurality of external electrodes so as to be connected in parallel to the multilayer chip varistor;
A reflective layer disposed between the multilayer chip varistor and the semiconductor light emitting device and reflecting light generated by the semiconductor light emitting device;
A light emitting device comprising:   The light emitting device according to claim 1, wherein the reflective layer includes glass and metal.   The light emitting device according to claim 1, wherein the reflective layer includes a resin and a metal.   The light emitting device according to claim 1, wherein the reflective layer includes glass and a metal oxide.   The light emitting device according to claim 1, wherein the reflective layer includes a resin and a metal oxide.   The light emitting device according to claim 1, wherein the reflective layer includes glass and metal powder, and the metal powder is coated with a metal oxide.   The light emitting device according to claim 1, wherein the reflective layer includes a resin and a metal powder, and the metal powder is coated with a metal oxide.   The light emitting device according to claim 1, wherein the reflective layer includes a thin film layer made of a metal.   9. The light emitting device according to claim 2, wherein the reflective layer includes at least one of Ag, Al, Ti, and Ni as the metal. .   The reflective layer includes at least one of silicone resin, polytetrafluoroethylene, polyethylene terephthalate, and xylene resin as the resin, according to any one of claims 3, 5, and 7. The light-emitting device of description. The reflective layer includes at least one of Al ₂ O ₃ , TiO ₂ , SiO ₂ , and ZrO ₂ as the metal oxide. A light-emitting device according to claim 1.   The light emitting device according to claim 1, wherein the reflective layer is formed on a surface of the multilayer chip varistor facing the semiconductor light emitting element.   The light emitting device according to claim 1, wherein the reflective layer is formed on a surface of the semiconductor light emitting element that faces the stacked chip varistor.   The light emitting device according to claim 1, wherein the semiconductor light emitting element is flip chip bonded or wire bonded on the multilayer chip varistor.

Images