JP2007103417A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where substrate noise can inexpensively be reduced without using an expensive substrate of SOI and the like and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device is provided with a high resistance silicone substrate 1 having high resistivity of 500 Ωcm or above, which is formed by a floating zone method, a silicone epitaxial layer 4 formed on the high resistance silicone substrate 1 and a deep trench structure 50 arranged from above the silicone epitaxial layer 4 to an inner part of the high resistance silicone substrate 1. The deep trench structure 50 separates an analog circuit part and a digital circuit part. Noise transmitted through a surface of the substrate can be suppressed by the deep trench structure 50, and noise transmitted through a deep part of the substrate by resistance of the substrate itself. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, can reduce substrate noise at low cost without using an expensive substrate such as SOI.

  In the case of a semiconductor device in which digital and analog circuits are mixed, for example, the potential of the substrate changes due to a change in current flowing in the digital portion. Usually, since the substrate resistance of a semiconductor device is several Ωcm to 20 Ωcm, a change in potential is transmitted through the substrate, which affects the substrate potential of the analog circuit portion and fluctuates the threshold value of the transistor. This is substrate noise. As these measures, the following methods have been studied.

FIG. 13 is a cross-sectional view illustrating a substrate noise reduction method according to Conventional Example 1. As shown in FIG. 13, in this substrate separation method, the substrate potential fluctuation can be suppressed by the P-type guard ring 19 provided around the analog circuit portion.
FIG. 14 is a cross-sectional view illustrating a substrate noise reduction method according to Conventional Example 2. As shown in FIG. 14, in this substrate separation method, a deep trench is formed in a silicon substrate formed by the Czochralski method (hereinafter referred to as “CZ method”), and an insulation such as a silicon oxide film is formed in the trench. The deep trench 20 is formed by filling the material amount. The propagation of noise can be suppressed by increasing the resistance of the substrate surface by the deep trench 20.

FIG. 15 is a cross-sectional view illustrating a substrate noise reduction method according to Conventional Example 3. As shown in FIG. 15, in this substrate isolation method, the lateral direction (that is, horizontal direction) of the substrate is separated by the deep trench 20, and the vertical direction (that is, depth direction) of the substrate is the buried insulating film of the SOI substrate. 21. That is, since individual circuits can be completely separated by an insulating film, noise transmitted through the substrate can be suppressed.
In addition, there is a method in which a high resistivity substrate is used instead of an SOI substrate or the like, and noise transmitted through a deep portion of the substrate is suppressed (for example, see Patent Document 1).
JP 2000-269225 A

  The method shown in FIG. 13 is effective for noise transmitted near the surface of the substrate. However, since the depth of the P + guard ring 19 is less than 1% of the wafer thickness, it is transmitted through a deep portion of the substrate. There has been a problem that noise has almost no reduction effect. Further, depending on the fluctuation of the potential on the substrate surface, the P + guard ring 19 may be a noise source. Therefore, the effect is insufficient as a noise reduction method.

In addition, in the method shown in FIG. 14, since the insulating property near the substrate surface is enhanced by the deep trench 20, there is an effect in reducing the noise near the substrate surface, but the noise transmitted deeper than the trench of the substrate is transmitted. Could not be suppressed.
Further, in the method shown in FIG. 15, as described above, each circuit can be completely separated by an insulating film, so that noise transmitted through the substrate can be suppressed. However, since the substrate itself is very expensive, there is a problem that the cost is increased.

In general, in the manufacturing process of a semiconductor device, the thermal diffusion temperature at the time of well formation is as high as about 1100 ° C., and there is a problem that the substrate slips and the device becomes defective. The substrate is used. This is because, in the manufacturing process of the CZ substrate, dissolved oxygen in the substrate is precipitated by heat treatment at a high temperature of 1000 ° C. or higher, and this increases resistance to thermal stress of the substrate, so that slip hardly occurs. However, in the case of a substrate prepared by the conventional CZ method, the dissolved oxygen in the substrate is as large as 1e18-2e18 atoms / cm ^ 3, and it acts as a donor, so that the resistance of the substrate is low even if the resistance is increased. There was also a problem of not going up. If the substrate resistance is not sufficiently high, noise transmitted through a deep portion of the substrate cannot be sufficiently suppressed.
Accordingly, the present invention has been made in view of such circumstances, and provides a semiconductor device and a method for manufacturing the same that can reduce substrate noise at low cost without using an expensive substrate such as SOI. Objective.

  In order to solve the above-described problems, a semiconductor device according to a first aspect of the present invention includes a silicon substrate having a resistivity of 500 Ωcm or higher, formed by a floating zone method, a silicon epitaxial layer formed on the silicon substrate, A deep trench structure provided from above the epitaxial layer to the inside of the silicon substrate, wherein the analog circuit portion and the digital circuit portion are separated by the deep trench structure.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising an impurity layer at an interface between the silicon substrate and the silicon epitaxial layer, wherein the impurity concentration of the silicon epitaxial layer is 5e14 atoms / cm ^ 3 or more. The impurity concentration of the impurity layer is 5e15 atoms / cm 3 or more and 1e17 atoms / cm 3 or less.
A semiconductor device according to a third aspect of the invention is the semiconductor device according to the first or second aspect of the invention, wherein the thickness of the silicon epitaxial layer is not less than 1 μm and not more than 5 μm.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a silicon oxide film on a silicon substrate having a resistivity of 500 Ωcm or more created by a floating zone method; and forming an interface between the silicon substrate and the silicon oxide film. A step of ion-implanting a predetermined impurity to form an impurity layer; a step of removing the silicon oxide film; and then forming a silicon epitaxial layer on the impurity layer; the silicon epitaxial layer; the impurity layer; Selectively etching each of the silicon substrates to form a deep trench structure extending from the silicon epitaxial layer to the inside of the silicon substrate; and forming a field insulating film on the deep trench structure; Isolate the silicon epitaxial layer and its upper part into one region and another region A step, said forming an analog circuit portion on one of the regions, it is characterized in that it comprises a step of forming a digital circuit portion in the other region.

A method for manufacturing a semiconductor device according to a fifth aspect is characterized in that, in the method for manufacturing a semiconductor device according to the fourth aspect, a maximum temperature of heat treatment for the silicon substrate is set to 1000 ° C. or less.
A method for manufacturing a semiconductor device according to a sixth aspect is the method for manufacturing a semiconductor device according to the fourth or fifth aspect, wherein the dose of the impurity in the step of forming the impurity layer is greater than the dose of the impurity to the silicon epitaxial layer. It is characterized by many.

  According to the present invention, it is not necessary to use an expensive substrate such as SOI, and it is not necessary to change the circuit design from that of the conventional CMOS, so that a device with low substrate noise can be realized at low cost. Further, noise transmitted through the substrate surface can be suppressed by a deep trench structure, and noise transmitted through a deep portion of the substrate can be suppressed by resistance of the substrate itself.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
(1) Example FIGS. 1-8 is sectional drawing which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. As shown in FIG. 1, in this embodiment, a wet zone is formed on an N-type or P-type high-resistance silicon substrate 1 formed by a floating zone method (hereinafter referred to as “FZ method”) having a resistivity of 1000 Ωcm or more. A silicon oxide film 2 having a thickness of 150 Å is formed at 850 ° C. in an atmosphere.

  Here, the FZ method is a method in which cylindrical polycrystalline silicon is held upright, a part thereof is melted by high-frequency heating, and is moved in a high-frequency coil to be sequentially single-crystallized from one end of the rod. is there. In order to obtain a desired resistivity, doping of impurities such as boron and phosphorus is performed, but in order to produce a high resistance silicon substrate having a resistivity of 1000 Ωcm or more, these dopings are not performed. In order to further increase the resistance, it is necessary to increase the purity of polysilicon as a raw material. The resistivity of the high-resistance silicon substrate 1 is preferably 500 Ωcm or more for the purpose of suppressing transmission of substrate noise, and the higher the resistivity, the more effective. The reason for forming the silicon oxide film 2 is to prevent damage to the substrate during the next ion implantation.

Next, as shown in FIG. 2, a P-type impurity (dopant) such as boron (B +) is ion-implanted near the upper surface of the high-resistance silicon substrate 1 at a dose of 1e12 to 5e12 atoms / cm 2. As a result, a P-type impurity layer 3 having an impurity concentration of about 1e16 atoms / cm 3 is formed at the interface between the high-resistance silicon substrate 1 and the silicon oxide film 2.
Next, after removing the silicon oxide film 2 with hydrogen fluoride water, as shown in FIG. 3, a P-type epitaxial silicon layer 4 doped with boron having a thickness of 1.3 μm and a resistivity of 10 Ωcm is formed. In this embodiment, the epitaxial silicon layer 4 is formed thick enough to prevent leakage between wells. The boron doping amount (dose amount) with respect to the epitaxial silicon layer 4 is smaller than the dose amount with respect to the P-type impurity layer 3, and the impurity concentration of the epitaxial silicon layer 4 is, for example, about 1e15 atoms / cm ^ 3. However, when the epitaxial silicon layer 4 is formed, boron, which is an impurity, diffuses into the high-resistance silicon substrate 1, so that the impurity concentration is greatly reduced near the interface of the substrate 1.

  Here, when there is no P-type impurity layer 3 between the high-resistance silicon substrate 1 and the epitaxial silicon layer 4, when a bias is applied to the N-type well, the depletion layer increases from the N-type well toward the epitaxial silicon layer 4. It spreads and leaks between adjacent N-type wells. However, in this embodiment, since the P-type impurity layer 3 exists between the high-resistance silicon substrate 1 and the epitaxial silicon layer 4, the spread of the depletion layer can be suppressed.

  Next, a deep trench structure extending from the epitaxial silicon layer 4 to the inside of the high resistance silicon substrate 1 is formed. That is, first, in FIG. 4, the epitaxial silicon layer 4, the P-type impurity layer 3, and the high-resistance silicon substrate 1 are selectively anisotropically etched in this order, so that the high-resistance silicon is formed on the epitaxial silicon layer 4. A deep trench 5 reaching the inside of the substrate 1 is formed. For this anisotropic etching, a mixed gas containing SF6 and oxygen is used. The size of the deep trench 5 is, for example, a width of 0.6 μm and a depth of 7 μm.

Next, as shown in FIG. 5, a silicon oxide film 6 having a thickness of 400 to 2000 mm is formed on the side surface of the deep trench 5. The silicon oxide film 6 is formed by wet oxidation at, for example, 950 ° C. to 1000 ° C. Then, polysilicon 7 is filled into the deep trench 5 whose inner wall surface and bottom surface are thinly covered with the silicon oxide film 6. The filling of the polysilicon 7 is performed by depositing a polysilicon film on the entire upper surface of the high resistance silicon substrate 1 by a low pressure CVD method, and then polishing and removing the polysilicon film deposited on the entire surface by a CMP method. By this polishing and removal, the polysilicon film is left only in the deep trench 5. In this manner, a deep trench structure 50 composed of the deep trench 5 and the silicon oxide film 6 and polysilicon 7 formed therein is completed.
The film filled in the deep trench 5 is not limited to polysilicon, and may be a silicon oxide film formed by, for example, a CVD method.

  Further, in this embodiment, the case where four deep trenches 5 are formed at an interval of about 1 μm between elements to be separated has been shown. The reason for forming a plurality of deep trenches 5 is that This is to increase the insulation between the sandwiched sides. Regarding the deep trench 5, the preferred number is 3 or more for the purpose of suppressing a minute current flowing along the interface between the deep trench 5 and the substrate 1, and 10 or less for the reason of suppressing an increase in the area of the device. . Moreover, the preferable space | interval of a trench is 0.5 um or more for the reason of suppressing the stress to the board | substrate by the deep trench 5, and is 3 um or less for the reason of improving insulation. Further, the reason why the deep trench 5 is formed so as to reach the silicon substrate 1 deeper than the epitaxial silicon layer 4 and the P-type impurity layer 3 is that the substrate noise transmitted through the low resistance layer (ie, the epitaxial silicon layer 4) near the substrate surface. This is because the resistance of the deep trench structure 50 is suppressed.

  Next, as shown in FIG. 6, the surface of the epitaxial silicon layer 4 is oxidized in a wet atmosphere at 850 ° C. to form a silicon oxide film 8 having a thickness of 150 μm. Further, a silicon nitride film 9 having a thickness of 1500 mm is formed by low pressure CVD. Then, after patterning with the photoresist film 10, the silicon nitride film 9 is etched. By this selective etching, the silicon nitride film 9 is left only in the element region.

  Next, the silicon nitride film 9 is used as a mask to oxidize the epitaxial silicon layer 4 in a wet atmosphere at 1000 ° C. Thereby, as shown in FIG. 7, a field insulating film 11 of, eg, 3000 mm is formed. Here, the reason why the temperature of the oxidation treatment is set to 1000 ° C. is to give the silicon oxide film a viscous flow, and the stress at the end of the field insulating film 11 can be relieved by this viscous flow.

  Subsequently, boron (B +) is first ion-implanted into the epitaxial silicon layer 4 at 150 keV to 300 keV and then at 50 keV to 100 keV to form the P-type well 13 as shown in FIG. Also, before and after the formation of the P-type well 13, phosphorus (P +) is ion-implanted into the epitaxial silicon layer 4 at 250 keV to 400 keV first and then at 20 keV to 200 keV to form the N-type well 12. Usually, the well is formed by performing ion implantation with an acceleration energy of about 100 keV and then annealing at a temperature of 1100 ° C. or higher (that is, the highest temperature throughout the entire manufacturing process) and diffusing to a depth of about 1 μm. However, in this embodiment, since ion implantation is performed with high acceleration energy to form a well, annealing is not necessary.

  Finally, as shown in FIG. 9, a gate oxide film 14, a polysilicon gate 15, and a source / drain 16 for forming a CMOS transistor in a wet atmosphere at 850 ° C. are formed, a polysilicon resistor 17, a metal / insulation Passive elements such as a film / metal capacitor 18 are formed. As shown in FIG. 9, in this embodiment, an analog circuit portion is formed in the left region (one region) of FIG. 9 with the deep trench structure 50 interposed therebetween, and the digital region is formed in the right region (other region). A circuit part is formed. That is, the analog circuit portion and the digital circuit portion are separated by the deep trench structure 50. In this way, the semiconductor device 100 is completed.

  FIG. 12 is a diagram showing an A-A ′ part impurity profile in FIG. 9. The horizontal axis (X axis) in FIG. 12 indicates the depth in the substrate of the semiconductor device 100, and the vertical axis (Y axis) indicates the impurity concentration. 0 on the X axis indicates the surface of the original high-resistance silicon substrate. The minus side of the X axis is the surface direction of the substrate. PHOS (phosphorus) is an N-type dopant and BORON (boron) is a P-type dopant, and the higher the concentration, the substrate type. The source / drain of the PMOS, the N-type well, the P-type epitaxial silicon layer, and the N-type high resistance substrate from the surface side of the substrate, and the impurity concentration of the original N-type high resistance substrate is 1e12 atoms / cm ^ 3 The impurity concentration of the layer is 1e15 atoms / cm 3, and the P-type impurity layer is formed with a width of about 1 μm therebetween.

  According to the semiconductor device 100, the P-type impurity layer can suppress the expansion of the depletion layer between the N-type well and the P-type epitaxial silicon layer, and can prevent leakage between adjacent N-type wells. In order to suppress the expansion of the depletion layer, the impurity concentration of the P-type impurity layer is preferably 5e15 atoms / cm 3 or more and the thickness is 0.4 μm or more. Further, for the reason that the threshold value of the CMOS is not affected, it is preferable that the impurity concentration of the P-type impurity layer is 1e17 atoms / cm 3 or less and the thickness is 0.8 μm or less.

  Furthermore, the impurity concentration of the P-type epitaxial silicon layer is preferably 5e14 atoms / cm ^ 3 or more and 5e15 atoms / cm ^ 3 or less because of the leak between wells and the ease of forming wells. The thickness of the P-type epitaxial silicon layer is preferably 1 μm or more for the reason that a CMOS well is formed, so that it does not become deeper than the deep trench (that is, the deep trench extends to the inside of the high-resistance silicon substrate). It is preferably 5 μm or less for the reason that it can be easily reached.

  As described above, according to the embodiment of the present invention, the crosstalk noise transmitted through the substrate by the combination of the high resistance silicon substrate 1, the low resistance epitaxial silicon layer 4 forming the transistor and the deep trench structure 50. There is an effect of reducing. Further, in the high resistance silicon substrate 1 produced by the FZ method, oxygen precipitation does not occur and slip may easily occur due to stress during heat treatment. By setting the temperature in the furnace body (that is, the heat treatment temperature for the high-resistance silicon substrate 1) to 1000 ° C. or less at maximum, device formation without slipping can be realized.

In this embodiment, the P-type impurity layer 3 corresponds to the “impurity layer” of the present invention, and the deep trench structure 50 corresponds to the “deep trench structure” of the present invention.
In this embodiment, the case where a substrate having a resistivity of 500 Ωcm or more prepared by the FZ method is used as the high resistance silicon substrate 1 has been described. However, in the present invention, instead of the high-resistance FZ substrate, a substrate prepared by the CZ method having an equivalent resistivity and subjected to appropriate annealing treatment to precipitate dissolved oxygen in the substrate may be used. good. Even with such a configuration, there is an effect of reducing crosstalk noise transmitted through the substrate.

(2) Verification and Results FIG. 10 shows the results of measuring the crosstalk noise reduction effect using the semiconductor device (device) formed as described above. The horizontal axis (X axis) in FIG. 10 indicates the frequency of the input signal, and the vertical axis (Y axis) indicates the amount of signal attenuation between the signal source side and the reception side. FIG. 11 shows a simple structure of the evaluated pattern. 10 and 11, (a) to (c) are conventional examples, and (d) is the present invention. In this verification, high frequency noise was input from the signal source side pad connected to the N-type diffusion layer with a network analyzer, and the attenuation amount of the noise was measured at the receiving side pad 150 μm away. A guard ring or deep trench with a P-type diffusion layer was placed around the receiving side pad, and the attenuation of crosstalk noise due to the difference in structure and the presence or absence of a high resistance substrate was compared.
As shown in FIG. 10, according to the combination (d) of the high resistance substrate and the deep trench, in the 1 GHz frequency band, the improvement is 50 dB or more compared with the conventional substrate only (a) and (c). As compared with the combination (b) of the conventional substrate and the deep trench, the effect was improved by 20 dB or more.

Sectional drawing which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention (the 1). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 2). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 3). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 4). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 5). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 6). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 7). Sectional drawing which shows the manufacturing method of the semiconductor device 100 (the 8). FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device 100 according to an embodiment of the present invention. Measurement figure of substrate noise, substrate noise reduction effect by presence or absence of deep trench. Sectional drawing which shows the simple structure of the pattern which evaluated. The A-A 'part impurity profile in FIG. Sectional drawing which shows the reduction method of the substrate noise which concerns on the prior art example 1. FIG. Sectional drawing which shows the reduction method of the substrate noise which concerns on the prior art example 2. FIG. Sectional drawing which shows the reduction method of the substrate noise which concerns on the prior art example 3. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High resistance silicon substrate 2, 6, 8 Silicon oxide film 3 P type impurity layer 4 (P type) epitaxial silicon layer 5 Deep trench 7 Polysilicon 9 Silicon nitride film 10 Photoresist film 11 Field insulating film 12 N type well 13 P Type well 14 gate oxide film 15 polysilicon gate 16 source / drain 17 polysilicon resistor 18 metal capacitor 50 deep trench structure 100 semiconductor device

Claims (6)

A silicon substrate having a resistivity of 500 Ωcm or more created by the floating zone method, a silicon epitaxial layer formed on the silicon substrate, and a deep trench provided from the silicon epitaxial layer to the inside of the silicon substrate A structure,
An analog circuit portion and a digital circuit portion are separated by the deep trench structure. An impurity layer is provided at the interface between the silicon substrate and the silicon epitaxial layer,
The impurity concentration of the silicon epitaxial layer is 5e14 atoms / cm ^ 3 or more and 5e15 atoms / cm ^ 3 or less,
2. The semiconductor device according to claim 1, wherein an impurity concentration of the impurity layer is 5e15 atoms / cm 3 or more and 1e17 atoms / cm 3 or less.   The semiconductor device according to claim 1, wherein the silicon epitaxial layer has a thickness of 1 μm or more and 5 μm or less. Forming a silicon oxide film on a silicon substrate having a resistivity of 500 Ωcm or more created by a floating zone method;
A step of ion-implanting a predetermined impurity at the interface between the silicon substrate and the silicon oxide film to form an impurity layer;
Removing the silicon oxide film, and then forming a silicon epitaxial layer on the impurity layer;
Selectively etching each of the silicon epitaxial layer, the impurity layer, and the silicon substrate to form a deep trench structure from the silicon epitaxial layer to the inside of the silicon substrate;
Forming a field insulating film on the deep trench structure and separating the silicon epitaxial layer and the upper portion thereof into one region and another region;
Forming an analog circuit portion in the one region and forming a digital circuit portion in the other region.   The method for manufacturing a semiconductor device according to claim 4, wherein a maximum temperature of the heat treatment for the silicon substrate is set to 1000 ° C. or less. The impurity dose in the step of forming the impurity layer is:
6. The method of manufacturing a semiconductor device according to claim 4, wherein the dose of impurities to the silicon epitaxial layer is larger than the dose amount of impurities.

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