JP6382288B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a groove and a manufacturing method thereof.

Element isolation with a high aspect ratio trench filled with an insulating film (Deep Trench Isolation: DTI)
The structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-118256.

  In the technique described in this publication, a groove is first formed on the surface of a semiconductor substrate, and then a first insulating film is formed on the surface of the semiconductor substrate so as to fill the groove. By anisotropically etching the first insulating film, an opening reaching the groove is formed in the first insulating film, and the upper corner portion of the opening of the first insulating film is the upper corner portion of the groove. The slope is gentler than that. Furthermore, the thickness of the first insulating film on the surface of the semiconductor substrate is reduced by the anisotropic etching. Thereafter, a second insulating film is formed on the surface of the semiconductor substrate so as to fill the opening.

  After the DTI structure is formed as described above, an electronic element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed on the semiconductor substrate.

JP 2002-118256 A

  In the above method, it is necessary to fill the trenches having a high aspect ratio with the first and second insulating films. For this reason, the insulating film is deposited twice and the anisotropic etching for expanding the upper end of the opening is required, and the flow time becomes long, and the processing time and cost are high.

  Further, if there is a hollow inside the groove, the hollow portion may be exposed on the substrate surface by the subsequent wet treatment. When the hollow portion inside the groove is exposed on the substrate surface, the resist material or the like enters the hollow portion from the exposed portion and cannot be removed. The resist material in the hollow portion is ejected in a later process and appears as a foreign substance, which causes a pattern defect.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that does not need to ensure high embeddability by a simple process and a method for manufacturing the same.

A manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps.
A MOS substrate having a structure in which a support substrate, a buried insulating film, and a semiconductor layer are stacked in this order is prepared, a gate electrode is provided on the semiconductor layer, and a source region and a drain region are provided in the semiconductor layer Is a manufacturing method. A trench surrounding the MOS transistor in plan view is formed so as to reach the buried insulating film from the semiconductor layer. A first insulating film covering the gate electrode and extending along the main surface of the semiconductor layer and filling the groove is formed so as to form a hollow in the groove.
First, a semiconductor substrate having a configuration in which a support substrate, a buried insulating film, and a semiconductor layer are stacked in this order is prepared. An element having a conductive portion on the main surface of the semiconductor layer is completed. A groove surrounding the element in plan view is formed so as to reach the buried insulating film from the main surface of the semiconductor layer. A first insulating film is formed on the element and in the groove so as to cover the element and to form a hollow in the groove. A hole reaching the conductive portion of the element is formed in the first insulating film.

  According to this embodiment, the groove is formed after the element is completed. For this reason, resist or the like does not enter the groove during the formation of the element. Therefore, it is possible to realize a semiconductor device and a method for manufacturing the same that do not require a high embedding property with a simple process.

  Further, the semiconductor substrate has a laminated structure of a support substrate, a buried insulating film, and a semiconductor layer, and the groove is formed so as to reach the buried insulating film from the main surface of the semiconductor layer. For this reason, the separation capability can be increased.

1 is a schematic plan view showing a configuration of a semiconductor device in a chip state according to a first embodiment of the present invention. It is a partially broken perspective view which shows a mode that the element formation area shown in FIG. 1 was surrounded by the groove | channel in planar view. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the structure of TEG for evaluation which investigates the characteristic of a semiconductor device. It is a graph which shows the relationship between the width | variety of the groove | channel of a DTI structure, and the pressure | voltage resistance of the said groove | channel. It is a schematic plan view which shows the structure of TEG in which the sheet resistance extended in the direction parallel to the direction where a groove | channel is extended was formed. It is a schematic sectional drawing in the part which follows the XVI-XVI line | wire of FIG. It is a schematic plan view which shows the structure of TEG in which the sheet resistance extended in the direction orthogonal to the direction where a groove | channel is extended was formed. It is a schematic sectional drawing in the part which follows the XVIII-XVIII line of FIG. It is a schematic sectional drawing which shows the structure by which the gettering site was formed so that an element formation area might be surrounded using the semiconductor substrate of Embodiment 1 of this invention. FIG. 20 is a schematic cross-sectional view showing a configuration in which a field oxide film is formed on the semiconductor substrate of FIG. 19. FIG. 21 is a schematic cross-sectional view illustrating a configuration in which a groove is formed in the semiconductor substrate of FIG. 20. It is a schematic sectional view showing a state where a groove is formed in a bulk semiconductor substrate in which a buried insulating film is not formed and etching damage is formed on a side surface of the groove. It is a schematic sectional view showing a state where a groove is formed in a semiconductor substrate on which a buried insulating film is formed and etching damage is formed on a side surface of the groove. It is a schematic sectional drawing which shows the shape of the groove | channel of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the shape of the groove | channel of one example of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the shape of the groove | channel of the other example of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the structure of one example of the semiconductor device in Embodiment 2 of this invention. It is an expanded sectional view which expands and shows the groove part of FIG. It is a schematic sectional drawing which shows the structure of the other example of the semiconductor device in Embodiment 2 of this invention. It is an expanded sectional view which expands and shows the groove part of FIG. FIG. 3 is a schematic cross-sectional view showing a state after a groove (through hole) is formed in an upper layer of a semiconductor layer and before a groove is formed in the semiconductor layer. It is a schematic sectional drawing which shows the principle by which a semiconductor layer is etched. It is a schematic sectional drawing which shows the state after the semiconductor layer in FIG. 32 was etched. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width is 0.8 micrometer in the center part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width | variety is 0.9 micrometer in the center part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width | variety is 1.0 micrometer in the center part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width | variety is 1.1 micrometers in the center part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width is 0.8 micrometer in the peripheral part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width | variety is 0.9 micrometer in the peripheral part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width | variety is 1.0 micrometer in the peripheral part of a wafer. It is a photograph which shows the state of the cross section of the upper part of the groove | channel whose DTI width is 1.1 micrometers in the peripheral part of a wafer. It is a schematic sectional drawing for demonstrating the position of the dimension of the width of a groove | channel and the height of a hollow vertex shown to the graph of FIG. It is a graph which shows the relationship between the width | variety of a groove | channel, and the height of a hollow vertex. It is the photograph which shows the shape which looked at the hollow normally formed in the inside of a groove | channel from the cross section. It is a photograph which shows an example of the shape which looked at the hollow which formed in the inside of a groove | channel and the upper part expanded from the cross section. It is a photograph which shows the shape which the hollow upper part of FIG. 45 expanded further. It is a photograph which shows an example of the shape which looked at the thin film of aluminum formed in the upper part of the groove | channel by sputtering from the cross section. It is a photograph which shows an example of the shape which looked at the hollow deformation | transformation after removing the thin film of aluminum of the upper part of the groove | channel shown in FIG. FIG. 26 is a schematic cross-sectional view showing a configuration in which a groove similar to FIG. 25 is formed in a bulk semiconductor substrate SUB in which no buried insulating film BOX exists. FIG. 27 is a schematic cross-sectional view showing a configuration in which a groove similar to FIG. 26 is formed in a bulk semiconductor substrate SUB in which no buried insulating film BOX exists. It is a schematic sectional drawing which shows the structure of one example of the semiconductor device in Embodiment 2 of this invention formed using the bulk semiconductor substrate SUB in which the embedded insulating film BOX does not exist. It is an expanded sectional view which expands and shows the groove part of FIG. It is a schematic sectional drawing which shows the structure of the other example of the semiconductor device in Embodiment 2 of this invention formed using the bulk semiconductor substrate SUB in which the embedded insulating film BOX does not exist. It is an expanded sectional view which expands and shows the groove part of FIG. It is a schematic sectional drawing which shows the shape of the groove | channel of one example of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the shape of the groove | channel of the other example of the semiconductor device in Embodiment 3 of this invention. FIG. 56 is a view showing a configuration in which a groove similar to FIG. 55 is formed in a bulk semiconductor substrate SUB in which no buried insulating film BOX exists. FIG. 57 is a diagram showing a configuration in which a groove similar to FIG. 56 is formed in a bulk semiconductor substrate SUB in which no buried insulating film BOX exists. It is a schematic sectional drawing which shows the structure of one example of the semiconductor device in Embodiment 3 of this invention. FIG. 60 is an enlarged cross-sectional view showing the groove portion of FIG. 59 in an enlarged manner. It is a schematic sectional drawing which shows the structure of the other example of the semiconductor device in Embodiment 3 of this invention. FIG. 62 is an enlarged cross-sectional view showing a groove portion of FIG. 61 in an enlarged manner. It is a schematic sectional drawing which shows the structure of the example of the semiconductor device in Embodiment 3 of this invention formed using the bulk semiconductor substrate SUB in which the embedded insulating film BOX does not exist. FIG. 64 is an enlarged cross-sectional view showing the groove portion of FIG. 63 in an enlarged manner. It is a schematic sectional drawing which shows the structure of the other example of the semiconductor device in Embodiment 3 of this invention formed using the bulk semiconductor substrate SUB in which the buried insulating film BOX does not exist. FIG. 66 is an enlarged cross-sectional view showing the groove portion of FIG. 65 in an enlarged manner. In Embodiment 4 of this invention, it is a schematic sectional drawing for demonstrating thickening the interlayer insulation film on a hollow. FIG. 68 is a schematic cross sectional view for explaining a state in which an interlayer insulating film is further laminated on the interlayer insulating film of FIG. 67 in Embodiment 4 of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 4 of this invention. FIG. 70 is an enlarged cross-sectional view showing a groove portion of FIG. 69 in an enlarged manner. In Embodiment 5 of this invention, it is a schematic sectional drawing which shows the state by which the insulating film for element isolation (LOCOS) was formed in the area | region which forms a groove | channel. In Embodiment 5 of this invention, it is a schematic sectional drawing which shows the state in which the groove | channel was formed so that an insulating film for element isolation might be penetrated and it may reach a buried insulating film. In Embodiment 5 of this invention, it is a schematic sectional drawing which shows the state in which the interlayer insulation film was formed on the underlay oxide film and the inside of a groove | channel. In Embodiment 5 of this invention, it is the graph which shows the stress inside the element in which the insulating film for element separation was formed, and a schematic sectional drawing of the said element. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 5 of this invention. In Embodiment 6 of this invention, it is a schematic sectional drawing which shows the state in which the underlying oxide film, the underlying nitride film, and the mask material were formed in the area | region which forms a groove | channel. In Embodiment 6 of this invention, it is a schematic sectional drawing which shows the state of the groove | channel formed as a process following FIG. In Embodiment 7 of this invention, it is a schematic sectional drawing which shows the state of the side wall insulating film formed as a process following FIG. FIG. 79 is a schematic cross sectional view showing the state of the inside of the groove formed as a step following FIG. 78 in Embodiment 7 of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 7 of this invention. It is an expanded sectional view which expands and shows the groove part of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
Referring to FIG. 1, the semiconductor device of the present embodiment is applicable to, for example, a BiC-DMOS (Bipolar Complementary Double-diffused Metal Oxide Semiconductor). This BiC-DMOS semiconductor chip SCC has, for example, a logic unit in which low breakdown voltage CMOS (Complementary MOS) transistors are integrated and an output driver unit using a high breakdown voltage element. In the output driver section, the element formation region DFR, which is the formation region of each element, is surrounded by the trench DTR having the DTI structure in plan view. Further, the plurality of element formation regions DFR are surrounded by the gettering site GT in plan view.

  Referring to FIG. 2, for example, in the output driver section, each element formation region DFR of each high breakdown voltage element is planarly surrounded by a trench DTR having a DTI structure. The trench DTR is formed on the surface of the semiconductor substrate SUB.

Referring to FIG. 3, a semiconductor substrate SUB includes an SOI (Silicon) having a configuration in which a support substrate SS, a buried insulating film BOX, and a semiconductor layer SL are stacked in this order (from the lower side to the upper side in FIG. 3). On Insulator) substrate. Support substrate SS is made of, for example, a p-type silicon substrate, buried insulating film BOX is made of, for example, a silicon oxide film, and semiconductor layer SL is made of, for example, an n ⁻ silicon layer. Elements such as a CMOS transistor and a high voltage MOS transistor are formed on the main surface (the upper surface in FIG. 3) of the semiconductor layer SL. These elements have conductive portions such as an n ⁺ region NR, a p ⁺ region PR, and a gate electrode layer GE.

  A trench DTR having a DTI structure is formed so as to penetrate the semiconductor layer SL from the main surface of the semiconductor layer SL so as to surround each element formation region DFR such as a CMOS transistor and a high voltage MOS transistor in a plan view. . That is, the trench DTR extends in the vertical direction in FIG. 3 so as to reach the buried insulating film BOX from the upper main surface of the semiconductor layer SL. The trench DTR electrically separates the element formation regions DFR by surrounding the element formation regions DFR.

The CMOS transistor has a configuration in which the left nMOS transistor in FIG. 3 and the right pMOS transistor are combined. The nMOS transistor mainly has a p-type well region PWR, an n ⁺ region NR as a source region or a drain region, a gate insulating film GI, and a gate electrode layer GE. The pMOS transistor mainly has an n-type well region NWR, a p ⁺ region PR as a source region or a drain region, a gate insulating film GI, and a gate electrode layer GE.

The high breakdown voltage MOS transistor is divided into two elements on the left side and the right side of the trench DTR due to the presence of the trench DTR in the central portion. The left high voltage MOS transistor includes an n-type well region NWR, an n-type region NDR, a p-type region PBR, an n ⁺ region NR as a source region or a drain region, a p ⁺ contact region PR, a gate insulating film It mainly has a GI and a gate electrode layer GE. The high voltage MOS transistor on the right side mainly has a p-type offset region POR, an n-type well region NWR, a p ⁺ region PR as a source region or a drain region, a gate insulating film GI, and a gate electrode layer GE. doing.

In the present embodiment, the silicide layer SC is preferably formed on the surface of each of the n ⁺ region NR and the p ⁺ region PR, but the silicide layer SC may be omitted.

  A mask insulating layer MI is formed on the p-type offset region POR of the right high voltage MOS transistor. A field oxide film FO is appropriately formed on the main surface of the semiconductor layer SL to have a thickness of, for example, 400 nm for electrical isolation between adjacent elements.

  An underlying oxide film NSG (second insulating film) and an interlayer insulating film II (first insulating film) are formed so as to cover the above-described CMOS transistor and high voltage MOS transistor. Underlay oxide film NSG is formed with a thickness of, for example, 300 nm on the main surface of semiconductor layer SL (that is, on the main surface of semiconductor substrate SUB). The underlying oxide film NSG is, for example, a non-doped silicon oxide film that is not doped with impurities.

  The interlayer insulating film II is formed on the underlying oxide film NSG and in the trench DTR so as to cover the underlying oxide film NSG and to form a hollow SP in the trench DTR. Similar to the underlying oxide film NSG, the interlayer insulating film II is formed to cover the semiconductor chip SCC.

  That is, the insulating film II formed in the trench DTR is an interlayer insulating film II formed on the high voltage MOS transistor. The trench DTR is not completely filled with the insulating film II, and a hollow (void) SP is formed inside the trench DTR.

  The hollow SP may have a height substantially equal to the depth of the groove. The aspect ratio (depth / width) of the trench DTR is preferably 1 or more. The width of the trench DTR is preferably 0.3 μm or more based on a breakdown voltage of 80V.

  The interlayer insulating film II has a laminated structure of, for example, BP-TEOS (Boro-Phospho-Tetra-Ethyl-Ortho-Silicate) and a silicon oxide film formed thereon by a plasma CVD (Chemical Vapor Deposition) method. Yes. Note that BP-TEOS included in the interlayer insulating film II is an impurity of at least one of group III elements and group V elements such as P-TEOS (PSG: Phosphorus Silicon Glass) and B-TEOS (BSG: Boro Silicata Glass). An insulating film containing any material may be used.

A contact hole CH is formed in the underlying oxide film NSG and the interlayer insulating film II, and a plug conductive layer PL is formed in the contact hole CH. A wiring layer ICL is formed on the interlayer insulating film II. The wiring layer ICL is electrically connected to a conductive portion of the element (for example, an n ⁺ region NR, a p ⁺ region PR, a gate electrode layer GE, etc. as a source region and a drain region) through a plug conductive layer PL in the contact hole CH. Has been. In other words, the contact hole CH is a hole formed in the underlying oxide film NSG and the interlayer insulating film II, and the hole extends to reach the conductive portion of the element. When the silicide layer SC is formed on the n ⁺ region NR and the p ⁺ region PR, the contact hole CH is formed so as to reach the silicide layer SC. When the silicide layer is not formed, the contact hole CH is formed so as to reach the n ⁺ region NR and the p ⁺ region PR.

  Next, as a semiconductor device of the present embodiment, a method of manufacturing a semiconductor chip SCC having the CMOS transistor and the high voltage MOS transistor shown in FIG. 3 will be described with reference to FIGS.

  Referring to FIG. 4, first, a semiconductor substrate SUB is prepared as an SOI substrate having a configuration in which a support substrate SS, a buried insulating film BOX, and a semiconductor layer SL are stacked in this order. In the semiconductor layer SL, an n-type region NDR, a field oxide film FO, and the like are formed. In this field oxide film FO, an oxide film OXI and a nitride film NI are stacked in this order on the main surface of the semiconductor layer SL, and after selectively removing the nitride film NI, a portion exposed from the nitride film NI is removed. It is formed by thermal oxidation. Thereafter, nitride film NI and oxide film OXI are removed, and the main surface of semiconductor layer SL in which field oxide film FO is not formed is exposed.

Referring to FIG. 5, n-type well region NWR, p-type well region PWR, n-type region NDR, p-type region PDR, p-type offset region POR, gate insulating film GI, gate electrode layer GE, oxide insulating film OI, An n ⁺ region NR, a p ⁺ region PR, a sidewall insulating film SW, and the like are formed.

  Thereby, each element (high voltage MOS transistor, CMOS transistor, etc.) is completed on the main surface of the semiconductor layer SL (surface of the semiconductor substrate SUB). In other words, completion of each element means that it is formed as follows.

The high-voltage MOS transistor on the left side in FIG. 5 includes an n-type well region NWR, an n-type region NDR, a p-type region PBR, an n ⁺ region NR as a source or drain, and a p ⁺ region as a contact region. It is formed to have PR, gate insulating film GI, and gate electrode layer GE.

As a high voltage MOS transistor, the transistor on the right side in FIG. 5 includes an n-type well region NWR, a p-type offset region POR, a p ⁺ region PR as a source or drain, an n ⁺ region NR as a contact region, and gate insulation. A film GI and a gate electrode layer GE are formed.

The CMOS transistor is formed so that a pMOS transistor and an nMOS transistor are completed. The pMOS transistor is formed to have an n-type well region NWR, a p ⁺ region PR as a pair of source / drain regions, a gate insulating film GI, and a gate electrode layer GE. The nMOS transistor is formed to have a p-type well region PWR, an n ⁺ region NR as a pair of source / drain regions, a gate insulating film GI, and a gate electrode layer GE.

Referring to FIG. 6, silicide layer SC is formed on the surface of each of n ⁺ region NR and p ⁺ region PR. The silicide layer SC is formed by forming a refractory metal layer so as to cover the entire surface of the semiconductor layer SL and then reacting the refractory metal with silicon by applying heat treatment. At this time, by forming the mask insulating layer MI on the main surface of the semiconductor layer SL, the main surface of the semiconductor layer SL and the refractory metal layer are in contact with each other at the position where the mask insulating layer MI is formed. Therefore, the silicide layer SC is not formed. Note that the unreacted refractory metal layer is removed after the formation of the silicide layer SC.

  Referring to FIG. 7, underlying oxide film NSG is formed so as to cover each element. The underlying oxide film NSG is made of a non-doped silicon oxide film having a thickness of 600 nm, for example.

  Referring to FIG. 8, photoresist PHR is applied to cover underlying oxide film NSG.

  The photoresist PHR is patterned by a normal photolithography technique. Using this patterned photoresist PHR as a mask, underlying oxide film NSG and field oxide film FO are anisotropically etched in order. As a result, a trench DTRA penetrating the underlying oxide film NSG and the field oxide film FO is formed. Thereafter, the photoresist PHR is removed by ashing or the like.

  Referring to FIG. 9, anisotropic etching is performed on semiconductor layer SL using underlying oxide film NSG as a mask. Thereby, the semiconductor substrate SUB (semiconductor layer SL) immediately below the trench DTRA is selectively removed. Thereby, the trench DTR is formed so as to reach the buried insulating film BOX from the main surface of the semiconductor substrate SUB (semiconductor layer SL).

  During this etching, the underlying oxide film NSG is also etched away by a predetermined thickness, resulting in a thickness approximately half of the original thickness of 600 nm, for example, 300 nm.

  If it is preferable to prevent impurities such as a group III element and a group V element from being solid-phase diffused into the semiconductor layer SL due to the characteristics of the element to be formed, It is preferable to form a protective insulating film (liner film). The liner film is preferably a silicon oxide film or a silicon nitride film formed using, for example, a thermal oxidation method, a nitriding treatment, or a plasma CVD method.

  Referring to FIG. 10, insulating film IIA (first insulating film) is formed on each element and in groove DTR so as to cover each element and to form hollow SP in groove DTR. This insulating film IIA is formed of, for example, BP-TEOS having a thickness of 1320 nm. The upper surface of the insulating film IIA is polished and removed by, for example, a CMP (Chemical Mechanical Polishing) method.

  Referring to FIG. 11, the upper surface of insulating film II is planarized by interlayer insulating film II by the above-described CMP method. By grinding, for example, 640 nm using the CMP method, the thickness of the interlayer insulating film II is, for example, 680 nm.

  Referring to FIG. 12, contact holes CH (holes) that reach the surface of the semiconductor substrate SUB (surface of the silicide layer SC) through the interlayer insulating film II and the underlying oxide film NSG by ordinary photolithography and etching techniques. Is formed. From this contact hole CH, for example, the surface of the silicide layer SC formed on the surface of the source region, the drain region or the like is exposed.

  Referring to FIG. 3, plug conductive layer PL is formed in contact hole CH. Thereafter, wiring layer ICL is formed on interlayer insulating film II so as to be electrically connected to the conductive portion of each element through plug conductive layer PL.

  Plug conductive layer PL and wiring layer ICL are preferably metal thin films made of aluminum, for example, and may be formed by laminating metal thin films of titanium and tungsten. Alternatively, a titanium nitride (TiN) thin film may be formed as a barrier metal, and an aluminum metal thin film may be stacked thereon.

Thus, the semiconductor device of the present embodiment shown in FIG. 3 is manufactured.
Next, the result of investigating the difference in characteristics between the case where there is a hollow in the groove DTR in the DTI structure and the case where there is no hollow is described.

  In order to examine the characteristics of the semiconductor device of this embodiment, an evaluation wafer was prepared. The pressure resistance of the semiconductor chip sample placed on the surface of the wafer was evaluated.

Each semiconductor chip is formed with an evaluation TEG shown in FIG. Referring to FIG. 13, this evaluation TEG has a region A in a plan view and a region B separated from the region A by the DTI structure. Each of regions A and B has an n-type well region NWR formed on the main surface of semiconductor layer SL, and an n ⁺ region NR formed on the surface in n-type well region NWR.

  As the width of the trench DTR increases from 0.6 μm to 1.0 μm, the value of the voltage at which the leakage current starts to increase rapidly increases from about 400V to about 600V. That is, it was found that the larger the width of the trench DTR, the smaller the leakage current, and the higher the breakdown voltage of the trench DTR. FIG. 14 is a graph showing the relationship between the width of the trench DTR (DTI width) and the breakdown voltage of each TEG.

  Referring to FIG. 14, as the width of groove DTR increases from 0.6 μm to 1.0 μm, the withstand voltage of groove DTR increases from about 400V to about 600V. It can be seen that when the width of the trench DTR is increased by 0.1 μm, the breakdown voltage of the trench DTR is increased by 60 V on average. FIG. 14 shows that the withstand voltage of the trench DTR increases as the width of the trench DTR increases.

  Next, the results of examining the stress on the surface of the semiconductor layer SL in the vicinity of the trench DTR will be described.

  This stress was measured by forming a resistance composed of an impurity region on the surface of the semiconductor layer SL in the vicinity of the trench DTR and measuring the resistance value. Specifically, as shown in FIGS. 15 and 16, the sheet resistance SHR arranged in parallel to the groove DTR in plan view, and the sheet arranged orthogonal to the groove DTR in plan view as shown in FIGS. The stress was measured by utilizing the fact that each resistance value with the resistor SHR exhibits different characteristics due to the influence of the stress.

  In both the parallel arrangement TEG in FIG. 15 and the orthogonal arrangement TEG in FIG. 17, the depth of the trench DTR is about 5 μm and the width is about 0.8 μm. The planar shape of the semiconductor layer SL surrounded by the trench DTR is about 100 μm × About 100 μm. In both the parallel arrangement TEG in FIG. 15 and the orthogonal arrangement TEG in FIG. 17, the parallel shape of the sheet resistance SHR is about 20 μm × about 2 μm, and the depth (diffusion depth) of the sheet resistance SHR is about 0.6 μm. It is.

  In both the parallel arrangement TEG in FIG. 15 and the orthogonal arrangement TEG in FIG. 17, a current flows in the longitudinal direction of the planar shape of the sheet resistance SHR. That is, in the parallel arrangement TEG in FIG. 15, stress is applied in a direction perpendicular to the current direction of the sheet resistance SHR, and in the orthogonal arrangement TEG in FIG. 17, parallel to the current direction of the sheet resistance SHR. The direction is stressed.

  The resistance value of the sheet resistance SHR was determined by measuring the value of the current flowing through the sheet resistance SHR when a voltage was applied to the sheet resistance SHR. Further, this measurement is performed by changing the distance between the sheet resistance SHR and the groove DTR in the range of 1 to 20 μm in the parallel arrangement TEG shown in FIGS. 15 and 16, and in the orthogonal arrangement TEG shown in FIGS. 17 and 18. This was performed by changing the distance between the sheet resistance SHR and the groove DTR in the range of 2 to 20 μm.

  When the hollow SP does not exist inside the groove DTR, the change in the resistance value becomes remarkable as the distance between the sheet resistance SHR and the groove DTR becomes shorter. In particular, in the case of “parallel to DTR” shown in FIGS. 15 and 16, when the distance from the groove DTR is 1 μm, the change rate of the resistance value of the sheet resistance SHR is close to 15%.

  On the other hand, when the hollow SP exists inside the groove DTR, the resistance value of the sheet resistance SHR hardly changed even if the distance between the sheet resistance SHR and the groove DTR changed. This means that when the hollow SP is provided inside the groove DTR, the stress inside the groove DTR is reduced. Therefore, it has been found that by forming an insulating film in the trench DTR so that a hollow SP is generated in the trench DTR, it is possible to suppress the stress from being generated on the surface of the semiconductor layer SL.

Next, the effect of this Embodiment is demonstrated.
According to the present embodiment, as shown in FIGS. 4 to 9, since the trench DTR having the DTI structure is formed after the elements such as the high voltage MOS transistor are completed, the trench DTR is buried with the interlayer insulating film II. Is possible. This eliminates the need to form an insulating film for filling the trench DTR separately from the interlayer insulating film, so that the number of steps in the manufacturing method can be greatly reduced.

  Further, after completion of an element such as a high voltage MOS transistor, a trench DTR having a DTI structure is formed. In the manufacturing flow after element completion, the number of times that the surface of the insulating film filling the trench DTR is exposed to wet etching is smaller than that in the manufacturing flow before element completion. For this reason, even if the hollow SP is present in the groove DTR, the exposure of the hollow SP to the surface is suppressed. Thereby, since foreign substances, such as a resist, do not enter into the hollow SP exposed on the surface, it is possible to prevent the occurrence of pattern defects due to the ejection of foreign substances in the hollow SP during the production.

  Further, by actively forming the hollow SP in the trench DTR, as described with reference to FIG. 14, the leakage current of the element separated by the DTI structure can be suppressed, and the breakdown voltage can be increased.

  Further, by actively forming the hollow SP in the groove DTR, the stress of the semiconductor layer SL in the vicinity of the groove DTR can be reduced. This is because the hollow SP, which is a void, can relieve the stress generated by the difference in thermal expansion coefficient between the silicon oxide film inside the trench DTR and silicon. By reducing the stress of the semiconductor layer SL in the vicinity of the trench DTR, generation of crystal defects in the semiconductor layer SL can be suppressed.

  Further, since the trench DTR having the DTI structure is formed after the element such as the high voltage MOS transistor is completed, the foreign matter formed inside the semiconductor layer SL in the element formation region DFR (see FIG. 1) during the element formation. CNTs (such as metal impurities) can be collected at the gettering site GT (see FIG. 1). This will be described below with reference to FIGS.

  Referring to FIG. 19, gettering site GT is formed so as to surround element formation region DFR in which an element is finally formed in semiconductor substrate SUB. Thereafter, field oxide film FO is formed as shown in FIG. 20, and trench DTR is formed so as to penetrate field oxide film FO and semiconductor layer SL as shown in FIG.

  For example, as shown in FIG. 20, when the foreign substance CNT enters the semiconductor layer SL before the trench DTR is formed, the foreign substance CNT moves inside the semiconductor layer SL by heat treatment during the process on the semiconductor substrate SUB. It moves and is absorbed by the gettering site GT. However, if the foreign matter CNT enters the semiconductor layer SL in the element formation region DFR surrounded by the trench DTR after the trench DTR is formed as shown in FIG. 21, the foreign matter CNT is gettered even during the heat treatment in the subsequent process. It becomes impossible to move toward the site GT. That is, the foreign substance CNT is left inside the region (element formation region DFR) surrounded by the trench DTR. If the foreign substance CNT is stored in the semiconductor layer SL, the characteristics of the element formed on the surface of the semiconductor substrate SUB may be deteriorated. Therefore, gettering is preferably performed with high efficiency.

  In the manufacturing method of the present embodiment in which the trench DTR is formed after the elements are formed in the element formation region DFR, the time during which the foreign matter CNT can be gettered becomes longer. Therefore, the foreign matter CNT inside the semiconductor layer SL can be gettered more reliably.

  Further, in the present embodiment, a semiconductor substrate SUB in which a buried insulating film BOX (silicon oxide film) is disposed on the support substrate SS is used. For this reason, by forming the diffusion region along the wall surface of the trench DTR, it is possible to suppress the leakage current passing through the damage layer formed on the side surface of the trench DTR. This will be described below with reference to FIGS.

  First, the case where the semiconductor substrate is not a SOI substrate but a bulk silicon substrate will be described with reference to FIG.

  Referring to FIG. 22A, when the trench DTR is formed in the semiconductor substrate SUB, etching damage (crystal defect) occurs in the wall portion of the trench DTR. For this reason, if there is a pn junction between the n-type semiconductor region NSR and the p-type semiconductor region PSR in the wall portion of the trench DTR, a leakage current is generated in the pn junction portion due to the etching damage.

  In order to prevent the occurrence of this leakage current, it is conceivable to form an n-type or p-type diffusion region SDR as shown in FIG. 22B on the wall portion where the etching damage of the trench DTR has occurred. In other words, by forming the diffusion region SDR, a pn junction is not formed at a portion in contact with the trench DTR, and generation of a leakage current at the pn junction can be prevented.

  However, when such a diffusion region SDR is formed when a bulk silicon substrate is used as the semiconductor substrate SUB, the p-type semiconductor regions PSR may be electrically connected to each other by the diffusion region SDR. The meaning of automatic separation is lost. For this reason, when a bulk silicon substrate is used as the semiconductor substrate SUB, a heat treatment for recovering crystallinity is required to eliminate crystal defects due to the etching damage, and the manufacturing process becomes complicated.

Next, the case where the semiconductor substrate SUB is made of an SOI substrate will be described with reference to FIG.
Referring to FIG. 23A, even when the semiconductor substrate SUB is formed of an SOI substrate, if there is a pn junction between the n-type semiconductor region NSR and the p-type semiconductor region PSR at a portion in contact with the wall portion of the trench DTR. A leak current is generated at the pn junction through etching damage to the wall of the trench DTR. However, as shown in FIG. 23B, by forming the diffusion region SDR along the wall portion of the trench DTR, the pn junction is not located at a portion in contact with the wall portion of the trench DTR. For this reason, generation | occurrence | production of the leakage current through the said etching damage can be prevented in the pn junction part.

  In this embodiment, since the semiconductor substrate SUB is an SOI substrate and the trench DTR is formed so as to reach the buried insulating film BOX, the diffusion regions SDR formed on both sides of the trench DTR are connected to each other by the buried insulating film BOX. Are electrically separated from each other. For this reason, the p-type semiconductor regions PSR on both sides of the trench DTR are not electrically connected to each other by the diffusion region SDR.

  Furthermore, this diffusion region SDR can be formed by solid phase diffusion of impurities (group III elements such as boron and phosphorus and group V elements) contained in the interlayer insulating film II. In this case, a process such as ion implantation of a separate impurity for forming the diffusion region SDR becomes unnecessary, and the manufacturing process can be simplified. Further, the heat treatment for recovering the crystallinity is not required, and the manufacturing process can be further simplified.

  Solid phase diffusion of impurities such as group III elements from the side surface of the trench DTR into the semiconductor layer SL is performed extremely uniformly. That is, the potential inside the solid phase diffusion region SDR is substantially constant within the region. For this reason, it is possible to suppress the leakage current from flowing so as to sew the inside of the solid phase diffusion region SDR, particularly between a plurality of etching damages.

  If the semiconductor substrate SUB made of an SOI substrate is used as in this embodiment, the true breakdown voltage of the trench DTR based on the electric field inside the trench DTR can be examined. For example, even in a semiconductor device in which a trench DTR is formed in a bulk semiconductor substrate SUB that does not have a buried insulating film BOX, if a hollow SP exists in the trench DTR, the electric field inside the trench DTR is reduced, and the trench DTR The breakdown voltage is improved. However, the breakdown voltage here is the breakdown voltage of the pn junction formed by the p-type semiconductor region PSR and the n-type semiconductor region NSR shown in FIG. 22, and there is an error between the true breakdown voltage of the trench DTR. However, in the semiconductor substrate SUB provided with the buried insulating film BOX, the true breakdown voltage inside the trench DTR can be examined with high accuracy.

(Embodiment 2)
The present embodiment is different from the first embodiment in the structure and manufacturing method of the trench DTR and the underlying oxide film NSG. Hereinafter, the configuration of the present embodiment will be described.

  As shown in FIG. 24, in the first embodiment, the width W1 of the trench DTR in the semiconductor layer SL is substantially the same as the width W2 of the trench DTR in the underlying oxide film NSG. On the other hand, in trench DTR of the second embodiment, referring to FIG. 25 and FIG. 26, the width W1 of the bottom of trench DTR (the lowermost portion of trench DTR) is the underlying oxide film NSG (second insulating film). The width is larger than the width W2 of the trench DTR (the width of the through hole penetrating the underlying oxide film NSG).

  The width W2 of the through hole (groove DTR in the underlying oxide film NSG) of the underlying oxide film NSG shown in FIGS. 25 and 26 is the same as the width W2 of the through hole of the underlying oxide film NSG of the first embodiment shown in FIG. Suppose there is. Here, as shown in FIG. 25, even if the width W2 of the trench DTR of the semiconductor layer SL is substantially uniform over the entire depth direction of the trench DTR and is larger than the width W2 of the trench DTR of the underlying oxide film NSG. Good. Alternatively, as shown in FIG. 26, the width W1 of the trench DTR of the semiconductor layer SL may become wider as it approaches the bottom of the trench DTR (as it approaches the buried insulating film BOX).

  24 to 26 show only the shape of the trench DTR, and the interlayer insulating film II and the field oxide film FO inside the trench DTR are not shown for convenience of explanation. The semiconductor device in which the trench DTR having the shape of FIG. 25 is formed has an aspect as shown in FIG. 27, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG. The semiconductor device in which the trench DTR having the shape of FIG. 26 is formed is as shown in FIG. 29, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG. 27 and 29 are diagrams corresponding to FIG. 3 in the first embodiment. The width of through hole PRCH in underlying oxide film NSG shown in FIGS. 28 and 30 is substantially the same as the width of the through hole in underlying oxide film NSG of the first embodiment.

  Since the configuration of the present embodiment is substantially the same as the configuration of the first embodiment except for the above, the same elements as those of the first embodiment are denoted by the same reference numerals in FIGS. Do not repeat the explanation.

Next, the manufacturing method of this embodiment will be described.
The manufacturing method of the present embodiment undergoes the same steps as in the first embodiment shown in FIGS. The configuration in the vicinity of the groove DTRA in FIG. 8 is simplified and enlarged and shown in FIG. Thereafter, the photoresist PHR is removed, and the semiconductor layer SL is etched using the underlying oxide film NSG as a mask, thereby forming a trench DTR reaching the buried insulating film BOX. By changing the etching method or conditions for forming the trench DTR from the conditions of the first embodiment, the trench DTR having the shape shown in FIG. 25 or FIG. 26 is formed.

  Specifically, in the formation of the wide trench DTR shown in FIG. 25, after the trench DTR is formed under the same conditions as in the first embodiment, wet etching is performed to increase the width of the trench DTR. By this wet etching, the semiconductor layer SL made of silicon is preferentially removed with respect to the underlying oxide film NSG made of the silicon oxide film and the field oxide film FO, and the width of the semiconductor layer SL portion of the trench DTR is widened.

In the formation of the tapered groove DTR shown in FIG. 26, the etching conditions of the semiconductor layer SL after the photoresist PHR is removed from the state shown in FIG. In the etching for forming the trench DTR of the first embodiment, as an example, Ar (argon) gas, SF ₆ (sulfur hexafluoride) gas, and O ₂ (oxygen) gas are each 50 sccm under a pressure of 4 Pa, It is supplied under the conditions of 60 sccm and 25 sccm, and a state in which high frequency power of 40 W is supplied is maintained for 120 seconds. On the other hand, in the etching for forming the tapered groove DTR of the present embodiment shown in FIG. 26, Ar gas, SF ₆ gas, and O ₂ gas are each 250 sccm under a pressure of 3 Pa, as an example. It is supplied under the conditions of 50 sccm and 30 sccm, and the state in which high frequency power of 50 W is supplied is maintained for 160 seconds.

When the semiconductor layer SL made of silicon is etched, as shown in FIG. 32, silicon Si and fluorine (F) ions ION in SF ₆ gas react to generate SiF _x . By forming SiF _x , Si in the semiconductor layer SL is scraped off.

Further, the side wall protective film PFM is formed on the side surface of the groove by the reaction between silicon Si and O ₂ gas. Sidewall protective film PFM suppresses deep etching in the left-right direction in FIG. That is, by forming the sidewall protective film PFM, the etching does not progress so much in the lateral direction of FIG. 32, but progresses in the vertical direction of FIG. 32 (so as to be deeply dug). Argon gas is added to neutralize the above reaction.

  In this way, as shown in FIG. 33, the semiconductor layer SL immediately below the region where the groove is dug in the underlying oxide film NSG or the like is selectively etched to form the groove DTR. By adopting the above etching conditions in this embodiment in such an etching mechanism, a tapered groove DTR shown in FIG. 26 can be formed.

  Thereafter, the semiconductor device of the second embodiment is manufactured through the same steps as those of the first embodiment shown in FIGS.

Next, the function and effect of this embodiment will be described.
In the present embodiment, since the bottom width W1 of the trench DTR is large, a large withstand voltage can be secured, and since the opening width W2 of the trench DTR is small, the hollow SP in the trench DTR is exposed to the outside by etching in a later process. Can be prevented. This will be described below.

  If the width of the trench DTR is increased in the first embodiment, the breakdown voltage due to the trench DTR can be improved.

  However, as shown in FIGS. 34 to 37, as the width of the groove DTR at the center of the wafer increases to 0.8 to 1.0 μm in the CAD design dimension, the apex of the hollow SP (hollow apex in the groove DTR). SPT) approaches the interface after polishing by the CMP method, and it can be seen that the hollow SP is not sufficiently capped when the width of the groove DTR is 1.1 μm. Also, as shown in FIGS. 38 to 41, when the width of the groove DTR in the peripheral portion of the wafer is as large as 0.8 to 1.1 μm in the CAD design dimension, the top of the hollow SP is also similar to the above. It can be seen that it approaches the interface after polishing by the CMP method. For this reason, in the configuration of the first embodiment, when the width of the trench DTR is increased, the distance from the hollow vertex SPT to the upper surface of the interlayer insulating film II is shortened. There is a possibility to penetrate the upper surface. This is because as the width of the trench DTR is larger, the hollow vertex SPT is present at a higher position than the upper surface of the semiconductor layer SL. As an example, as shown in FIG. 36, the distance from the hollow apex SPT to the apex of the underlying oxide film NSG in the element formation region DFR in which the width of the trench DTR is 1.0 μm is 1680 mm (168 nm).

  In the schematic cross-sectional view of FIG. 42, the width (DTI width) of the trench DTR is denoted by W, and the vertical distance from the upper surface of the semiconductor layer SL to the hollow vertex SPT is denoted by H. FIG. 43 shows the result of examining the change in H when W is changed with respect to the trench DTR formed in each of the element formation region DFR and the peripheral region of the element formation region DFR.

  The horizontal axis of the graph in FIG. 43 represents the value of W in FIG. 42, and the vertical axis represents the value of H in FIG. Of the plotted marks, the diamond “center” indicates the trench DTR formed in the element formation region DFR formed in the central region of the semiconductor chip SCC, and the square “periphery” is formed in the peripheral region of the semiconductor chip SCC. The trench DTR formed in the formed element formation region DFR is shown.

  From the graph of FIG. 43, it can be seen that the distance from the top surface of the semiconductor layer SL to the SP vertex (SPT) increases as the width of the trench DTR increases in both “center” and “periphery”. In other words, it can be seen that the distance from the uppermost surface of the interlayer insulating film II to the hollow vertex SPT is reduced.

  If the distance from the hollow vertex SPT to the upper surface of the interlayer insulating film II becomes short as a result of the presence of the hollow vertex SPT at a high position, the wiring layer ICL and the plug conductive layer PL are formed after the interlayer insulating film II is formed. The hollow apex SPT may be deformed by heat treatment during the post-process (see FIG. 3).

  Specifically, like the hollow SP shown in the photograph of FIG. 44, the distance from the top of the interlayer insulating film II to the hollow vertex SPT is sufficiently high, and the hollow vertex SPT has a sharp cross-sectional shape. This is a preferable state. At this time, since the interlayer insulating film II having a sufficient thickness is disposed on the hollow vertex SPT, the possibility that the hollow vertex SPT penetrates the upper surface of the interlayer insulating film II is low.

  However, when the distance from the hollow apex SPT to the interlayer insulating film II is short (the interlayer insulating film II on the hollow apex SPT is thin), the hollow apex SPT is changed by, for example, heat treatment after forming the TiN thin film in the subsequent process. Deforms to expand. This is because the gas constituting the hollow SP expands due to the heat treatment. 45 and 46 show a state after TiN is formed on the interlayer insulating film II by sputtering and heat-treated at 880 ° C.

  During the etching for forming the wiring layer ICL and the plug conductive layer PL, the thin interlayer insulating film II on the hollow vertex SPT is also etched simultaneously. Thereby, the hollow vertex SPT may penetrate through the interlayer insulating film II.

  47, when the aluminum thin film ICLA (not yet etched) is formed on the interlayer insulating film II on the hollow SP, for example, by sputtering, the aluminum thin film ICLA on the hollow SP is also a region other than the hollow SP. The upper aluminum thin film ICLA also has substantially the same film thickness.

  However, when the aluminum thin film ICLA on the trench DTR (on the hollow SP) is removed by patterning the aluminum thin film ICLA, the interlayer insulating film II is also removed to some extent by the etching, so that the hollow SP becomes the interlayer insulating film as shown in FIG. May break through II. This is because the thin interlayer insulating film II under the aluminum is simultaneously etched and the upper part of the hollow SP expands. The greater the expansion of the upper part of the hollow SP, the higher the possibility of breaking through the interlayer insulating film II.

  As described above, when the width of the trench DTR is increased, the hollow vertex SPT is increased and the interlayer insulating film II on the hollow vertex SPT is thinned. Then, it can be said that the upper part of the hollow SP is deformed and deformed during heat treatment in a subsequent process, and a problem of breaking through the thin interlayer insulating film II on the hollow SP may occur. If the interlayer insulating film II on the hollow SP is broken through, there is a possibility that the inside of the trench DTR is completely buried in the subsequent film forming process, etc. In this case, the function of electrically isolating elements in the trench DTR is lowered. To do. Considering this, it is preferable to narrow the width of the trench DTR.

  Therefore, as in the second embodiment, the width of the through hole PRCH in the underlying oxide film NSG formed so as to be continuous with at least the trench DTR is formed to be smaller than the width of the trench DTR in the semiconductor layer SL. Conversely, as described above, the width of the through hole PRCH of the underlying oxide film NSG is the same as that of the trench DTR of the first embodiment, and the width of the trench DTR of the semiconductor layer SL is larger than the width of the through hole PRCH. To.

  In this way, the withstand voltage of the trench DTR can be increased by the large width of the trench DTR, and the width of the through hole PRCH is smaller than that of the trench DTR, so that the upper portion of the hollow SP is deformed and the interlayer insulating film II is formed. It is possible to suppress the occurrence of defects that penetrate.

  The groove DTR of the second embodiment described above has the same effect as the groove DTR of the first embodiment. However, the trench DTR of the second embodiment may be formed for the semiconductor substrate SUB in which the buried insulating film BOX is not present. The aspect in that case is shown in FIGS.

  In addition, by setting the temperature of the heat treatment after the formation by sputtering of TiN described in FIGS. 45 and 46 to 800 ° C. or less, it is possible to suppress deformation such as expansion of the upper part of the hollow SP. .

  The second embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the second embodiment of the present invention are all in accordance with the first embodiment of the present invention.

(Embodiment 3)
The present embodiment is different from the first embodiment in the structure and manufacturing method of the trench DTR and the underlying oxide film NSG. Hereinafter, the configuration of the present embodiment will be described.

  Referring to FIGS. 55 and 56, trench DTR of the third embodiment has a width of trench DTR in underlying oxide film NSG (second insulating film) (width of a through-hole penetrating underlying oxide film NSG). The width of the opening end of the trench DTR is larger than the width of the trench DTR formed in the semiconductor layer SL at the uppermost portion closest to the underlying oxide film NSG. In this respect, the groove DTR of the third embodiment is different from the groove DTR of the first embodiment shown in FIG. 24 and the groove DTR of the second embodiment shown in FIG.

  The width of the open end of groove DTR shown in FIGS. 55 and 56 (the width of the uppermost portion of groove DTR formed in semiconductor layer SL closest to underlying oxide film NSG) is the groove of the first embodiment shown in FIG. Assume that it is the same as the width of the DTR. Here, as shown in FIG. 55, the width of the trench DTR in the underlying oxide film NSG may be larger than the width of the opening end of the trench DTR in the semiconductor layer SL. Alternatively, as shown in FIG. 56, a shape (tapered shape) in which corners in the cross section of the semiconductor layer SL are cut off may be formed.

  55 and 56 show only the shape of the trench DTR, and the trench DTR and the field oxide film FO are not shown for convenience of explanation. FIGS. 55 and 56 show an example in which the trench DTR of the third embodiment is formed using the semiconductor substrate SUB provided with the buried insulating film BOX. However, in the third embodiment, as in the second embodiment, the trench DTR may be formed in the semiconductor substrate SUB made of bulk silicon without the embedded insulating film BOX. In that case, FIG. 55 becomes like FIG. 57, and FIG. 56 becomes like FIG.

  The semiconductor device in which the trench DTR having the shape of FIG. 55 is formed is as shown in FIG. 59, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG. The semiconductor device in which the trench DTR having the shape of FIG. 56 is formed has an aspect as shown in FIG. 61, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG. The semiconductor device in which the trench DTR having the shape of FIG. 57 is formed has an aspect as shown in FIG. 63, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG. The semiconductor device in which the trench DTR having the shape of FIG. 58 is formed has an embodiment as shown in FIG. 65, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG.

  59, 61, 63, and 65 correspond to FIG. 3 in the first embodiment. 60, 62, 64, and 66, the width of the trench DTR of the semiconductor layer SL is substantially the same as the width of the trench DTR of the semiconductor layer SL of the first embodiment.

  Since the configuration of the present embodiment is substantially the same as the configuration of the first embodiment except for the above, the same reference numerals are given to the same elements as those in the first embodiment in FIGS. Description is omitted.

In the third embodiment, in order to make the width of the trench DTR (through hole PRCH) of the underlying oxide film NSG larger than the width of the trench DTR of the semiconductor layer SL, the trench DTR is formed so as to reach the normal buried insulating film. After performing the step (for example, corresponding to FIG. 9 of the first embodiment), it is preferable to perform further etching to increase the width of the trench DTR (through hole PRCH) of the underlying oxide film NSG. At this time, a gas in which argon gas, sulfur hexafluoride (SF ₆ ) gas, and oxygen gas are mixed is preferably used as an etching gas for the underlying oxide film NSG.

  In Embodiment 3, contrary to Embodiment 2, processing is performed so that the width of through hole PRCH in underlying oxide film NSG is larger than the width of trench DTR in semiconductor layer SL. For this reason, it seems that the effect opposite to that of the second embodiment, that is, the width of the through hole PRCH is large, the hollow vertex SPT exists at a high position, and the interlayer insulating film II thereon is thinned. However, in practice, if the through hole PRCH is made larger than the width of the trench DTR of the semiconductor layer SL, the interlayer insulating film II formed in a later process can be filled more smoothly into the trench DTR. This is because the width of the through hole PRCH of the underlying oxide film NSG, which is the entrance of the interlayer insulating film II into the trench DTR, is large.

  When the interlayer insulating film II is smoothly embedded in the trench DTR, the filling rate of the interlayer insulating film II in the trench DTR increases. For this reason, the hollow vertex SPT is formed at a lower position by the amount of the volume of the hollow SP formed inside the groove DTR. Then, a thicker interlayer insulating film II can be formed on the hollow vertex SPT. Therefore, the possibility that the upper part of the hollow SP causes deformation such as expansion can be reduced, and the quality of the groove DTR can be improved.

  As described above, in order to smoothly fill the interlayer insulating film II in the trench DTR, the underlying oxide film NSG preferably has a thickness of 100 nm or more. Further, by optimizing the content ratio of the group III element and the group V element contained in the BP-TEOS that constitutes the interlayer insulating film II, the interlayer insulating film II into the trench DTR as described above can be obtained. Embedding can be smooth.

  The third embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the third embodiment of the present invention are all in accordance with the first embodiment of the present invention.

(Embodiment 4)
As described above, if the interlayer insulating film II on the hollow vertex SPT of the trench DTR is thin, the hollow SP may penetrate through the interlayer insulating film II in a later process. In order to suppress this phenomenon, for example, it is preferable to form the interlayer insulating film II on the hollow apex SPT shown in FIG. 67 so that the thickness H ₁ is thicker, that is, the entire interlayer insulating film II is thicker. . Such a configuration can be manufactured, for example, by the following method.

For example, after forming an insulating film thicker than the insulating film IIA formed in FIG. 10 of the first embodiment, there is a method of polishing and removing by the same thickness as in FIG. 11 of the first embodiment. In this way, the interlayer insulating film II having a larger thickness (indicated by H ₁ in FIG. 67) than the interlayer insulating film II shown in FIG. 11 of the first embodiment is formed on the hollow SP.

Alternatively, for example, after forming the interlayer insulating film II having a thickness of H ₁ on the hollow SP shown in FIG. 67, an interlayer insulating film IIL made of the same material as the interlayer insulating film II is added as shown in FIG. There is also a method of stacking as described above. In this way, the thickness of the interlayer insulating film II on the hollow SP becomes H ₁ + H _{2 as} shown in FIG. That is, for example, interlayer insulating film II having a thickness larger than that of interlayer insulating film II shown in FIG. 11 of the first embodiment is formed on hollow SP.

Alternatively, after forming an insulating film having substantially the same thickness as the insulating film IIA formed in FIG. 10 of the first embodiment, a thickness smaller than that of FIG. 11 of the first embodiment is polished and removed by CMP. Also in this case, interlayer insulating film II having a larger thickness (indicated by H ₁ in FIG. 67) than interlayer insulating film II shown in FIG. 11 of the first embodiment is formed.

  67 and 68, the width of the underlying oxide film NSG and the width of the trench DTR in the semiconductor layer SL are shown to be substantially equal to those in the first embodiment. However, in the fourth embodiment, the size relationship between the width of the underlying oxide film NSG and the width of the trench DTR in the semiconductor layer SL may satisfy the relationship shown in the second or third embodiment, for example. In the fourth embodiment, as in the second or third embodiment, the presence or absence of the buried insulating film BOX in the semiconductor substrate SUB does not matter.

Specifically, in either case of FIGS. 67 and 68, the thickness of the interlayer insulating film II or the interlayer insulating film II and the interlayer insulating film IIL disposed immediately above the hollow SP (FIG. 67). H _{1 of} FIG. 68 or H ₁ + H ₂ of FIG. 68 is preferably 500 nm or more.

  The semiconductor device in which the trench DTR having the shape of FIG. 68 is formed is as shown in FIG. 69, and an enlarged view in the vicinity of the trench DTR portion is as shown in FIG.

  The fourth embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, in the fourth embodiment of the present invention, all the configurations, conditions, procedures, effects, and the like not described above are in accordance with the first embodiment of the present invention.

(Embodiment 5)
In any of the first to fourth embodiments described above, the field oxide film FO is not shown in a partial schematic cross-sectional view showing only the shape of the groove, for example, FIG. However, in a semiconductor device in which elements are actually combined, there exists a field oxide film FO that is disposed in the vicinity of the trench DTR in FIG. 3, for example. The field oxide film FO is formed as a LOCOS (element isolation insulating film) for electrically isolating elements.

  Conversely, for example, it is preferable that trench DTR is formed in a region where LOCOS is disposed, such as field oxide film FO. Referring to FIG. 71, a field oxide film FO as LOCOS is formed in a part of a region of a certain depth from the uppermost surface of semiconductor layer SL of semiconductor substrate SUB. An underlying oxide film NSG is formed on semiconductor substrate SUB (semiconductor layer SL) so as to cover field oxide film FO. 71 corresponds to the state after formation of underlying oxide film NSG shown in FIG. 7 of the first embodiment.

  72, the field oxide film FO and the underlying oxide film NSG over the field oxide film FO and the semiconductor layer SL under the field oxide film FO are penetrated to reach the buried insulating film BOX. A DTR is formed. The state of FIG. 72 corresponds to the state after formation of trench DTR shown in FIG. 9 of the first embodiment. Thereafter, referring to FIG. 73, interlayer insulating film II is formed, and interlayer insulating film II is also formed in trench DTR.

The horizontal axis of the graph of FIG. 74 corresponds to each position (coordinate) in the horizontal direction of the lower element of the same FIG. The vertical axis of the graph of FIG. 74 corresponds to an index called the Raman displacement, which indicates the direction and magnitude of the stress inside each coordinate area inside the element. In the vertical axis, the region above the central 520 cm ⁻¹ is a region indicating that compressive stress is applied, and the region below 520 cm ⁻¹ is a region indicating that tensile stress is applied.

  In FIG. 74, the horizontal axis of the graph is shown so that the horizontal position of the element indicated by each coordinate of the horizontal axis coincides. In this way, the specific position of the coordinate on the horizontal axis of the graph can be easily grasped. In addition, the solid line and the dotted line in the graph of FIG. 74 indicate data of elements formed by performing heat treatment at different temperatures (temperature A and temperature B, respectively).

  From the graph of FIG. 74, it can be seen that the tensile stress increases in the region where the LOCOS (field oxide film FO) exists regardless of the temperature at which the heat treatment is performed. This tensile stress is caused by the difference in thermal expansion coefficient between silicon and the silicon oxide film because LOCOS is a field oxide film FO made of a silicon oxide film and the field oxide film FO is formed on the semiconductor layer SL made of silicon. It is considered that the stress is caused by

  On the other hand, the compressive stress increases in the region where the groove DTR is formed. For this reason, since the trench DTR is formed so as to penetrate the field oxide film FO, the compressive stress of the trench DTR and the tensile stress of the field oxide film FO cancel each other, so that the internal stress in the vicinity of the trench DTR is reduced. be able to.

  As described above, by reducing the stress in the vicinity of the trench DTR, the stress concentration in the vicinity of the trench DTR, the side surface of the trench DTR, and the opening of the underlying oxide film NSG (through hole PRCH in FIG. 28) can be suppressed. it can. Therefore, the generation of crystal defects in the vicinity of the trench DTR, the through hole PRCH, and the like can be further reliably suppressed. In addition, as a result of suppressing the generation of crystal defects, it is also possible to suppress the generation of leak current due to etching damage (see FIGS. 22 and 23) near the side surface of the trench DTR.

  An overall view of the semiconductor device in which the field oxide film FO as LOCOS is formed is as shown in FIG. This is the same as the overall view of the semiconductor device shown in FIG.

  Note that the semiconductor device having LOCOS as in the fifth embodiment may also be formed using a bulk semiconductor substrate SUB that does not have the buried insulating film BOX (the semiconductor layer SL is formed on the support substrate SS). Good.

(Embodiment 6)
The present embodiment is different from the first embodiment in the mask for forming the trench DTR. Hereinafter, the configuration of the present embodiment will be described.

  In the present embodiment, as shown in FIG. 76, the insulating film formed so as to cover the element before forming the trench DTR is not only the underlying oxide film NSG (second insulating film), The underlying nitride film NTF (third insulating film) and further the underlying oxide film NSG (fourth insulating film) are formed.

  That is, in the manufacturing method of the present embodiment, prior to the step of forming the trench DTR, a step of forming a lower underlying oxide film NSG (second insulating film), and an underlying nitride film NTF on the underlying oxide film NSG. The method further includes the step of forming (third insulating film) and the step of forming the upper underlying oxide film NSG (fourth insulating film) on the underlying nitride film NTF.

  Underlay nitride film NTF is, for example, a silicon nitride film. Each of the upper and lower underlying oxide films NSG is, for example, a non-doped silicon oxide film as described above. Therefore, the third insulating film is made of a material different from that of the second insulating film, and the fourth insulating film is made of a material different from that of the third insulating film. The state of FIG. 76 corresponds to the state after formation of underlying oxide film NSG shown in FIG. 7 of the first embodiment.

  Thus, after forming a plurality of insulating films on the semiconductor layer SL, a trench DTR is formed as shown in FIG. The state of FIG. 77 corresponds to the state after formation of trench DTR shown in FIG. 9 of the first embodiment.

  Thereafter, a photoresist pattern (not shown) is formed on the upper underlying oxide film NSG by a normal photoengraving technique. Etching is performed using this photoresist pattern as a mask, so that the upper underlying oxide film NSG and the underlying nitride film are etched. The film NTF and the underlying oxide film NSG on the lower side are patterned in order. Thereafter, the resist pattern is removed by ashing, for example. Next, the semiconductor layer SL is etched using the patterned upper underlying oxide film NSG as a mask. Thereby, a trench DTR reaching the buried insulating film BOX from the main surface of the semiconductor layer SL is formed. After formation of trench DTR, upper underlying oxide film NSG and underlying nitride film NTF are removed to obtain the state shown in FIG. Thereafter, through the same process as in the first embodiment, the semiconductor device of the present embodiment having the same configuration as that in FIG. 3 is manufactured.

  When the underlying oxide film NSG single layer is used as an etching mask when forming the trench DTR as in the first embodiment shown in FIG. 9, the film thickness is formed on a part of the underlying oxide film NSG by etching for forming the trench DTR. And variations in film quality may occur.

  In contrast, in the present embodiment, trench DTR is formed using upper underlying oxide film NSG as a mask. At this time, the upper surface of the lower underlying oxide film NSG is protected by the underlying nitride film NTF and the upper underlying oxide film NSG. For this reason, the upper surface of the lower underlying oxide film NSG is not etched by the etching at the time of forming the trench DTR. Therefore, variations in the thickness of the underlying oxide film NSG on the lower side can be suppressed.

  A semiconductor device formed as a result of employing the manufacturing method shown in the sixth embodiment has the same mode as that shown in FIGS. Also in the sixth embodiment, the characteristics and manufacturing conditions of the trench DTR shown in the second, third, fourth, and fifth embodiments may be appropriately combined.

  The sixth embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the sixth embodiment of the present invention are all in accordance with the first embodiment of the present invention.

(Embodiment 7)
The present embodiment is different from the sixth embodiment in that a sidewall insulating film SW is formed on the side surface of the trench DTR. Hereinafter, the configuration of the present embodiment will be described.

  Referring to FIG. 77, in the present embodiment, as in the sixth embodiment, a lower underlying oxide film NSG, an underlying nitride film NTF, and an upper underlying oxide film NSG are sequentially formed on the main surface of semiconductor layer SL. After the formation, the semiconductor layer SL is etched using the upper underlying oxide film NSG as a mask. Thereby, the trench DTR is formed in the semiconductor layer SL.

  Referring to FIG. 78, an insulating film made of, eg, a silicon oxide film is formed on the inner wall of trench DTR and on the upper surface of upper underlying oxide film NSG. Thereafter, this insulating film is etched back until the upper surface of the upper underlying oxide film NSG is exposed. Thus, sidewall insulating film SW is formed of, for example, a silicon oxide film so as to cover the sidewall of trench DTR. Thereafter, the upper underlying oxide film NSG and the underlying nitride film NTF are removed.

  Referring to FIG. 79, on the lower underlying oxide film NSG and in the trench DTR so as to cover the surface of the exposed lower underlying oxide film NSG and to form a hollow SP in the trench DTR. Interlayer insulating film II is formed. Thereafter, through the same process as in the first embodiment, the semiconductor device of the present embodiment shown in FIG. 80 is manufactured.

  A semiconductor device in which the sidewall insulating film SW is formed in the trench DTR has a mode as shown in FIG. 80, and an enlarged view of the vicinity of the trench DTR portion is as shown in FIG.

  The configuration of the present embodiment is almost the same as the configuration of the first embodiment except that the sidewall insulating film SW is formed, and therefore the same as the first embodiment in FIGS. 78 to 81. Elements are given the same reference numerals and the description thereof is not repeated.

Next, the effect of this Embodiment is demonstrated.
Referring to FIG. 77, a phosphoric acid chemical solution is generally used when removing underlying nitride film NTF. When the chemical solution of phosphoric acid adheres to the surface of the semiconductor layer SL made of, for example, silicon, the surface of the semiconductor layer SL is roughened in the region where phosphoric acid has adhered. Then, there is a possibility that the leakage current due to the roughness of the surface of the semiconductor layer SL increases.

  Therefore, as in the present embodiment, by forming the sidewall insulating film SW for protecting the surface (side surface) of the semiconductor layer SL, the surface of the semiconductor layer SL is prevented from being directly exposed to phosphoric acid. be able to. Therefore, an increase in the roughness of the surface of the semiconductor layer SL can be suppressed, and an increase in leakage current can be suppressed.

  Further, since the sidewall insulating film SW is formed, a region where the interlayer insulating film II is formed in the trench DTR is substantially narrowed. For this reason, the vertex SPT of the hollow SP formed inside the trench DTR when the interlayer insulating film II is formed is at a lower position. This is because the size of the hollow SP becomes smaller as the area where the hollow SP can be formed becomes narrower. Therefore, as in the second and third embodiments, the interlayer insulating film II on the hollow apex SPT can be thickened to suppress problems that the hollow SP is deformed or breaks through the interlayer insulating film II.

  For example, when it is preferable to prevent solid-phase diffusion of a group III element or a group V element into the element due to the characteristics of the element to be formed, the sidewall insulating film SW is preferably non-doped.

  Also in the seventh embodiment, the characteristics and manufacturing conditions of the trench DTR shown in the second, third, fourth, and fifth embodiments may be appropriately combined. Alternatively, the manufacturing method using the underlying nitride film NTF as described in the sixth embodiment is taken as an example in the above, but for example, the underlying nitride film NTF is not used as in the first embodiment, and the trench DTR is formed inside. A manufacturing method in which the sidewall insulating film SW is formed may be used.

  The seventh embodiment of the present invention differs from the sixth embodiment of the present invention only in the points described above. That is, the configuration, conditions, procedures, effects, and the like not described above for the seventh embodiment of the present invention are all in accordance with the sixth embodiment of the present invention.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device having a groove and a method of manufacturing the same.

BOX buried insulating film, CH contact hole, CNT foreign material, DFR element formation region, DTR, DTRA groove, FO field oxide film, GE gate electrode layer, GI gate insulating film, GT gettering site, ICL wiring layer, ICLA aluminum thin film, II, IIL interlayer insulating film, IIA insulating film, ION ion, MI mask insulating layer, NDR n-type region, NI nitride film, NR n ⁺ region, NSG underlay oxide film, NSR n-type semiconductor region, NTF underlay nitride film, NWR n-type well region, OI oxide insulating film, OXI oxide film, PBR p-type region, PFM sidewall protective film, PHR photoresist, PL plug conductive layer, POR p-type offset region, PR p ⁺ region, PRCH through hole, PSR p Type semiconductor region, PWR p-type well region, SC silicide layer, SCC half Body chips, SDR solid phase diffusion region, SHR sheet resistance, SL semiconductor layer, SP hollow, SPT hollow vertex, SS supporting substrate, SUB semiconductor substrate, SW sidewall insulating films.

Claims (13)

Preparing a semiconductor substrate having a configuration in which a support substrate, a buried insulating film, and a semiconductor layer are stacked in this order;
Forming a MOS transistor having a gate electrode on the semiconductor layer and having a source region and a drain region in the semiconductor layer, and a method of manufacturing a semiconductor device ,
Forming a groove surrounding in plan view said MOS transistor to reach the semiconductor layer or al the buried insulating film,
And a step of forming a first insulating film to fill said spread on along the main surface of the covering has the semiconductor layer on the gate electrode, and before Symbol groove so as to form a hollow in the trench A method for manufacturing a semiconductor device. An oxide film and a nitride film are stacked in this order on the semiconductor layer , and after selectively removing the nitride film, the portion exposed from the nitride film is thermally oxidized to thereby form the source in the semiconductor layer. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second insulating film in contact with the region or the drain region. The method of manufacturing a semiconductor device according to claim 2, wherein the groove is formed so as to surround the MOS transistor and the second insulating film. After the step of forming the first insulating film,
Forming a conductive layer extending in the first insulating film so as to reach the source region or the drain region;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a wiring layer in contact with the conductive layer on the first insulating film. Forming a third insulating film on the main surface of the semiconductor layer so as to cover the MOS transistor before forming the trench;
Forming a fourth insulating film made of a material different from the third insulating film on the third insulating film;
On the fourth insulating film, further comprising a step of forming a fifth insulating film made of a material different from that of the fourth insulating film,
The step of forming the groove includes the step of selectively removing the semiconductor layer using the fifth insulating film as a mask, and the step of removing the fifth and fourth insulating films after the formation of the groove. The manufacturing method of the semiconductor device of any one of Claims 1-4 provided. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed so that an aspect ratio indicating a ratio of a depth to a width of the groove is 5.0 or more. The method for manufacturing a semiconductor device according to claim 1, wherein the groove is formed such that the width of the groove becomes wider as the bottom of the groove is approached. A semiconductor substrate having a configuration in which a support substrate, a buried insulating film, and a semiconductor layer are stacked in this order;
A MOS transistor having a gate electrode on the semiconductor layer and having a source region and a drain region in the semiconductor layer;
The spread in along the main surface of said semiconductor layer has covered over the gate electrode, and a first filling the groove so as to leave a hollow in a groove extending to reach the buried insulating layer from the semiconductor layer and an insulating film,
The semiconductor device, wherein the trench surrounds the MOS transistor . A second insulating film formed on the main surface of the semiconductor layer and in contact with the source region or the drain region in the semiconductor layer;
The semiconductor device according to claim 8, wherein the second insulating film is shallower than the first insulating film. A plurality of the grooves and the second insulating film are formed,
10. The semiconductor device according to claim 9, wherein at least a part of the second insulating film among the plurality of second insulating films is penetrated by at least a part of the plurality of grooves. A conductive layer extending in a portion of the first insulating film extending along the main surface of the semiconductor layer so as to reach the source region or the drain region of the MOS transistor;
  The semiconductor device according to claim 8, further comprising: a wiring layer disposed on the first insulating film and in contact with the conductive layer. The semiconductor device according to claim 8, wherein an aspect ratio indicating a ratio of a depth to a width of the groove is 5.0 or more. 13. The semiconductor device according to claim 8, wherein the width of the groove has a shape that becomes wider as it approaches the bottom of the groove.