JP2006147800A - Soi-mos transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an SOI-MOS transistor which can make a separation lower silicon film into low resistance, and to provide its manufacturing method. <P>SOLUTION: The SOI-MOS transistor comprises an insulating film, a body region with a channel and a source drain provided on the insulating layer, a body contact region set apart from the body region and provided on the insulating layer, a separation oxide film for separating the body region and the body contact region, and a separation lower silicon film for connecting the body region and the body contact region provided under the separation oxide film. The bottom of the separation lower silicon film is lower than the bottom of the body region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an SOI (Silicon on Insulator) structure MOSFET formed in a semiconductor layer formed on an insulating film, and more particularly to an SOI-MOS transistor having a body contact region and a method for manufacturing the same.

  In the NMOSFET having the SOI structure, holes accumulate in the SOI among hot carriers generated in the channel portion due to the impact ionization phenomenon during operation. Due to the accumulation of holes, a substrate floating effect and a parasitic bipolar effect occur, which may cause a problem of a decrease in drain breakdown voltage. Therefore, a technique for removing accumulated holes from the SOI by providing a body contact to the SOI-MOS transistor has been proposed (see, for example, Patent Document 1).

A conventional SOI-MOS transistor will be described with reference to FIG. FIG. 15A shows a planar structure of the NMOS transistor. The NMOS transistor includes a gate polysilicon electrode 1, an N ⁺ type source 2, an N ⁺ type drain 3, a P ⁺ type body contact region 4, an isolation oxide film 5, a gate contact 6, and a source contact. 7a, 7b, 7c, 7d, drain contacts 8a, 8b, 8c, 8d, and body contacts 9a, 9b, 9c.

Specific dimensions and impurity concentrations are as follows. The gate length (vertical direction in the figure) of the gate polysilicon electrode 1 is 0.05 to 1.0 μm, the gate width (horizontal direction in the figure) of the gate polysilicon electrode 1 is 0.1 to 10 μm, and the contact diameter is 0.1. 0.3 μm, the width of the isolation oxide film 5 is 0.1 to several μm, the impurity concentration of the gate polysilicon electrode 1 is 10 ¹⁹ to 10 ²⁰ cm ⁻³ , and the impurity concentration of the N ⁺ type source / drain is 10 ¹⁹ to The impurity concentration of 10 ²⁰ cm ⁻³ and body contact region 4 is 10 ¹⁹ to 10 ²⁰ cm ⁻³ .

FIG. 15B is a cross-sectional view taken along the line XX ′ in FIG. An insulating film 11 made of a buried oxide film is formed on a silicon substrate 10, and a P ⁻ type body region (SOI) 12 having a channel, a source / drain is provided thereon. A gate polysilicon electrode 1 is provided on the body region 12 via a gate oxide film 13. A body contact region 4 is provided on the insulating film 11 so as to be separated from the body region 12. The body region 12 and the body contact region 4 are separated by the isolation oxide film 5, but are connected by a lower isolation silicon film 20 provided under the isolation oxide film 5. The body region 12 is given a potential by the body contacts 9a to 9c.

Next, a conventional method for manufacturing an SOI-MOS transistor will be described. First, as shown in FIG. 16A, an insulating film 11, a P ⁻ -type silicon film 12 a, and a mask nitride film 50 are sequentially stacked on the silicon substrate 10. Then, photoresist patterns 51 a and 51 b are formed on the mask nitride film 50. Next, the mask nitride film 50 is anisotropically etched using the photoresist patterns 51a and 51b as masks to form nitride films 50a and 50b. Thereafter, the photoresist patterns 51a and 51b are removed.

  Next, as shown in FIG. 16B, anisotropic etching is performed using the nitride films 50a and 50b as a mask to form trenches 15 in the silicon film 12a. The silicon film 12 a separated by the trench 15 becomes the body region 12 and the body contact region 4. Then, the trench 15 is filled with the silicon oxide film 5a having good filling characteristics.

  Next, as shown in FIG. 16C, the silicon oxide film 5a is polished by a planarization method such as CMP (Chemical Mechanical Polishing) to expose the nitride films 50a and 50b. The silicon oxide film 5 a remaining in the trench 15 becomes an isolation oxide film 5 that separates the body region 12 and the body contact region 4. Thereafter, nitride films 50a and 50b are removed, and impurity doping and heat treatment for adjusting the resistance of body region 12 and adjusting the impurity concentration of the channel portion are performed.

  Next, as shown in FIG. 17A, after forming a gate oxide film 13 on the body region 12, a polysilicon film 1a is formed on the entire surface. Then, the polysilicon film 1a is patterned to form the gate polysilicon electrode 1. Thereafter, N-type ion implantation is performed on the source / drain.

Next, as shown in FIG. 17B, a P-type impurity 14 such as boron (B) is implanted into the body contact region 4 using the photoresist 52 as a mask. Then, as shown in FIG. 17C, the P-type impurity 14 is activated by heat treatment, so that the body contact region 4 is made P ⁺ -type. Thereafter, although not shown, an interlayer insulating film is formed on the surface, contacts to the gate, source, drain, and body are formed, and metal wiring is formed, whereby the transistor is completed.

  In the above example, the nitride films 50a and 50b are used as masks when forming the trench 15, but instead, a two-layer structure of nitride film and oxide film or a three-layer structure of nitride film / polysilicon / oxide film is used. May be.

Japanese Patent Laid-Open No. 11-233785

  The body region 12 and the body contact region 4 are connected to the isolation lower silicon film 20 below the isolation oxide film 5. However, the conventional SOI-MOS transistor has a problem that since the silicon film under the isolation is thin, the resistance becomes high, and the potential of the body region 12 is floated so that the normal operation cannot be performed. In addition, there is a problem that an operation delay occurs with respect to a high frequency operation, and jitter increases.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain an SOI-MOS transistor capable of reducing the resistance of the silicon film under isolation and a method for manufacturing the same.

  An SOI-MOS transistor according to the present invention includes an insulating film, a body region provided on the insulating film and having a channel and a source / drain, and a body contact region provided on the insulating film and spaced apart from the body region. An isolation oxide film that separates the body region and the body contact region, and an isolation lower silicon film that is provided under the isolation oxide film and connects the body region and the body contact region. Lower than the bottom of the area. Other features of the present invention will become apparent below.

  According to the present invention, the resistance of the silicon film under isolation can be reduced. Thus, the potential of the body region can be prevented from floating, and the transistor can be operated normally.

Embodiment 1 FIG.
An SOI-MOS transistor according to Embodiment 1 of the present invention will be described with reference to FIG. The SOI-MOS transistor has the same plan view as FIG. 14A of the background art, but has a cross-sectional view of the structure shown in FIG. 1 unlike the background art.

As shown in the drawing, an insulating film 11 made of a buried oxide film is formed on a silicon substrate 10, and a P ⁻ type body region (SOI) 12 having a channel, source / drain is provided thereon. A gate polysilicon electrode 1 is provided on the body region 12 via a gate oxide film 13. A body contact region 4 is provided on the insulating film 11 so as to be separated from the body region 12. The body region 12 and the body contact region 4 are separated by the isolation oxide film 5, but are connected by a lower isolation silicon film 20 provided under the isolation oxide film 5. The body region 12 is given a potential by the body contacts 9a to 9c. Further, unlike the background art, the bottom surface of the isolation silicon film 20 is lower than the bottom surface of the body region 12. However, the upper surface of the lower isolation silicon film 20 is made higher than the bottom surface of the body region 12 in order to ensure the connection between the body region 12 and the lower isolation silicon film 20.

Specific film thickness and impurity concentration are as follows. Gate polysilicon electrode 1 has a thickness of 50 to 200 nm, gate oxide film 13 has a thickness of 1.5 to 10 nm, body region 12 has a thickness of 50 to 200 nm, and insulating film 11 has a thickness of 100 to 200 nm. The film thickness of the oxide film 5 is 30 to 150 nm, and the impurity concentration of the body region 12 is 10 ¹⁷ to 10 ¹⁸ cm ⁻³ .

Next, a method for manufacturing the SOI-MOS transistor according to the first embodiment will be described. First, as shown in FIG. 2A, an insulating film 11, a P ⁻ -type silicon film 12 a, and a mask nitride film 50 are sequentially stacked on the silicon substrate 10. Then, photoresist patterns 51a and 51b are formed on the mask nitride film 50 by photolithography (photolithography).

  Next, as shown in FIG. 2B, the mask nitride film 50 is anisotropically etched using the photoresist patterns 51a and 51b as masks to form nitride films 50a and 50b. Thereafter, the photoresist patterns 51a and 51b are removed. Then, the trench 15 is formed by anisotropically etching the silicon film 12a and the insulating film 11 using the nitride films 50a and 50b as a mask. The silicon film 12 a separated by the trench 15 becomes the body region 12 and the body contact region 4.

  Next, as shown in FIG. 2C, selective epitaxial growth is performed under an ELO (Epitaxial Lateral Overgrowth) condition, and the silicon films 20a, 20b, 20c, 20d is grown and the trench 15 is buried. Then, as shown in FIG. 3A, the silicon films 20a, 20b, 20c, and 20d are anisotropically etched so as to remain in a desired thickness so that the body region 12 and the body contact region 4 are connected. A lower silicon film 20 is formed. Note that the epitaxial film may be etched back after non-selective epi growth instead of selective epi growth.

  Next, as shown in FIG. 3B, the trench 15 is filled with the silicon oxide film 5a having good filling characteristics. Then, as shown in FIG. 3C, the silicon oxide film 5a is polished by a planarization method such as CMP to expose the nitride films 50a and 50b. The silicon oxide film 5 a remaining in the trench 15 becomes an isolation oxide film 5 that separates the body region 12 and the body contact region 4. Thereafter, nitride films 50a and 50b are removed, and impurity doping and heat treatment for adjusting the resistance of body region 12 and adjusting the impurity concentration of the channel portion are performed.

  Next, as shown in FIG. 4A, a gate oxide film 13 is formed on the body region 12, and a polysilicon film 1a is formed on the entire surface. Then, the polysilicon film 1a is patterned to form the gate polysilicon electrode 1. Thereafter, N-type ion implantation is performed on the source / drain.

Next, as shown in FIG. 4B, a P-type impurity 14 such as boron (B) is implanted into the body contact region 4 using the photoresist 52 as a mask. Then, as shown in FIG. 4C, the body contact region 4 is made P ⁺ -type by activating the P-type impurity 14 by heat treatment. Thereafter, although not shown, an interlayer insulating film is formed on the surface, contacts to the gate, source, drain, and body are formed, and metal wiring is formed, whereby the transistor is completed.

  As described above, by making the bottom surface of the isolation silicon film lower than the bottom surface of the body region, the isolation silicon film can be made thicker by about 2.5 to 4 times. Can be reduced to 1 / 2.5-1 / 4.

Embodiment 2. FIG.
An SOI-MOS transistor according to the second embodiment of the present invention will be described with reference to FIG. However, the same number is attached | subjected to the component similar to FIG. 1, and description is abbreviate | omitted.

  As shown in the figure, in the vicinity of the boundary with the isolation silicon film 20, the bottom surface of the body region 12 has a tapered shape that becomes lower as the isolation silicon film 20 is approached. Specifically, the inside of the body region 12 is thicker than the center portion from the end by the difference between the lower surface of the body region 12 and the lower surface of the separated lower silicon film 20. Other configurations are the same as those in the first embodiment.

Next, a method for manufacturing the SOI-MOS transistor according to the second embodiment will be described. First, as shown in FIG. 6A, an insulating film 11, a P ⁻ type silicon film 12a, and a mask nitride film 50 are sequentially stacked on a silicon substrate 10. Then, photoresist patterns 51 a and 51 b are formed on the mask nitride film 50.

  Next, as shown in FIG. 6B, the mask nitride film 50 is anisotropically etched using the photoresist patterns 51a and 51b as masks to form nitride films 50a and 50b. Thereafter, the photoresist patterns 51a and 51b are removed. Then, the silicon film 12a is anisotropically etched to the bottom using the nitride films 50a and 50b as a mask to form a trench 15 in the silicon film 12a. The silicon film 12 a separated by the trench 15 becomes the body region 12 and the body contact region 4.

  Next, as shown in FIG. 6C, the insulating film 11 is isotropically etched by wet etching with hydrofluoric acid or the like, so that the body region 12 and the body contact region 4 have the same dimension as the lower scraped dimension. Undercut 16 is formed below.

  Next, as shown in FIG. 6D, selective epitaxial growth is performed under ELO (Epitaxial Lateral Overgrowth) conditions, and the silicon films 20a, 20b, 20c, 20d is grown and the trench 15 and the undercut 16 are embedded.

  Next, as shown in FIG. 7A, anisotropic etching is performed so that the silicon films 20a, 20b, 20c, and 20d remain by a desired thickness, and the body region 12 and the body contact region 4 are connected. A separated silicon film 20 is formed. Note that the epitaxial film may be etched back after non-selective epi growth instead of selective epi growth.

  Then, as shown in FIG. 7B, the trench 15 is filled with a silicon oxide film having good filling characteristics, and the silicon oxide film is polished by a flattening method such as CMP to expose the nitride films 50a and 50b. The silicon oxide film remaining in the trench 15 becomes an isolation oxide film 5 that separates the body region 12 and the body contact region 4. Thereafter, nitride films 50a and 50b are removed, and impurity doping and heat treatment for adjusting the resistance of body region 12 and adjusting the impurity concentration of the channel portion are performed.

  Next, as shown in FIG. 7C, a gate oxide film 13 is formed on the body region 12, and a polysilicon film 1a is formed on the entire surface. Then, the polysilicon film 1a is patterned to form the gate polysilicon electrode 1. Thereafter, N-type ion implantation is performed on the source / drain. Further, using the photoresist 52 as a mask, a P-type impurity 14 such as boron (B) is implanted into the body contact region 4.

Next, as shown in FIG. 7D, the P-type impurity 14 is activated by heat treatment, so that the body contact region 4 is made P ⁺ -type. Thereafter, although not shown, an interlayer insulating film is formed on the surface, contacts to the gate, source, drain, and body are formed, and metal wiring is formed, whereby the transistor is completed.

  As described above, the contact area between the body region 12 and the silicon film can be increased by forming the bottom surface of the body region in the vicinity of the boundary with the isolation silicon film so as to become lower as it approaches the isolation silicon film. Therefore, the resistance can be further reduced as compared with the first embodiment.

Embodiment 3 FIG.
An SOI-MOS transistor according to Embodiment 3 of the present invention will be described with reference to FIG. However, the same number is attached | subjected to the component similar to FIG. 1, and description is abbreviate | omitted.

In the present embodiment, the impurity concentration of the silicon film 20 under separation is 10 ¹⁸ to 10 ¹⁹ cm ⁻³ , which is higher than that in the first embodiment. Further, impurities are diffused from the separated silicon film 20 to the end of the body region 12. Other configurations are the same as those in the first embodiment.

  Next, a method for manufacturing the SOI-MOS transistor according to the third embodiment will be described. First, the steps from FIG. 1A to FIG. 3A are performed as in the first embodiment.

  Next, as shown in FIG. 9A, using the nitride films 50a and 50b as a mask, a P-type impurity 22 such as boron (B) is ion-implanted into the silicon film 20 under isolation.

  Next, as shown in FIG. 9B, the trench 15 is filled with a silicon oxide film having good filling characteristics, and the silicon oxide film is polished by a planarization method such as CMP to expose the nitride films 50a and 50b. The silicon oxide film remaining in the trench 15 becomes an isolation oxide film 5 that separates the body region 12 and the body contact region 4. Also, the implanted P-type impurity 22 is activated by heat when the silicon oxide film is buried, and a high concentration impurity region 21 is formed.

  Next, as in the first embodiment, the gate oxide film 13 and the gate polysilicon electrode 1 are formed on the body region 12, and N-type ion implantation is performed on the source and drain.

  Next, as shown in FIG. 9C, a P-type impurity 14 such as boron (B) is implanted into the body contact region 4 using the photoresist 52 as a mask.

Then, by activating the P-type impurity 14 by heat treatment, the body contact region 4 is made P ⁺ -type. At that time, impurities in the high concentration impurity region 21 diffuse to the bottom of the silicon film 20 under separation and the body region 12. Thereafter, although not shown, an interlayer insulating film is formed on the surface, contacts to the gate, source, drain, and body are formed, and metal wiring is formed, whereby the transistor is completed.

  In the above example, the impurity doping is performed on the silicon under the isolation oxide film in a self-aligned manner. However, the impurity may be doped at a desired position using a photoresist as a mask.

  As described above, by making the impurity concentration of the silicon film under isolation higher than the impurity concentration of the body region, the resistance can be further reduced as compared with the first embodiment. Specifically, the resistance of this portion can be reduced to 1/10 to 1/20 of the conventional one by increasing the impurity concentration of the silicon film by about one digit compared with the first embodiment.

Embodiment 4 FIG.
An SOI-MOS transistor according to Embodiment 4 of the present invention will be described with reference to FIG. However, the same number is attached | subjected to the component similar to FIG. 1, and description is abbreviate | omitted.

  As shown in the figure, the isolation silicon film 20 has a high-concentration impurity region 21 having an impurity concentration higher than that of the body region 12 inside the boundary with the body region 12. Other configurations are the same as those of the third embodiment.

  Next, a method for manufacturing the SOI-MOS transistor according to the fourth embodiment will be described. First, the steps from FIG. 1A to FIG. 3A are performed as in the first embodiment.

  Next, as shown in FIG. 11A, an oxide film of the same type as the buried isolation oxide film 5 is deposited and anisotropically etched to form sidewalls on the side surfaces of the body region 12 and the body contact region 4, respectively. 23a and 23b are formed. Then, using the nitride films 50a and 50b and the sidewalls 23a and 23b as masks, a P-type impurity 22 such as boron (B) is ion-implanted into the silicon film 20 under separation.

  Next, as shown in FIG. 11B, the trench 15 is filled with a silicon oxide film having good filling characteristics, and the silicon oxide film is polished by a planarization method such as CMP to expose the nitride films 50a and 50b. At this time, the side walls 23a and 23b are also flattened simultaneously. The silicon oxide film remaining in the trench 15 becomes an isolation oxide film 5 that separates the body region 12 and the body contact region 4. Further, the implanted impurity is activated by heat when the silicon oxide film is buried, and the high concentration impurity region 21 is formed.

  Next, as in the first embodiment, the gate oxide film 13 and the gate polysilicon electrode 1 are formed on the body region 12, and N-type ion implantation is performed on the source and drain.

  Next, as shown in FIG. 11C, a P-type impurity 14 such as boron (B) is implanted into the body contact region 4 using the photoresist 52 as a mask.

Then, by activating the P-type impurity 14 by heat treatment, the body contact region 4 is made P ⁺ -type. At this time, the impurities in the high concentration impurity region 21 are also diffused to the bottom of the isolation silicon film 20. However, the impurities in the high concentration impurity region 21 do not diffuse up to the body region 12. Thereafter, although not shown, an interlayer insulating film is formed on the surface, contacts to the gate, source, drain, and body are formed, and metal wiring is formed, whereby the transistor is completed.

  In the above example, the impurity doping is performed on the silicon under the isolation oxide film in a self-aligned manner. However, the impurity may be doped at a desired position using a photoresist as a mask.

  As described above, since the impurity concentration of the silicon film under isolation is higher than the impurity concentration of the body region, the resistance can be reduced as in the third embodiment. Further, since the impurities in the silicon film under separation do not ooze out into the body region, there is no concern that the characteristics will be changed by affecting the impurity profile of the channel.

Embodiment 5. FIG.
A method for manufacturing an SOI-MOS transistor according to the fifth embodiment of the present invention will be described.

First, as shown in FIG. 12A, an insulating film 101, a P ^- type silicon film 102, a silicon oxide film 103, and a silicon nitride film 104 are sequentially stacked on a silicon substrate (not shown). Then, a resist film is applied to the entire surface, and a resist pattern 105 for trench formation is formed by photolithography.

  Next, as shown in FIG. 12B, the silicon nitride film 104, the silicon oxide film 103, and the silicon film 102 are anisotropically etched using the resist pattern 105 as a mask to form a trench.

  Next, after forming a silicon oxide film 107 by thermal oxidation on the inner wall of the trench 106 as shown in FIG. 12C, along the inner wall of the trench 106 by plasma oxidation as shown in FIG. A silicon oxide film 108 having a thickness of 10 to 100 nm that does not fill the trench 106 is formed conformally. However, the silicon oxide film 108 may not be conformal. Further, a silicon nitride film or a polysilicon film may be used instead of the silicon oxide film 108. Then, the step of forming the silicon oxide film 107 may be omitted.

  Next, as shown in FIG. 13A, an impurity 109 is ion-implanted into the silicon film 102 under the central portion of the trench 106 through the silicon oxide film 108 to form an impurity implantation region 110.

  Then, as shown in FIG. 13B, the trench 106 is filled with the silicon oxide film 111, and the annealing is performed by annealing.

  Next, as shown in FIG. 13C, the silicon oxide films 107 and 108 are polished by CMP to flatten the surface.

  Then, as shown in FIG. 13D, after the silicon nitride film 104 is removed, impurities are implanted as channel implantation.

  Next, as shown in FIG. 14A, after the silicon oxide film 103 is removed, a gate insulating film 112 is formed. Then, as shown in FIG. 14B, a polycrystalline silicon film 113 for the gate electrode is formed on the entire surface. Thereafter, a normal MOS flow is performed to manufacture a MOS transistor.

  As described above, by implanting impurities after forming a silicon oxide film in the trench, the resistance of the silicon film under separation can be reduced. Further, by implanting impurities only in the central part of the trench, the impurities in the silicon film under separation do not exude into the body region, so that there is no concern of affecting the impurity profile of the channel and changing the characteristics. Further, since the impurity is implanted after the silicon oxide film is formed, it is possible to suppress the implantation damage to the separated silicon film that causes the junction leakage. Since the silicon film under the isolation oxide film is thinner in the SOI-MOS transistor than in the non-SOI MOS transistor, impurities can be implanted with relatively low energy (5 to 50 KeV in boron), and a protective film such as a photoresist. There is no need to protect the active area.

It is sectional drawing which shows the SOI-MOS transistor which concerns on Embodiment 1 of this invention. FIG. 6 is a cross-sectional view (part 1) illustrating the manufacturing process of the SOI-MOS transistor according to the first embodiment of the invention; FIG. 6 is a cross-sectional view (No. 2) showing the manufacturing process of the SOI-MOS transistor according to the first embodiment of the invention; FIG. 6 is a sectional view (No. 3) showing a manufacturing step of the SOI-MOS transistor according to the first embodiment of the invention; It is sectional drawing which shows the SOI-MOS transistor which concerns on Embodiment 2 of this invention. It is sectional drawing (the 1) which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 2 of this invention. It is sectional drawing (the 2) which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the SOI-MOS transistor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the SOI-MOS transistor which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 4 of this invention. It is sectional drawing (the 1) which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 5 of this invention. It is sectional drawing (the 2) which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 5 of this invention. It is sectional drawing (the 3) which shows the manufacturing process of the SOI-MOS transistor which concerns on Embodiment 5 of this invention. It is the top view (a) and sectional drawing (b) which show the conventional SOI-MOS transistor. It is sectional drawing (the 1) which shows the manufacturing process of the conventional SOI-MOS transistor. It is sectional drawing (the 2) which shows the manufacturing process of the conventional SOI-MOS transistor.

Explanation of symbols

4 Body contact region 5 Isolation oxide film 11 Insulating film 12 Body region 15 Trench 16 Undercut 20 Underlying silicon film 21 High-concentration impurity region 23a, 23b Side wall 50 Mask nitride film 50a, 50b Nitride film 101 Insulating film (first Insulating film)
102 Silicon film 103 Silicon oxide film (second insulating film)
104 Silicon nitride film (second insulating film)
106 trench 108 silicon oxide film (third insulating film)
110 Impurity implantation region 111 Silicon oxide film (fourth insulating film)

Claims (6)

An insulating film;
A body region provided on the insulating film and having a channel and a source / drain;
On the insulating film, a body contact region provided apart from the body region,
An isolation oxide film separating the body region and the body contact region;
An isolation silicon film provided under the isolation oxide film and connecting the body region and the body contact region;
The SOI-MOS transistor, wherein the bottom surface of the isolation silicon film is lower than the bottom surface of the body region.   2. The SOI-MOS transistor according to claim 1, wherein the bottom surface of the body region has a shape that becomes lower toward the isolation silicon film in the vicinity of the boundary with the isolation silicon film.   3. The SOI-MOS transistor according to claim 1, wherein the isolation silicon film has a region having an impurity concentration higher than that of the body region.   4. The SOI-MOS transistor according to claim 3, wherein the region having an impurity concentration higher than that of the body region is located on an inner side than an end of the isolation silicon film. Forming a semiconductor film over the first insulating film;
Forming a second insulating film on the semiconductor film;
Etching the second insulating film and the semiconductor film to form a trench;
Forming a third insulating film along the inner wall of the trench;
Ion-implanting the semiconductor film under the trench through the third insulating film;
A method of manufacturing an SOI-MOS transistor, wherein the surface is planarized after the trench is filled with a fourth insulating film. 6. The method of manufacturing an SOI-MOS transistor according to claim 5, wherein a silicon oxide film or a silicon nitride film is used as the third insulating film.

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