JP2007096958A - Agc circuit and high frequency receiving apparatus equipped with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AGC circuit which switches reference voltages of variable gain type amplifiers 18/19/20 so that a variable gain type amplifying means 18 of the first stage has the maximum gain, or that a variable gain type amplifying means 20 of the last stage has the maximum gain among the variable gain type amplifiers 18/19/20, and also to provide a high frequency receiving apparatus equipped with the AGC circuit. <P>SOLUTION: The AGC circuit 60 is provided with: fixed gain type amplifying means 14/15 which amplify high frequency signals, and the variable gain type amplifying means 18/19/20 which perform amplify one of output signals selected by an amplifier selection signal, one by one, among output signals of the fixed gain type amplifying means 14/15. The AGC circuit 60 is further provided with a gain control means 2 which switches reference voltages V1-V3 of the variable gain type amplifying means 18/19/20, based on the amplifier selection signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automatic gain control circuit (hereinafter referred to as an AGC circuit) included in a high-frequency receiver that receives digital television broadcasts and the like.

  FIG. 12 shows a configuration of a conventional high-frequency receiving device 100.

  The high-frequency receiving device 100 includes an RF unit A that converts a high-frequency signal into an orthogonal baseband signal, and a demodulator B that digitally converts the orthogonal baseband signal and demodulates it by phase recovery / timing recovery. Yes. Hereinafter, configurations of the RF unit A and the demodulation unit B will be described.

  First, the RF unit A includes an RF input terminal 13, fixed gain amplifiers 14 and 15, amplifier selection signal input terminal 16, amplifier selection circuit 17, variable gain amplifiers 18, 19, and 20, gain control signal input terminal 21, gain Control circuit 22, voltage controlled local oscillator (hereinafter referred to as VCO) 23, local oscillator 24, PLL circuit 25, loop filter 26, 90 ° phase shifter 27, mixer circuits 28 and 29, low pass filter (hereinafter referred to as LPF) Description: 30 and 31, I baseband signal output terminal 32, and Q baseband signal output terminal 33.

  The RF input terminal 13 is a terminal to which a high frequency signal transmitted from a broadcasting station is input.

  The fixed gain amplifiers 14 and 15 have different gains (gain of the fixed gain amplifier 14> gain of the fixed gain amplifier 15), and amplify the high-frequency signals input from the RF input terminal 13, respectively.

  The amplifier selection circuit 17 selects and outputs one of the high-frequency signals amplified and output by the fixed gain amplifiers 14 and 15 based on the amplifier selection signal input from the amplifier selection signal input terminal 16.

  The amplifier selection signal is input from the outside, and causes the amplifier selection circuit 17 to select a fixed gain amplifier that can obtain a required characteristic according to the level of the high-frequency signal.

  The variable gain amplifiers 18, 19, and 20 have different gains, and amplify the high-frequency signals output from the amplifier selection circuit 17 in order.

  The gain control circuit 22 controls the gains of the variable gain amplifiers 18, 19 and 20 based on the gain control signal input from the gain control signal input terminal 21. The gain control signal will be described later.

  The VCO 23 outputs a local signal for frequency-converting the high-frequency signal into the orthogonal baseband signal.

  The local oscillator 24 outputs a reference frequency signal of the local signal.

  The PLL circuit 25 performs feedback control of the VCO 23 with the reference frequency signal as a reference so that the local signal converges to a value corresponding to a set period.

  The loop filter 26 balances the output of the PLL circuit 25 and inputs it to the VCO 23.

  The 90 ° phase shifter 27 generates a 90 ° phase shift signal by shifting the phase of the local signal by 90 °, and outputs a 0 ° phase shift signal that does not shift the phase of the local signal.

  The mixer circuits 28 and 29 perform frequency conversion of the high-frequency signal in order to detect the orthogonal baseband signals of I and Q. The mixer circuit 28 converts the signal into an I baseband signal using the 0 ° phase shift signal output from the 90 ° phase shifter 27. The mixer circuit 29 uses the 90 ° phase shift signal output from the 90 ° phase shifter 27 to convert the signal into a Q baseband signal.

  The LPFs 30 and 31 pass the frequency band of the orthogonal baseband signal and block other unnecessary frequency components.

  The I baseband signal output terminal 32 and the Q baseband signal output terminal 33 output the orthogonal baseband signal to the demodulator B, respectively.

  Next, the demodulator B includes an I baseband signal input terminal 34, a Q baseband signal input terminal 35, analog-digital converters (hereinafter referred to as ADC) 36 and 37, a VCO 38, a numerically controlled oscillator (hereinafter referred to as NCO). 39), complex arithmetic unit 40, FIR filter 41/42, phase / frequency detector 43, timing detector 44, level detector 45, loop filter 46/47/48, digital-analog converter (hereinafter referred to as DAC) Description) 49, 50, I output terminal 52, Q output terminal 53, and gain control signal output terminal 54. The level detector 45, the loop filter 46, and the DAC 49 constitute a gain control signal generation circuit 51. Further, the VCO 38 and the loop filters 46, 47, and 48 have the same configuration as the VCO 28 and the loop filter 26 described above, and thus description thereof is omitted.

  The orthogonal baseband signals output from the I baseband signal output terminal 32 and the Q baseband signal output terminal 33 are input to the I baseband signal input terminal 34 and the Q baseband signal input terminal 35, respectively.

  The ADCs 36 and 37 sample the orthogonal baseband signal at the oscillation frequency output from the VCO 38 and convert it into a digital signal (digital modulated wave).

  The NCO 39 outputs a sine wave and a cosine wave for demodulating the digital signal by the complex arithmetic unit 40.

  The complex computing unit 40 multiplies the digital signal by the sine wave and cosine wave.

  The FIR filters 41 and 42 pass the frequency band of the digital signal complex-multiplied by the complex computing unit 40, and cut off other unnecessary frequency components.

  The phase / frequency detector 43 detects a phase / frequency error generated in the transmission path.

  The timing detector 44 detects a timing error that has occurred in the transmission path.

  As described above, the gain control signal generation circuit 51 includes the level detector 45, the loop filter 46, and the DAC 49, detects the level error generated in the transmission path, and performs the variable gain amplifiers 18, 19, and 20 The gain control signal for feedback control of the gain is generated.

  The DAC 49 converts the digital signal into an analog signal.

  The I output terminal 52 and the Q output terminal 53 output the digital signal output from the FIR filters 41 and 42.

  The gain control signal output terminal 54 outputs the gain control signal output from the gain control signal generation circuit 51 to the gain control signal input terminal 21.

  Next, the processing operation of the high frequency receiving apparatus 100 having the above configuration will be described.

  The high frequency signals input from the RF input terminal 13 are amplified by the fixed gain amplifiers 14 and 15, respectively. Of the output signals, only one of the output signals is output from the amplifier selection circuit 17, and is sequentially amplified by the variable gain amplifiers 18, 19, and 20 whose gains are controlled by the gain control circuit 22, respectively.

  After that, the frequency is converted into the orthogonal baseband signal by the mixer circuits 28 and 29 and is output from the I baseband signal output terminal 32 and the Q baseband signal output terminal 33 to the demodulator B via the LPFs 30 and 31.

  The orthogonal baseband signals input via the I baseband signal input terminal 34 and the Q baseband signal input terminal 35 are digitally converted by the ADCs 36 and 37. The orthogonal baseband signal is thereafter processed with a digital signal.

  The digital signals digitally converted by the ADCs 36 and 37 are demodulated by complex multiplication with the sine wave and cosine wave output from the NCO 39 by the complex arithmetic unit 40, and output through the FIR filters 41 and 42 to the I output. Output from terminal 52 and Q output terminal 53.

  In the processing operation as described above, a phase / frequency error, a timing error, and a level error occur in the transmission path. Hereinafter, correction of phase / frequency errors, timing errors, and level errors generated in the transmission path will be described.

  First, regarding the correction of the phase / frequency error, the phase / frequency error is detected by the phase / frequency detector 43 from the outputs of the FIR filters 41 and 42. The detection result is balanced by the loop filter 47 and the sine wave and cosine wave output from the NCO 39 are adjusted. As a result, the phase / frequency error is corrected.

  Next, with respect to the correction of the timing error, the timing detector 44 detects the timing error from the outputs of the FIR filters 41 and 42 as in the case of the correction of the phase / frequency error. The detection result is balanced by the loop filter 48, converted to an analog signal by the DAC 50, and the oscillation frequency of the VCO 38 is controlled. As a result, the timing error is corrected.

  Finally, the level error is corrected in two stages. First, in the first stage, the amplifier selection circuit 17 selects the fixed gain amplifiers 14 and 15 according to the level of the high frequency signal.

  In the second stage, the gain control signal generation circuit 51 generates the gain control signal, and feedback controls the gains of the variable gain amplifiers 18, 19, and 20 using the gain control signal. .

  Specifically, the level detector 45 provided in the gain control signal generation circuit 51 detects the level error from the outputs of the ADCs 36 and 37, the detection result is balanced by the loop filter 46, and converted into an analog signal by the DAC 49. Thus, the gain control signal is generated. The gain control signal is input to the gain control circuit 22 via the gain control signal output terminal 54 and the gain control signal input terminal 21, and the gains of the variable gain amplifiers 18, 19, and 20 are feedback-controlled. This is repeated until the output of the variable gain amplifier 20 reaches a predetermined value. As a result of such two-stage correction, the level error is corrected.

  Next, the level error correction will be described in more detail with reference to FIGS. Prior to the description, configuration examples of the gain control circuit 22 and the variable gain amplifiers 18, 19, and 20 will be described with reference to FIG. FIG. 13 is a diagram illustrating a configuration example of the gain control circuit 22 and the variable gain amplifiers 18, 19, and 20. The DC power sources V1 to V3 provided in the gain control circuit 22 are reference voltages for the variable gain amplifiers 18, 19, and 20, and have a relationship of V1> V2> V3.

  As shown in the figure, the variable gain amplifier 18 includes three transistor differential pairs Q1 and Q2, Q3 and Q4, and Q5 and Q6, each of which includes an NPN transistor. Source I1 is connected. Further, the emitters of the transistor differential pairs Q3 and Q4 and Q5 and Q6 are respectively connected to the collectors of the transistors Q1 and Q2 of the transistor differential pair Q1 and Q2, and the transistor differential pairs Q3 and Q4 are connected to the collectors of the transistor differential pairs Q3 and Q6. Loads are connected to the collectors of the transistors Q3, Q4, Q5, and Q6, respectively.

  The gain control signal is input to the base of the transistor Q3 of the transistor differential pair Q3 and Q4 and the base of the transistor Q6 of the transistor differential pair Q5 and Q6, and the transistor Q4 of the transistor differential pair Q3 and Q4 The reference voltage V3 is applied to the base of the transistor Q5 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6.

  The variable gain amplifiers 19 and 20 have the same configuration as described above, and the bases of the transistors Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 19 and the transistors Q5 of the transistor differential pair Q5 and Q6. The reference voltage V2 is applied to the base, and the reference voltage V2 is applied to the base of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 20 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6. V1 is applied.

  The bases of the transistor differential pairs Q1 and Q2 of the variable gain amplifiers 18, 19, and 20 are the differential input terminals in18 to in20, respectively, and the collectors of the transistors Q3 of the transistor differential pairs Q3 and Q4. A connection point between the load and a connection point between the collector of the transistor Q6 of each transistor differential pair Q5 and Q6 and the load are the differential output terminals out18 to out20.

  The differential input terminal in18 of the variable gain amplifier 18 is connected to the output of the amplifier selection circuit 17, and the differential output terminal out18 of the variable gain amplifier 18 is connected to the differential input terminal in19 of the variable gain amplifier 19. ing. The differential output terminal out19 of the variable gain amplifier 19 is connected to the differential input terminal in20 of the variable gain amplifier 20, and the differential output terminal out20 of the variable gain amplifier 20 is connected to the inputs of the mixer circuits 28 and 29. Has been.

  Next, the level error correction operation will be described with reference to FIGS. Here, a high-frequency signal of −70 dBm is input, the level correction as described above (the second stage) is performed so as to be converted into a baseband signal of 0 dBm and output to the demodulator B, and then − A case will be described as an example where a 20 dBm high-frequency signal is input, and level correction is performed again so that it is similarly converted to a 0 dBm baseband signal and output to the demodulator B. The fixed gain amplifier 14 has a gain of 20 dB, and the fixed gain amplifier 15 has a gain of 0 dB.

  FIG. 14 is a diagram showing the relationship between the gains of the variable gain amplifiers 18, 19, and 20. FIG. 15 shows that a high frequency signal of −70 dBm is input, and the fixed gain amplifier 14 is FIG. 16 shows the result of the level correction that has been selected so that the baseband signal is 0 dBm. FIG. 16 shows that a high frequency signal of −20 dBm is input, and the fixed gain amplifier 15 is selected by the amplifier selection circuit 17. , The result of level correction again so as to obtain a baseband signal of 0 dBm is shown.

  Hereinafter, the level error correction operation will be described. First, when a high-frequency signal of −70 dBm is input and the level correction is completed, the variable gain amplifiers 18, 19, and 20 are as shown in FIG. Each has a gain of 20 dB, 20 dB, and 10 dB. Further, the gain control signal S3 when the level correction is completed is as shown in FIG.

  Next, when the high frequency signal of −20 dBm is input, the fixed gain amplifier 15 is selected by the amplifier selection signal, and then the high frequency signal is sequentially amplified by the variable gain amplifiers 18, 19, and 20. The At this time, since the gains of the variable gain amplifiers 18, 19, and 20 remain 20 dB, 20 dB, and 10 dB, the high-frequency signal output from the variable gain amplifier 20 becomes −30 dBm.

Therefore, until the gain control signal generation circuit 51 generates a new gain control signal and the output of the variable gain amplifier 20 becomes 0 dBm, the gain of the variable gain amplifiers 18, 19, and 20 is repeatedly feedback controlled. Is done. As a result, as shown in FIG. 16, the variable gain amplifiers 18, 19, and 20 have gains of 20 dB, 10 dB, and −10 dB, respectively, and the gain control signal S4 at this time is as shown in FIG. . That is, the gains of the variable gain amplifiers 18, 19, and 20 are feedback controlled from the gain control signal S3 to the gain control signal S4.
Japanese Patent Laid-Open No. 9-46140 (published on February 24, 1997) JP 10-22755 A (published January 23, 1998)

  By the way, when the range of the input level is wide as in the above-described level error correction, each of the variable gain amplifiers 18, 19, and 20 requires good NF characteristics and distortion characteristics.

  More specifically, as shown in FIG. 15, a high-frequency signal of −70 dBm is input and level correction is completed. As a result, the maximum level of the high-frequency signal in the middle is −10 dBm input to the variable gain amplifier 20. . However, as shown in FIG. 16, a high frequency signal of −20 dBm is input and level correction is completed. As a result, the maximum level of the high frequency signal in the middle reaches 10 dBm at the input of the variable gain amplifier 20, and variable gain is obtained. The type amplifier 20 may cause signal distortion.

  The reason why such a problem occurs is that the reference voltages V3, V2, and V1 are applied to the variable gain amplifiers 18, 19, and 20, respectively, as is apparent from FIG. That is, no matter what feedback control is performed, the gain of each of the variable gain amplifiers 18, 19, and 20 is always the gain of the variable gain amplifier 18> the gain of the variable gain amplifier 19> the variable gain amplifier 20. The relationship of gain is obtained.

  The variable gain amplifiers 18, 19, and 20 have such a gain relationship in consideration of the C / N ratio (Carrier / Noise) when the level of the input high-frequency signal is low, so that the NF characteristics are not deteriorated. Because. However, when the level of the input high-frequency signal is high, there is a risk of causing the signal distortion as described above. In order to avoid such signal distortion, it is necessary to pass a large amount of current, and power consumption Leads to an increase in

  The present invention has been made in view of the above problems, and an object thereof is an AGC circuit capable of freely controlling the gains of a plurality of variable gain amplifiers according to the level of an input high-frequency signal. And a high-frequency receiving device including the same.

  In order to solve the above problems, an AGC circuit according to the present invention includes a plurality of fixed gain amplifying means for amplifying a high frequency signal, and a plurality of output signals of the fixed gain amplifying means according to the level of the high frequency signal. A plurality of serially connected variable gain amplification means for sequentially amplifying the output signals selected by the amplifier selection signal for selecting any one of the output signals, and the plurality of variable gain amplification means A gain control signal for feedback-controlling the gains of the plurality of variable gain amplifiers is input from the outside so that the output of the variable gain amplifier of the final stage has a predetermined value. The change range of the gain control signal corresponding to the change range of the gain of the plurality of variable gain amplifiers that change by feedback control with a signal is In the AGC circuit translating the reference voltage is set for each variable gain amplifying means having, on the basis of the amplifier selection signal, it is characterized in that it comprises a gain control means for switching the reference voltage.

  According to the above configuration, the AGC circuit includes gain control means for switching the reference voltage based on the amplifier selection signal. Accordingly, there is an effect that the gains of the plurality of variable gain amplification means can be freely controlled according to the level of the input high frequency signal.

  In the AGC circuit according to the present invention, in addition to the above configuration, the gain control means preferably has an option of switching the reference voltage so that the first-stage variable gain amplification means has the maximum gain.

  According to the above configuration, the gain control means of the AGC circuit has an option of switching the reference voltage so that the first-stage variable gain amplification means has the maximum gain. As a result, the NF characteristic can be improved.

  In the AGC circuit according to the present invention, in addition to the above configuration, the gain control means preferably has an option of switching the reference voltage so that the variable gain amplification means at the final stage has the maximum gain.

  According to said structure, the said gain control means of the said AGC circuit has an option which switches the said reference voltage so that the variable gain type amplification means of the last stage may have the maximum gain. Thus, there is an effect that the high-frequency signal level is not increased unnecessarily during amplification by the plurality of variable gain amplification means, and distortion of the high-frequency signal can be made difficult to occur.

  In the AGC circuit according to the present invention, in addition to the above configuration, the gain control means preferably includes an amplifier selection signal generation means for generating the amplifier selection signal.

  According to the above configuration, the gain control means of the AGC circuit includes the amplifier selection signal generation means for generating the amplifier selection signal. Accordingly, there is an additional effect that both the plurality of fixed gain amplification units and the plurality of variable gain amplification units can be controlled by themselves without inputting the amplifier selection signal from the outside.

  In the AGC circuit according to the present invention, in addition to the above configuration, the amplifier selection signal generation means includes a comparison means for comparing the gain control signal with a comparison value having a hysteresis characteristic. Preferably, the amplifier selection signal is generated.

  According to the above configuration, the amplifier selection signal generation means includes comparison means for comparing the gain control signal with a comparison value having hysteresis characteristics, and generates the amplifier selection signal from the comparison result by the comparison means.

  Here, for example, when the comparison value does not have a hysteresis characteristic, the amplifier selection signal generation means cannot obtain an accurate comparison result, and therefore cannot accurately generate the amplifier selection signal. Since the plurality of fixed gain amplifiers are switched by the amplifier selection signal, the gain control signal may fluctuate and the AGC circuit may operate normally if the accurate amplifier selection signal cannot be obtained. Can not.

  On the other hand, since the amplifier selection signal generating means has a hysteresis characteristic in the comparison value, an accurate comparison result can be obtained and an accurate amplifier selection signal can be generated. Thereby, there is an additional effect that the plurality of fixed gain amplification means are prevented from being switched unnecessarily.

  In addition to the above-described configuration, the AGC circuit according to the present invention does not connect the fixed gain amplification means that outputs an output signal that is not selected among the plurality of output signals to a power source based on the amplifier selection signal. It is preferable that power supply control means is provided.

  According to the above configuration, the AGC circuit includes a power supply that prevents the fixed gain amplification means that outputs an unselected output signal from the plurality of output signals from being connected to a power supply based on the amplifier selection signal. Supply control means is provided. Thereby, there is a further effect that wasteful power can be reduced and noise can be suppressed.

  A high frequency receiving apparatus according to the present invention includes the AGC circuit.

  According to said structure, the said high frequency receiver is provided with the said AGC circuit. Accordingly, there is an effect that the gains of the plurality of variable gain amplification means can be freely controlled according to the level of the input high frequency signal.

  Since the AGC circuit according to the present invention and the high frequency receiver including the AGC circuit include gain control means, the gains of a plurality of variable gain amplifiers can be freely controlled according to the level of the input high frequency signal. There is an effect that can be.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 shows a configuration of a high-frequency receiving device 60 including an AGC circuit 10A according to the present embodiment. Since the high-frequency receiving device 60 has the same configuration as the high-frequency receiving device 100 shown in the above prior art, members having the same reference numerals as the high-frequency receiving device 100 have the same functions unless otherwise specified. Description of the configuration and operation thereof will be omitted.

  As shown, the AGC circuit 10A includes fixed gain amplifiers 14 and 15 (fixed gain amplification means), amplifier selection circuit 17, variable gain amplifiers 18, 19, and 20 (variable gain amplification means), and gain control. The circuit 2 (gain control means) is used.

  FIG. 2 shows a detailed configuration of the AGC circuit 10A. As described above, the AGC circuit 10A includes the fixed gain amplifiers 14 and 15, the amplifier selection circuit 17, the variable gain amplifiers 18, 19, and 20, and the gain control circuit 2. For the sake of simplicity, only the configurations of the variable gain amplifiers 18, 19, 20 and the gain control circuit 2 are shown. The fixed gain amplifiers 14 and 15, the amplifier selection circuit 17, and the variable gain amplifiers 18, 19, and 20 have the same configuration as that shown in the above prior art. Omitted.

  As shown in the figure, the gain control circuit 2 includes the same number of switches A, B, and C as the number of variable gain amplifiers 18, 19, and 20, and each of the switches A, B, and C includes two CMOS analog switches. It is composed of Hereinafter, the CMOS analog switches provided in the switch A are A1 and A2, and similarly, the CMOS analog switches provided in the switches B and C are B1 and B2, and C1 and C2.

  The configuration will be described in detail. The amplifier selection signal is inputted as it is to the gate of the p-channel MOSFET of the CMOS analog switch A1 and the gate of the n-channel MOSFET of the CMOS analog switch A2, and the CMOS analog switch A1 The amplifier selection signal is input via the NOT circuit 1 to the gate of the n-channel MOSFET and the gate of the p-channel MOSFET of the CMOS analog switch A2.

  Similarly, the amplifier selection signal is directly input to the gates of the p-channel MOSFETs of the CMOS analog switches B1 and C1 and the gates of the n-channel MOSFETs of the CMOS analog switches B2 and C2, respectively. The amplifier selection signal is input via the NOT circuit 1 to the gates of the n-channel MOSFETs of the switches B1 and C1 and the gates of the p-channel MOSFETs of the CMOS analog switches B1 and C1, respectively.

  The current output terminal of the switch A is connected to the bases of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 18 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6.

  Similarly, the current output terminals of the switches B and C are respectively connected to the bases of the transistors Q4 of the transistor differential pairs Q3 and Q4 of the variable gain amplifiers 19 and 20, and the transistors of the transistor differential pairs Q5 and Q6. It is connected to the base of Q5.

  The current output terminal of the switch A is a connection between the current output terminal of the CMOS analog switch A1 and the current output terminal of the CMOS analog switch A2. Similarly, the current output terminals of the switches B and C are the same. Are connected to the current output terminals of the CMOS analog switches B1 and C1 and the current output terminals of the CMOS analog switches B2 and C2.

  The bases of the transistors Q3 of the transistor differential pairs Q3 and Q4 of the variable gain amplifiers 18, 19 and 20 and the bases of the transistors Q6 of the respective transistor differential pairs Q5 and Q6 are described above. The gain control signal is input as shown in the prior art.

  Further, the reference voltage V3 is applied to the current input terminals of the CMOS analog switches A1 and C2, the reference voltage V1 is applied to the current input terminals of the CMOS analog switches A2 and C1, and the CMOS analog switches B1 and B2 A reference voltage V2 is applied to each current input terminal. The reference voltages V1, V2, and V3 have a relationship of V1> V2> V3 as shown in the above prior art.

  Next, the operation of the AGC circuit 10A will be described with reference to FIGS. In the following description, a low-level high-frequency signal is input after a high-level high-frequency signal has already been input to the AGC circuit 10A (hereinafter referred to as an initial state), and then a high-level high-frequency signal is again input. A case where the state transitions to a state in which is input will be described as an example.

  FIG. 3 shows the gains of the variable gain amplifiers 18, 19, and 20 when a low-frequency high-frequency signal is input from the initial state, and FIG. 4 shows a high level again from the state of FIG. 3. The gains of the variable gain amplifiers 18, 19, and 20 when high-frequency signals are input are shown.

  When the level of the input high frequency signal is low, the amplifier selection signal is L (low), and when it is input to the amplifier selection circuit 17, the fixed gain amplifier 14 having a high gain is selected. On the other hand, when the level of the input high frequency signal is high, the amplifier selection signal is H (high), and when it is input to the amplifier selection circuit 17, the fixed gain amplifier 15 having a low gain is selected. In the following description, the selection of the fixed gain amplifier by the amplifier selection circuit 17 is omitted.

  Further, in each of the CMOS analog switches of the switches A, B, and C included in the gain control circuit 2, when the L amplifier selection signal is input to the p-channel MOSFET and the H amplifier selection signal is input to the n-channel MOSFET, the CMOS Assume that the analog switch is turned on.

  Further, in the AGC circuit 10A in the initial state, the gain control signal S0 and the amplifier selection signal of H output from the gain control signal generation circuit 51 are input to the gain control circuit 2, and the variable gain amplifier 18 is input to the variable gain amplifier 18. Assume that the reference voltage V1 is applied, the reference voltage V2 is applied to the variable gain amplifier 19, and the reference voltage V3 is applied to the variable gain amplifier 20. The operation will be described below.

  When a low-level high-frequency signal is input to the AGC circuit 10A in the initial state as described above, an L amplifier selection signal is newly input to the gain control circuit 2 to which the gain control signal S0 is input.

  The amplifier selection signal of L is input to the switches A, B, and C through the NOT circuit 1 as they are. As described above, in the CMOS analog switches of the switches A, B, and C, when the L amplifier selection signal is input to the p-channel MOSFET and the H amplifier selection signal is input to the n-channel MOSFET, the CMOS analog switch is Turn on. Therefore, in this case, the CMOS analog switches A1, B1, and C1 of the switches A, B, and C are turned on.

  Here, as described above, the switches A, B, and C include the bases of the transistors Q4 of the transistor differential pairs Q3 and Q4 of the variable gain amplifiers 18, 19, and 20, and the transistors of the transistor differential pairs Q5 and Q6. The transistor Q5 is connected to the base of the transistor Q5.

  Therefore, when the CMOS analog switches A1, B1, and C1 are turned ON, the base of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 18 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6 are The reference voltage V3 is applied, and the reference voltage V1 is applied to the bases of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 20 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6. . Note that the reference voltage V2 is applied to the variable gain amplifier 19 as it is.

  Thereafter, a level error is detected by the gain control signal generation circuit 51 from the outputs of the ADCs 36 and 37, and a new gain control signal is generated and input to the gain control circuit 2. By the gain control signal, the gains of the variable gain amplifiers 18, 19, and 20 are subjected to feedback control many times and level correction is performed. The gain control signal S1 when the level correction is completed is as shown in FIG. That is, the gains of the variable gain amplifiers 18, 19, and 20 are feedback controlled from the gain control signal S0 to the gain control signal S1.

  Next, when a high-level high-frequency signal is input from the above state, an H amplifier selection signal is newly input to the gain control circuit 2 to which the gain control signal S1 is input. The H amplifier selection signal is input to the switches A, B, and C through the NOT circuit 1 as they are. As a result, in this case, the CMOS analog switches A2, B2, and C2 of the switches A, B, and C are turned on.

  When the switches A2, B2, and C2 are turned ON, the reference voltage V1 is again applied to the bases of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 18 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6. Is applied, and the reference voltage V3 is again applied to the bases of the transistor Q4 of the transistor differential pair Q3 and Q4 of the variable gain amplifier 20 and the base of the transistor Q5 of the transistor differential pair Q5 and Q6.

  Thereafter, a level error is detected by the gain control signal generation circuit 51 from the outputs of the ADCs 36 and 37, and a new gain control signal is generated and input to the gain control circuit 2. By the gain control signal, the gains of the variable gain amplifiers 18, 19, and 20 are subjected to feedback control many times and level correction is performed. The gain control signal S when the level correction is completed is as shown in FIG. That is, the gains of the variable gain amplifiers 18, 19, and 20 are feedback controlled from the gain control signal S1 to the gain control signal S2.

  As described above, the AGC circuit 10A according to the present embodiment and the high-frequency receiving device 60 including the AGC circuit 10A are variable gain amplifiers 18 and 19 according to the amplifier selection signal, that is, according to the level of the input high-frequency signal. • 20 reference voltages can be switched. Thereby, when the level of the input high frequency signal is low, the reference voltages of the variable gain amplifiers 18, 19, and 20 can be switched so that the first stage variable gain amplifier 18 has the maximum gain. The characteristics can be improved.

  On the other hand, when the level of the input high-frequency signal is high, the reference voltages of the variable gain amplifiers 18, 19, and 20 can be switched so that the final stage variable gain amplifier 20 has the maximum gain. It is possible to prevent the level of the high-frequency signal from increasing excessively during amplification. That is, distortion of the high-frequency signal can be made difficult to occur without increasing power consumption.

  In the operation of the AGC circuit 10A as described above, an example in which level correction is performed so that a high frequency signal of −20 dBm is actually input, converted into a baseband signal of 0 dBm, and output to the demodulator B is an example. As shown in FIG. This case corresponds to the case where the high-level high-frequency signal described above is input. That is, since the H amplifier selection signal is input, the fixed gain amplifier 15 is selected, and the gains of the variable gain amplifiers 18, 19, and 20 are respectively −10 dB, 10 dB, Feedback control is performed so as to have a gain of 20 dB. The gain of the fixed gain amplifier 15 is 0 dB.

  From the figure, it can be seen that the maximum level of the high-frequency signal during amplification by the variable gain amplifiers 18, 19, and 20 is -20 dBm. As a result, it can be seen that the AGC circuit 10A prevents the level of the high-frequency signal from increasing unnecessarily during amplification and makes it difficult to cause distortion of the high-frequency signal.

[Embodiment 2]
Another embodiment of the present invention will be described below with reference to FIGS.

  FIG. 6 shows a configuration of a high-frequency receiving device 70 including the AGC circuit 10B according to the present embodiment. Since the high-frequency receiving device 70 has the same configuration as the high-frequency receiving device 100 shown in the prior art, members having the same reference numerals as those of the high-frequency receiving device 100 have the same functions unless otherwise described. The description of the configuration and operation is omitted.

  FIG. 7 shows a detailed configuration of the AGC circuit 10B. 7, only the configuration of the variable gain amplifiers 18, 19, and 20 and the gain control circuit 6 is shown for simplification of FIG. The gain control circuit 6 includes an amplifier selection signal generation circuit 4 (amplifier selection signal generation means) as shown in the figure, in addition to the configuration of the gain control circuit 2 included in the AGC circuit 10A. Therefore, the configuration and operation of the AGC circuit 10B have the same function as the AGC circuit 10A unless otherwise described, and the amplifier selection signal generation circuit 4 will be mainly described below.

  The amplifier selection signal generation circuit 4 includes a comparator 3 (comparison means) and a switch D including two CMOS analog switches D1 and D2, and an amplifier using the gain control signal output from the gain control signal generation circuit 51 A selection signal is generated.

  The gain control signal is used for feedback control of the gains of the variable gain amplifiers 18, 19, and 20 according to the level of the input high-frequency signal, so that the approximate input level is set by the gain control signal. I can know. The result of comparing this with the following comparison value can be used as the amplifier selection signal.

  The configuration will be described in detail. The gain control signal is connected to the negative input terminal of the comparator 3, and the current output terminal of the switch D is connected to the positive input terminal. Note that the current output terminal of the switch D is a connection between the current output terminal of the CMOS analog switch D1 and the current output terminal of the CMOS analog switch D2.

  The comparison values V5 and V4 are connected to the current input terminals of the CMOS analog switches D1 and D2, respectively. The gate of the p-channel MOSFET of the CMOS analog switch D1 of the switch D and the n-channel MOSFET of the CMOS analog switch D2 The amplifier selection signal generated by the comparator 3 is directly input to the gate of the n-channel MOSFET of the CMOS analog switch D1 and the gate of the p-channel MOSFET of the CMOS analog switch D2. An amplifier / amplifier selection signal generated by the comparator 3 is input through the NOT circuit 5.

  Next, the operation of the amplifier selection signal generation circuit 4 will be described with reference to FIGS. In the following description, as in the description of the operation of the AGC circuit 1A shown in the first embodiment, a low-level high-frequency signal is input from the initial state, and then a high-level high-frequency signal is input again. A case of transition to a state will be described as an example.

  FIG. 8 shows the respective gains of the variable gain amplifiers 18, 19, and 20 when a low-level high-frequency signal is input from the initial state, and FIG. 9 shows a high-level high-frequency signal from the state of FIG. The gains of the variable gain amplifiers 18, 19, and 20 when signals are input are shown.

  In the AGC circuit 10B in the initial state, an H amplifier selection signal is output from the comparator based on the gain control signal S0 and input to the gain control circuit 6 and to the switch D. In the switch D, the CMOS analog switch D2 is turned on, and the comparator 3 is connected to the comparison value V4.

  When a low-frequency high-frequency signal is input from the initial state as described above, the gain control signal generation circuit 51 detects the level of the high-frequency signal, and a gain control signal S1 is newly output. Is input. The gain control signal S1 is larger than the gain control signal S0 in the initial state because the level of the newly input high-frequency signal is low.

  When such a gain control signal S1 is input to the comparator 3 and is larger than the comparison value V4, an L amplifier selection signal is output from the comparator 3. The L amplifier selection signal is input to the amplifier selection circuit 17, the gain control circuit 2, and the switch D.

  In the amplifier selection circuit 17, the fixed gain amplifier 14 is selected in accordance with the L amplifier selection signal, and the gain control circuit 2 is variable so as not to deteriorate the NF characteristic as described in the first embodiment. The gains of the gain amplifiers 18, 19 and 20 are controlled. In the switch D, the CMOS analog switch D1 is turned on, and the comparison value V5 is connected to the comparator.

  Next, when a high-frequency signal having a high level is input again from the above state, the gain control signal generation circuit 51 detects the level of the high-frequency signal, and a gain control signal S2 is newly output. 6 is input. The gain control signal S2 is smaller than the gain control signal S1 because the level of the newly input high-frequency signal is high.

  When such a gain control signal S2 is input to the comparator 3 and is smaller than the comparison value V5, the comparator 3 outputs an H amplifier selection signal. The H amplifier selection signal is input to the amplifier selection circuit 17, the gain control circuit 2, and the switch D.

  In the amplifier selection circuit 17, the fixed gain amplifier 15 is selected according to the H amplifier selection signal, and the gain control circuit 2 makes it difficult to cause signal distortion as described in the first embodiment. The gains of the variable gain amplifiers 18, 19, and 20 are controlled. In the switch D, the CMOS analog switch D2 is turned on again, and the comparison value V4 is connected to the comparator.

  Next, switching of the comparison values V4 and V5 according to the amplifier selection signal in the operation of the amplifier selection signal generation circuit 4 as described above will be described.

  For example, when the comparison value of the comparator 3 is only the comparison value V4, that is, when the comparator 3 does not have hysteresis characteristics, a high-frequency signal having a high level is input again from the state of FIG. Think about the case.

  In this case, as described above, the gain control signal generation circuit 51 detects the level of the high-frequency signal, and the gain control signal S2 is newly output and input to the gain control circuit 6. The gain control signal S2 is input to the comparator 3, and if it is smaller than the comparison value V5, an H amplifier selection signal is output from the comparator 3. However, since the comparison value is only the comparison value V4 at this time, the H amplifier selection signal is output from the comparator 3 when it becomes smaller than the comparison value V4. That is, an accurate amplifier selection signal is not generated. Since the fixed gain amplifiers 14 and 15 are selected based on the amplifier selection signal, if the amplifier selection signal is not accurate, the fixed gain amplifiers 14 and 15 are switched in conjunction with each other. As a result, the gain control signal fluctuates, and the AGC circuit 10B and the high-frequency receiving device 60 having the same cannot operate normally.

  Therefore, the amplifier selection signal generation circuit 4 includes the comparison values V4 and V5 as described above, and is configured to switch the comparison values V4 and V5 according to the amplifier selection signal, so that the comparator 3 has hysteresis characteristics. Is given. As a result, an accurate amplifier selection signal can be generated, and the fixed gain amplifiers 14 and 15 can be prevented from being switched unnecessarily.

  As described above, the AGC circuit 10B according to the present embodiment and the high-frequency receiving device 60 including the same use the gain control signal generated by the gain control signal generation circuit 51 to generate an amplifier selection signal. A selection signal generation circuit 4 is provided. Thereby, the fixed gain amplifiers 14 and 15 and the variable gain amplifiers 18, 19 and 20 can be controlled by themselves without inputting the amplifier selection signal from the outside. The amplifier selection signal generation circuit 4 compares the gain control signal with a comparison value having hysteresis characteristics, and generates the amplifier selection signal from the comparison result. As a result, an accurate amplifier selection signal can be generated, and fluctuations in the gain control signal due to unnecessary switching of the fixed gain amplifiers 14 and 15 can be prevented.

[Embodiment 3]
Another embodiment of the present invention will be described below with reference to FIGS.

  FIG. 10 shows a configuration when the power supply control circuit 7 (power supply control means) is provided in the high-frequency receiving device 60 including the AGC circuit 10A according to the first embodiment. In the present embodiment, the case where the AGC circuit 10A includes the power supply control circuit 7 will be described as an example. However, the present invention is not limited to this configuration, and the AGC circuit 10B may include the power supply control circuit 7.

  FIG. 11 shows a configuration of the power supply control circuit 7 and a connection example thereof.

  The power supply control circuit 7 includes a switch E composed of two CMOS analog switches E1 and E2. The gate of the p-channel MOSFET of the CMOS analog switch E1 and the gate of the n-channel MOSFET of the CMOS analog switch E2 are: The amplifier selection signal is input as it is, and the amplifier amplifier selection signal is input via the NOT circuit 1 to the gate of the n-channel MOSFET of the CMOS analog switch E1 and the gate of the p-channel MOSFET of the CMOS analog switch E2. The

  The current input terminal of the switch E is connected to a power source (not shown), and the current output terminals of the CMOS analog switches E1 and E2 are connected to the fixed gain amplifiers 14 and 15, respectively, as shown. Note that the current input terminal of the switch E is a connection between the current input terminal of the CMOS analog switch E1 and the current input terminal of the CMOS analog switch E2.

  Next, the operation of the power supply control circuit 7 will be described.

  As described in the first embodiment, when the level of the input high-frequency signal is low, an L amplifier selection signal is input to the AGC circuit 10A. When the L amplifier selection signal is input to the switch E, the CMOS analog switch E1 is turned on, and the fixed gain amplifier 14 is connected to the power source. On the other hand, when the level of the input high-frequency signal is high, an H amplifier selection signal is input to the AGC circuit 10A. When the H amplifier selection signal is input to the switch E, the CMOS analog switch E2 is turned on, and the fixed gain amplifier 15 is connected to the power source.

  As described above, the power supply control circuit 7 can connect or not connect one of the fixed gain amplifiers 14 and 15 to the power supply according to the amplifier selection signal. That is, a fixed gain amplifier capable of obtaining a required characteristic is connected to a power supply in accordance with the level of an input high-frequency signal, and a fixed gain amplifier which cannot obtain a required characteristic is not connected to a power supply. Thereby, useless power reduction and noise can be suppressed.

  Further, since only one of the fixed gain amplifiers 14 and 15 is connected to the power source by the power supply control circuit 7, if the output terminals of the fixed gain amplifiers 14 and 15 are connected to each other, the power supply control is performed. The circuit 7 can also serve as the amplifier selection circuit 17. For this reason, when the power supply control circuit 7 is provided, the amplifier selection circuit 17 need not be provided.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The AGC circuit of the present invention can be suitably used for a high-frequency receiving device that receives digital television broadcasting or the like.

1, showing an embodiment of the present invention, is a block diagram showing a high-frequency receiving device including an AGC circuit 10A according to the present invention. It is a circuit diagram which shows the structure of a part of AGC circuit 10A. It is a figure which shows the processing operation of AGC circuit 10A. It is a figure which shows the processing operation of AGC circuit 10A. FIG. 5 is a diagram specifically showing the processing operation of the AGC circuit 10A in FIG. Another embodiment of the present invention is shown, and is a block diagram showing a high-frequency receiving device including an AGC circuit 10B according to the present invention. It is a circuit diagram which shows the structure of a part of AGC circuit 10B. It is a figure which shows the processing operation of AGC circuit 10B. It is a figure which shows the processing operation of AGC circuit 10B. 14 is a block diagram showing a high-frequency receiving device including an AGC circuit 10A according to the present invention, showing still another embodiment of the present invention. FIG. It is a circuit diagram which shows the structure of the power supply circuit with which AGC circuit 10A is provided, and the example of a connection. It is a block diagram which shows the conventional high frequency receiver. It is a circuit diagram which shows a part of structure of the said high frequency receiver. It is a figure which shows the processing operation of the said high frequency receiver. It is the figure which showed concretely the processing operation of the said high frequency receiver. It is the figure which showed concretely the processing operation of the said high frequency receiver.

Explanation of symbols

2, 6 Gain control circuit (gain control means)
3 comparator (comparison means)
4. Amplifier selection signal generation circuit (amplifier selection signal generation means)
7 Power supply control circuit (Power supply control means)
14.15 Fixed Gain Amplifier (Fixed Gain Amplifier)
18.19.20 Variable Gain Amplifier (Variable Gain Amplifier)
60, 70, 100 high frequency receiver

Claims (7)

A plurality of fixed gain amplification means for amplifying a high-frequency signal;
A plurality of serially amplifying the output signals selected by an amplifier selection signal for selecting any one of the plurality of output signals of the fixed gain amplification means according to the level of the high frequency signal. Connected variable gain amplification means,
A gain control signal for feedback-controlling the gains of the plurality of variable gain amplification means so that the output of the last stage variable gain amplification means has a predetermined value among the plurality of variable gain amplification means. Input from outside,
A change range of the gain control signal corresponding to a change range of the gain of the plurality of variable gain type amplifying means that is changed by feedback control by the gain control signal is set for each of the plurality of variable gain type amplifying means. In an AGC circuit that translates according to a reference voltage,
An AGC circuit comprising gain control means for switching the reference voltage based on the amplifier selection signal.   2. The AGC circuit according to claim 1, wherein the gain control means has an option of switching the reference voltage so that the first-stage variable gain amplification means has a maximum gain.   2. The AGC circuit according to claim 1, wherein the gain control means has an option of switching the reference voltage so that the last stage variable gain amplification means has the maximum gain.   The AGC circuit according to any one of claims 1 to 3, wherein the gain control means includes amplifier selection signal generation means for generating the amplifier selection signal. The amplifier selection signal generation means includes a comparison means for comparing the gain control signal with a comparison value having a hysteresis characteristic,
5. The AGC circuit according to claim 4, wherein the amplifier selection signal is generated from a comparison result by the comparison means.   A power supply control means for preventing the fixed gain amplification means for outputting an output signal not selected from the plurality of output signals from being connected to a power supply in response to the amplifier selection signal. Item 6. The AGC circuit according to any one of Items 1 to 5.   A high frequency receiver comprising the AGC circuit according to claim 1.

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