JP2007036621A - Automatic gain control circuit and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic gain control circuit, capable of preventing power consumption from increasing even if the value of the power supply voltage is shifted, and to provide a receiver. <P>SOLUTION: The receiver 1 is provided with an RF block 2 and a demodulation block 3. The RF block 2 includes a discrete variable-gain amplifier 4, mixers 5a, 5b, and continuous variable-gain amplifiers 7a, 7b. The demodulation block 3 includes AD converters 8a, 8b, a gain control circuit 9 having a gain control voltage generator 10 and a DA converter 8, and a gain switching control circuit 12 for generating a gain-switching signal S1 to switch the gain of the discrete variable-gain amplifier 4, on the basis of a gain control voltage CTRL. The RF block 2 further includes a gain control voltage correction circuit 14 for generating a corrected gain control voltage CTRLcrt, generated by correcting the shift of an analog gain control voltage CTRLA generated due to the shift of a power supply voltage VDDDAC from a standard value, on the basis of the analog gain control voltage CTRLA and the power supply voltage VDDDAC of the gain control circuit 9. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automatic gain control (AGC) circuit and a receiver that automatically adjusts the gain of an input signal, and more particularly to an AGC circuit and a receiver that input a high-frequency signal to receive digital television broadcasting or the like.

  Receivers that receive digitally modulated high frequency signals are widely known. FIG. 5 is a block diagram showing a configuration of a conventional receiver 90. The receiver 90 includes an RF block 92 that converts a high-frequency signal into a low-frequency signal such as a baseband, and a demodulation block 93 that demodulates a digital modulated wave converted to a low frequency by phase reproduction / timing reproduction or the like. .

  The RF block 92 has an RF input terminal 79 to which a high frequency signal transmitted from a broadcasting station is input. The high frequency signal input to the RF input terminal 79 is applied to the continuous variable gain amplifier 97c, and the continuous variable gain amplifier 97c amplifies the high frequency signal.

  The RF block 92 is provided with a voltage controlled local oscillator (VCO) 62. The VCO 62 outputs a local signal whose frequency is controlled by a control voltage to the 90 ° phase shifter 61 and the PLL circuit 63 in order to frequency-convert the high-frequency signal into a baseband signal. The PLL circuit 63 performs feedback control on the basis of the signal from the local oscillator 64 so that the local signal converges to a value corresponding to the set period. This feedback signal (VCO control signal) is input from the VCO control terminal 65 to the VCO 62.

  The 90 ° phase shifter 61 generates a 90 ° phase shift signal in which the phase of the local signal from the VCO 62 is shifted by 90 ° based on the local signal output from the VCO 62, together with a 0 ° local signal that does not shift the phase. The signals are output to the mixers 95b and 95a, respectively.

  The mixers 95b and 95a convert the frequency of the high-frequency signal in order to detect the orthogonal baseband signals of I and Q. The mixer circuit 95a demodulates the high-frequency signal into an I baseband signal using the 0 ° signal output from the 90 ° phase shifter 61. The mixer circuit 95b demodulates the high frequency signal into a Q baseband signal using the 90 ° phase shift signal output from the 90 ° phase shifter 61. The two mixer circuits 95a and 95b demodulate the received high frequency signal into an orthogonal baseband signal. Low-pass filters (LPF) 96a and 96b block frequency components other than the desired band from the outputs of the mixers 95a and 96b, respectively. Continuous variable gain amplifiers 97a and 97b amplify the outputs of LPFs 96a and 96b, respectively. The amplification factors of the continuous variable gain amplifiers 97a, 97b, and 97c are controlled by the control signal input from the amplifier control terminal 86.

  The baseband signal frequency-converted in the RF block 92 is sampled at the ADC 98 a and 98 b in the demodulation block 93 by the oscillation frequency of the VCO 66 and digitally converted. The baseband signal is thereafter processed by the digital signal.

  The outputs of the ADCs 98 a and 98 b are complex multiplied by cos Δθ and sin Δθ output from the numerically controlled oscillator (NCO) 55 by the complex arithmetic unit 68. The complex multiplied signal is output from the I output terminal 51 and the Q output terminal 52 after the frequency components other than the desired band are cut off by the FIR filters 69 and 50.

  Further, the demodulation block 93 corrects phase / frequency errors, timing errors and level errors generated in the transmission path. As for the phase / frequency error, the phase / frequency error is detected by the phase / frequency detector 53 using the outputs of the FIR filters 69 and 50. The detection result is balanced by the loop filter 54, and Δθ of the NCO 55 is adjusted. As a result, the phase / frequency error is removed.

  The timing error is detected by the timing detector 56 using the outputs of the FIR filters 69 and 50 and balanced by the loop filter 57. The balanced result is converted to an analog signal by the DAC 58 and output from the VCO control terminal 67. The oscillation frequency of the VCO 66 is controlled by this output signal. As a result, timing errors are removed.

  As for the level error, the level error is detected by the level detector 74 using the outputs of the ADCs 98a and 98b, and is balanced by the loop filter 75. The balanced result is converted into an analog signal by the DAC 81. The analog-converted signal is input from the amplifier control terminal 86 of the RF block 92, and controls the continuous variable gain amplifiers 97a, 97b, and 97c in the RF block 92. This eliminates level errors.

  In such a receiver, the RF block 92 must have excellent noise characteristics and linearity. This is because if the noise characteristic is poor, the reception sensitivity is deteriorated, and if the linearity is bad, the signal is distorted when a signal having a strong electric field strength is received, and the system characteristic is deteriorated.

  When the receivable electric field strength required by the system is in a wide range, the desired noise characteristics and linearity will be realized by combining a variable gain amplifier whose gain changes continuously and a single gain amplifier. Then, there is a problem that power consumption increases.

  Therefore, in recent years, in addition to a variable gain amplifier whose gain continuously changes, when the input level is low, a high gain path with excellent noise characteristics is adopted, and when the input level is high, In many cases, a variable gain amplifier that switches gains discretely is realized, which is realized by means such as adopting a low-gain path having excellent linearity. According to the configuration of the discrete variable gain amplifier, since it is not necessary to achieve both linearity and noise characteristics through one path, signals with a wide range of input levels can be received with low power consumption. This discrete variable gain amplifier is often used as a low noise amplifier in the first stage of RF input.

  As a means for switching the gain of such a discrete variable gain amplifier, the electric field strength of the received signal is detected by the electric field strength detecting means, and when the detected electric field strength is higher than a predetermined value, a low noise amplifier (discrete There has been proposed a receiver for reducing the gain of a dynamic variable gain amplifier (see, for example, Patent Document 1). However, for the field strength detection, it is common to add the rectifier circuit and the amplifier circuit and the rectifier circuit in cascade. The method of adding the output of the rectifier circuit is generally used, but it is necessary to increase the number of cascaded stages for high-precision field strength detection Therefore, there is a problem that the circuit scale becomes very large, leading to an increase in manufacturing cost.

  As a means for avoiding this problem, a gain control signal of a variable gain amplifier whose gain changes continuously is detected, and the detected gain control signal controls the gain of the continuous variable gain amplifier below a predetermined value. In some cases, there is a method of reducing the gain of the discrete variable gain amplifier (see, for example, Patent Document 2 and Patent Document 3). FIG. 6 is a block diagram showing the configuration of another conventional receiver 90a. The same components as those described above with reference to FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The receiver 90a includes an RF block 92a. A discrete variable gain amplifier 94 is provided in the RF block 92a. The discrete variable gain amplifier 94 amplifies the high frequency signal input to the RF input terminal 79 and supplies the amplified signal to the continuous variable gain amplifier 97c.

  The receiver 90a includes a demodulation block 93a. The demodulation block 93 a is provided with a gain control circuit 99 and a gain switching control circuit 82. The gain control circuit 99 and the gain switching control circuit 82 operate by the power supply voltage supplied from the power supply 83.

  The gain control circuit 99 has a gain control voltage generation unit 80. The gain control voltage generator 80 is provided with a level detector 74. The level detector 74 detects a level error based on the outputs of the ADCs 98a and 98b. The gain control voltage generation unit 80 includes a loop filter 75. The loop filter 75 balances the level error detected by the level detector 74 to generate a digital controllable gain control voltage CTRL and supplies it to the DAC 81 and the gain switching control circuit 82. The DAC 81 generates an analog gain control voltage CTRLA obtained by analog conversion of the gain control voltage CTRL generated by the loop filter 75, and outputs the analog gain control voltage CTRLA to the continuous variable gain amplifiers 97a, 97b, and 97c of the RF block 92a.

  The gain switching control circuit 82 outputs a comparison result between the gain control signal CTRL generated by the loop filter 75 and a preset threshold value as a gain switching signal S1, and controls gain switching of the discrete variable gain amplifier 94. To do. The comparison between the threshold value and the gain control signal CTRL can be easily realized by digital processing. Further, since the RF block does not require a means for detecting the electric field strength, the means for switching the gain of the discrete variable gain amplifier is used. Can be realized at low cost.

  7A and 7B show the relationship between the input level of the high-frequency signal input to the receiver 90a and the gains of the discrete variable gain amplifier 94 and the continuous variable gain amplifiers 97a, 97b, and 97c. (A) shows the transition of the gain when the input level increases, and (b) shows the transition of the gain when the input level decreases.

  The operation when the discrete variable gain amplifier switches between two gains, high gain and low gain, will be described. As shown in FIG. 7A, when the input level increases and exceeds the threshold Th1, and further exceeds the threshold Th2 larger than the threshold Th1, the gain of the discrete variable gain amplifier is changed from g1. It is switched to g2 smaller than g1. The RF block 92a operates as an AGC and operates so that the output level is constant regardless of the input level at the RF input terminal 79. Therefore, when the input level is low and the gain of the discrete variable gain amplifier is set high as g1 (input level <Th2), when the input level is high, the gain of the continuous variable gain amplifier is continuously increased. Lower (upper graph in FIG. 7A). When the input level exceeds the threshold Th2, the gain of the discrete variable gain amplifier is switched from g1 to g2, and when the threshold Th2 is reached so as to keep the output level constant, the continuously variable gain amplifier is switched. The gain of the amplifier is increased stepwise from g3 to g4. When the input level further increases beyond the threshold Th2, the gain of the continuously variable gain amplifier is continuously reduced from g4 so as to keep the output level constant.

  As shown in FIG. 7B, conversely, when the input level decreases and falls below the threshold value Th2, and further falls below the threshold value Th1, the gain of the discrete variable gain amplifier is switched from g2 to g1. . When the input level is high and the gain of the discrete variable gain amplifier is set low as g2 (input level> Th1), the gain of the continuous variable gain amplifier is continuously increased as the input level decreases. (Upper graph in FIG. 7B). When the input level falls below the threshold value Th1, the gain of the discrete variable gain amplifier is switched from g2 to g1, and when the input level decreases and reaches the threshold value Th1 so as to keep the output level constant. The gain of the continuous variable gain amplifier is decreased stepwise from g5 to g6. Further, when the input level decreases below the threshold Th1, the gain of the continuous variable gain amplifier is continuously increased from g6 so as to keep the output level constant.

In order to stably switch the high gain / low gain of the discrete variable gain amplifier, the threshold Th1 and the threshold Th2 have a relationship of Th1 <Th2.
Japanese Patent Laid-Open No. 7-30445 (published January 31, 1995) JP 2003-198405 A (July 11, 2003 (2003. 7.11.) JP 2002-290254 A (October 4, 2002 (2002. 10.4)

  However, in the conventional configuration described with reference to FIG. 6 described above, when the power supply voltage supplied from the power supply 83 to the gain control circuit 99 deviates from the standard value, the output of the DAC 81 deviates. There arises a problem that the gain switching point of the variable gain amplifier 94 is shifted. Details will be described below.

  FIG. 8 is a graph showing the relationship between the gain control voltage CTRL and the analog gain control voltage CTRLA in the gain control circuit 99. As the DAC 81 provided in the gain control circuit 99, a resistor string type DAC is generally used. The output of the resistor string type DAC is proportional to the power supply voltage supplied from the power supply 83.

  That is, as shown in FIG. 8, even if the threshold Th_D for switching the gain of the discrete variable gain amplifier 94 is constant, the analog gain control voltage CTRLA output via the DAC 81 is gain control. The circuit 99 shifts like Th_AH and Th_AL in accordance with the deviation of the value of the power supply voltage supplied from the power supply 83. That is, when the power supply voltage is a standard value, the value of the analog gain control voltage CTRLA is Th_AN as shown by a straight line L1, but when the power supply voltage is shifted to a value lower than the standard value, it is shown by a straight line L2. On the other hand, the value of the analog gain control voltage CTRLA shifts to a low value of Th_AL, and when it shifts to a value higher than the standard value, it shifts to a high value of Th_AH as indicated by a straight line L3.

  Since the operation of the continuous variable gain amplifier provided in the RF block 92a with respect to the analog gain control voltage CTRLA does not change even when the power supply voltage of the gain control circuit 99 fluctuates, the value of the analog gain control voltage CTRLA itself If the shift occurs, the output value (gain) of the continuous variable gain amplifier shifts. For this reason, the value of the gain control voltage CTRL generated by the gain control voltage generation unit 10 also shifts based on the output value of the continuous variable gain amplifier, and the gain switching control circuit 82 outputs the shifted gain control voltage CTRL. As a result of outputting the gain switching signal S1 to the discrete variable gain amplifier 94 in comparison with the threshold value, a shift occurs in the gain switching point of the discrete variable gain amplifier 94.

The amount of deviation ΔCTRL of the analog gain control voltage CTRLA is assumed that the standard value of the power supply voltage supplied from the power supply 83 to the gain control circuit 99 is VDD_DAC_NOM and the power supply voltage supplied to the gain control circuit 99 is VDD_DAC.
ΔCTRL = CTRLA × (VDD_DAC−VDD_DAC_NOM) / VDD_DAC_NOM,
Thus, the analog gain control voltage is deviated by an amount proportional to the deviation from the standard value of the power supply voltage of the gain control circuit 99.

  Consider a case where a shift occurs in the gain switching point of the discrete variable gain amplifier 94 as described above. When the point where the high gain is switched to the low gain is shifted to the high input level, that is, in FIG. 7A, the input level corresponding to the falling edge where the gain g1 is switched to the gain g2 is higher than the threshold Th2. When it is shifted to a larger value, a higher level than expected is input to the high gain path. That is, an input level higher than the threshold Th2 is input to a high gain path that is assumed to have an input level lower than the threshold Th2. On the other hand, when the point where the low gain is switched to the high gain is shifted to the low input level side, a level lower than expected is input to the low gain path. That is, an input level lower than the threshold Th1 is input to a low gain path that is assumed to have an input level higher than the threshold Th1.

  Accordingly, it is necessary to increase the margins in the linearity and noise characteristics for the high gain path and the low gain path of the discrete variable gain amplifier according to the shift of the switching point. That is, in the low gain path, it is necessary to increase the noise characteristic margin in order to handle an input level lower than expected, and in the high gain path, it is necessary to increase the linearity margin in order to handle an input level higher than expected. Arise.

  In the amplifier circuit, linearity, noise characteristics, and power consumption are in a trade-off relationship. In an amplifier circuit composed of a transistor that amplifies an input signal to the gate terminal, linearity depends on a voltage drop in the emitter resistor RE (emitter current IE × emitter resistor RE). The greater the voltage drop, the better the linearity. The noise characteristic is almost determined by the size of the emitter resistor RE. The smaller the value of the emitter resistance, the better the noise characteristics because the generated thermal noise is smaller. Therefore, when the value of the emitter resistor RE is reduced in order to obtain good noise characteristics, in order to obtain sufficient linearity, it is necessary to increase the emitter current IE in order to increase the voltage drop in the emitter resistor. It leads to increase. As described above, if the margin is increased in noise characteristics and linearity, the power consumption increases.

  Thus, if the power supply voltage of the gain control circuit deviates from the standard value, the gain switching point of the discrete variable gain amplifier will be deviated, so the margin of the linearity and noise characteristics of the discrete variable gain amplifier must be increased. Therefore, there arises a problem that power consumption increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an automatic gain control circuit and a receiver in which power consumption does not increase even when a power supply voltage value is deviated.

  In order to solve the above problems, an automatic gain control circuit of the present invention includes a discrete variable gain amplifier that is a variable gain amplifier whose gain changes discretely, and a front stage side and a rear stage of the discrete variable gain amplifier. A continuous variable gain amplifier that is a variable gain amplifier that is provided on at least one of the sides and whose gain continuously changes, an AD converter that digitally converts the amplified output signal, and the digitally converted continuous signal A gain control voltage generator for receiving a signal based on the output of the static variable gain amplifier and generating a gain control voltage for controlling the gain of the continuous variable gain amplifier; and the analog gain control voltage as the gain control voltage. A gain control circuit having a DA converter for analog conversion to the signal and a gain switching signal for switching the gain of the discrete variable gain amplifier based on the gain control voltage Based on the gain switching control circuit, the analog gain control voltage, and the power supply voltage of the gain control circuit, the deviation of the analog gain control voltage caused by the deviation from the standard value of the power supply voltage is corrected And a gain control voltage correction circuit for generating a correction gain control voltage.

  According to the above configuration, based on the analog gain control voltage analog-converted from the gain control voltage by the DA conversion unit and the power supply voltage of the gain control circuit provided with the DA conversion unit, the standard value of the power supply voltage The gain control voltage correction circuit generates a correction gain control voltage that corrects the deviation of the analog gain control voltage caused by the deviation from. Therefore, the gain of the continuously variable gain amplifier can be controlled by the correction gain control voltage obtained by correcting the deviation of the analog gain control voltage caused by the deviation of the power supply voltage from the standard value.

  For this reason, the deviation of the output value of the continuous variable gain amplifier is reduced, a signal based on the output value of the continuous variable gain amplifier is received, the gain control voltage generator generates, and is input to the gain switching control circuit. The deviation of the gain control voltage value is also reduced. As a result, since the shift of the gain switching signal generated by the gain switching control circuit is reduced, the shift of the gain switching point of the discrete variable gain amplifier can be reduced. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier can be reduced, and an automatic gain control circuit capable of reducing power consumption can be provided.

  In order to solve the above problems, the receiver of the present invention includes an RF block that frequency-converts a high-frequency signal into a baseband signal and amplifies the signal, and a demodulation block that demodulates the baseband signal. A discrete variable gain amplifier, which is a variable gain amplifier whose gain changes discretely, and a variable whose gain is continuously changed by being provided on at least one of the front side and the rear side of the discrete variable gain amplifier. A continuous variable gain amplifier that is a gain amplifier, and the demodulation block includes an AD converter that digitally converts the output of the RF block, and the continuous block based on the output of the digitally converted RF block. A gain control voltage generator for generating a gain control voltage for controlling the gain of the variable gain amplifier; and the gain control voltage is converted into an analog gain control voltage. A gain control circuit having a DA converter for converting, and a gain switching control circuit for generating a gain switching signal for switching the gain of the discrete variable gain amplifier based on the gain control voltage, Based on the analog gain control voltage and the power supply voltage of the gain control circuit, a corrected gain control voltage is generated by correcting the deviation of the analog gain control voltage caused by the deviation from the standard value of the power supply voltage. And a gain control voltage correction circuit.

  According to the above configuration, based on the analog gain control voltage analog-converted from the gain control voltage by the DA conversion unit and the power supply voltage of the gain control circuit provided with the DA conversion unit, the standard value of the power supply voltage A correction gain control voltage that corrects the deviation of the analog gain control voltage caused due to the deviation from is generated by the gain control voltage correction circuit of the RF block. Therefore, the gain of the continuously variable gain amplifier can be controlled by the correction gain control voltage obtained by correcting the deviation of the analog gain control voltage caused by the deviation of the power supply voltage from the standard value.

  Therefore, the deviation of the output value of the continuous variable gain amplifier is reduced, and the gain control voltage generation unit of the demodulation block is generated based on the output value of the continuous variable gain amplifier and is input to the gain switching control circuit. The deviation of the gain control voltage value is also reduced. As a result, since the shift of the gain switching signal generated by the gain switching control circuit of the demodulation block is reduced, the shift of the gain switching point of the discrete variable gain amplifier of the RF block can be reduced. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier can be reduced, and it is possible to provide a receiver that can reduce power consumption.

  In the receiver of the present invention, the gain control voltage correction amount defined by the difference between the correction gain control voltage and the gain control voltage is a deviation from a standard value of the gain control voltage and the power supply voltage of the gain control circuit. It is preferable to be proportional to the amount.

  According to this configuration, the deviation of the analog gain control voltage caused by the deviation from the standard value of the power supply voltage is proportional to the gain control voltage and the deviation amount from the standard value of the power supply voltage of the gain control circuit. By adjusting the gain control voltage correction amount defined by the difference between the correction gain control voltage and the gain control voltage to be proportional to the gain control voltage and the deviation from the standard value of the power supply voltage of the gain control circuit, an analog gain is obtained. The deviation of the control voltage can be completely corrected. Therefore, the deviation of the output value of the continuous variable gain amplifier disappears, and the gain control voltage generator generates the gain control voltage based on the output value of the continuous variable gain amplifier and is input to the gain switching control circuit. The deviation of the voltage value disappears. As a result, since the shift of the gain switching signal generated by the gain switching control circuit disappears, the shift of the gain switching point of the discrete variable gain amplifier can be eliminated. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier can be further reduced, and the power consumption can be further reduced.

  In the receiver of the present invention, the gain control voltage correction circuit includes a transconductance amplifier that generates a gain control voltage correction current based on the analog gain control voltage and the power supply voltage, the gain control voltage, and the gain control voltage. An inverting amplifier circuit that generates the correction gain control voltage based on a correction current, the inverting amplifier circuit having an inverting input terminal to which the gain control voltage is applied, and the inverting input terminal of the operational amplifier. And a resistor for converting the gain control voltage correction current into a voltage.

  According to this configuration, a correction voltage can be added to the analog gain control voltage with a simple circuit configuration.

  In the receiver of the present invention, the inverting amplifier circuit preferably converts the analog gain control voltage into a voltage within a range that can be handled by the continuous variable gain amplifier.

  According to this configuration, the gain of the continuous variable gain amplifier can be controlled based on the analog gain control voltage that can take a wide range of voltage values from the ground potential to the power supply potential.

  In the receiver of the present invention, the gain control voltage correction circuit includes a power supply differential voltage proportional to a deviation from a standard value of the power supply voltage, a gain control voltage proportional current proportional to the analog gain control voltage, and a reference current. A first transconductance amplifier that generates a gain control voltage correction current based on the first control circuit, and a first inverting amplifier circuit that generates the correction gain control voltage based on the gain control voltage and the gain control voltage correction current. The conductance of the first transconductance amplifier is preferably proportional to a current ratio between the gain control voltage proportional current and the reference current and an emitter resistance of the differential amplifier.

  According to this configuration, the correction amount proportional to the deviation of the analog gain control voltage caused by the deviation from the standard value of the power supply voltage can be accurately obtained by a relatively simple circuit without using a complicated multiplication circuit. be able to.

  Here, the transconductance amplifier is an amplifier that inputs voltage and outputs current, and its conversion gain (output current / input voltage) is called conductance (gm).

  In the receiver of the present invention, the gain control voltage correction circuit includes a gain control differential voltage between an output of the second inverting amplifier circuit that inputs the analog gain control voltage and an output of the third inverting amplifier circuit that inputs the ground potential. It is preferable to further include a second transconductance amplifier that generates the gain control voltage proportional current and supplies the gain control voltage proportional current to the first transconductance amplifier.

  According to this configuration, a gain control voltage correction current that is accurately proportional to the analog gain control voltage that can take a wide range of voltage values from the ground potential to the power supply potential can be applied to the first inverting amplifier circuit.

  As described above, the automatic gain control (AGC) circuit according to the present invention is based on the analog gain control voltage and the power supply voltage of the gain control circuit, and the analog gain generated due to the deviation from the standard value of the power supply voltage. A gain control voltage correction circuit is provided that generates a correction gain control voltage in which the deviation of the control voltage is corrected.

  Therefore, the gain of the continuously variable gain amplifier can be controlled by the correction gain control voltage obtained by correcting the deviation of the analog gain control voltage caused by the deviation of the power supply voltage from the standard value. Therefore, the deviation of the output value of the continuous variable gain amplifier is reduced, and the gain control voltage generator generates the gain control based on the output value of the continuous variable gain amplifier and is input to the gain switching control circuit. The voltage deviation is also reduced.

  As a result, since the shift of the gain switching signal generated by the gain switching control circuit is reduced, the shift of the gain switching point of the discrete variable gain amplifier can be reduced. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier can be reduced, and an AGC circuit capable of reducing power consumption can be provided.

  The receiver according to the present invention corrects the deviation of the analog gain control voltage caused by the deviation from the standard value of the power supply voltage based on the analog gain control voltage and the power supply voltage of the gain control circuit in the RF block. A gain control voltage correction circuit for generating the corrected gain control voltage.

  Therefore, the gain of the continuously variable gain amplifier can be controlled by the correction gain control voltage obtained by correcting the deviation of the analog gain control voltage caused by the deviation of the power supply voltage from the standard value. Therefore, the deviation of the output value of the continuous variable gain amplifier is reduced, and the gain control voltage generation unit of the demodulation block is generated based on the output value of the continuous variable gain amplifier and is input to the gain switching control circuit. The deviation of the gain control voltage value is also reduced.

  As a result, since the shift of the gain switching signal generated by the gain switching control circuit of the demodulation block is reduced, the shift of the gain switching point of the discrete variable gain amplifier of the RF block can be reduced. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier can be reduced, and it is possible to provide a receiver that can reduce power consumption.

  An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration of a receiver 1 according to an embodiment of the present invention.

  The receiver 1 includes an RF block 2 that converts a high-frequency signal into a low-frequency signal such as a baseband, and a demodulation block 3 that demodulates a digital modulated wave converted to a low frequency by phase reproduction / timing reproduction or the like. .

  The RF block 2 has an RF input terminal 29 to which a high frequency signal transmitted from a broadcasting station is input. The high-frequency signal input to the RF input terminal 29 is applied to the discrete variable gain amplifier 4, and the discrete variable gain amplifier 4 amplifies the high-frequency signal and supplies it to the continuous variable gain amplifier 7c. The continuous variable gain amplifier 7c amplifies this high frequency signal.

  The RF block 2 is provided with a voltage controlled local oscillator (VCO) 32. The VCO 32 outputs a local signal whose frequency is controlled by a control voltage to the 90 ° phase shifter 31 and the PLL circuit 33 in order to frequency-convert the high-frequency signal into a baseband signal. The PLL circuit 33 performs feedback control using the signal from the local oscillator 34 as a reference so that the local signal converges to a value corresponding to the set period. This feedback signal (VCO control signal) is input from the VCO control terminal 35 to the VCO 32.

  Based on the local signal output from the VCO 32, the 90 ° phase shifter 31 generates a 90 ° phase shift signal in which the phase of the local signal from the VCO 32 is shifted by 90 °, along with a 0 ° local signal that does not shift the phase. Output to mixers 5b and 5a, respectively.

  The mixers 5b and 5a convert the frequency of the high-frequency signal in order to detect the orthogonal baseband signals of I and Q. The mixer circuit 5a demodulates the high-frequency signal into an I baseband signal using the 0 ° signal output from the 90 ° phase shifter 31. The mixer circuit 5b demodulates the high-frequency signal into a Q baseband signal using the 90 ° phase shift signal output from the 90 ° phase shifter 31. By these two mixer circuits 5a and 5b, the received high-frequency signal is demodulated into an orthogonal baseband signal. Low-pass filters (LPF) 6a and 6b block frequency components other than the desired band from the outputs of the mixers 5a and 5b, respectively. The continuous variable gain amplifiers 7a and 7b amplify the outputs of the LPFs 6a and 6b, respectively.

  The baseband signal frequency-converted in the RF block 2 is sampled by the oscillation frequency of the VCO 36 in the ADCs 8a and 8b of the demodulation block 3 and digitally converted. The baseband signal is thereafter processed by the digital signal.

  The outputs of the ADCs 8 a and 8 b are complex multiplied by cos Δθ and sin Δθ output from the numerically controlled oscillator (NCO) 45 by the complex arithmetic unit 38. The complex multiplied signal is output from the I output terminal 41 and the Q output terminal 42 after the frequency components other than the desired band are cut off by the FIR filters 39 and 40.

  Further, the demodulation block 3 corrects phase / frequency errors, timing errors and level errors generated in the transmission path. As for the phase / frequency error, the phase / frequency error is detected by the phase / frequency detector 43 using the outputs of the FIR filters 39 and 40. The detection result is balanced by the loop filter 44, and Δθ of the NCO 45 is adjusted. As a result, the phase / frequency error is removed.

  The timing error is detected by the timing detector 46 using the outputs of the FIR filters 39 and 40 and balanced by the loop filter 47. The balanced result is converted into an analog signal by the DAC 48 and output from the VCO control terminal 37. By this output signal, the oscillation frequency of the VCO 36 is controlled. As a result, timing errors are removed.

  The demodulation block 3 is provided with a gain control circuit 9 and a gain switching control circuit 12. The gain control circuit 9 and the gain switching control circuit 12 operate with the power supply voltage VDDDAC supplied from the power supply 13.

  The gain control circuit 9 includes a gain control voltage generation unit 10. The gain control voltage generator 10 is provided with a level detector 24. The level detector 24 detects a level error based on the outputs of the ADCs 8a and 8b. The gain control voltage generation unit 10 includes a loop filter 25. The loop filter 25 generates a gain control voltage CTRL that can be digitally processed by balancing the level error detected by the level detector 24, and supplies the gain control voltage CTRL to the DAC 11 and the gain switching control circuit 12. The DAC 11 generates an analog gain control voltage CTRLA obtained by analog conversion of the gain control voltage CTRL generated by the loop filter 25 and supplies the analog gain control voltage CTRLA provided in the RF block 2 to the gain control voltage correction circuit 14.

  The gain switching control circuit 12 outputs a comparison result between the gain control signal CTRL generated by the loop filter 25 and a preset threshold value as a gain switching signal S1, and controls gain switching of the discrete variable gain amplifier 4 To do. Comparison between the threshold value and the gain control signal CTRL can be easily realized by digital processing.

  The gain control voltage correction circuit 14 generates an analog signal generated due to a deviation from the standard value of the power supply voltage VDDDAC based on the analog gain control voltage CTRLA supplied from the DAC 11 and the power supply voltage VDDDAC supplied from the power supply 13. A corrected gain control voltage CTRLcrt in which the deviation of the gain control voltage CTRLA is corrected is generated, and the gains of the continuous variable gain amplifiers 7a, 7b, and 7c are controlled.

  FIG. 2 is a circuit diagram for explaining the gain control voltage correction circuit 14. The gain control voltage correction circuit 14 includes a transconductance amplifier (gm amplifier) 15 that generates a gain control voltage correction current Icrt based on the analog gain control voltage CTRLA and the power supply voltage VDDDAC. The gain control voltage correction current Icrt is a current proportional to the analog gain control voltage CTRLA and the deviation from the standard value of the power supply voltage VDDDAC of the gain control circuit. The gm amplifier 15 has a built-in voltage source that generates a standard value of the power supply voltage VDDDAC, compares the standard value with the power supply voltage VDDDAC, calculates a deviation from the standard value, and calculates the gain control voltage correction current Icrt. Generate.

  The gain control voltage correction circuit 14 is provided with an inverting amplifier circuit 18 that generates a correction gain control voltage CTRLcrt based on the analog gain control voltage CTRLA and the gain control voltage correction current Icrt. The inverting amplifier circuit 18 includes an operational amplifier 19. The operational amplifier 19 has an inverting input terminal to which the analog gain control voltage VTRLA is applied through the resistor R6, and a non-inverting input terminal connected to the power source. The inverting amplifier circuit 18 is provided with a resistor R5 connected to the inverting input terminal and the output of the operational amplifier 19. The gain control voltage correction current Icrt is input to a node VC2 between the resistor R5 and the inverting input terminal, and converted into a voltage by the resistor R5. The correction gain control voltage CTRLcrt has an appropriate gain control sensitivity and is a voltage within a range that can be handled by the continuous variable gain amplifier 7a. In this way, the inverting amplifier circuit 18 converts the analog gain control voltage CTRLA into a voltage within a range that can be handled by the continuous variable gain amplifier with appropriate gain control sensitivity.

  The continuous variable gain amplifier 7a is a general voltage controlled variable gain amplifier. An input signal input to the input terminals 26a and 26b is converted into a current by a differential pair of transistors Tr1 and Tr2 connected by an emitter resistor RE. When the correction gain control voltage CTRLcrt applied to the node VC1 is sufficiently larger than the reference voltage VB, no current flows through the transistors Tr4 and Tr5, and the collector currents of the transistors Tr1 and Tr2 pass through the transistors Tr3 and Tr6 and the load resistances RL and RLX. And an amplified voltage output is obtained at the output terminals 27a and 27b. When the correction gain control voltage CTRLcrt applied to the node VC1 decreases, the current flowing through the transistors Tr4 and Tr5 increases, so that the current flowing through the transistors Tr3 and Tr6 to the load resistors RL and RLX decreases, and the voltage gain decreases.

  With the above configuration, the gain control voltage correction current Icrt can be added to the analog gain control signal CTRLA with a simple circuit configuration. Further, since the gm amplifier 15 is additionally arranged in parallel to the inverting amplifier circuit 18 constituting the path of the analog gain control voltage CTRLA, the control signal vs. gain characteristic of the continuous variable gain amplifier by adding the circuit is obtained. There is almost no influence. Further, in a system in which the power supply voltage of the gain control circuit 9 is sufficiently stable and correction is not necessary, it is possible to easily realize a state in which correction is not performed by simply stopping the operation of the gm amplifier 15.

  Here, as a circuit of the continuous variable time amplifier 7a, a circuit that is generally used is shown as an example, but the circuit format is not limited to this.

  In the receiver 1 according to the present embodiment, the discrete variable gain amplifier 4 is provided in the first stage, so that the gain can be discretely changed according to the input level, so that signals of a wide range of input levels are received. Is possible. Further, even when the gain switching point of the discrete variable gain amplifier 4 is deviated due to the power supply voltage of the gain control circuit 9 deviating from the standard value, the gain control voltage correction circuit 14 does not change the analog gain control voltage CTRLA. And a deviation from the standard value of the power supply voltage VDDDAC of the gain control circuit, a corrected gain control voltage CTRLcrt in which the deviation of the output of the DAC 11 is corrected is generated, and the continuous variable gain amplifier 7a is generated by the corrected gain control voltage CTRLcrt.・ Controls 7b and 7c. Therefore, it is possible to correct the shift of the gain switching point of the discrete variable gain amplifier 4. Therefore, the margin of the linearity and noise characteristics of the discrete variable gain amplifier 4 can be reduced, and the power consumption can be reduced.

  Further, the gain control voltage correction amount defined by the difference between the correction gain control voltage CTRLcrt and the analog gain control voltage CTRLA is changed to the analog gain control voltage CTRLA and the deviation amount from the standard value of the power supply voltage VDDDAC of the gain control circuit. By making it proportional, the deviation can be completely compensated. In the present embodiment, the discrete variable gain amplifier 4 is employed as the first-stage low noise amplifier, but it may be used for other circuit blocks including a mixer or the like, or a plurality of them may be used.

  FIG. 3 is a circuit diagram showing a configuration of a modified example of the gain control voltage correction circuit 14. The same components as those described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The gain control voltage correction circuit 14 has a regulator 28. The regulator 28 generates a reference potential that is absolutely stable with reference to the bandgap voltage source, and a reference current that is based on the current that flows through the resistor with the voltage of the bandgap voltage source applied to both ends. A reference potential VREFVDDDAC of the power supply voltage VDDDAC supplied from the power supply 13, a reference potential VREFOP supplied to the operational amplifiers 20 and 21, a reference current Iref supplied to the gm amplifier 16, and a reference potential VREFVGA supplied to the operational amplifier 19 are generated. .

  The gain control voltage correction circuit 14 is provided with an inverting amplifier circuit 22. The inverting amplifier circuit 22 includes an operational amplifier 20. The analog gain control voltage CTRLA is input to the inverting input terminal of the operational amplifier 20 through the resistor R1, and the reference potential VREFOP is input from the regulator 28 to the non-inverting input terminal. A resistor R2 is connected to the inverting input terminal and the output of the operational amplifier 20. The gain control voltage correction circuit 14 has an inverting amplifier circuit 23. The inverting amplifier circuit 23 includes an operational amplifier 21. The inverting input terminal of the operational amplifier 21 is grounded via the resistor R1, and the reference potential VREFOP is input to the non-inverting input terminal. A resistor R2 is connected to the inverting input terminal and the output of the operational amplifier 21.

  A gain control differential voltage CTRLD which is a difference between the outputs of the operational amplifiers 20 and 21 is input to the gm amplifier 17.

  The value of the gain control differential voltage CTRLD is R2 / R1 × CTRLA and is proportional to the analog gain control voltage CTRLA in which a wide voltage range from the power supply voltage to the ground voltage is used. In this way, the inverting amplifier circuits 22 and 23 convert the voltage range of the analog gain control voltage CTRLA into a voltage range that can be handled by the next stage gm amplifier 17.

  The gm amplifier 17 can be configured by a simple circuit such as a circuit in which a current mirror is connected to a load of a differential amplifier in which a resistor is inserted between emitters. The mutual conductance gm2 at this time is 1 / R3 when the emitter resistance is R3. The gm amplifier 17 converts the gain control differential voltage CTRLD into a gain control voltage proportional current IA and supplies it to the gm amplifier 16.

  The gm amplifier 16 receives a voltage proportional to the power supply voltage deviation of the gain control circuit as a differential voltage VIN + · VIN− (FIG. 4). As a voltage proportional to the deviation of the power supply voltage of the gain control circuit input to the gm amplifier 16, a power supply differential voltage that is a difference between the power supply voltage VDDDAC of the gain control circuit and the standard value VREFVDDDAC of the power supply voltage of the gain control circuit is used. In order to obtain voltages that can be input to the gm amplifier 16, voltages obtained by voltage division or level shift may be used.

  FIG. 4 is a circuit diagram showing a typical configuration example of the gm amplifier 16. The gm amplifier 16 is configured by a circuit whose mutual conductance gm1 is proportional to the current ratio between the gain control voltage proportional current IA and the reference current Iref and the emitter resistance R4 of the differential amplifier.

  A gain control voltage proportional current IA is input to a current mirror circuit including a transistor and a resistor on the lower right in FIG. Since the emitter area of the second transistor from the right is 0.5 times and the emitter resistance is twice that of the current IA flowing through the rightmost transistor, 0.5 times the current (IA × 0.5) is extracted. In the third transistor from the right, since the emitter area is 1 time and the emitter resistance is 1 time, a current (IA) that is 1 time is taken out.

The mutual conductance gm1 when the gm amplifier 16 is configured by such a circuit is as follows. The emitter resistance that determines the mutual conductance gm1 is R4.
gm1 = IA / Iref / R4 / 2,
It becomes.

Since the gain control voltage proportional current IA output from the gm amplifier 17 is input as the input current constituting the current ratio of the gm amplifier 16, the gain control voltage correction current Icrt output from the gm amplifier 16 is
Icrt = {(R2 / R1 × CTRLA) / R3} / Iref / R4 × (power supply voltage deviation),
It becomes.

  That is, a current proportional to the difference between the analog gain control voltage CTRLA and the power supply voltage of the gain control circuit is output from the gm amplifier 16.

  With the above operation, the deviation of the analog gain control voltage CTRLA can be accurately corrected using the output of the gm amplifier 16 as the gain control voltage correction current Icrt with a relatively simple circuit configuration.

Next, the temperature characteristics of each resistor provided in the gain control voltage correction circuit 14 will be described. When the temperature coefficient in each element is represented by TC, the temperature coefficient TC (gm1) of the gain control voltage correction current Icrt is:
Temperature coefficient TC (gm1)
= TC [{(R2 / R1 × CTRLA) / R3} / Iref / R4 × (power supply voltage deviation)],
= TC (R2) -TC (R1) -TC (R3) -TC (Iref) -TC (R4),
It becomes.

Here, when resistors having the same temperature characteristics are used for the resistors R1, R2, R3, and R4, the temperature coefficient TC (R)
Temperature coefficient TC (gm1) = (− 2) × TC (R) −TC (Iref),
It becomes.

If the resistor used when generating the reference current Iref is a resistor having the same temperature characteristic,
Temperature coefficient TC (gm1) = − TC (R),
It becomes. Therefore, if a resistor having the same temperature characteristic is used for the resistor R5 that converts the gain control voltage correction current Icrt output from the gm amplifier 16 into a voltage, the temperature coefficient of the gain control voltage correction current Icrt becomes zero, Regardless, appropriate correction can be performed.

  In the above-described embodiment, an example of a receiver is shown. However, the present invention is not limited to this, and the present invention can be applied to, for example, an AGC circuit.

  In the above-described embodiment, the discrete variable gain amplifier is arranged at the first stage of the RF block to amplify the high frequency signal, and the continuous variable gain amplifier is arranged at the last stage to amplify the baseband signal. Although shown, the present invention is not limited to this. A discrete variable gain amplifier may be arranged in the final stage of the RF block, or a fixed gain amplifier may be arranged in the final stage. In addition, although the example in which the continuous variable gain amplifier is arranged on the rear stage side of the discrete variable gain amplifier is shown, the continuous variable gain amplifier may be arranged on the front stage side of the discrete variable gain amplifier. Furthermore, although the system which converts a high frequency signal into a baseband signal by one frequency conversion is shown, an RF (high frequency) signal is converted into an IF (intermediate frequency) signal, and this IF (intermediate frequency) signal is converted into a baseband signal. The present invention can also be applied to a system that involves two frequency conversions for conversion into. In this case, the continuous variable gain amplifier is also used to amplify IF (intermediate frequency) signals.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to an AGC circuit and a receiver that automatically adjust the gain of an input signal, and in particular, can be applied to an AGC circuit and a receiver that input a high-frequency signal in order to receive digital television broadcasting or the like. .

1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of a receiver. FIG. It is a circuit diagram for demonstrating the gain control voltage correction circuit provided in the said receiver. It is a circuit diagram which shows the structure of the modification of the said gain control voltage correction circuit. It is a circuit diagram which shows the structure of the gm amplifier in the modification of the said gain control voltage correction circuit. It is a block diagram which shows the structure of the conventional receiver. It is a block diagram which shows the structure of the other conventional receiver. It is a graph which shows the relationship between the input level of the high frequency signal input into the said other conventional receiver, and the gain of a discrete variable gain amplifier and a continuous variable gain amplifier, (a) is an input level. Both gain transitions when increasing, (b) shows both gain transitions when the input level decreases. It is a graph which shows the relationship between the gain control voltage and analog gain control voltage in the gain control circuit provided in the other said conventional receiver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Receiver 2 RF block 3 Demodulation block 4 Discrete variable gain type amplifier 5a, 5b Mixer (frequency conversion circuit)
7a, 7b, 7c Continuous variable gain amplifiers 8a, 8b ADC (AD converter)
9 Gain Control Circuit 10 Gain Control Voltage Generation Unit 11 DAC (DA Conversion Unit)
12 Gain switching control circuit 13 Power supply 14 Gain control voltage correction circuit 15 gm amplifier (transconductance amplifier)
16 gm amplifier (first transconductance amplifier)
17 gm amplifier (second transconductance amplifier)
18 Inversion amplifier circuit (first inversion amplifier circuit)
19 operational amplifier 22 inverting amplifier circuit (second inverting amplifier circuit)
23. Inversion amplifier circuit (third inversion amplifier circuit)
CTRL gain control voltage CTRLA analog gain control voltage CTRLcrt correction gain control voltage CTRLD gain control differential voltage S1 gain switching signal VDDDAC power supply voltage VREFVDDDAC power supply voltage standard value Icrt gain control voltage correction current IA gain control voltage proportional current Iref reference current R4 emitter resistance R5 resistance

Claims (7)

A discrete variable gain amplifier which is a variable gain amplifier whose gain changes discretely;
A continuous variable gain amplifier which is a variable gain amplifier which is provided on at least one of the front side and the rear side of the discrete variable gain amplifier and whose gain continuously changes;
An AD converter for digitally converting the amplified output signal;
A gain control voltage generator for receiving a signal based on the output of the digitally converted continuous variable gain amplifier and generating a gain control voltage for controlling the gain of the continuous variable gain amplifier; and the gain control A gain control circuit having a DA converter for analog-converting the voltage into an analog gain control voltage;
A gain switching control circuit for generating a gain switching signal for switching the gain of the discrete variable gain amplifier based on the gain control voltage;
Based on the analog gain control voltage and the power supply voltage of the gain control circuit, a corrected gain control voltage is generated by correcting the deviation of the analog gain control voltage caused by the deviation of the power supply voltage from the standard value. An automatic gain control circuit comprising a gain control voltage correction circuit. An RF block for frequency-converting and amplifying a high-frequency signal into a baseband signal;
A demodulation block for demodulating the baseband signal,
The RF block is a discrete variable gain amplifier that is a variable gain amplifier whose gain varies discretely;
A continuous variable gain amplifier that is a variable gain amplifier that is provided on at least one of the front-stage side and the rear-stage side of the discrete variable gain amplifier and that continuously changes the gain;
The demodulation block includes an AD converter that digitally converts the output of the RF block;
Based on the output of the digitally converted RF block, a gain control voltage generator for generating a gain control voltage for controlling the gain of the continuously variable gain amplifier, and the gain control voltage as an analog gain control voltage A gain control circuit having a DA converter for analog conversion;
A gain switching control circuit for generating a gain switching signal for switching the gain of the discrete variable gain amplifier based on the gain control voltage;
The RF block corrects a deviation of the analog gain control voltage caused by a deviation from a standard value of the power supply voltage based on the analog gain control voltage and the power supply voltage of the gain control circuit. A receiver further comprising a gain control voltage correction circuit for generating a control voltage.   The gain control voltage correction amount defined by the difference between the correction gain control voltage and the analog gain control voltage is proportional to the analog gain control voltage and the deviation from the standard value of the power supply voltage of the gain control circuit. The receiver according to claim 2. The gain control voltage correction circuit includes a transconductance amplifier that generates a gain control voltage correction current based on the analog gain control voltage and the power supply voltage;
An inverting amplifier circuit that generates the correction gain control voltage based on the analog gain control voltage and the gain control voltage correction current;
The inverting amplifier circuit includes an operational amplifier having an inverting input terminal to which the analog gain control voltage is applied;
The receiver according to claim 2, further comprising a resistor connected to the inverting input terminal and an output of the operational amplifier, and converting the gain control voltage correction current into a voltage.   5. The receiver according to claim 4, wherein the inverting amplifier circuit converts the analog gain control voltage into a voltage within a range that the continuous variable gain amplifier can handle. The gain control voltage correction circuit corrects a gain control voltage based on a power supply differential voltage proportional to a deviation from a standard value of the power supply voltage, a gain control voltage proportional current proportional to the analog gain control voltage, and a reference current. A first transconductance amplifier for generating a current;
A first inverting amplifier circuit that generates the corrected gain control voltage based on the gain control voltage and the gain control voltage correction current;
The receiver according to claim 2, wherein the conductance of the first transconductance amplifier is proportional to a current ratio between the gain control voltage proportional current and the reference current and an emitter resistance of the differential amplifier.   The gain control voltage correction circuit is configured to control the gain control based on a gain control differential voltage between an output of a second inverting amplifier circuit that inputs the analog gain control voltage and an output of a third inverting amplifier circuit that inputs a ground potential. The receiver according to claim 6, further comprising a second transconductance amplifier that generates a voltage proportional current and supplies the voltage proportional current to the first transconductance amplifier.

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