JP4332726B2 - Receiver and receiver IC - Google Patents

Description

  The present invention relates to a receiver and a receiver IC.

  As a superheterodyne receiver, there is a so-called low IF receiver in which the intermediate frequency is made considerably lower than the reception frequency by bringing the local oscillation frequency close to the reception frequency. There is also a so-called direct conversion system in which the intermediate frequency is made zero by making the local oscillation frequency equal to the reception frequency. In these receivers, a received signal is converted into a pair of intermediate frequency signals orthogonal to each other by a pair of mixer circuits, and image characteristics are improved by phase processing.

  FIG. 5 shows an example of a low-IF receiver. That is, a reception signal SRX having a target reception frequency is taken out from the electronic tuning antenna tuning circuit 11, and this reception signal SRX is supplied to the pair of mixer circuits 13A and 13B through the high-frequency amplifier 12.

  Further, the local oscillation circuit 31 is constituted by a PLL, and two signals SLOA and SLOB having a frequency close to the frequency of the reception signal SRX (for example, a frequency higher by 50 kHz when receiving a medium wave broadcast) and phases different from each other by 90 ° are obtained. These signals SLOA and SLOB are supplied to the mixer circuits 13A and 13B as local oscillation signals.

  Thus, in the mixer circuits 13A and 13B, the received signal SRX is frequency-converted into a pair of intermediate frequency signals SIFA and SIFB by the local oscillation signals SLOA and SLOB. In this case, the intermediate frequency signals SIFA and SIFB include a signal component of the intended reception frequency (original signal component) and a signal component of the image frequency. The signal components of the reception frequency are called intermediate frequency signals SIFA and SIFB, and the signal components of the image frequency are called image components.

  Since the local oscillation signals SLOA and SLOB have a phase difference of 90 °, the intermediate frequency signals SIFA and SIFB have a phase difference of 90 °, and the image components are opposite to those of the intermediate frequency signals SIFA and SIFB. Due to the phase relationship, the phase difference is 90 °.

  Further, a part of the control voltage supplied to the variable capacitance diode of the VCO (not shown) of the PLL is extracted from the PLL constituting the local oscillation circuit 31, and this control voltage is supplied to the tuning circuit 11 as a tuning voltage. Thus, tuning with respect to the received signal SRX is realized.

  Then, the intermediate frequency signals SIFA and SIFB from the mixer circuits 13A and 13B are supplied to the phase shift circuits 16A and 16B through the bandpass filters 15A and 15B. The phase shift circuits 16A and 16B give a phase difference of 90 ° to the intermediate frequency signals SIFA and SIFB supplied thereto, and therefore, for example, the intermediate frequency signals SIFA and SIFB are in phase, and , The image components are shifted in phase.

  Then, the intermediate frequency signals SIFA and SIFB after the phase shift are supplied to and added to the operation 17, and the image calculation circuit 17 cancels the image component and only the intermediate frequency signal SIF is taken out. Subsequently, the intermediate frequency signal SIF is supplied to the digital processing circuit 20 through the intermediate frequency amplifier 18 and the band pass filter 19 and A / D converted, and predetermined digital processing corresponding to the format of the received signal SRX. And audio signals L and R are extracted.

  According to the low IF receiver, a one-chip IC can be formed except for the tuning circuit 11 and the resonance circuit of the PLL 31.

  However, in the case of the above-described receiver, if there is a relative amplitude error or phase error in the intermediate frequency signals SIFA and SIFB supplied to the arithmetic circuit 17, when the intermediate frequency signals SIFA and SIFB are added in the arithmetic circuit 17, The image components included in the intermediate frequency signals SIFA and SIFB are not equal in amplitude or out of phase. As a result, the image components are not sufficiently canceled out, and the image characteristics are deteriorated.

For example,
Δ: Relative amplitude error of intermediate frequency signals SIFA and SIFB
Δ = | SIFA−SIFB | / SIFA
Θ: Relative phase error [rad] of intermediate frequency signals SIFA and SIFB
RIMG: When using image attenuation ratio
RIMG = (Δ ² + Θ ² ) ^1/2 / 2
Is represented by
Δ = 0.01 (= 1 [%]) Θ = 0.01 [rad]
given that,
RIMG = -43 [dB]
It becomes. Also,
Δ = 0.01 Θ = 1 [°]
Then
RIMG = -40 [dB]
It becomes. Conversely, in order to obtain an image attenuation ratio RIMG of about −60 dB, the relative amplitude error and phase error must be better by one digit or more than the above values.

  Therefore, first, it is conceivable to suppress the relative amplitude error and phase error (in this case, the deviation of the phase difference from 90 °) of the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B.

  FIG. 6 shows an example of the mixer circuits 13A and 13B in consideration of such amplitude error and phase error. The mixer circuits 13A and 13B are each configured as a double balance type. The mixer circuit 13A is supplied with one local oscillation signal SLOA and the reception signal SRX in a balanced manner, and the mixer circuit 13B is supplied with the other local oscillation signal SLOB and the reception signal SRX in a balanced manner. . The mixer circuits 13A and 13B are configured in a one-chip IC together with other circuits as described above. A semi-fixed resistor VR11 is externally connected to the mixer circuits 13A and 13B through external terminal pins T11 and T12. Is done.

  Therefore, although the intermediate frequency signals SIFA and SIFB are output from the mixer circuits 13A and 13B, since this circuit is configured in a balanced manner, the relative arrangement of the intermediate frequency signals SIFA and SIFB is determined by devising the layout in the IC chip. A typical phase error can be reduced. When the semi-fixed resistor VR11 is adjusted, the gains of the mixer circuits 13A and 13B change in a complementary manner, so that the relative amplitude error of the intermediate frequency signals SIFA and SIFB can be corrected. As a result, in the case of the mixer circuits 13A and 13B, the image attenuation ratio can be set to −40 dB to −50 dB.

  FIG. 7 shows an example of the local oscillation circuit 31. An oscillation signal SLO is extracted from the VCO 311 of the PLL, and this signal SLO is a variable phase circuit 312, 313 composed of a variable low-pass filter and a variable high-pass filter. To be supplied. The output signals of the variable phase circuits 312 and 313 are supplied to the phase comparison circuit 315 for phase comparison, and the comparison output is supplied as a control signal to the variable phase circuits 312 and 313 through the low pass filter 316.

  Therefore, the amount of phase delay and the amount of phase advance of the variable phase circuits 312 and 313 are controlled so that the phase difference between the two signals supplied to the phase comparison circuit 315 is 90 °, and the circuit is stabilized. Therefore, if the two signals supplied to the phase comparison circuit 315 are supplied to the mixer circuits 13A and 13B as the local oscillation signals SLOA and SLOB, the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are relative to each other. Phase errors can be suppressed, and as a result, image characteristics can be improved.

  In addition to the above, there is also a method of supplying a test signal to the mixer circuits 13A and 13B and performing feedback control so that the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB at that time are minimized. It is considered.

For example, there are the following prior art documents.
JP 11-252047 A JP 2001-44776 A

  In the receiver of the low IF method and the direct conversion method as described above, the orthogonality of the local oscillation signals SLOA and SLOB can be realized by devising the circuit configuration and the circuit layout in the IC, or the intermediate frequency signal SIFA, The relative amplitude error and phase error of SIFB are kept within specified values.

  However, in the case of an IC having a large circuit scale, the relative error of the elements is about 1 to 3% in mass production between the mixer circuits 13A and 13B and the subsequent phase shift circuits 16A and 16B. For this reason, the image attenuation ratio deteriorates to about −30 dB to −40 dB.

  In the case of the mixer circuits 13A and 13B shown in FIG. 6, it is necessary to externally attach a semi-fixed resistor VR11 to the IC and adjust it. Further, in the case of the local oscillation circuit 31 shown in FIG. 7, the phase difference between the local oscillation signals SLOA and SLOB is automatically secured by the feedback loop, but the mixer circuits 13A and 13B are outside the feedback loop. The phase error of the intermediate frequency signals SIFA and SIFB output from 13A and 13B cannot be corrected.

  Also, in the case of a feedback control method using a test signal so that the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB are minimized, the image component itself cannot be used, and the received signal and image Amplitude errors and phase errors due to frequency differences from the components cannot be corrected.

  The present invention is intended to solve the above problems.

In this invention,
A pair of mixer circuits for converting the received signal into a pair of intermediate frequency signals orthogonal to each other by a pair of local oscillation signals orthogonal to each other;
An arithmetic circuit that outputs an intermediate frequency signal that is finally required ;
An amplitude phase correction circuit connected to an intermediate frequency signal line between the pair of mixer circuits and the arithmetic circuit and supplied with a pair of intermediate frequency signals;
A pair of phase shift circuits connected to the intermediate frequency signal line,
The amplitude phase correction circuit is
First and second operational amplifiers to which the pair of intermediate frequency signals are respectively supplied;
First and second variable resistance circuits connected in series between an inverting output terminal and a non-inverting output terminal of the first operational amplifier;
Third and fourth variable resistance circuits connected in series between the inverting output terminal and the non-inverting output terminal of the second operational amplifier;
A first inverting amplifier for adding the inverting output or non-inverting output of the first operational amplifier and the output of the connection point of the third and fourth variable resistance circuits;
A second inverting amplifier for adding the inverting output or non-inverting output of the second operational amplifier and the output of the connection point of the first and second variable resistance circuits;
Fifth and sixth variable resistance circuits for controlling negative feedback amounts of the first and second inverting amplifiers, respectively
Have
Each of the first to sixth variable resistance circuits includes:
Series circuit of multiple resistors and multiple MOS-FETs
Consisting of
By controlling on / off of the plurality of MOS-FETs in each of the first to fourth variable resistance circuits by the first digital data, the ratio of the addition in the first and second inverting amplifiers is changed. Change in opposite directions,
By this change, the phases of the pair of intermediate frequency signals supplied to the arithmetic circuit are changed in opposite directions to correct a phase error between the pair of intermediate frequency signals,
By turning on and off the plurality of MOS-FETs in each of the fifth and fifth variable resistance circuits by the second digital data, the gains in the pair of amplitude control circuits are changed in opposite directions. ,
This change corrects an amplitude error between the pair of intermediate frequency signals supplied to the arithmetic circuit by this change.
It is what.

  According to the present invention, even if there is a relative amplitude error and phase error in the intermediate frequency signal output from the mixer circuit, it is possible to provide an intermediate frequency signal in which the amplitude error and phase error are corrected. Further, when correcting the relative phase error of the intermediate frequency signal, it is possible to correct the phase error while keeping the amplitude error of the intermediate frequency signal small.

  Furthermore, when correcting the relative phase error of the intermediate frequency signal, it is not necessary to alternately repeat the phase adjustment and the amplitude adjustment, and after correcting the relative phase error of the intermediate frequency signal, the amplitude error is corrected. Adjustment is easy.

  Also, even if a relative amplitude error or phase error occurs in the intermediate frequency signal in the subsequent circuit, the relative amplitude or phase of the intermediate frequency signal can be adjusted so as to cancel the error, and therefore the subsequent circuit It is also possible to improve the deterioration of image characteristics due to the above.

[1] Configuration and Operation of Receiver FIG. 1 shows an embodiment when the present invention is applied to a low-IF receiver. That is, a reception signal SRX having a target reception frequency is taken out from the electronic tuning antenna tuning circuit 11, and this reception signal SRX is supplied to the pair of mixer circuits 13A and 13B through the high-frequency amplifier 12.

  Further, the local oscillation circuit 31 is constituted by a PLL, and two signals SLOA and SLOB having a frequency close to the frequency of the reception signal SRX (for example, a frequency higher by 50 kHz when receiving a medium wave broadcast) and phases different from each other by 90 ° are obtained. These signals SLOA and SLOB are supplied to the mixer circuits 13A and 13B as local oscillation signals.

  Thus, in the mixer circuits 13A and 13B, the received signal SRX is frequency-converted into a pair of intermediate frequency signals SIFA and SIFB by the local oscillation signals SLOA and SLOB. In this case, since the local oscillation signals SLOA and SLOB have a phase difference of 90 °, the intermediate frequency signals SIFA and SIFB are orthogonal with a phase difference of 90 °, and the image components are the intermediate frequency signals SIFA, It is orthogonal with a phase difference of 90 ° in reverse relation to SIFB.

  Further, a part of the control voltage supplied to the variable capacitance diode of the VCO (not shown) of the PLL is extracted from the PLL constituting the local oscillation circuit 31, and this control voltage is supplied to the tuning circuit 11 as a tuning voltage. Thus, tuning with respect to the received signal SRX is realized.

  Then, the intermediate frequency signals SIFA and SIFB from the mixer circuits 13A and 13B are supplied to the amplitude phase correction circuit 14. Although details of the correction circuit 14 will be described later, the correction circuit 14 is for correcting the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B.

  The intermediate frequency signals SIFA and SIFB whose amplitude error and phase error have been corrected by the correction circuit 14 are supplied to the phase shift circuits 16A and 16B through the band pass filters 15A and 15B. For example, the intermediate frequency signals SIFA and SIFB are in phase, At the same time, the image components are shifted in phase. Then, the intermediate frequency signals SIFA and SIFB after the phase shift are supplied to and added to the arithmetic circuit 17, and the image circuit is canceled from the arithmetic circuit 17, and only the intermediate frequency signal SIF is extracted.

  Subsequently, the intermediate frequency signal SIF is supplied to the digital processing circuit 20 through the intermediate frequency amplifier 18 and the band pass filter 19 and A / D converted, and predetermined digital processing corresponding to the format of the received signal SRX. And audio signals L and R are extracted.

  Further, a part of the intermediate frequency signal SIF is supplied from the band pass filter 19 to the AGC voltage forming circuit 32 to form the AGC voltage VAGC. This AGC voltage VAGC is supplied to the amplifier 18 as a gain control signal, and the intermediate frequency stage AGC is performed. Further, the AGC voltage VAGC is supplied as a gain control signal to the high-frequency amplifier 12 through the adding circuit 34, and AGC is performed for the high-frequency stage.

  Further, when the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are supplied to the excessive input detection circuit 33 and become an excessive reception level, the AGC voltage VOL is formed, and the AGC voltage VOL is added to the adding circuit. 34 is supplied as a gain control signal to the high-frequency amplifier 12 through a delay AGC for the high-frequency stage.

  The above receiving circuit is integrated into a one-chip IC except for the tuning circuit 11 and the resonance circuit of the PLL 31.

  Further, a microcomputer 40 is provided as a system control circuit, and an operation switch 41 such as a channel selection switch is connected to the microcomputer 40. When the switch 41 is operated, a predetermined control signal is supplied from the microcomputer 41 to the local oscillation circuit 31, the oscillation frequencies of the local oscillation signals SLOA and SLOB are changed, and the reception frequency is changed.

  For example, when the power is turned on, the correction circuit 14 is controlled by the microcomputer 40, and the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are corrected as described above. The This correction result is held by the microcomputer 40 until the next correction is executed.

[2] Configuration and Operation of Amplitude Phase Correction Circuit 14 FIG. That is, the mixer circuits 13A and 13B are configured in a balanced manner as shown in FIG. 6, for example, and the intermediate frequency signals SIFA and SIFB are respectively taken out from the mixer circuits 13A and 13B in a balanced manner. The intermediate frequency signal SIFA from the mixer circuit 13A is supplied to the non-inverting input terminal and the inverting input terminal of the operational amplifier 141A, and the inverting output terminal and the non-inverting output terminal are connected to the non-inverting input terminal and the inverting input terminal. Between them, negative feedback resistors R41A and R42B are connected.

  The inverting output terminal of the operational amplifier 141A is connected to the input terminal of the inverting amplifier 142A constituted by the operational amplifier through the resistor R43A, and the output terminal is connected to the input terminal of the bandpass filter 15A. A variable resistor circuit R44A is connected between the output terminal and the input terminal of the inverting amplifier 142A.

  Similarly, the intermediate frequency signal SIFB from the mixer circuit 13B is supplied to the non-inverting input terminal and the inverting input terminal of the operational amplifier 141B, the inverting output terminal and the non-inverting output terminal, the non-inverting input terminal and the inverting input terminal, In between, negative feedback resistors R41B and R42B are connected. The inverting output terminal of the operational amplifier 141B is connected to the input terminal of the inverting amplifier 142B constituted by the operational amplifier through the resistor R43B, and the output terminal is connected to the input terminal of the bandpass filter 15B. A variable resistance circuit R44B is connected between the output terminal and the input terminal of the inverting amplifier 142B.

  Furthermore, variable resistance circuits R45A and R46A are connected in series between the inverting output terminal and the non-inverting output terminal of the operational amplifier 141A, and the midpoint of this series connection is connected to the input terminal of the inverting amplifier 142B. Similarly, variable resistance circuits R45B and R46B are connected in series between the inverting output terminal and the non-inverting output terminal of the operational amplifier 141B, and the midpoint of this series connection is connected to the input terminal of the inverting amplifier 142A.

  Further, an amplitude error correction control signal DAV is extracted from the microcomputer 40, and this signal DAV is supplied to the variable resistance circuits R44A and R44B as its control signal. Further, a phase error correction control signal DPS is taken out from the microcomputer 40, and this signal DPS is supplied to the variable resistance circuits R45A, R46A, R45B and R46B as its control signal.

  In this case, when the variable resistance circuits R44A and R44B are controlled by the correction control signal DAV, the change directions are controlled to be opposite to each other. Further, when the variable resistor circuits R45A, R46A, R45B, and R46B are controlled by the correction control signal DPS, the change directions of the variable resistor circuits R45A and R45B are equal to each other, and the change directions of the variable resistor circuits R46A and R46B are also equal to each other. In addition, the change direction of the variable resistance circuits R45A and R45B and the change direction of the variable resistance circuits R46A and R46B are controlled to be opposite to each other.

  According to such a configuration, the intermediate frequency signal SIFA is output from the inverting output terminal of the operational amplifier 141A, and this signal SIFA is supplied to the inverting amplifier 142A through the resistor R43A. Further, an intermediate frequency signal SIFB is output from the inverting output terminal of the operational amplifier 141B, and this signal SIFB is supplied to the inverting amplifier 142B through the resistor R43B.

  If the phase difference θ between the intermediate frequency signals SIFA and SIFB is smaller than 90 °, the intermediate frequency signals SIFA and SIFB at this time can be shown by the solid line in FIG. If so, the intermediate frequency signals SIFA and SIFB at this time can be shown by broken lines in FIG.

  Since the operational amplifier 141B outputs the intermediate frequency signals SIFB having opposite phases to each other and supplied to the series connection of the variable resistance circuits R45B and R46B, as shown in FIG. 3, from the connection middle point of the variable resistance circuits R45B and R46B. The signal ΔSIFB having the polarity and level corresponding to the resistance ratio is taken out. The signal ΔSIFB is supplied to the inverting amplifier 142A.

  Therefore, in the inverting amplifier 142A, the intermediate frequency signal SIFA supplied through the resistor R43A and the signal ΔSIFB supplied from the variable resistance circuits R45B and R46B are vector-added.

  Similarly, a signal ΔSIFA having a polarity and a level corresponding to the resistance ratio is taken out from the connection middle point of the variable resistance circuits R45A and R46A, and an intermediate frequency signal SIFB supplied through the resistor R43B in the inverting amplifier 142B; The signal ΔSIFA taken out from the variable resistance circuits R45A and R46A is vector-added.

  Therefore, if the signals resulting from the vector addition in the inverting amplifiers 142A and 142B are the addition signals SIFA0 and SIFB0, the addition signals SIFA0 and SIFB0 are adjusted as shown in FIG. 3 by adjusting the polarities and levels of the signals ΔSIFB and ΔSIFA. The phase difference θ can be 90 °.

  At this time, the polarities and levels of the signals ΔSIFB and ΔSIFA are determined by the resistance ratio of the variable resistance circuits R45B, R46B, R45A, and R46A, and the resistance ratio can be changed by the correction control signal DPS. Therefore, the phase difference θ between the addition signals SIFA0 and SIFB0 can be set to 90 ° by the correction control signal DPS.

  Further, since the values of the variable resistance circuits R44A and R44B change complementarily by the correction control signal DAV, the gains of the inverting amplifiers 142A and 142B change complementarily and the levels of the addition signals SIFA0 and SIFB0 are complementary. To change. Therefore, the amplitudes of the addition signals SIFA0 and SIFB0 can be made equal by the correction control signal DAV.

  Accordingly, the inverting amplifiers 142A and 142B output the addition signals SIFA0 and SIFB0 having the phase difference θ of 90 ° and the same amplitude, and these signals SIFA0 and SIFB0 are used as intermediate frequency signals SIFA and SIFB in the next stage bandpass filter. 15A and 15B.

  Thus, according to the amplitude phase correction circuit 14, even if the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B have a relative amplitude error and phase error, the amplitude error and phase error are corrected. The intermediate frequency signals SIFA and SIFB thus obtained can be provided.

  Further, when correcting the relative phase error between the intermediate frequency signals SIFA and SIFB, for example, if the phase of the intermediate frequency signal SIFB is corrected with reference to the phase of the intermediate frequency signal SIFA, the amplitude of the intermediate frequency signal SIFB relative to the intermediate frequency signal SIFA is corrected. However, in the correction circuit 14 of FIG. 2, as is clear from FIG. 3, the phase of the intermediate frequency signal SIFA and the phase of the intermediate frequency signal SIFB are simultaneously changed in opposite directions and are relative to each other. Since the phase error is corrected, it is possible to correct the phase error while keeping the amplitude error of the intermediate frequency signals SIFA0 and SIFB0 small.

  In addition, the gains of the inverting amplifiers 142A and 142B change complementarily to correct the relative amplitude error of the intermediate frequency signals SIFA and SIFB, and this amplitude correction may affect the phase of the intermediate frequency signals SIFA and SIFB. Absent.

  Further, when correcting the relative phase error between the intermediate frequency signals SIFA and SIFB, for example, if the phase of the intermediate frequency signal SIFB is corrected with reference to the phase of the intermediate frequency signal SIFA, the amplitude of the intermediate frequency signal SIFB relative to the intermediate frequency signal SIFA is corrected. Changes, it is necessary to repeat phase adjustment and amplitude adjustment alternately, and the adjustment becomes complicated. However, in the correction circuit 14 of FIG. 2, the amplitude correction of the intermediate frequency signals SIFA and SIFB does not affect the phase. Therefore, after correcting the relative phase error of the intermediate frequency signals SIFA and SIFB, the amplitude error is corrected. It is only necessary to correct the above, and adjustment is easy.

  Further, when relative amplitude errors or phase errors occur in the intermediate frequency signals SIFA and SIFB in the band pass filters 15A and 15B and the phase shift circuits 16A and 16B, the intermediate frequency signals SIFA, The relative amplitude or phase of SIFB can be adjusted, and therefore the degradation of image characteristics caused by the bandpass filters 15A and 15B and the phase shift circuits 16A and 16B can be improved.

[3] Specific Example of Amplitude Phase Correction Circuit 14 FIG. 4 shows the amplitude phase correction circuit 14 more specifically. In this example, the gain error correction control signal DAV and the phase error correction control signal DPS are 4-bit digital data.

That is, the operational amplifiers 141A and 141B, the inverting amplifiers 142A and 142B, the resistors R43A and R43B, and the variable resistance circuits R44A to R46A and R44B to R46B are connected as described in FIG. In this case, the variable resistance circuit R44A is provided with MOS-FETs (Q0 to Q3) as switching elements, and resistors R0 to R3 are connected in series between their drains and sources, respectively. A resistor R5 is connected in series with the resistor R4. At this time, the values of the resistors R0 to R3 are
R1 = 2 ・ R0
R2 = 4 ・ R0
R3 = 8 ・ R0
It is said.

  The variable resistance circuit R44B is configured in the same manner as the variable resistance circuit R44A, and the variable resistance circuits R45A to R46B are configured in the same manner as the variable resistance circuit R44A.

  A gain error correction control signal DAV is taken out from the microcomputer 40, and the least significant bit b0 to the most significant bit b3 of the control signal DAV are supplied to the gates of the FETs (Q0 to Q3) of the variable resistance circuit R44A, respectively. And supplied to the gates of the FETs (Q0 to Q3) of the variable resistance circuit R44B through the inverters Q41 to Q41, respectively.

  Further, the phase error correction control signal DPS is taken out from the microcomputer 40, and the least significant bit b0 to the most significant bit b3 of the control signal DPS are FETs (Q0 to Q3), (Q0 to Q3) of the variable resistance circuits R46A and R46B. Q3) are supplied to the gates of Q3) and through inverters Q42 to Q42 to the FETs (Q0 to Q3) and (Q0 to Q3) of variable resistance circuits R45A and R45B, respectively.

  According to such a configuration, in the variable resistance circuit R44A, the FETs (Q0 to Q3) are turned on / off corresponding to the bits b0 to b3 of the control signal DAV, but a certain FET (Qi) (i = 0 to 3). ) Is on, the resistor Ri connected in series to the FET (Qi) is connected in parallel to the resistor R4.

  Therefore, when the value indicated by the bits b0 to b3 of the control signal DAV changes by "1" from "0" to "15", the value of the variable resistor circuit R44A is changed from the value (R4 + R5) to the value ((R0‖R1‖). R2‖R3‖R4) + R5) (‖ indicates a parallel value) changes over 16 steps by the amount of change when resistor R0 is connected in parallel.

  Therefore, the gain of the inverting amplifier 142A changes in 16 steps according to the control signal DAV, and at this time, the amplitude of the intermediate frequency signal SIFA passing through the amplifier 142A is controlled over 16 steps.

  At this time, since the same operation is performed in the variable resistor circuit R44B, the amplitude of the intermediate frequency signal SIFB passing through the inverting amplifier 142B is controlled over 16 steps. At this time, the variable resistor circuit R44B is supplied to the variable resistor circuit R44B. The level of the control signal DAV is inverted by inverters Q41 to Q41.

  Therefore, when the amplitudes of the intermediate frequency signals SIFA and SIFB are controlled in the inverting amplifiers 142A and 142B by the control signal DAV, the amplitude of the intermediate frequency signal SIFA and the amplitude of the intermediate frequency signal SIFB change in opposite directions. . That is, the amplitude error of the intermediate frequency signals SIFA and SIFB can be corrected by changing them in opposite directions by the control signal DAV. The correction range at this time can be set to 3%, for example.

  In the variable resistance circuits R45A to R46B, the same operation is performed by the phase error correction control signal DPS. Therefore, the phase errors of the intermediate frequency signals SIFA and SIFB can be adjusted by the control signal DPS.

[4] Image Characteristic Adjustment Method In the case of the receiver and the amplitude / phase correction circuit 14 described above, the image characteristic can be adjusted as follows. That is,
(1) Set the receiving frequency of the receiver to the frequency for adjusting the image characteristics. Also, AGC is turned off.
(2) A test signal having a frequency (image frequency) corresponding to the reception frequency at this time is supplied to the receiver as an image signal.
(3) While observing the amplitude of the intermediate frequency signal SIF output from the bandpass filter 19, the phase error correction control signal DPS is changed.
(4) Since the phase error of the intermediate frequency signals SIFA and SIFB is minimum when the amplitude of the intermediate frequency signal SIF is minimized, the value of the control signal DPS at this time is stored in the microcomputer 40.
(5) While observing the amplitude of the intermediate frequency signal SIF output from the bandpass filter 19, the amplitude error correction control signal DAV is changed.
(6) Since the amplitude error of the intermediate frequency signals SIFA and SIFB is minimum when the amplitude of the intermediate frequency signal SIF is minimized, the value of the control signal DAV at this time is stored in the microcomputer 40.

  The above processing can be automatically executed by the microcomputer 40 if the signal source of the test signal is built in the receiver, but the adjustment of the image characteristics is thus completed.

  Thereafter, at the time of reception, the control signals DPS and DAV having the values stored in steps (4) and (6) are supplied from the microcomputer 40 to the respective variable resistance circuits R44A to R46B. In this way, the best adjusted image characteristics can be obtained during reception.

[5] Summary In the above-described receiver, it is possible to sufficiently improve the degradation of image characteristics due to manufacturing variations. In addition, since the adjustment result is obtained with digital data, it is easy to use the adjustment result at the time of reception.

  Furthermore, if a test signal source for adjusting image characteristics is built in the receiver, the image characteristics can be adjusted when necessary, and it is possible to easily cope with changes in temperature, changes in reception conditions, and the like. Also, the amplitude / phase correction circuit 14 shown in FIG. 2 and FIG. 4 can be integrated with another receiving circuit as a one-chip IC, and does not require an external component.

  In the above description, the intermediate frequency signals SIFA and SIFB output from the phase shift circuits 16A and 16B are in phase and the image components included in these signals are in reverse phase, but are output from the mixer circuits 13A and 13B. The phase relationship between the intermediate frequency signals SIFA and SIFB is reversed, and the phase shift relationship between the phase shift circuits 16A and 16B is reversed and the intermediate frequency signals SIFA and SIFB output from the phase shift circuits 16A and 16B are in reverse phase. When the image components included in these are in phase, the arithmetic circuit 17 may perform subtraction.

  The phase shift circuits 16A and 16B can be constituted by polyphase filters or the like, but these filters generally have bandpass characteristics, and therefore the bandpass filters 15A and 15B and the phase shift circuits 16A and 16B are provided. It can also be configured simultaneously (integrally).

[List of abbreviations]
A / D: Analog to Digital
AGC: Automatic Gain Control
FET: Field Effect Transistor
IC: Integrated Circuit
IF: Intermediate Frequency
MOS-FET: Metal Oxide Semiconductor type FET
PLL: Phase Locked Loop
VCO: Voltage Controlled Oscillator
Operational Amplifier: Operational Amplifier

It is a systematic diagram showing one embodiment of the present invention. It is a connection diagram showing one embodiment of the present invention. It is a vector diagram for demonstrating this invention. It is a connection diagram showing one embodiment of the present invention. It is a systematic diagram for demonstrating this invention. It is a connection diagram for explaining the present invention. It is a connection diagram for explaining the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Antenna tuning circuit, 13A and 13B ... Mixer circuit, 14 ... Amplitude phase correction circuit, 16A and 16B ... Phase shift circuit, 17 ... Arithmetic circuit, 19 ... Band pass filter, 20 ... Digital processing circuit, 31 ... Local oscillation circuit 32 ... AGC voltage forming circuit, 33 ... excessive input detection circuit, 40 ... microcomputer, 141A and 141B ... operational amplifier, 142A and 142B ... inverting amplifier, R44A-R46B ... variable resistance circuit

Claims (2)

A pair of mixer circuits for converting the received signal into a pair of intermediate frequency signals orthogonal to each other by a pair of local oscillation signals orthogonal to each other;
An arithmetic circuit that outputs an intermediate frequency signal that is finally required ;
An amplitude phase correction circuit connected to an intermediate frequency signal line between the pair of mixer circuits and the arithmetic circuit and supplied with a pair of intermediate frequency signals;
A pair of phase shift circuits connected to the intermediate frequency signal line,
The amplitude phase correction circuit is
First and second operational amplifiers to which the pair of intermediate frequency signals are respectively supplied;
First and second variable resistance circuits connected in series between an inverting output terminal and a non-inverting output terminal of the first operational amplifier;
Third and fourth variable resistance circuits connected in series between the inverting output terminal and the non-inverting output terminal of the second operational amplifier;
A first inverting amplifier for adding the inverting output or non-inverting output of the first operational amplifier and the output of the connection point of the third and fourth variable resistance circuits;
A second inverting amplifier for adding the inverting output or non-inverting output of the second operational amplifier and the output of the connection point of the first and second variable resistance circuits;
Fifth and sixth variable resistance circuits for controlling negative feedback amounts of the first and second inverting amplifiers, respectively
Have
Each of the first to sixth variable resistance circuits includes:
Series circuit of multiple resistors and multiple MOS-FETs
Consisting of
By controlling on / off of the plurality of MOS-FETs in each of the first to fourth variable resistance circuits by the first digital data, the ratio of the addition in the first and second inverting amplifiers is changed. Change in opposite directions,
By this change, the phases of the pair of intermediate frequency signals supplied to the arithmetic circuit are changed in opposite directions to correct a phase error between the pair of intermediate frequency signals,
By turning on and off the plurality of MOS-FETs in each of the fifth and fifth variable resistance circuits by the second digital data, the gains in the pair of amplitude control circuits are changed in opposite directions. ,
A receiver IC which corrects an amplitude error between the pair of intermediate frequency signals supplied to the arithmetic circuit by this change . A pair of mixer circuits for converting the received signal into a pair of intermediate frequency signals orthogonal to each other by a pair of local oscillation signals orthogonal to each other;
  An arithmetic circuit that outputs an intermediate frequency signal that is finally required;
  An amplitude phase correction circuit connected to an intermediate frequency signal line between the pair of mixer circuits and the arithmetic circuit and supplied with a pair of intermediate frequency signals;
  A pair of phase shift circuits connected to the intermediate frequency signal line;
  A system control circuit for holding and outputting the first and second digital data;
Have
  The amplitude phase correction circuit is
    First and second operational amplifiers to which the pair of intermediate frequency signals are respectively supplied;
    First and second variable resistance circuits connected in series between an inverting output terminal and a non-inverting output terminal of the first operational amplifier;
    Third and fourth variable resistance circuits connected in series between the inverting output terminal and the non-inverting output terminal of the second operational amplifier;
    A first inverting amplifier for adding the inverting output or non-inverting output of the first operational amplifier and the output of the connection point of the third and fourth variable resistance circuits;
    A second inverting amplifier for adding the inverting output or non-inverting output of the second operational amplifier and the output of the connection point of the first and second variable resistance circuits;
    Fifth and sixth variable resistance circuits for controlling negative feedback amounts of the first and second inverting amplifiers, respectively
  Have
  Each of the first to sixth variable resistance circuits includes:
    Series circuit of multiple resistors and multiple MOS-FETs
  Consisting of
  By controlling on / off of the plurality of MOS-FETs in each of the first to fourth variable resistance circuits by the first digital data, the ratio of the addition in the first and second inverting amplifiers is changed. Change in opposite directions,
  By this change, the phases of the pair of intermediate frequency signals supplied to the arithmetic circuit are changed in opposite directions to correct a phase error between the pair of intermediate frequency signals,
  By turning on and off the plurality of MOS-FETs in each of the fifth and fifth variable resistance circuits by the second digital data, the gains in the pair of amplitude control circuits are changed in opposite directions. ,
  This change corrects an amplitude error between the pair of intermediate frequency signals supplied to the arithmetic circuit.
  Like receiver.

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