JP2007096265A - Integrated capacitor for wiring board, and wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated capacitor for a wiring board capable of reducing continuity failures when the capacitor is integrated in the wiring board; and also to provide a wiring board equipped with the capacitor. <P>SOLUTION: This integrated capacitor 1 for the wiring board comprises multiple laminated ceramic layers 3, multiple internal electrode layers 4 and 5 arranged between the ceramic layers 3 different from each other, and dummy electrode layers 12 and 13 arranged at predetermined spacing from the internal electrode layers 4 and 5 between the ceramic layers 3 on the peripheral side of the ceramic layers 3 from the internal electrode layers 4 and 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board built-in capacitor and a wiring board including the same.

  In recent years, the operation of semiconductor chips has been increasingly accelerated due to advances in integrated circuit technology. As a result, noise may be superimposed on the power supply wiring and the like, causing malfunction. Therefore, a capacitor is mounted on the upper surface or the lower surface of the wiring substrate on which the semiconductor chip is mounted to remove noise.

  However, in the above method, it is necessary to separately mount a capacitor after the wiring board is completed, so that the number of processes increases. In addition, it is necessary to secure a region for mounting the capacitor on the wiring board in advance, which reduces the degree of freedom of other electronic components. Furthermore, by being limited to other wirings and the like, the wiring distance between the capacitor and the semiconductor chip is increased, and the resistance and inductance of the wirings are increased.

  For this reason, it has been proposed to incorporate a capacitor in the wiring board. As a technique for incorporating a capacitor in the wiring board, for example, there is a technique in which an opening is provided in a core substrate that forms the core of the wiring board and the capacitor is accommodated in the opening.

  In this method, since it is necessary to fix the capacitor to the core substrate, the resin filler is filled in the gap between the core substrate and the capacitor in a state where the capacitor is disposed in the opening of the core substrate. Specifically, the adhesive tape is affixed to the back surface of the core substrate, and the capacitor is disposed in the opening of the core substrate so that the back surface of the capacitor is affixed to the adhesive tape. The resin filler is filled in a state where is fixed.

  However, since the thickness of the end portion of the conventional capacitor is thinner than the thickness of other portions, a step is formed in the vicinity of the end portion of the capacitor. For this reason, when the resin filler is filled, the resin filler enters the back side of the capacitor. As a result, the resin filler comes into contact with the external terminals arranged on the back surface of the capacitor, which may cause a conduction failure and a process of removing the filler resin.

A capacitor is disclosed in which the outer peripheral surface of the internal electrode layer is exposed from the ceramic layer (see, for example, Patent Document 1). However, since only the outer peripheral surface of one side of the internal electrode layer is exposed, the above step is sufficiently relaxed. It is thought that it was not done.
JP 2004-228190 A

  The present invention has been made to solve the above problems. That is, it is an object of the present invention to provide a wiring board built-in capacitor capable of reducing poor conduction when incorporated in a wiring board, and a wiring board provided with the same.

  According to one aspect of the present invention, a plurality of stacked dielectric layers, a plurality of internal electrode layers disposed between the different dielectric layers, and the dielectric layer between the dielectric layers and from the internal electrode layers. Provided is a wiring board built-in capacitor comprising the internal electrode layer and a dummy electrode layer disposed at a predetermined interval on the outer peripheral side of the body layer.

  According to another aspect of the present invention, there is provided a wiring board built-in capacitor comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers arranged between the different dielectric layers, A wiring board built-in capacitor is provided in which almost all of the outer peripheral surface of the internal electrode layer is exposed from the dielectric layer.

  According to another aspect of the present invention, there is provided a wiring board comprising the wiring board built-in capacitor according to any one of claims 1 to 10.

  According to the wiring board built-in capacitor of one and other aspects of the present invention, the step near the end of the wiring board built-in capacitor is sufficiently relaxed, so that the wiring board built-in capacitor is built into the wiring board. In such a case, poor conduction can be reduced. Moreover, according to the wiring board of another aspect of the present invention, it is possible to provide a wiring board with reduced conduction defects.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic longitudinal sectional view of a capacitor with a built-in wiring board according to the present embodiment, and FIGS. 2A and 2B are schematic views of the capacitor with a built-in wiring board according to the present embodiment. FIG. FIG. 3 is a schematic plan view of the wiring board built-in capacitor according to the present embodiment.

  A capacitor 1 shown in FIGS. 1 to 3 is a multilayer capacitor formed in a rectangular parallelepiped shape. The capacitor 1 includes a capacitor body 2 that forms the core of the capacitor 1. The capacitor body 2 includes a plurality of ceramic layers 3 (dielectric layers) stacked in the vertical direction and a plurality of internal electrode layers 4 and 5 disposed between the ceramic layers 3.

The ceramic layer 3 is made of a ceramic material such as a high dielectric constant ceramic such as barium titanate (BaTiO ₃ ).

  The internal electrode layers 4 (first internal electrode layers) and the internal electrode layers 5 (second internal electrode layers) are alternately arranged via the ceramic layers 3 in the stacking direction of the ceramic layers 3. The internal electrode layer 4 and the internal electrode layer 5 are electrically insulated by the ceramic layer 3. The total number of internal electrode layers 4 and 5 is about 100 layers. The internal electrode layers 4 and 5 are mainly composed of a conductive material such as Ni, but may contain a ceramic material similar to the ceramic material that constitutes the ceramic layer 3. The thickness of the internal electrode layers 4 and 5 is, for example, 2 μm or less.

  A plurality of external terminals 6 to 9 that are used, for example, as power supply terminals or ground connection terminals are formed on the front and back surfaces of the capacitor body 2. Note that the external terminals 6 to 9 are not necessarily formed on both the front surface and the back surface of the capacitor body 2 and may be formed on either the front surface or the back surface.

  The external terminals 6 to 9 are mainly made of a conductive material such as Ni, but the external terminals 6 to 9 contain a ceramic material similar to the ceramic material that forms the ceramic layer 3. By including such a ceramic material in the external terminals 6 to 9, the adhesion between the ceramic layer 3 and the external terminals 6 to 9 can be enhanced. The external terminals 6 to 9 need not contain such a ceramic material.

  A first plating film (not shown) is formed on the surfaces of the external terminals 6 to 9 for improving adhesion with an insulating layer 43 and via conductors 60 described later. The first plating film also has a function of preventing oxidation of the external terminals 6 to 9. The first plating film is made of a conductive material such as Au or Cu.

  Between the external terminals 6-9 and the 1st plating film, the 2nd plating film (not shown) for suppressing the fall of the adhesiveness of the external terminals 6-9 and the 1st plating film is provided. Is formed. More specifically, when the ceramic material is contained in the external terminals 6 to 9 as described above, the ceramic material is exposed on the surfaces of the external terminals 6 to 9, and the external terminals 6 to 9 and the first plating film There is a possibility that the adhesiveness of the material will be lowered. In order to suppress this, a second plating film is formed. The second plating film is preferably made of, for example, the same conductive material as the conductive material that is the main component of the external terminals 6 to 9. When the external terminals 6 to 9 to which the ceramic material is added can be directly plated and the adhesion strength is high, the second plating film need not be formed.

  In the capacitor main body 2, via conductors 10 and 11 penetrating the capacitor main body 2 from the front surface to the back surface of the capacitor main body 2 are formed. The via conductors 10, 11 need only penetrate at least one ceramic layer 3 in the thickness direction of the ceramic layer 3, and do not necessarily penetrate the capacitor body 2.

  Via conductors 10 and 11 have upper surfaces connected to external terminals 6 and 7, lower surfaces connected to external terminals 8 and 9, and side surfaces connected to internal electrode layers 4 and 5. Here, as shown in FIG. 2A, a clearance hole 4a is formed in a region where the via conductor 11 penetrates in the internal electrode layer 4, and the internal electrode layer 4 and the via conductor 11 are electrically insulated. Has been. Similarly, as shown in FIG. 2B, a clearance hole 5a is formed in the internal electrode layer 5 in a region where the via conductor 10 penetrates, and the internal electrode layer 5 and the via conductor 10 are electrically connected to each other. Insulated.

  The via conductors 10 and 11 are mainly made of a conductive material such as Ni, but contain a ceramic material similar to the ceramic material forming the ceramic layer 3. By including such a ceramic material in the via conductors 10 and 11, respectively, the adhesion between the ceramic layer 3 and the via conductors 10 and 11 can be improved. The via conductors 10 and 11 do not need to contain such a ceramic material.

  In the capacitor body 2, dummy electrode layers 12 and 13 that do not function as electrodes are disposed. Specifically, the dummy electrode layers 12 and 13 are arranged between the ceramic layers 3 and on the outer peripheral side of the ceramic layer 3 with respect to the internal electrode layers 4 and 5 with a predetermined distance from the internal electrode layers 4 and 5. Yes.

  The dummy electrode layer 12 (first dummy electrode layer) is disposed in substantially the same plane as the internal electrode layer 4, and the dummy electrode layer 13 (second dummy electrode layer) is formed in substantially the same plane as the internal electrode 5. ing. Specifically, the dummy electrode layer 12 is disposed between the same layers as the ceramic layer 3 where the internal electrode layer 4 is disposed, and the dummy electrode layer 13 is disposed between the ceramic layer 3 where the internal electrode layer 5 is disposed. Arranged between the same layers. The dummy electrode layers 12 and 13 may be formed between different layers from between the ceramic layers 3 on which the internal electrode layers 4 and 5 are arranged.

The internal electrode layer 4 and the dummy electrode layer 12 and the internal electrode layer 5 and the dummy electrode layer 13 are electrically insulated from each other. The ceramic layers 3 are respectively inserted in the gaps S ₁ and S ₂ between the internal electrode layers 4 and 5 and the dummy electrode layers 12 and 13, and the internal electrode layers 4 and 5 and the dummy electrode layers 12 and 13 Are reliably electrically insulated.

Gap S ₁ between the internal electrode layer 4 and the dummy electrode layer 12 and the _(first gap), and the gap S _{2 (second} gap) between the internal electrode layer 5 and the dummy electrode layer 13, a ceramic They are in a positional relationship shifted in the stacking direction of the layers 3 and do not overlap. The gaps S ₁ between the internal electrode layer 4 and the dummy electrode layer 12 are aligned in the stacking direction of the ceramic layers 3, and the gaps S ₂ between the internal electrode layer 5 and the dummy electrode layer 13 are Each of them is aligned in the stacking direction of the ceramic layers 3.

Clearance (including later-described width _{w 1a} and the width _{w 1b.) S 1} width _{w 1} (including. A gap _{S 1a} and the gap _{S 1b} will be described later) and a clearance _{S 2} (described later clearance _{S 2a} and the gap _{S 2b} Width w ₂ (including a width w _2a and a width w _2b described later) is preferably 50 μm or more. The width _{w 2} of width _{w 1} and the gap _{S 2} of the gap _{S 1} defined as described above, is less than 50 [mu] m, the ceramic into the gap _S 1, _{S 2} during lamination of the ceramic green sheets 23, 26 to be described later This is because the green sheets 23 and 26 are not filled and delamination may occur.

The dummy electrode layers 12 and 13 are formed so as to surround the internal electrode layers 4 and 5. Here, the dummy electrode layer 12 is formed using a printing method such as screen printing as described later, the width of the gap S _1a extending in a direction perpendicular to the printing direction of the dummy electrode layer 12 among the gaps S ₁ width _{w 1b} of the gap _{S 1b} extending in the printing direction parallel to the direction of w _1a and the dummy electrode layers 12 are respectively a 50～350Myuemu, and the width _{w 1a} of the gap _{S 1a} is more than the width _{w 1b} of the gap _{S 1b} It is preferable that The width _{w 1b} of width _{w 1a} and the gap _{S 1b} of the gap _{S 1a} respectively and 50~350μm, if less than 50 [mu] m, may bleed printing gap _{S 1a} and the gap _{S 1b} occurs during printing, the This is because the reliability may not be ensured in some cases, and if it exceeds 350 μm, the area for forming the capacitor becomes small and the electrical characteristics deteriorate. Further, the width _{w 1a} of the gap _{S 1a} was above the width _{w 1b} of the gap _{S 1b,} the nature of the printing, in order to form a small pattern of such bleeding.

The dummy electrode layer 13 also are formed using a printing method such as screen printing as described later, the gap extends in a direction perpendicular to the printing direction of the dummy electrode layer 13 among the gaps S ₂ for the same reason as above S _2a the width _{w 2b} width _{w 2a} and the gap _{S 2b} extending in the printing direction parallel to the direction of dummy electrode layer 13 of which respectively a 50～350Myuemu, and widths _{w 2a} gap _{S 2b} of the gap _{S 2a} It is preferable that it is _w2b or more.

  The outer peripheral surfaces 12 a and 13 a of the dummy electrode layers 12 and 13 are exposed from between the ceramic layers 3. Here, considering relaxation of the step formed near the end of the capacitor 1, it is preferable that all the outer peripheral surfaces 12 a and 13 a of the dummy electrode layers 12 and 13 are exposed from between the ceramic layers 3. Only the outer peripheral surfaces 12a and 13a of the part may be exposed. The outer circumference of the dummy electrode layers 12 and 13 is preferably 80% or more of the outer circumference of the ceramic layer 3.

A part of the dummy electrode layer 12 overlaps a part of the dummy electrode layer 13 and the internal electrode layer 5 in the stacking direction of the ceramic layer 3. Here, the width w ₃ of the overlapping portion of the dummy electrode layer 12 and the dummy electrode layer 13 in the stacking direction of the ceramic layer 3 is equal to the overlapping portion of the dummy electrode layer 12 and the internal electrode layer 5 in the stacking direction of the ceramic layer 3. The width is preferably ₄ or more. In the present embodiment, an example in which a part of the dummy electrode layer 12 overlaps a part of the internal electrode layer 5 in the stacking direction of the ceramic layer 3 is described. However, a part of the dummy electrode layer 13 is described. However, it may overlap with a part of the internal electrode layer 4 in the laminating direction of the ceramic layer 3. In this case, the width of the overlapping portion of the dummy electrode layer 12 and the dummy electrode layer 13 in the stacking direction of the ceramic layer 3 is equal to the width of the overlapping portion of the dummy electrode layer 13 and the internal electrode layer 4 in the stacking direction of the ceramic layer 3. It is preferable that it is more than the width.

The width w ₃ of the overlapping portion of the dummy electrode layer 12 and the dummy electrode layer 13 in the stacking direction of the ceramic layer 3 is preferably 100 μm or more. When the width w ₃ is defined as described above, if the width is less than 100 μm, the end of the capacitor has a sharply raised shape, and the step formed at the end of the capacitor is not sufficiently relaxed, and the resin filler This is because there is a possibility that may enter the back side of the capacitor.

  The total number of dummy electrode layers 12 and 13 is preferably at least half of the total number of internal electrode layers 4 and 5 (about 50 layers) in consideration of the relief of the step formed near the end of capacitor 1. It is more preferable that the total number of internal electrode layers 4 and 5 is approximately the same (about 100 layers).

  Although the dummy electrode layers 12 and 13 are made of a conductive material, the conductive material constituting the dummy electrode layers 12 and 13 takes into consideration the influence and the forming process at the time of firing ceramic green sheets 23 and 26 described later. Then, it is preferable that it is the same material as the electroconductive material which comprises the internal electrode layers 4 and 5. For the same reason, the thickness of the dummy electrode layers 12 and 13 is preferably substantially the same as the thickness of the internal electrode layers 4 and 5 (for example, 2 μm or less).

Note that the corners of the four positions of the outer peripheral surface 1a of the capacitor 1, the chamfered portion 1b chamfer dimension C ₁ is shaped 0.6mm or more planes as shown in FIG. 3 is formed. Here, the outer peripheral surface 1 a of the capacitor 1 is a side surface other than the surface on which the external terminals 6 to 9 are formed in the capacitor 1. Specifically, the outer peripheral surface 1 a of the capacitor 1 is the outer peripheral surface of the ceramic layer 3. 3a and the outer peripheral surfaces 12a and 13a of the dummy electrode layers 12 and 13. The chamfer dimension C _1, the length shown in FIG. Chamfer dimension C ₁ may be actually measured, it is possible to determine from the C face length C _2. The C face length C ₂ is the length of the line as shown in FIG. 3, a value obtained by dividing the C face length C ₂ in √2 is chamfer dimension C _1.

Chamfer dimension _{C 1} is preferably from the viewpoint of the capacitor fabrication is 0.8mm or more 1.2mm or less. Instead of the chamfered portion 1 b or together with the chamfered portion 1 b, a rounded portion having a curvature radius of 0.6 mm or more may be formed at at least one corner of the outer peripheral surface 1 a of the capacitor 1. In this case, the radius of curvature of the rounded portion is desirably 0.8 mm or greater and 1.2 mm or less from the viewpoint of manufacturing a capacitor.

  The capacitor 1 can be manufactured, for example, by the following procedure. In the present embodiment, a process for manufacturing a plurality of capacitors 1 at once will be described. 4 (a) and 4 (b) are a cross-sectional view and a plan view schematically showing a manufacturing process of the wiring board built-in capacitor according to the present embodiment, and FIGS. 5 (a) and 5 (b). FIG. 6A is a cross-sectional view and a plan view schematically showing the manufacturing process of the wiring board built-in capacitor according to this embodiment. FIGS. 6A and 6B are wiring boards according to this embodiment. FIG. 7A is a cross-sectional view schematically showing a manufacturing process of a built-in capacitor, and FIGS. 7A and 7B are plan views schematically showing the manufacturing process of the wiring board built-in capacitor according to the present embodiment. FIG.

  First, a plurality of ceramic green sheets each having an internal electrode pattern 21 that becomes the internal electrode layer 4 after firing and a dummy electrode pattern 22 that becomes the dummy electrode layer 12 after firing are formed on the surface by, for example, screen printing, and become the ceramic layer 3 after firing. 23 (dielectric sheet) is prepared (FIGS. 4A and 4B).

  In addition, a plurality of ceramic green sheets which are formed on the surface by, for example, screen printing to form an internal electrode pattern 24 which becomes the internal electrode layer 5 after firing and a dummy electrode pattern 25 which becomes the dummy electrode layer 13 after firing, and which becomes the ceramic layer 3 after firing. 26 (dielectric sheet) is prepared (FIGS. 5A and 5B).

  In the present embodiment, since a plurality of capacitors 1 are produced at a time, a plurality of internal electrode patterns 21 and a plurality of dummy electrode patterns 22 are formed on the surface of each ceramic green sheet 23, and each ceramic green sheet is formed. A plurality of internal electrode patterns 24 and a plurality of dummy electrode patterns 25 are formed in 26. Here, the broken lines shown in FIG. 4B and FIG. 5B represent the boundary lines of the individual capacitors, but the outer periphery of the dummy electrode patterns 22 and 25 is formed up to this boundary line. The dummy electrode patterns 22 and 25 are formed integrally with the adjacent dummy electrode patterns 22 and 25.

  The internal electrode patterns 21 and 24 are respectively formed in regions (hereinafter referred to as “capacitor forming regions”) R surrounded by a broken line shown in FIGS. 4B and 5B. . In the internal electrode patterns 21 and 24, clearance holes 21a and 24a to be the clearance holes 4a and 5a are formed.

  The dummy electrode patterns 22 and 25 are formed on the outer peripheral side of the ceramic green sheets 23 and 26 with respect to the internal electrode patterns 21 and 24 so as to surround the internal electrode patterns 21 and 24 at a predetermined interval. Has been. The inner peripheries of the dummy electrode patterns 22 and 25 are located in the capacitor forming region R.

  The dummy electrode patterns 22 and 25 may be formed in a process different from the process of forming the internal electrode patterns 21 and 24, but are formed in the same process as the process of forming the internal electrode patterns 21 and 24 from the viewpoint of efficiency. It is preferable.

  Next, on a cover layer 27 formed by laminating a predetermined number of ceramic green sheets, a ceramic green sheet 23 in which internal electrode patterns 21 and the like are formed, and a ceramic green sheet 26 in which internal electrode patterns 24 and the like are formed, Are alternately laminated, and a cover layer 28 formed by the same procedure as that for the cover layer 27 is further laminated thereon and pressed to form a laminated body 29. Thereafter, a via hole penetrating from the front surface to the back surface of the multilayer body 29 is formed, and a conductive paste is press-fitted into the via hole to form a via conductor paste 30 to be the via conductors 10 and 11 after firing (FIG. 6A). .

  Next, the laminated body 29 formed by the same procedure is stacked on the laminated body 29 on which the via conductor paste 30 is formed, and pressed to form the laminated body 31. Thereafter, external terminal patterns 32 to be the external terminals 6 to 9 after firing connected to the via conductor paste 30 by, for example, screen printing or the like are formed on the front and back surfaces of the multilayer body 31 (FIG. 6B).

  After the external terminal pattern 32 is formed, the portions of the ceramic green sheets 23 and 26 and the dummy electrode patterns 22 and 25 at the corners of the capacitor 1 are punched into a rectangular shape by punching or the like, for example, to become the chamfered portion 1b 31a is formed (FIG. 7A). Further, a break groove along the broken line shown in FIG.

  Thereafter, these are degreased and further baked at a predetermined temperature for a predetermined time. By this firing, the ceramic green sheet 23 and the like are thereby sintered to form the ceramic layer 3, and the internal electrode pattern 21 and the like are sintered to form the internal electrode layer 4 and the like.

  After firing, a second plating film is formed on the surfaces of the external terminals 6 to 9 by, for example, electroless plating, and further, a first plating film is formed on the surface of the second plating film, for example, by electroless plating. When the external terminals 6 to 9 to which the ceramic material is added can be directly plated and the adhesion strength is high, the second plating film need not be formed.

  Finally, adjacent capacitors 1 are separated along the broken line shown in FIG. 7A (FIG. 7B). Thereby, a plurality of capacitors 1 shown in FIG. 1 are produced.

  The capacitor 1 is used by being built in a wiring board. Hereinafter, a wiring board incorporating the capacitor 1 will be described. FIG. 8 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  The wiring substrate 40 shown in FIG. 8 is an organic substrate formed in a rectangular parallelepiped shape. The wiring board 40 is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers, for example.

  The wiring board 40 includes, for example, a core board 41 as a wiring board body that forms the core of the wiring board 40. The core substrate 41 includes a core material 41a formed of, for example, a glass-epoxy resin composite material, and a wiring layer 41b made of, for example, Cu having a desired pattern, formed on both surfaces of the core material 41a.

  The core substrate 41 has a plurality of through holes penetrating in the vertical direction of the core substrate 41, and a through hole conductor 41c electrically connected to the wiring layer 41b is formed in the through hole.

  For example, an opening 41 d as a capacitor housing portion for housing the capacitor 1 is formed in the central portion of the core substrate 41. The opening 41d is formed in, for example, a rectangular parallelepiped shape larger than the capacitor 1, and the capacitor 1 is accommodated in the opening 41d. The capacitor housing portion of the core substrate 41 is not limited to the opening 41d, and may be a recess.

  Round corners with a radius of curvature of 0.1 mm or more and 2 mm or less or chamfered portions with a chamfer dimension of 0.1 mm or more and 2 mm or less are formed at the corners of four inner side surfaces of the core substrate 41.

  A gap between the core substrate 41 and the capacitor 1 is filled with a resin filler 42 made of, for example, a polymer material as a filler, and the capacitor 1 is attached to the core substrate 41 via the resin filler 42. It is fixed against.

  Here, the resin filler 42 is filled into the gap between the core substrate 41 and the capacitor 1, for example, by sticking an adhesive tape to the back surface of the core substrate 41 and attaching the back surface of the capacitor 41 to the adhesive tape. In this manner, the capacitor 1 is disposed in the opening 41d of the core substrate 41, and the position of the capacitor 1 with respect to the core substrate 41 is fixed with an adhesive tape. The resin filler 42 also has an action of absorbing the thermal expansion difference between the in-plane direction and the thickness direction between the core substrate 41 and the capacitor 1 by its own elastic deformation.

  A build-up wiring layer is formed above the surfaces of the core substrate 41 and the capacitor 1 and below the back surfaces of the core substrate 41 and the capacitor 1. The buildup wiring layer includes insulating layers 43 to 49 made of a thermosetting resin such as an epoxy resin. Wiring layers 50 to 55 made of a conductive material such as Cu are formed between the insulating layers 43 and 44, for example.

  The surface of the insulating layer 46 and the back surface of the insulating layer 49 are covered with solder resists 56 and 57 made of, for example, a photosensitive resin composition. Openings are formed in the solder resists 56 and 57, and terminals 58 for electrically connecting to the semiconductor chip (not shown) from the openings and terminals 59 for connecting to, for example, a main substrate (not shown) or the like. Is exposed. The terminals 58 are electrically connected to the external terminals 6 and 7 and the wiring layer 41b through via conductors 60 and the like, and the terminal 59 is connected to the external terminals 8 and 9 and wiring layers 41b through the via conductor 61. Are electrically connected.

  In this embodiment, since the dummy electrode layers 12 and 13 are formed on the outer peripheral side of the ceramic layer 3 from the internal electrode layers 4 and 5, the thickness of the end portion of the capacitor 1 can be increased. It is possible to provide the capacitor 1 in which the step formed near the end portion is relaxed. This makes it difficult for the resin filler 42 to enter the back side of the capacitor 1 when the resin filler 42 is filled in the gap between the core substrate 41 and the capacitor 1. As a result, it becomes difficult for the resin filler 42 to come into contact with the external terminals 8 and 9 disposed on the back surface of the capacitor 1, so that conduction failure can be reduced. For example, when the distance from the front surface of the external terminals 6 and 7 to the back surface of the external terminals 8 and 9 is 0.87 mm, and the dummy electrode layers 12 and 13 are not formed, While the step was 40-50 μm, when the dummy electrode layers 12 and 13 were formed, the step near the end of the capacitor was relaxed to about 10 μm.

  In this embodiment, since the dummy electrode layers 12 and 13 are formed at a predetermined interval from the internal electrode layers 4 and 5, when forming the first and second plating films on the external terminals 6 to 9 Even when the plating solution adheres to the dummy electrode layers 12 and 13, the plating solution hardly adheres to the internal electrode layers 4 and 5. Thereby, it is difficult to electrically short-circuit between the internal electrode layers 4 and 5, and the conduction failure can be reduced.

And the gap S ₁ between the internal electrode layer 4 and the dummy electrode layer 12, when the gap S ₂ between the internal electrode layer 5 and the dummy electrode layer 13 are overlapped in the stacking direction of the ceramic layers 3, In the stacking direction of the ceramic layer 3, there are portions where both the internal electrode layers 4 and 5 and the dummy electrode layers 12 and 13 do not exist. Since the internal electrode layers 4 and 5 and the dummy electrode layers 12 and 13 do not exist in such a portion, the thickness becomes thinner than the other portions, resulting in a locally recessed shape. If the dent is formed at a location relatively close to the outer periphery of the capacitor 1, the resin filler 42 may enter the back side of the capacitor 1. In contrast, in the present embodiment, the gap S ₁ between the internal electrode layer 4 and the dummy electrode layer 12, between the internal electrode layer 5 and the dummy electrode layer 13 gap S ₂ and the ceramic layer 3 Since they do not overlap in the stacking direction, it is difficult to form such local dents, and the conduction failure can be further reduced.

In this embodiment, since the chamfer dimension C ₁ at a corner of the outer peripheral surface 1a of the capacitor 1 are formed chamfered portions 1b of the above 0.6 mm, the thermal stress on the corners of the capacitor 1 side of the resin filler 42 Are less likely to concentrate, and the occurrence of cracks at the corner of the resin filler 42 on the capacitor 1 side can be suppressed. Even when the rounded portion 1c having a radius of curvature of 0.6 mm or more is formed at the corner of the outer peripheral surface 1a of the capacitor 1, the same effect as the chamfered portion 1b can be obtained.

  In the present embodiment, since the chamfered portion 1b and the rounded portion are formed at the corner portion of the outer peripheral surface 1a of the capacitor 1, the corner portion of the capacitor 1 is compared with the case where the chamfered portion 1b and the rounded portion are not formed. The distance from the signal line existing in the vicinity to the ceramic layer 4 increases. Thereby, the signal delay of the signal line existing near the corner of the capacitor 1 can be reduced.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, an example in which a dummy electrode layer is arranged so as to be substantially flush with either one of the first internal electrode layer and the second internal electrode layer will be described. In the present embodiment and the subsequent embodiments, the same members as those described in the first embodiment are denoted by the same reference numerals and described in the first embodiment. Contents that overlap with the contents that have been made may be omitted. FIG. 9 is a schematic longitudinal cross-sectional view of the wiring board built-in capacitor according to the present embodiment.

  As shown in FIG. 9, in the capacitor 70 of the present embodiment, the dummy electrode layer 12 is disposed, but the electrode layer corresponding to the dummy electrode layer 13 of the first embodiment is not disposed. The outer peripheral surface of the internal electrode layer 5 is not exposed from between the ceramic layers 3.

  In the present embodiment, since the dummy electrode layer 12 is disposed on the outer peripheral side of the internal electrode layer 4, the same effects as those described in the first embodiment can be obtained. Note that the dummy electrode layer 13 corresponding to the first embodiment may be arranged without arranging the dummy electrode layer 12 shown in FIG. 9, and in this case, the same effect as in the present embodiment can be obtained. It is done.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an example will be described in which all outer peripheral surfaces of the internal electrode layers are exposed from the ceramic layers in almost all internal electrode layers without forming the dummy electrode layers. FIG. 10 is a schematic longitudinal sectional view of the capacitor with a built-in wiring board according to the present embodiment, and FIGS. 11A and 11B are schematic views of the capacitor with a built-in wiring board according to the present embodiment. FIG.

  As shown in FIG. 10 to FIG. 11B, in the capacitor 80 of the present embodiment, almost all the outer peripheral surfaces 4 b and 5 b in almost all the internal electrode layers 4 and 5 are exposed from the ceramic layer 3. . Also in this embodiment, a chamfered portion 80 b is formed on the outer peripheral surface 80 a of the capacitor 80, but in this embodiment, the outer peripheral surface 80 a of the capacitor 80 is the outer peripheral surface 3 a of the ceramic layer 3. And outer peripheral surfaces 4b and 5b of the internal electrode layers 4 and 5.

  The capacitor 80 can be manufactured, for example, by the following procedure. 12A and 12B are plan views schematically showing the manufacturing process of the wiring board built-in capacitor according to the present embodiment.

  The capacitor 80 of the present embodiment can be manufactured by a procedure substantially similar to the procedure described in the first embodiment, but as shown in FIGS. 12 (a) and 12 (b). Further, the dummy electrode patterns 22 and 25 in the first embodiment are not formed on the surfaces of the ceramic green sheets 23 and 26, and the outer peripheries of the internal electrode patterns 21 and 24 are formed up to the boundary line of the capacitor. Yes. The internal electrode patterns 21 and 24 are formed integrally with the adjacent internal electrode patterns 21 and 24.

  In the present embodiment, almost all of the outer peripheral surfaces 4b and 5b are exposed from between the ceramic layers 3 in almost all of the internal electrode layers 4 and 5, and therefore the same effects as those described in the first embodiment. Is obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an example in which a ceramic pattern is formed on the surface of a ceramic green sheet different from the ceramic green sheet on which the internal electrode pattern is formed and at a position corresponding to the clearance hole will be described.

  Hereinafter, a process for manufacturing a capacitor will be described. FIGS. 13A and 13B are a side view and a plan view of a ceramic green sheet on which the ceramic pattern according to the present embodiment is formed, and FIG. 14 is a wiring board built-in capacitor according to the present embodiment. It is sectional drawing which showed typically the manufacturing process.

  First, cover layers 27 and 28 are formed, and a plurality of ceramic green sheets 36 (dielectric sheets) on which ceramic patterns 35 (dielectric patterns) are formed are prepared (FIGS. 13A and 13B). . In the present embodiment, the ceramic pattern 35 is formed on the surface of the ceramic green sheet 26 constituting the cover layers 27, 28, but the ceramic green sheets 23, 26 on which the internal electrode patterns 21, 24 are formed. May be formed in the clearance holes 21a and 24a.

  The ceramic pattern 35 is formed at a position corresponding to the clearance holes 21a and 24a. The material constituting the ceramic pattern 35 is preferably the same material as the ceramic material constituting the ceramic green sheet 36.

  After preparing the ceramic green sheet 36 and the like, the ceramic green sheet 36 on which the ceramic pattern 35 is formed and a predetermined number of ceramic green sheets on which the internal electrode pattern 21 and the like are not formed are laminated to produce the cover layer 27. To do. Then, the ceramic green sheets 23 on which the internal electrode patterns 21 and the dummy electrode patterns 22 are formed and the ceramic green sheets 26 on which the internal electrode patterns 24 and the dummy electrode patterns 25 are formed are alternately stacked on the cover layer 27, and A cover layer 28 formed by the same procedure is laminated thereon. Then, these are pressurized and the laminated body 90 is formed. After forming the laminated body 90, a via hole penetrating from the front surface to the back surface of the laminated body 90 is formed, and a conductive paste is pressed into the via hole to form a via conductor paste 30 to be the via conductors 10 and 11 after firing ( FIG. 14). Since the following manufacturing process is the same as that of the first embodiment, the description thereof is omitted.

  Usually, the thickness of the capacitor body where the clearance hole exists is thinner than the thickness of the other part of the capacitor body because one internal electrode layer does not exist. In contrast, in the present embodiment, since the ceramic pattern 35 is formed on the cover layers 27 and 28 at positions corresponding to the clearance holes 21a and 24a, the portion of the capacitor body 2 where the clearance holes 21a and 24a are present. The thickness can be increased, and the thickness can be substantially the same as the thickness of the other part of the capacitor body 2. Even when the ceramic pattern 35 is formed on the surfaces of the ceramic green sheets 23 and 26 on which the internal electrode patterns 21 and 24 are formed and in the clearance holes 21a and 24a, the same effect as described above can be obtained.

  When a ceramic pattern having a thickness greater than that of the internal electrode patterns 21 and 24 is formed on the surface of the ceramic green sheets 23 and 26 on which the internal electrode patterns 21 and 24 are formed and in the clearance holes 21a and 24a, the ceramic green sheet 23 and the like When the layers are stacked, the ceramic pattern may be deformed and the internal electrode patterns 21 and 24 may be misaligned. On the other hand, in the present embodiment, the ceramic pattern 35 is provided on the surface of the ceramic green sheet 36 different from the ceramic green sheets 23 and 26 on which the internal electrode patterns 21 and 24 are formed, and at positions corresponding to the clearance holes 21a and 24a. Therefore, even if the ceramic pattern 35 thicker than the thickness of the internal electrode patterns 21 and 24 is formed and the ceramic pattern 35 is slightly deformed, the internal electrode patterns 21 and 24 are formed on the ceramic green sheet 36. Since they are not formed, it is difficult for the internal electrode patterns 21 and 24 to be misaligned when the ceramic green sheets 23 and the like are stacked.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. In this embodiment, an example in which capacitors are arranged in an insulating layer on a core substrate will be described. FIG. 15 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  As shown in FIG. 15, no opening is formed in the core substrate 41 of the wiring substrate 100, and the capacitor 110 is disposed in the insulating layer 44 on the core substrate 41. In the capacitor 110 of this embodiment, the total number of internal electrode layers 4 and 5 is about 10, which is smaller than the thickness of the capacitors 1, 70 and 80 described in the first to third embodiments. Yes. In this embodiment, the capacitor 110 has the same structure as the capacitor 1 described in the first embodiment, but the same structure as the capacitors 70 and 80 described in the second and third embodiments. It may be.

  The capacitor 110 can be disposed in the insulating layer 44 by the following procedure, for example. First, the capacitor body 2 in which the dummy electrode layers 12 and 13 are formed is disposed on the insulating layer 43 formed on the core substrate 41. Thereafter, the insulating layer 44 is placed on the capacitor body 2 and pressed while heating. As a result, the insulating layer 44 on the capacitor body 2 flows to the side of the capacitor body 2, and the capacitor body 2 is disposed in the insulating layer 44. Further, a via hole penetrating the insulating layers 43 and 44 and the capacitor body 2 is formed immediately above the wiring layer 41b. Via conductors 10 and 11 connected to the wiring layer 41b are formed in the via hole, and the capacitor body. External terminals 6 and 7 are formed on the surface of 2 to complete the capacitor 110.

  When the thickness of the capacitor is extremely thin, the mechanical strength of the capacitor is lowered and the capacitor may be warped. On the other hand, in the present embodiment, since the dummy electrodes 12 and 13 are provided, the mechanical strength of the capacitor 110 can be improved and the warpage generated in the capacitor 110 can be reduced. The same effect can be obtained when the capacitors 70 and 80 described in the second and third embodiments are used as the capacitor 110 of the present embodiment.

  In the present embodiment, since the capacitor 110 is disposed in the insulating layer 44 formed on the core substrate 41, the distance between the capacitor 110 and the semiconductor chip can be further shortened. Thereby, wiring resistance and an inductance can be reduced more.

  In the second embodiment, when the dummy electrode layer 12 is arranged on the outer peripheral side of the internal electrode layer 4, at least a part of the outer peripheral surface of the internal electrode layer 5 is exposed from the ceramic layer 3. Also good. Further, when the dummy electrode layer 13 is arranged on the outer peripheral side of the internal electrode layer 5, at least a part of the outer peripheral surface of the internal electrode layer 4 may be exposed from the ceramic layer 3. It is possible to alleviate a level difference caused by the electrode layer corresponding to the dummy electrode layer not being disposed in a part of the dielectric layer near the outer periphery.

  The present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention.

1 is a schematic longitudinal sectional view of a wiring board built-in capacitor according to a first embodiment. (A) And (b) is a typical cross-sectional view of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. 1 is a schematic plan view of a wiring board built-in capacitor according to a first embodiment. (A) And (b) is sectional drawing and the top view which showed typically the manufacturing process of the capacitor | condenser for wiring board built-in concerning 1st Embodiment. (A) And (b) is sectional drawing and the top view which showed typically the manufacturing process of the capacitor | condenser for wiring board built-in concerning 1st Embodiment. (A) And (b) is sectional drawing which showed typically the manufacturing process of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. (A) And (b) is the top view which showed typically the manufacturing process of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. 1 is a schematic longitudinal sectional view of a wiring board in which a wiring board built-in capacitor according to a first embodiment is built. It is a typical longitudinal cross-sectional view of the capacitor | condenser for wiring board built-in which concerns on 2nd Embodiment. FIG. 6 is a schematic longitudinal sectional view of a wiring board built-in capacitor according to a third embodiment. (A) And (b) is a typical cross-sectional view of the capacitor | condenser for wiring board incorporation which concerns on 3rd Embodiment. (A) And (b) is the top view which showed typically the manufacturing process of the capacitor | condenser for wiring board built-in which concerns on 3rd Embodiment. (A) And (b) is the side view and top view of a ceramic green sheet in which the ceramic pattern based on 4th Embodiment was formed. It is sectional drawing which showed typically the manufacturing process of the capacitor for wiring board built-in which concerns on 4th Embodiment. It is a typical longitudinal cross-sectional view of the wiring board with which the wiring board built-in capacitor concerning a 5th embodiment was built.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,70,80,110 ... Capacitor, 3 ... Ceramic layer, 4,5 ... Internal electrode layer, 4b, 5b ... Outer peripheral surface, 10, 11 ... Via conductor, 12, 13 ... Dummy electrode layer, 12a, 13a ... Outer periphery Surface, 40, 100 ... Wiring substrate, 41 ... Core substrate, 42 ... Resin filler.

Claims (11)

A plurality of stacked dielectric layers;
A plurality of internal electrode layers disposed between different dielectric layers;
A dummy electrode layer disposed between the dielectric layers and on the outer peripheral side of the dielectric layer with respect to the internal electrode layer; and a dummy electrode layer disposed at a predetermined interval from the internal electrode layer. Capacitor.   2. The wiring board built-in capacitor according to claim 1, wherein an outer peripheral surface of the dummy electrode layer is exposed from the dielectric layer. The dummy electrode layer is formed in substantially the same plane as the internal electrode layer using a printing method,
Of the gap between the internal electrode layer and the dummy electrode layer, the width of the gap extending in the direction perpendicular to the printing direction of the dummy electrode layer and the width of the gap extending in the direction parallel to the printing direction of the dummy electrode layer are: Each gap is 50 to 350 μm, and the width of the gap extending in the direction perpendicular to the printing direction of the dummy electrode layer is greater than the width of the gap extending in the direction parallel to the printing direction of the dummy electrode layer. 3. The wiring board built-in capacitor according to claim 1 or 2. The internal electrode layer includes a first internal electrode layer and second internal electrode layers arranged alternately with the first internal electrode layer via the dielectric layer,
The dummy electrode layer includes a first dummy electrode disposed substantially in the same plane as the first internal electrode layer, and a second dummy electrode layer disposed substantially in the same plane as the second internal electrode layer. With
The first gap between the first internal electrode layer and the first dummy electrode layer and the second gap between the second internal electrode layer and the second dummy electrode layer are: 4. The wiring board built-in capacitor according to claim 1, wherein the capacitor does not overlap in the stacking direction of the dielectric layers. 5.   5. The wiring board built-in capacitor according to claim 4, wherein a width of the first gap and a width of the second gap are each 50 μm or more. The first dummy electrode layer and the second dummy electrode layer, and the first dummy electrode layer and the second internal electrode layer or the second dummy electrode and the first internal electrode layer, A part of the dielectric layers overlap in the stacking direction,
The width of the overlapping portion between the first dummy electrode layer and the second dummy electrode layer in the stacking direction of the dielectric layer is such that the width of the first dummy electrode layer and the second dummy layer in the stacking direction of the dielectric layer is as follows. 6. The wiring board built-in according to claim 4, wherein the width is equal to or larger than a width of an overlapping portion between the second dummy electrode layer and the first internal electrode layer. Capacitor. The first dummy electrode layer and the second dummy electrode layer partially overlap in the stacking direction of the dielectric layer,
7. The width of the overlapping portion between the first dummy electrode layer and the second dummy electrode layer in the stacking direction of the dielectric layers is 100 μm or more. 7. Wiring board built-in capacitor as described in 1. The internal electrode layer includes a first internal electrode layer and second internal electrode layers arranged alternately with the first internal electrode layer via the dielectric layer,
4. The dummy electrode layer according to claim 1, wherein the dummy electrode layer is disposed so as to be substantially flush with any one of the first internal electrode layer and the second internal electrode layer. A capacitor for wiring board as set forth in claim 1. A wiring board built-in capacitor comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers disposed between the different dielectric layers,
A circuit board built-in capacitor, wherein substantially all of the outer peripheral surface of almost all of the internal electrode layers is exposed from the dielectric layer.   10. The semiconductor device according to claim 1, further comprising a via conductor that penetrates at least one of the dielectric layers in a thickness direction of the dielectric layer and is electrically connected to at least one of the internal electrode layers. 5. A wiring board built-in capacitor according to any one of the above.   A wiring board comprising the wiring board built-in capacitor according to any one of claims 1 to 10.

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