JP2007096004A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007096004A
JP2007096004A JP2005283616A JP2005283616A JP2007096004A JP 2007096004 A JP2007096004 A JP 2007096004A JP 2005283616 A JP2005283616 A JP 2005283616A JP 2005283616 A JP2005283616 A JP 2005283616A JP 2007096004 A JP2007096004 A JP 2007096004A
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metal
circuit
semiconductor device
circuit board
metal terminal
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Junichi Nakao
淳一 中尾
Atsushi Kajiwara
淳志 梶原
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for electric power which mitigates a stress in the solder joint between a metal terminal and a circuit substrate, by keeping the thickness of solder between the metal terminal and the circuit substrate in constant. <P>SOLUTION: The semiconductor device is provided with a chip 1, metal terminals 7b, 7c electrically connected to the electrode of the chip 1, and a circuit substrate 3 mounting chip mounting unit 3a for mounting the chip 1 and the metal terminals 7b, 7c while having terminal mounting units 3b, 3c with a metal circuit formed thereon. In this case, one end 7d of the metal terminals 7b, 7c is opposed in parallel to the surfaces of the metal circuits 3b, 3c, and both of them are bonded by solders 10b, 10c between them. At least one projection 9 for maintaining a space is formed on the bent part at one end of the metal terminals 7b, 7c or the surfaces of the metal circuits 3b, 3c opposed to the bent part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、高信頼性が要求される放熱用金属ベースと回路基板間のはんだ接合部を有する大電力用の半導体装置に関するものである。   The present invention relates to a high-power semiconductor device having a solder joint between a heat dissipation metal base and a circuit board, which requires high reliability.

従来の半導体装置は、ＩＧＢＴ(Insulated Gate Bipolar Transistor) やパワーＭＯＳＦＥＴなどの大電力用の半導体素子が形成された半導体チップ（以下、チップという）と、このチップに設けられた電極に電気的に接続された金属端子と、このチップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板とから構成され、前記金属端子の一端は、前記金属回路表面と平行に対向し、この金属端子の一端と前記金属回路表面との間は、ハンダ層により接合されている。回路基板は、セラミックスからなり、主面及び裏面両面に銅などの金属回路が設けられている。チップ及び金属端子が搭載され、チップ及び金属端子が搭載された回路基板は、ケース内において、樹脂封止されている。回路基板は、放熱基板上に搭載され、回路基板裏面に形成された金属層を介して前記放熱基板にハンダ付けされている。チップと回路基板とをはんだにより接着してから、アルミニウムなどのボンディングワイヤで回路基板の金属回路とチップの電極とを接続する。回路基板は、放熱用基板に搭載してから、これをケースに収容する。その後、ケースシリコーンゲルを注入し、さらに液状エポキシ樹脂を注入して回路基板等を封止して製品組立てを完了する。   A conventional semiconductor device is electrically connected to a semiconductor chip (hereinafter referred to as a chip) on which a high-power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET is formed, and an electrode provided on the chip. And a circuit board having a chip mounting portion on which the chip is mounted and a terminal mounting portion on which the metal terminal is mounted and a metal circuit is formed, and one end of the metal terminal is connected to the metal terminal. Opposite the circuit surface in parallel, one end of the metal terminal and the metal circuit surface are joined by a solder layer. The circuit board is made of ceramics, and metal circuits such as copper are provided on both the main surface and the back surface. The chip and the metal terminal are mounted, and the circuit board on which the chip and the metal terminal are mounted is resin-sealed in the case. The circuit board is mounted on the heat dissipation board and soldered to the heat dissipation board via a metal layer formed on the back surface of the circuit board. After the chip and the circuit board are bonded together by solder, the metal circuit of the circuit board and the electrode of the chip are connected by a bonding wire such as aluminum. The circuit board is mounted on the heat dissipation board and then accommodated in the case. Thereafter, case silicone gel is injected, and liquid epoxy resin is further injected to seal the circuit board and the like, thereby completing the product assembly.

この半導体装置、いわゆる半導体モジュールの問題点としては、ＴＣＴ３００サイクル（−４０℃×３０分〜２５℃×１０分〜１２５℃×３０分）において、はんだ接合部にはんだクラック（３／１０ｐｃｓＮＧ）が入り信頼性が問題となった。市場での要求は、１０００サイクルで製品信頼性保証する必要があり対策を要するものであった。
寿命の短い製品はんだ接合部を調査した結果、金属端子と回路基板とのはんだ接合部のはんだ厚が設計値１００μｍに対し薄い所で３０μｍしかなく接合部応力が増加して、はんだ厚が薄いほど製品寿命が短いという結果が得られた。また金属端子と回路基板間のはんだ厚を一定に保つことは難しく技術対策が必要であうという問題があった。
特許文献１には、パワーモジュールで基板に電極端子をはんだ付けする場合に熱的破壊応力を抑制するために電極端子にベントを設けることが記載されている。即ち、この半導体装置は、Ｃベンド先端の肉厚を薄肉化することによって効果的に配線端子の剛性を低減させて配線端子半田付け部にかかる応力を低減できる構造とし、配線抵抗をほとんど増加させることなしに温度変化により発生する配線端子半田付け部の応力を低減させることができる。
特開平８−８３７４号公報 As a problem of this semiconductor device, so-called semiconductor module, a solder crack (3/10 pcsNG) enters the solder joint in TCT 300 cycle (-40 ° C. × 30 minutes to 25 ° C. × 10 minutes to 125 ° C. × 30 minutes). Reliability became a problem. The demand on the market is that it is necessary to guarantee product reliability in 1000 cycles and to take countermeasures.
As a result of investigating the product solder joints with short lifespan, the solder thickness of the solder joints between the metal terminals and the circuit board is only 30 μm where the solder thickness is thinner than the design value of 100 μm. The result was a short product life. In addition, it is difficult to keep the solder thickness between the metal terminal and the circuit board constant, and there is a problem that technical measures are required.
Patent Document 1 describes that a vent is provided in an electrode terminal in order to suppress thermal breakage stress when the electrode terminal is soldered to a substrate with a power module. That is, this semiconductor device has a structure capable of effectively reducing the rigidity of the wiring terminal by reducing the thickness of the tip of the C bend and reducing the stress applied to the soldering portion of the wiring terminal, and almost increases the wiring resistance. It is possible to reduce the stress at the soldering portion of the wiring terminal that occurs due to temperature changes.
JP-A-8-8374

金属端子と回路基板間のはんだ厚を一定に保つことによって、金属端子と回路基板のはんだ接合部における応力を緩和する半導体装置を提供する。   Provided is a semiconductor device that relieves stress at a solder joint between a metal terminal and a circuit board by keeping the solder thickness between the metal terminal and the circuit board constant.

本発明の半導体装置の一態様は、チップと、前記チップの電極に電気的に接続された金属端子と、前記チップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板と、前記金属端子の一端は、前記金属回路表面と平行に対向し、前記金属端子の一端と前記金属回路との間ははんだ層により接合され、且つ前記金属端子の一端もしくは前記一端に対向する金属回路表面には少なくとも１つの突起が形成されていることを特徴としている。   In one embodiment of the semiconductor device of the present invention, a chip, a metal terminal electrically connected to the electrode of the chip, a chip mounting portion on which the chip is mounted, and the metal terminal are mounted, and a metal circuit is formed. A circuit board having a terminal mounting portion, one end of the metal terminal facing the metal circuit surface in parallel, the one end of the metal terminal and the metal circuit are joined by a solder layer, and the metal terminal At least one protrusion is formed on one end of the metal circuit or on the surface of the metal circuit facing the one end.

金属端子と回路基板間のはんだ厚を一定に保つことによって、金属端子と回路基板のはんだ接合部における応力を緩和した半導体装置が得られる。   By keeping the solder thickness between the metal terminal and the circuit board constant, a semiconductor device can be obtained in which the stress at the solder joint between the metal terminal and the circuit board is relaxed.

以下、実施例を参照して発明の実施の形態を説明する。   Hereinafter, embodiments of the invention will be described with reference to examples.

まず、図１乃至図４を参照して実施例１を説明する。
図１は、半導体装置の断面図、図２は、図１の半導体装置に用いられる回路基板と金属端子との接合構造を示す断面図、図３は、図１の半導体装置に用いられる金属端子の部分斜視図、図４は、半導体装置の組み立て工程を説明する斜視図である。図１に示すように、回路基板３は、セラミックス材料を用いた絶縁基板であり、主面にアルミニウム箔などの金属回路３ａ、３ｂ、３ｃが形成され、裏面にアルミニウム箔などの金属回路３ｄが形成されている。この裏面の金属回路３ｄは、銅板などからなる放熱基板８にはんだ１０ａにより接合されている。主面の金属回路３ａには、シリコン半導体などのチップ１が、搭載される。即ち、チップ１裏面は、金属回路３ａにはんだ１０により接合される。金属端子７ａは、金属回路３ａにはんだ（図示しない）により接合されている。金属端子７ｂは、金属回路３ｂにはんだ１０ｂにより接合されている。金属端子７ｃは、金属回路３ｃにはんだ１０ｃにより接合されている。金属端子７（７ａ、７ｂ、７ｃ）は、チップ１に対してほぼ垂直に配置されているが、一端部は、金属回路３ａ、３ｂ、３ｃとの接合面と平行に対向するように先端が折り曲げられており、他端部は、共通の樹脂封止板６に固定されている。 First, Embodiment 1 will be described with reference to FIGS.
1 is a cross-sectional view of the semiconductor device, FIG. 2 is a cross-sectional view showing a junction structure between a circuit board and a metal terminal used in the semiconductor device of FIG. 1, and FIG. 3 is a metal terminal used in the semiconductor device of FIG. FIG. 4 is a perspective view for explaining the assembly process of the semiconductor device. As shown in FIG. 1, the circuit board 3 is an insulating substrate using a ceramic material. Metal circuits 3a, 3b, 3c such as aluminum foil are formed on the main surface, and a metal circuit 3d such as aluminum foil is formed on the back surface. Is formed. The metal circuit 3d on the back surface is joined to a heat dissipation board 8 made of a copper plate or the like by solder 10a. A chip 1 such as a silicon semiconductor is mounted on the metal circuit 3a on the main surface. That is, the back surface of the chip 1 is joined to the metal circuit 3a by the solder 10. The metal terminal 7a is joined to the metal circuit 3a by solder (not shown). The metal terminal 7b is joined to the metal circuit 3b by solder 10b. The metal terminal 7c is joined to the metal circuit 3c by solder 10c. The metal terminals 7 (7a, 7b, 7c) are arranged substantially perpendicular to the chip 1, but one end of the metal terminal 7 (7a, 7b, 7c) has a tip so as to face the joint surface with the metal circuits 3a, 3b, 3c. The other end is fixed to a common resin sealing plate 6.

他端部の先端は、樹脂封止板６を貫通し、外部の配線を接続するためのナットなどが取り付けられ，樹脂封止板６に取り付けられている。
チップ１の電極と金属端子７とはアルミニウムなどのボンディングワイヤ２により電気的に接続されている。例えば、チップ１に形成された半導体素子がＩＧＢＴの場合、ゲート電極（図示しない）と金属回路３ｂとがボンディングワイヤ２により接続され、エミッタ電極（図示しない）と金属回路３ｃとが他のボンディングワイヤ２により接続されている。コレクタ電極はチップ１裏面に設けられている。ＩＧＢＴ以外に、バイポーラパワートランジスタやパワーＭＯＳＦＥＴを用いることができる。このような電力用半導体装置は、３０〜８０Ａの電流が流れる。チップ１が搭載された回路基板３は、放熱基板８に取り付けられたＰＢＴなどの合成樹脂からなるケース４に収納されている。ケース４内部には封止体５が充填されている。ケース４の下部にはシリコーンゲルからなる封止体５ａが充填され、その上にエポキシ樹脂からなる封止体５ｂが充填されている。ケース４に収納された回路基板３は、チップ１及び金属端子７の一部とともに封止体５ａに封止され、樹脂封止板６は、一部が封止体５ｂに封止され、上部と金属端子７の他端部先端とが封止体５ｂから露出している。 The tip of the other end portion penetrates through the resin sealing plate 6 and is attached to the resin sealing plate 6 with a nut or the like for connecting an external wiring.
The electrode of the chip 1 and the metal terminal 7 are electrically connected by a bonding wire 2 such as aluminum. For example, when the semiconductor element formed on the chip 1 is an IGBT, the gate electrode (not shown) and the metal circuit 3b are connected by the bonding wire 2, and the emitter electrode (not shown) and the metal circuit 3c are connected to another bonding wire. 2 are connected. The collector electrode is provided on the back surface of the chip 1. In addition to the IGBT, a bipolar power transistor or a power MOSFET can be used. In such a power semiconductor device, a current of 30 to 80 A flows. The circuit board 3 on which the chip 1 is mounted is housed in a case 4 made of a synthetic resin such as PBT attached to the heat dissipation board 8. The case 4 is filled with a sealing body 5. A lower portion of the case 4 is filled with a sealing body 5a made of silicone gel, and a sealing body 5b made of an epoxy resin is filled thereon. The circuit board 3 housed in the case 4 is sealed with the sealing body 5a together with the chip 1 and a part of the metal terminal 7, and the resin sealing plate 6 is partially sealed with the sealing body 5b. And the other end of the metal terminal 7 are exposed from the sealing body 5b.

次に、図２及び図３を参照して回路基板の金属回路と金属端子との接合構造の詳細を説明する。回路基板３の主面には金属回路３ａ、３ｂ、３ｃが設けられており、金属端子７ａは、チップ１が接合された金属回路３ａに接続され、金属端子７ｂは、金属回路３ｂに接続され、金属端子７ｃは、金属回路３ｃに接続されている（図４（ｄ）参照）。図２は、金属端子７ｂと回路基板３との接続構造を示しており、他の金属端子と回路基板との接続構造は、これと全く同じなので、説明を省略する。金属端子７ｂの一端部７ｄは、折曲され、この折曲部は金属回路３ｂ表面と平行に対向している。両者３ｂ、７ｄは、例えば、はんだ厚１００μｍのはんだ層１０ｂにより接合されている。図３は、金属端子７の部分斜視図である。金属端子７の一端部７ｄは、金属回路表面に対向する面に、例えば、この実施例では４つの突起９が形成されている。この突起９が金属端子と回路基板の金属回路間の間隔を維持し、はんだ厚を維持している。したがって、この実施例の突起９の高さは、１００μｍ程度にしてある。   Next, the details of the joint structure between the metal circuit of the circuit board and the metal terminal will be described with reference to FIGS. Metal circuits 3a, 3b, and 3c are provided on the main surface of the circuit board 3. The metal terminal 7a is connected to the metal circuit 3a to which the chip 1 is bonded, and the metal terminal 7b is connected to the metal circuit 3b. The metal terminal 7c is connected to the metal circuit 3c (see FIG. 4D). FIG. 2 shows a connection structure between the metal terminal 7b and the circuit board 3. Since the connection structure between the other metal terminals and the circuit board is exactly the same as this, the description thereof is omitted. One end portion 7d of the metal terminal 7b is bent, and this bent portion faces the surface of the metal circuit 3b in parallel. Both 3b and 7d are joined by a solder layer 10b having a solder thickness of 100 μm, for example. FIG. 3 is a partial perspective view of the metal terminal 7. For example, in this embodiment, four protrusions 9 are formed on the end 7d of the metal terminal 7 on the surface facing the surface of the metal circuit. The protrusions 9 maintain the distance between the metal terminals and the metal circuit of the circuit board, and maintain the solder thickness. Therefore, the height of the protrusion 9 in this embodiment is about 100 μm.

次に、図４を参照して半導体装置の組み立て工程を説明する。図４（ａ）は、放熱基板８にケース４が搭載された斜視図であり、図４（ｂ）は、樹脂封止板６に固定された金属端子７（７ａ、７ｂ、７ｃ）の斜視図である。金属端子７ａは、封止板６に隠れているので、図４（ｂ）には示さない。まず、主面に金属回路３ａ、３ｂ、３ｃを設け、金属回路３ａ上にはんだ付けしたチップ１を設けた配線基板３を放熱基板８に取付ける（図４（ｃ））。次に、封止板６に取付けた金属端子７（７ａ、７ｂ、７ｃ）を回路基板３の金属回路３ａ、３ｂ、３ｃにはんだ付けする（図４（ｄ））。その後、樹脂などのケース４を放熱基板８に取り付け、ケース４に回路基板３に収納するように構成する。その後、樹脂封止体５をケース４に充填し、回路基板３及びチップ１を封止する。   Next, the assembly process of the semiconductor device will be described with reference to FIG. 4A is a perspective view in which the case 4 is mounted on the heat dissipation board 8, and FIG. 4B is a perspective view of the metal terminals 7 (7a, 7b, 7c) fixed to the resin sealing plate 6. FIG. FIG. Since the metal terminal 7a is hidden behind the sealing plate 6, it is not shown in FIG. First, the metal circuit 3a, 3b, 3c is provided on the main surface, and the wiring board 3 provided with the chip 1 soldered on the metal circuit 3a is attached to the heat dissipation board 8 (FIG. 4C). Next, the metal terminals 7 (7a, 7b, 7c) attached to the sealing plate 6 are soldered to the metal circuits 3a, 3b, 3c of the circuit board 3 (FIG. 4 (d)). Thereafter, a case 4 made of resin or the like is attached to the heat radiating board 8, and the case 4 is configured to be stored in the circuit board 3. Thereafter, the resin sealing body 5 is filled in the case 4, and the circuit board 3 and the chip 1 are sealed.

従来の半導体装置におけるはんだ付け部は、はんだ厚１００μｍで設計しているが実際は製造上において、金属端子の先端が直角に折曲されていない、傾いて金属端子が組み立てられる等のバラツキ要因がある。この要因によって、はんだ厚のバラツキが、回路基板上に電力用金属端子を直接はんだ付けしているために、ＴＣＴによる各部品の熱膨張差により発生する応力が一番弱いはんだ部に掛かるので、ＴＣＴサイクル数増加によりはんだクラックに至る。
この実施例においては、従来の半導体装置ではＴＣＴ３００サイクル完了品分解調査においてはんだクラック３／１０ｐｃｓ発生したが、ＴＣＴ１０００サイクル完了品分解後０／１０ｐｃｓＮＧであり大幅に信頼性が向上した。 The soldering portion in the conventional semiconductor device is designed with a solder thickness of 100 μm, but in actuality, there are variations in manufacturing such that the tip of the metal terminal is not bent at a right angle or the metal terminal is assembled at an angle. . Due to this factor, the variation in solder thickness is because the power metal terminal is directly soldered on the circuit board, so the stress generated by the difference in thermal expansion of each component due to TCT is applied to the weakest solder part. An increase in the number of TCT cycles leads to solder cracks.
In this example, in the conventional semiconductor device, the solder crack 3/10 pcs occurred in the TCT 300 cycle completed product disassembly investigation, but after the TCT 1000 cycle completed product disassembly, it was 0/10 pcs NG, and the reliability was greatly improved.

次に、図５及び図６を参照して実施例２を説明する。
図５は、この実施例の半導体装置に用いられる回路基板と金属端子との接合構造を示す部分断面図、図６は、図５の半導体装置に用いられる回路基板の平面図である。この実施例における半導体装置は、図１に示す半導体装置の構造と同じであるが、金属端子と回路基板の金属回路との接続構造が実施例１とは異なる。即ち、この実施例の半導体装置は、チップと、チップの電極に電気的に接続された金属端子と、チップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板と、金属端子の一端は、金属回路表面と平行に対向し、両者の間のハンダ層により接合され、且つ金属端子の一端に対向する金属回路表面には少なくとも１つの突起が形成されている。 Next, Example 2 will be described with reference to FIGS.
FIG. 5 is a partial cross-sectional view showing a junction structure between a circuit board and a metal terminal used in the semiconductor device of this embodiment, and FIG. 6 is a plan view of the circuit board used in the semiconductor device of FIG. The semiconductor device in this embodiment is the same as the structure of the semiconductor device shown in FIG. 1, but the connection structure between the metal terminal and the metal circuit on the circuit board is different from that in the first embodiment. That is, the semiconductor device of this embodiment includes a chip, a metal terminal electrically connected to the electrode of the chip, a chip mounting portion for mounting the chip and the metal terminal, and a terminal on which a metal circuit is formed. The circuit board having the mounting portion and one end of the metal terminal face each other in parallel with the surface of the metal circuit, are joined by a solder layer therebetween, and at least one protrusion on the surface of the metal circuit facing the one end of the metal terminal Is formed.

回路基板２３の主面には金属回路２３ａ、２３ｂ、２３ｃが設けられており、金属端子２７ａは、チップが接合された金属回路２３ａに接続され、金属端子２７ｂは、金属回路２３ｂに接続され、金属端子２７ｃは、金属回路２３ｃに接続されている（図４（ｄ）参照）。図５は、金属端子２７ｂと回路基板２３との接続構造を示しており、他の金属端子と回路基板との接続構造は、これと全く同じである。金属端子２７ｂの一端部２７ｄは、折曲され、この折曲部は金属回路２３ｂ表面と平行に対向している。両者２３ｂ、２７ｄは、例えば、はんだ厚１００μｍのはんだ層２０により接合されている。図６は、回路基板２３の平面図である。金属回路２３ｂの金属端子２７ｂの一端部２７ｄに対向する面に、例えば、この実施例では４つの突起２９が形成されている。この突起２９が金属端子と回路基板の金属回路間の間隔を維持し、はんだ厚を維持している。したがって、この実施例の突起２９の高さは、１００μｍ程度にしてある。   Metal circuits 23a, 23b, and 23c are provided on the main surface of the circuit board 23, the metal terminal 27a is connected to the metal circuit 23a to which the chip is bonded, the metal terminal 27b is connected to the metal circuit 23b, The metal terminal 27c is connected to the metal circuit 23c (see FIG. 4D). FIG. 5 shows a connection structure between the metal terminal 27b and the circuit board 23, and the connection structure between the other metal terminals and the circuit board is exactly the same. One end 27d of the metal terminal 27b is bent, and this bent portion faces the surface of the metal circuit 23b in parallel. Both 23b and 27d are joined by, for example, a solder layer 20 having a solder thickness of 100 μm. FIG. 6 is a plan view of the circuit board 23. In this embodiment, for example, four protrusions 29 are formed on the surface of the metal circuit 23b facing the one end 27d of the metal terminal 27b. The protrusions 29 maintain the distance between the metal terminal and the metal circuit of the circuit board, and maintain the solder thickness. Therefore, the height of the protrusion 29 in this embodiment is about 100 μm.

以上、従来の半導体装置におけるはんだ付け部は、はんだ厚１００μｍで設計しているが実際は製造上において、金属端子の先端が直角に折曲されていない、傾いて金属端子が組み立てられる等のバラツキ要因がある。この要因によって、はんだ厚のバラツキが、回路基板上に電力用金属端子を直接はんだ付けしているために、ＴＣＴによる各部品の熱膨張差により発生する応力が一番弱いはんだ部に掛かるので、ＴＣＴサイクル数増加により、はんだクラックに至る。この実施例は、実施例１と同様な効果を有し、従来の半導体装置ではＴＣＴ３００サイクル完了品分解調査においてはんだクラック３／１０ｐｃｓ発生したが、ＴＣＴ１０００サイクル完了品分解後０／１０ｐｃｓＮＧであり大幅に信頼性が向上する。   As described above, the soldering part in the conventional semiconductor device is designed with a solder thickness of 100 μm, but in actuality, in manufacturing, the tip of the metal terminal is not bent at a right angle, or the metal terminal is assembled at an inclination There is. Due to this factor, the variation in solder thickness is because the power metal terminal is directly soldered on the circuit board, so the stress generated by the difference in thermal expansion of each component due to TCT is applied to the weakest solder part. An increase in the number of TCT cycles leads to solder cracks. This embodiment has the same effect as that of the first embodiment. In the conventional semiconductor device, the solder crack 3/10 pcs occurred in the TCT300 cycle completed product disassembly investigation, but after the TCT1000 cycle complete product disassembly, it was 0/10 pcsNG. Reliability is improved.

次に、図７及び図８を参照して実施例２を説明する。
図７は、この実施例の半導体装置の断面図、図８は、図７の半導体装置に用いられる回路基板裏面の平面図である。この実施例における半導体装置は、図１に示す半導体装置の構造と同じである。即ち、この実施例の半導体装置は、チップと、チップの電極に電気的に接続された金属端子と、チップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板と、金属端子の一端は、金属回路表面と平行に対向し、両者の間のハンダ層により接合され、且つ金属端子の一端には少なくとも１つの突起が形成されている。また、金属端子の一端の代わりに、この一端に対向する金属回路表面に少なくとも１つの突起が形成されているように構成することができる。この実施例における半導体装置は、図１に示す半導体装置の構造と基本的に同じであるが、回路基板の金属回路と放熱基板との接続構造が実施例１とは異なる。 Next, Embodiment 2 will be described with reference to FIGS.
FIG. 7 is a cross-sectional view of the semiconductor device of this embodiment, and FIG. 8 is a plan view of the back surface of the circuit board used in the semiconductor device of FIG. The semiconductor device in this embodiment has the same structure as the semiconductor device shown in FIG. That is, the semiconductor device of this embodiment includes a chip, a metal terminal electrically connected to the electrode of the chip, a chip mounting portion for mounting the chip and the metal terminal, and a terminal on which a metal circuit is formed. The circuit board having the mounting portion and one end of the metal terminal face each other in parallel to the surface of the metal circuit, are joined by a solder layer therebetween, and at least one protrusion is formed on one end of the metal terminal. Moreover, it can comprise so that at least 1 protrusion may be formed in the metal circuit surface facing this one end instead of the one end of a metal terminal. The semiconductor device in this embodiment is basically the same as the structure of the semiconductor device shown in FIG. 1, but the connection structure between the metal circuit of the circuit board and the heat dissipation board is different from that in the first embodiment.

ケース３４に収納され放熱基板３８上に形成された回路基板３３の主面には金属回路３３ａ、３３ｂ、３３ｃが設けられており、金属端子３７ａは、チップ３１が接合された金属回路３３ａに接続され、金属端子３７ｂは、金属回路３３ｂに接続され、金属端子３７ｃは、金属回路３３ｃに接続されている（図４（ｄ）参照）。金属回路３３ｂ、３３ｃとチップ３１とはそれぞれボンディングワイヤ３２により電気的に接続される。図７は、回路基板３３と放熱基板３８との接続構造を詳細に示している。金属端子３７ｂ、３７ｃの一端は、折曲され、この折曲部は金属回路３３ｂ、３３ｃ表面と平行に対向している。金属端子３３ｂ、３３ｃのそれぞれの一端は、例えば、はんだ厚１００μｍのはんだ３０ｂ、３０ｃにより接合されている。回路基板３３の裏面の金属回路３３ｄは、はんだ３０ａにより放熱基板３８に接合される。図８は、回路基板３３の金属回路３３ｄが形成された裏面が示された平面図である。回路基板３３の裏面に形成された金属回路３３ｄと放熱基板３８とは、例えば、はんだ厚１００μｍのはんだ３０ａにより接合されている。   Metal circuits 33a, 33b, and 33c are provided on the main surface of the circuit board 33 housed in the case 34 and formed on the heat dissipation board 38, and the metal terminals 37a are connected to the metal circuit 33a to which the chip 31 is bonded. The metal terminal 37b is connected to the metal circuit 33b, and the metal terminal 37c is connected to the metal circuit 33c (see FIG. 4D). The metal circuits 33b and 33c and the chip 31 are electrically connected by bonding wires 32, respectively. FIG. 7 shows the connection structure between the circuit board 33 and the heat dissipation board 38 in detail. One ends of the metal terminals 37b and 37c are bent, and the bent portions face the surfaces of the metal circuits 33b and 33c in parallel. One end of each of the metal terminals 33b and 33c is joined by, for example, solders 30b and 30c having a solder thickness of 100 μm. The metal circuit 33d on the back surface of the circuit board 33 is joined to the heat dissipation board 38 by the solder 30a. FIG. 8 is a plan view showing the back surface of the circuit board 33 on which the metal circuit 33d is formed. The metal circuit 33d formed on the back surface of the circuit board 33 and the heat dissipation board 38 are joined by, for example, solder 30a having a solder thickness of 100 μm.

図８に示すように、回路基板３３の裏面に設けられた金属回路３３ｄには、例えば、５つの突起３９が形成されている。この突起３９が回路基板３３の金属回路３３ｄと放熱基板３８との間の間隔を維持し、はんだ厚を維持している。したがって、この実施例の突起３９の高さは、１００μｍ程度にしてある。勿論、実施例１と同様に、回路基板３３上の金属回路３３ｂ、３３ｃと金属端子３７ｂ、３７ｃ一端との間にも前記一端側に突起３５、３６が設けられて、その間の間隔を一定に維持している。   As shown in FIG. 8, for example, five protrusions 39 are formed on the metal circuit 33 d provided on the back surface of the circuit board 33. The protrusions 39 maintain the distance between the metal circuit 33d of the circuit board 33 and the heat dissipation board 38, and maintain the solder thickness. Therefore, the height of the protrusion 39 in this embodiment is about 100 μm. Of course, as in the first embodiment, the projections 35 and 36 are provided on the one end side between the metal circuits 33b and 33c on the circuit board 33 and one end of the metal terminals 37b and 37c, and the interval between them is constant. Is maintained.

以上、従来の半導体装置におけるはんだ付け部は、はんだ厚１００μｍで設計しているが実際は製造上において、金属端子の先端が直角に折曲されていない、傾いて金属端子が組み立てられる等のバラツキ要因がある。この要因によって、はんだ厚のバラツキが、回路基板上に電力用金属端子を直接はんだ付けしているために、ＴＣＴによる各部品の熱膨張差により発生する応力が一番弱いはんだ部に掛かるので、ＴＣＴサイクル数増加により、はんだクラックに至る。この実施例は、実施例１と同様な効果を有し、従来の半導体装置ではＴＣＴ３００サイクル完了品分解調査においてはんだクラック３／１０ｐｃｓ発生したが、ＴＣＴ１０００サイクル完了品分解後０／１０ｐｃｓＮＧであり大幅に信頼性が向上する。この実施例では、回路基板と放熱基板間においてもはんだ層を一定に維持しているので、実施例１、２に比較してさらに向上する。   As described above, the soldering part in the conventional semiconductor device is designed with a solder thickness of 100 μm, but in actuality, in manufacturing, the tip of the metal terminal is not bent at a right angle, or the metal terminal is assembled at an inclination There is. Due to this factor, the variation in solder thickness is because the power metal terminal is directly soldered on the circuit board, so the stress generated by the difference in thermal expansion of each component due to TCT is applied to the weakest solder part. An increase in the number of TCT cycles leads to solder cracks. This embodiment has the same effect as that of the first embodiment. In the conventional semiconductor device, the solder crack 3/10 pcs occurred in the TCT300 cycle completed product disassembly investigation, but after the TCT1000 cycle complete product disassembly, it was 0/10 pcsNG. Reliability is improved. In this embodiment, since the solder layer is kept constant between the circuit board and the heat dissipation board, it is further improved as compared with the first and second embodiments.

次に、図９及び図１０を参照して実施例２を説明する。
図９は、この実施例の半導体装置の断面図、図１０は、図９の半導体装置に用いられる放熱基板主面の平面図である。この実施例における半導体装置は、図１に示す半導体装置の構造と同じである。即ち、この実施例の半導体装置は、チップと、チップの電極に電気的に接続された金属端子と、チップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板と、金属端子の一端は、金属回路表面と平行に対向し、両者の間のハンダ層により接合され、且つ金属端子の一端には少なくとも１つの突起が形成されている。また、金属端子の一端の代わりに、この一端に対向する金属回路表面に少なくとも１つの突起が形成されているように構成することができる。この実施例における半導体装置は、図１に示す半導体装置の構造と基本的に同じであるが、回路基板の金属回路と放熱基板との接続構造が実施例１とは異なる。 Next, Embodiment 2 will be described with reference to FIGS.
FIG. 9 is a cross-sectional view of the semiconductor device of this embodiment, and FIG. 10 is a plan view of the main surface of the heat dissipation board used in the semiconductor device of FIG. The semiconductor device in this embodiment has the same structure as the semiconductor device shown in FIG. That is, the semiconductor device of this embodiment includes a chip, a metal terminal electrically connected to the electrode of the chip, a chip mounting portion for mounting the chip and the metal terminal, and a terminal on which a metal circuit is formed. The circuit board having the mounting portion and one end of the metal terminal face each other in parallel to the surface of the metal circuit, are joined by a solder layer therebetween, and at least one protrusion is formed on one end of the metal terminal. Moreover, it can comprise so that at least 1 protrusion may be formed in the metal circuit surface facing this one end instead of the one end of a metal terminal. The semiconductor device in this embodiment is basically the same as the structure of the semiconductor device shown in FIG. 1, but the connection structure between the metal circuit of the circuit board and the heat dissipation board is different from that in the first embodiment.

ケース４４に収納され放熱基板４８上に形成された回路基板４３の主面には金属回路４３ａ、４３ｂ、４３ｃが設けられており、金属端子４７ａは、チップ４１が接合された金属回路４３ａに接続され、金属端子４７ｂは、金属回路４３ｂに接続され、金属端子４７ｃは、金属回路４３ｃに接続されている（図４（ｄ）参照）。金属回路４３ｂ、４３ｃとチップ４１とはそれぞれボンディングワイヤ４２により電気的に接続される。図９は、回路基板４３と放熱基板４８との接続構造を詳細に示している。金属端子４７ｂ、４７ｃの一端は、折曲され、この折曲部は金属回路４３ｂ、４３ｃ表面と平行に対向している。金属端子４３ｂ、４３ｃのそれぞれの一端は、例えば、はんだ厚１００μｍのはんだ４０ｂ、４０ｃにより接合されている。回路基板４３の裏面の金属回路４３ｄは、はんだ４０ａにより放熱基板４８に接合される。図１０は、放熱基板４８主面が示された平面図である。回路基板４３の裏面に形成された金属回路４３ｄと放熱基板４８とは、例えば、はんだ厚１００μｍのはんだ４０ａにより接合されている。   Metal circuits 43a, 43b, 43c are provided on the main surface of the circuit board 43 housed in the case 44 and formed on the heat dissipation board 48, and the metal terminals 47a are connected to the metal circuit 43a to which the chip 41 is bonded. The metal terminal 47b is connected to the metal circuit 43b, and the metal terminal 47c is connected to the metal circuit 43c (see FIG. 4D). The metal circuits 43b and 43c and the chip 41 are electrically connected by bonding wires 42, respectively. FIG. 9 shows the connection structure between the circuit board 43 and the heat dissipation board 48 in detail. One ends of the metal terminals 47b and 47c are bent, and the bent portions face the metal circuits 43b and 43c in parallel. One end of each of the metal terminals 43b and 43c is joined by, for example, solder 40b and 40c having a solder thickness of 100 μm. The metal circuit 43d on the back surface of the circuit board 43 is joined to the heat dissipation board 48 by solder 40a. FIG. 10 is a plan view showing the main surface of the heat dissipation board 48. The metal circuit 43d formed on the back surface of the circuit board 43 and the heat dissipation board 48 are joined by, for example, solder 40a having a solder thickness of 100 μm.

図１０に示すように、回路基板４３の裏面に設けられた金属回路４３ｄに対向する放熱基板４８には、例えば、５つの突起４９が形成されている。この突起４９が回路基板４３の金属回路４３ｄと放熱基板４８との間の間隔を維持し、はんだ厚を維持している。したがって、この実施例の突起４９の高さは、１００μｍ程度にしてある。勿論、実施例１と同様に、回路基板４３上の金属回路４３ｂ、４３ｃと金属端子４７ｂ、４７ｃ一端との間にも前記一端側に突起４５、４６が設けられて、その間の間隔を一定に維持している。   As shown in FIG. 10, for example, five protrusions 49 are formed on the heat dissipation board 48 facing the metal circuit 43 d provided on the back surface of the circuit board 43. The protrusions 49 maintain the distance between the metal circuit 43d of the circuit board 43 and the heat dissipation board 48, and maintain the solder thickness. Therefore, the height of the protrusion 49 in this embodiment is about 100 μm. Of course, as in the first embodiment, the projections 45 and 46 are provided on the one end side between the metal circuits 43b and 43c on the circuit board 43 and one end of the metal terminals 47b and 47c, and the interval between them is constant. Is maintained.

以上、従来の半導体装置におけるはんだ付け部は、はんだ厚１００μｍで設計しているが実際は製造上において、金属端子の先端が直角に折曲されていない、傾いて金属端子が組み立てられる等のバラツキ要因がある。この要因によって、はんだ厚のバラツキが、回路基板上に電力用金属端子を直接はんだ付けしているために、ＴＣＴによる各部品の熱膨張差により発生する応力が一番弱いはんだ部に掛かるので、ＴＣＴサイクル数増加により、はんだクラックに至る。この実施例は、実施例１と同様な効果を有し、従来の半導体装置ではＴＣＴ３００サイクル完了品分解調査においてはんだクラック３／１０ｐｃｓ発生したが、ＴＣＴ１０００サイクル完了品分解後０／１０ｐｃｓＮＧであり大幅に信頼性が向上するこの実施例では、回路基板と放熱基板間においてもはんだ層を一定に維持しているので、実施例１、２に比較して更に向上する。   As described above, the soldering part in the conventional semiconductor device is designed with a solder thickness of 100 μm, but in actuality, in manufacturing, the tip of the metal terminal is not bent at a right angle, or the metal terminal is assembled at an inclination There is. Due to this factor, the variation in solder thickness is because the power metal terminal is directly soldered on the circuit board, so the stress generated by the difference in thermal expansion of each component due to TCT is applied to the weakest solder part. An increase in the number of TCT cycles leads to solder cracks. This embodiment has the same effect as that of the first embodiment. In the conventional semiconductor device, the solder crack 3/10 pcs occurred in the TCT300 cycle completed product disassembly investigation, but after the TCT1000 cycle complete product disassembly, it was 0/10 pcsNG. In this embodiment in which the reliability is improved, since the solder layer is kept constant between the circuit board and the heat dissipation board, the reliability is further improved as compared with the first and second embodiments.

本発明の一実施例である実施例１の半導体装置の断面図。Sectional drawing of the semiconductor device of Example 1 which is one Example of this invention. 図１の半導体装置に用いられる回路基板と金属端子との接合構造を示す断面図。Sectional drawing which shows the junction structure of the circuit board and metal terminal which are used for the semiconductor device of FIG. 図１の半導体装置に用いられる金属端子の部分斜視図。FIG. 2 is a partial perspective view of a metal terminal used in the semiconductor device of FIG. 1. 図１の半導体装置の組み立て工程を説明する斜視図。FIG. 3 is a perspective view illustrating an assembly process of the semiconductor device of FIG. 1. 本発明の一実施例である実施例２半導体装置に用いられる回路基板と金属端子との接合構造を示す部分断面図。FIG. 7 is a partial cross-sectional view showing a junction structure between a circuit board and a metal terminal used in a semiconductor device according to a second embodiment which is an embodiment of the present invention. 図５の半導体装置に用いられる回路基板の平面図。The top view of the circuit board used for the semiconductor device of FIG. 本発明の一実施例である実施例３の半導体装置の断面図。Sectional drawing of the semiconductor device of Example 3 which is one Example of this invention. 図７の半導体装置に用いられる回路基板裏面の平面図。The top view of the circuit board back surface used for the semiconductor device of FIG. 本発明の一実施例である実施例４の半導体装置の断面図。Sectional drawing of the semiconductor device of Example 4 which is one Example of this invention. 図９の半導体装置に用いられる放熱基板主面の平面図。The top view of the heat sink main surface used for the semiconductor device of FIG.

符号の説明Explanation of symbols

１、３１、４１・・・チップ
２、３２、４２・・・ボンディングワイヤ
３、２３、３３、４３・・・回路基板
４、３４、４４・・・ケース
５、５ａ、５ｂ・・・樹脂封止体
６、３６、４６・・・樹脂封止板
７、７ａ、７ｂ、７ｃ、２７、２７ａ、２７ｂ、２７ｃ、３７ａ、３７ｂ、３７ｃ、４７ａ、４７ｂ、４７ｃ・・・金属端子
７ｄ、２７ｄ・・・金属端子の一端部
８、３８、４８・・・放熱基板
９、２９、３５、３６、３９、４５、４６、４９・・・突起
１０、１０ａ、１０ｂ、１０ｃ、２０、３０、３０ａ、３０ｂ、３０ｃ、４０、４０ａ、４０ｂ、４０ｃ・・・はんだ

DESCRIPTION OF SYMBOLS 1, 31, 41 ... Chip 2, 32, 42 ... Bonding wire 3, 23, 33, 43 ... Circuit board 4, 34, 44 ... Case 5, 5a, 5b ... Resin sealing Stopping body 6, 36, 46 ... Resin sealing plate 7, 7a, 7b, 7c, 27, 27a, 27b, 27c, 37a, 37b, 37c, 47a, 47b, 47c ... Metal terminal 7d, 27d ..One end portion of metal terminal 8, 38, 48 ... heat dissipation substrate 9, 29, 35, 36, 39, 45, 46, 49 ... projection 10, 10a, 10b, 10c, 20, 30, 30a, 30b, 30c, 40, 40a, 40b, 40c ... solder

Claims (5)

半導体チップと、
前記半導体チップの電極に電気的に接続された金属端子と、
前記半導体チップを搭載するチップ搭載部及び前記金属端子を搭載し、且つ金属回路が形成された端子搭載部を有する回路基板と、
前記金属端子の一端は、前記金属回路表面と平行に対向し、前記金属端子の一端と前記金属回路との間ははんだ層により接合され、且つ前記金属端子の一端もしくは前記一端に対向する金属回路表面には少なくとも１つの突起が形成されていることを特徴とする半導体装置。 A semiconductor chip;
A metal terminal electrically connected to the electrode of the semiconductor chip;
A circuit board having a chip mounting portion for mounting the semiconductor chip and a terminal mounting portion on which the metal terminal is mounted and a metal circuit is formed;
One end of the metal terminal faces the metal circuit surface in parallel, the one end of the metal terminal and the metal circuit are joined by a solder layer, and the one end of the metal terminal or the metal circuit facing the one end A semiconductor device, wherein at least one protrusion is formed on a surface. 前記突起は、前記金属端子一端と前記一端に対向する金属回路表面との間隔を一定に保持することを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the protrusion maintains a constant distance between one end of the metal terminal and a metal circuit surface facing the one end. 前記回路基板は、セラミックスからなることを特徴とする請求項１又は請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the circuit board is made of ceramics. 前記半導体チップ及び前記金属端子が搭載された前記回路基板は、ケースに収納され、前記半導体チップ及び前記金属端子が搭載された前記回路基板は、前記ケース内において、樹脂封止されていることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。 The circuit board on which the semiconductor chip and the metal terminal are mounted is housed in a case, and the circuit board on which the semiconductor chip and the metal terminal are mounted is resin-sealed in the case. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 前記回路基板は、放熱基板上に搭載され、前記回路基板裏面に形成された金属回路を介して前記放熱基板にはんだ付けされていることを特徴とする請求項１乃至請求項４のいずれかに記載の半導体装置。
5. The circuit board according to claim 1, wherein the circuit board is mounted on the heat dissipation board and soldered to the heat dissipation board via a metal circuit formed on the back surface of the circuit board. The semiconductor device described.
JP2005283616A 2005-09-29 2005-09-29 Semiconductor device Pending JP2007096004A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100794408B1 (en) * 2000-07-19 2008-01-16 스냅-온 이쿠엡먼트 게엠베하 Method and apparatus for optically scanning a vehicle wheel
KR100822014B1 (en) * 2006-06-12 2008-04-15 주식회사 비츠로셀 Battery with supporter
KR100832932B1 (en) * 2006-03-20 2008-05-27 후지쯔 가부시끼가이샤 Read out information registration apparatus
JP2017188528A (en) * 2016-04-04 2017-10-12 三菱電機株式会社 Semiconductor device
JP2020141010A (en) * 2019-02-27 2020-09-03 株式会社豊田自動織機 Semiconductor device
US11973015B2 (en) 2020-06-25 2024-04-30 Fuji Electric Co., Ltd. Plurality of overlapping power terminals in a semiconductor module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100794408B1 (en) * 2000-07-19 2008-01-16 스냅-온 이쿠엡먼트 게엠베하 Method and apparatus for optically scanning a vehicle wheel
KR100832932B1 (en) * 2006-03-20 2008-05-27 후지쯔 가부시끼가이샤 Read out information registration apparatus
KR100822014B1 (en) * 2006-06-12 2008-04-15 주식회사 비츠로셀 Battery with supporter
JP2017188528A (en) * 2016-04-04 2017-10-12 三菱電機株式会社 Semiconductor device
JP2020141010A (en) * 2019-02-27 2020-09-03 株式会社豊田自動織機 Semiconductor device
US11973015B2 (en) 2020-06-25 2024-04-30 Fuji Electric Co., Ltd. Plurality of overlapping power terminals in a semiconductor module

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