JP2007095954A - Circuit board, electronic equipment using it, and manufacturing method thereof - Google Patents

Circuit board, electronic equipment using it, and manufacturing method thereof Download PDF

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JP2007095954A
JP2007095954A JP2005282622A JP2005282622A JP2007095954A JP 2007095954 A JP2007095954 A JP 2007095954A JP 2005282622 A JP2005282622 A JP 2005282622A JP 2005282622 A JP2005282622 A JP 2005282622A JP 2007095954 A JP2007095954 A JP 2007095954A
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brazing material
circuit board
electronic element
electronic
insulating substrate
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Reiji Matsushita
玲治 松下
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board capable of surely and stably mounting an electronic element without confirming the melted state of a solder interposed between the electronic element and the circuit board, when mounting electronic elements on the circuit board. <P>SOLUTION: An insulating board 1 comprises a mounting part 2 for electronic elements on its surface with a joint pad 4 of first solder formed on the mounting part 2, and a labelled part 6 where a second solder 5 is coated on the surface except for the mounting part 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は電子素子を搭載するための回路基板および電子装置並びにその製造方法に関するものである。   The present invention relates to a circuit board for mounting an electronic element, an electronic device, and a manufacturing method thereof.

近年、CD(Compact Disk)、DVD(Digital Video Disk)等に用いられる電子装置の電子素子は高出力化が要求されており、このような電子素子が搭載される従来の回路基板について説明する。   In recent years, electronic devices of electronic devices used for CDs (Compact Disks), DVDs (Digital Video Disks) and the like have been required to have high output, and a conventional circuit board on which such electronic devices are mounted will be described.

従来の回路基板の斜視図を図3に示す。図3において、104は回路基板、21は絶縁基板、22は電子部品の搭載部、23は配線導体層、24は接合パッドを示しており、絶縁基板21は、表面に電子素子の搭載部22と、配線導体層23とを有しており、このような搭載部22にろう材からなる接合パッド24が形成され、接合パッド24を介して電子素子が搭載される。そして、電子素子と配線導体層23とがボンディングワイヤ等を介して電気的に接続されることによって、電子素子が搭載された回路基板104となる。   A perspective view of a conventional circuit board is shown in FIG. 3, 104 is a circuit board, 21 is an insulating substrate, 22 is an electronic component mounting portion, 23 is a wiring conductor layer, and 24 is a bonding pad. The insulating substrate 21 has an electronic element mounting portion 22 on the surface. And a wiring conductor layer 23, a bonding pad 24 made of a brazing material is formed on the mounting portion 22, and an electronic element is mounted via the bonding pad 24. The electronic element and the wiring conductor layer 23 are electrically connected via a bonding wire or the like, whereby the circuit board 104 on which the electronic element is mounted is obtained.

また、このような電子素子が搭載された回路基板104を基体に搭載し、必要に応じて電子素子を取り囲むように枠体や蓋体等が基体に取着されることにより、電子装置が得られる。   In addition, an electronic device can be obtained by mounting the circuit board 104 on which such electronic elements are mounted on a base, and attaching a frame, a lid, or the like to the base so as to surround the electronic elements as necessary. It is done.

このような電子装置は、たとえば半導体素子が光半導体素子である場合、外部電気回路から外部リード端子を介して供給される駆動信号が光半導体素子を励起し、その後光半導体素子から放出された光を光ファイバ等を介して外部に伝達することによって高速光通信等に使用される。近年、このような光半導体装置に対して、2.5Gbps以上での良好な高周波特性,小型化,低背化および低コスト化等が益々要求されてきている。
特開1999−168147号公報
In such an electronic device, for example, when the semiconductor element is an optical semiconductor element, the drive signal supplied from the external electric circuit via the external lead terminal excites the optical semiconductor element, and then the light emitted from the optical semiconductor element Is transmitted to the outside through an optical fiber or the like to be used for high-speed optical communication or the like. In recent years, such optical semiconductor devices have been increasingly required to have good high frequency characteristics at 2.5 Gbps or more, downsizing, low profile, low cost, and the like.
JP 1999-168147 A

しかしながら、従来の回路基板104の搭載部22に電子素子を搭載する場合、次のような問題点を有していた。   However, when an electronic element is mounted on the mounting portion 22 of the conventional circuit board 104, the following problems have been encountered.

すなわち回路基板104に電子素子が搭載される場合、上述のように搭載部22に接合パッド24を介して搭載されるのだが、その際、搭載部22上の接合パッド24を形成するろう材の溶融状態は電子素子により隠れてしまい確認し難い。このため、電子素子を適切な条件で安定して接合出来ないという問題点を有していた。   That is, when an electronic element is mounted on the circuit board 104, it is mounted on the mounting portion 22 via the bonding pad 24 as described above. At this time, the brazing material for forming the bonding pad 24 on the mounting portion 22 is used. The molten state is hidden by the electronic element and is difficult to confirm. For this reason, there has been a problem that electronic devices cannot be stably bonded under appropriate conditions.

本発明は、かかる従来技術の問題点に鑑みて完成されたものであり、その目的は、電子素子を安定して確実に搭載できる回路基板を提供することにある。   The present invention has been completed in view of the problems of the prior art, and an object of the present invention is to provide a circuit board on which electronic elements can be stably and reliably mounted.

本発明の回路基板は、表面に電子素子の搭載部を有するとともに、該搭載部に第1のろう材からなる接合パッドが形成され、前記搭載部を除く前記表面に第2のろう材が被着された標識部を有する絶縁基板を具備することを特徴とする。   The circuit board of the present invention has a mounting portion for an electronic element on the surface, a bonding pad made of a first brazing material is formed on the mounting portion, and a second brazing material is covered on the surface excluding the mounting portion. An insulating substrate having a sign portion attached thereto is provided.

本発明の回路基板において好ましくは、前記第2のろう材は、前記第1のろう材と同一組成のろう材から成ることを特徴とする。   In the circuit board according to the present invention, preferably, the second brazing material is made of a brazing material having the same composition as the first brazing material.

本発明の回路基板において好ましくは、前記第2のろう材は平面視で外周部に角部を有することを特徴とする。   In the circuit board of the present invention, preferably, the second brazing material has a corner portion on an outer peripheral portion in a plan view.

本発明の回路基板において好ましくは、前記標識部の前記第2のろう材が被着された部位の表面の算術平均粗さRaをR1、前記搭載部の表面の算術平均粗さRaをR2としたとき、R1≦R2の関係を有することを特徴とする。   In the circuit board according to the present invention, preferably, the arithmetic average roughness Ra of the surface of the mark portion where the second brazing material is attached is R1, and the arithmetic average roughness Ra of the surface of the mounting portion is R2. Then, it has a relationship of R1 ≦ R2.

本発明の回路基板において好ましくは、前記第2のろう材と前記接合パッドとが平面視で同じ形状であることを特徴とする。   In the circuit board of the present invention, preferably, the second brazing material and the bonding pad have the same shape in plan view.

本発明の電子装置は、上記本発明の回路基板と、該回路基板に搭載された電子部品とを具備していることを特徴とする。   An electronic device of the present invention includes the circuit board of the present invention and an electronic component mounted on the circuit board.

本発明の電子装置の製造方法は、前記第2のろう材の状態を観察して、前記電子素子を前記絶縁基板に搭載する工程を具備することを特徴とする。   The electronic device manufacturing method of the present invention includes a step of observing the state of the second brazing material and mounting the electronic element on the insulating substrate.

本発明の電子装置は、表面に接合材を介して電子素子が接合され、前記電子素子が搭載される部位を除く前記絶縁基板に前記接合材の溶融状態推定用のパターンが設けられた絶縁基板を有することを特徴とする。   The electronic device according to the present invention is an insulating substrate in which an electronic element is bonded to a surface via a bonding material, and a pattern for estimating a molten state of the bonding material is provided on the insulating substrate excluding a portion where the electronic element is mounted It is characterized by having.

本発明の回路基板は、表面に電子素子の搭載部を有するとともに、搭載部に第1のろう材からなる接合パッドが形成され、搭載部を除く表面に第2のろう材が被着された標識部を有する絶縁基板を具備していることによって、電子素子を回路基板に搭載する際に、たとえ、接合パッドを形成する第1のろう材の溶融状態が確認できなくても、標識部に被着された第2のろう材の溶融状態を確認することで、第1のろう材の溶融状態が推定可能となり、電子素子を適切な条件で搭載部に搭載することができる。よって、第1のろう材が十分に溶融していない、あるいは第1のろう材が溶融して搭載部領域外へ流れている等の第1のろう材の溶融状態に起因する電子素子と回路基板との接続不良を抑制し、安定して高信頼に電子素子を搭載することが可能な回路基板を提供することができる。   The circuit board of the present invention has an electronic element mounting portion on the surface, a bonding pad made of a first brazing material is formed on the mounting portion, and a second brazing material is deposited on the surface excluding the mounting portion. By providing the insulating substrate having the marking portion, when the electronic element is mounted on the circuit board, even if the melting state of the first brazing material forming the bonding pad cannot be confirmed, By confirming the molten state of the deposited second brazing material, the molten state of the first brazing material can be estimated, and the electronic element can be mounted on the mounting portion under appropriate conditions. Therefore, the electronic device and the circuit resulting from the molten state of the first brazing material, such as the first brazing material is not sufficiently melted or the first brazing material is melted and flows out of the mounting portion region. It is possible to provide a circuit board capable of suppressing poor connection with the board and stably mounting the electronic element with high reliability.

本発明の回路基板は、第2のろう材が第1のろう材と同一組成のろう材から成ることによって、電子素子を回路基板に搭載する際に第1のろう材と同一組成の第2のろう材の溶融状態を確認することで、電子素子をさらに適切な条件で接合することができる。つまり、標識部に被着された第2のろう材と接合パッドを形成する第1のろう材とは同一組成からなるため、電子素子の搭載時に熱等が加わったとしてもほぼ同一の溶融状態をなしている。よって、標識部に被着された第2のろう材の溶融状態を確認することにより、電子素子を回路基板上に所望の状態で搭載することがさらに容易となる。   In the circuit board according to the present invention, the second brazing material is made of the brazing material having the same composition as the first brazing material, so that when the electronic element is mounted on the circuit board, the second brazing material has the same composition as the first brazing material. By confirming the molten state of the brazing filler metal, the electronic element can be bonded under more appropriate conditions. In other words, since the second brazing material applied to the marking portion and the first brazing material forming the bonding pad have the same composition, even if heat is applied when the electronic element is mounted, almost the same molten state I am doing. Therefore, it becomes easier to mount the electronic element on the circuit board in a desired state by confirming the molten state of the second brazing material attached to the marking portion.

本発明の回路基板は、第2のろう材が平面視で外周部に角部を有することによって、溶融開始時の第2のろう材の動きがより視認しやすくなり、電子素子をより最適な条件で接合することが可能となる。つまり、標識部に被着された第2のろう材が溶融した際、角部を形成する位置の第2のろう材は、例えば丸みを帯びるなど形状に変化が生じて溶融するため、標識部に被着された第2のろう材の溶融開始状態をより確認しやすくなる。よって、このような第2のろう材の、特に角部の位置の溶融状態を確認することで、第1のろう材からなる接合パッドの溶融開始状態がよりわかり易くなる。   In the circuit board of the present invention, since the second brazing material has corners on the outer peripheral portion in plan view, the movement of the second brazing material at the start of melting becomes easier to visually recognize, and the electronic element is more optimal. It becomes possible to join on condition. That is, when the second brazing material applied to the marking portion is melted, the second brazing material at the position where the corner portion is formed melts due to a change in shape such as rounded shape. It becomes easier to confirm the melting start state of the second brazing material deposited on the metal. Therefore, by confirming the melting state of the second brazing material, particularly at the corners, it becomes easier to understand the melting start state of the bonding pad made of the first brazing material.

本発明の回路基板は、標識部の第2のろう材が被着された部位の表面の算術平均粗さRaをR1、搭載部の表面の算術平均粗さRaをR2としたとき、R1≦R2の関係を有することにより、電子素子をより最適な条件で回路基板に接合しやすくなる。これは、一般的に、より滑らかな面の上に形成されたもののほうが流動性を有するためであり、本発明において、電子素子の搭載部よりもより滑らかな面の上に形成された標識部に被着された第2のろう材は、溶融開始時に電子素子の搭載部に形成された接合パッドをなす第1のろう材よりも大きく形状をかえて溶融するため視認し易くなる。   In the circuit board of the present invention, when the arithmetic average roughness Ra of the surface of the portion where the second brazing material of the marking portion is attached is R1, and the arithmetic average roughness Ra of the surface of the mounting portion is R2, R1 ≦ By having the relationship of R2, it becomes easy to bond the electronic element to the circuit board under more optimal conditions. This is because, in general, those formed on a smoother surface have more fluidity, and in the present invention, a marker portion formed on a smoother surface than the mounting portion of the electronic element. Since the second brazing material applied to is melted in a larger shape than the first brazing material forming the bonding pad formed on the mounting portion of the electronic element at the start of melting, the second brazing material becomes easy to visually recognize.

本発明の回路基板は、第2のろう材と接合パッドとが平面視で同じ形状とすることによって、第1のろう材と第2のろう材との溶融状態をより近い状態とすることができ、電子素子をさらに最適な条件で接合することができる。   In the circuit board of the present invention, the first brazing material and the second brazing material can be brought into a closer state by making the second brazing material and the bonding pad the same shape in plan view. In addition, the electronic device can be further bonded under optimum conditions.

本発明の電子装置は、上記本発明の回路基板と、回路基板に搭載された電子部品とを具備していることによって、電子素子が安定に接合された動作信頼性の高いものとなる。   The electronic device according to the present invention includes the circuit board according to the present invention and the electronic component mounted on the circuit board, and thus has high operational reliability in which electronic elements are stably bonded.

本発明の電子装置の製造方法によると、第2のろう材の状態を観察して、電子素子を絶縁基板に搭載する工程を具備することによって、電子素子が適切な状態で回路基板に搭載された、動作信頼性の高い電子装置とすることができる。   According to the method for manufacturing an electronic device of the present invention, by observing the state of the second brazing material and mounting the electronic element on the insulating substrate, the electronic element is mounted on the circuit board in an appropriate state. In addition, an electronic device with high operation reliability can be obtained.

本発明の電子装置は、表面にろう材を介して電子素子が接合され、電子素子が搭載される部位を除く絶縁基板にろう材の溶融状態推定用のパターンが設けられた絶縁基板を有することによって、ろう材の溶融状態にあわせて電子素子を所望の状態で搭載することができる。   The electronic device of the present invention has an insulating substrate in which an electronic element is bonded to the surface via a brazing material, and a pattern for estimating the melting state of the brazing material is provided on the insulating substrate excluding a portion where the electronic device is mounted. Thus, the electronic element can be mounted in a desired state according to the molten state of the brazing material.

次に、本発明の回路基板を添付の図面に基づいて詳細に説明する。図1は本発明の回路基板の実施の形態の一例を示す斜視図である。図1において、14は回路基板、1は絶縁基板、2は電子素子の搭載部、3は配線導体、4は第1のろう材からなる接合パッド、5は第2のろう材、6は導電膜からなる標識部を示しており、回路基板14は、表面に電子素子の搭載部2を有するとともに、搭載部2に第1のろう材からなる接合パッド4が形成され、搭載部2を除く表面に第2のろう材5が被着された標識部6を有する絶縁基板1を具備している。   Next, the circuit board of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing an example of an embodiment of a circuit board according to the present invention. In FIG. 1, 14 is a circuit board, 1 is an insulating substrate, 2 is an electronic element mounting portion, 3 is a wiring conductor, 4 is a bonding pad made of a first brazing material, 5 is a second brazing material, and 6 is conductive. The circuit board 14 has an electronic element mounting portion 2 on the surface, and a bonding pad 4 made of a first brazing material is formed on the mounting portion 2, excluding the mounting portion 2. An insulating substrate 1 having a marking portion 6 having a second brazing material 5 attached on the surface thereof is provided.

絶縁基板1は、電子素子を搭載する機能を有し、例えば、縦0.5〜10mm、横0.5〜5mm、厚み0.1〜1mm程度の直方体であり、酸化アルミニウム(Al)質焼結体や窒化アルミニウム(AlN)質焼結体,炭化珪素(SiC)質焼結体,窒化珪素(Si)質焼結体,ガラスセラミックス等のセラミックス、エポキシ樹脂やポリイミド樹脂,ポリイミドシロキサン樹脂等の樹脂を含む絶縁材料から成る。電子素子として光半導体素子を用いる場合、熱伝導率が40W/m・K以上である材料、例えば窒化アルミニウム質焼結体,炭化珪素質焼結体,窒化珪素質焼結体等を用いると、駆動時の熱を効率良く放散させることができるため好ましい。 The insulating substrate 1 has a function of mounting electronic elements, and is, for example, a rectangular parallelepiped having a length of about 0.5 to 10 mm, a width of 0.5 to 5 mm, and a thickness of about 0.1 to 1 mm, and aluminum oxide (Al 2 O 3 ) Quality sintered body, aluminum nitride (AlN) type sintered body, silicon carbide (SiC) type sintered body, silicon nitride (Si 3 N 4 ) type sintered body, ceramics such as glass ceramics, epoxy resin and polyimide resin It is made of an insulating material containing a resin such as polyimide siloxane resin. When an optical semiconductor element is used as the electronic element, a material having a thermal conductivity of 40 W / m · K or more, such as an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, or the like, This is preferable because heat at the time of driving can be efficiently dissipated.

また、このような絶縁基板1は、例えばシート状にしたセラミックグリーンシートを積層し、約1500℃の温度で焼成する方法等により形成できる。   Further, such an insulating substrate 1 can be formed by, for example, a method of laminating ceramic green sheets in a sheet shape and firing at a temperature of about 1500 ° C.

絶縁基板1の表面に形成された搭載部2は電子素子を搭載し、配線導体3は搭載部2と外部電気回路(図示せず)とを電気的に接続する。このような搭載部2、配線導体3は、従来周知の蒸着法やスパッタリング法,CVD法,めっき法等の薄膜形成法により形成された後、従来周知のフォトリソグラフィ法やエッチング法,リフトオフ法等によって所定パターンに加工される。なお、搭載部2は、絶縁基板1の表面を用いて形成されていてもよく、回路基板14表面に形成された配線導体3の一部を用いて形成されていてもよい。   The mounting portion 2 formed on the surface of the insulating substrate 1 mounts an electronic element, and the wiring conductor 3 electrically connects the mounting portion 2 and an external electric circuit (not shown). The mounting portion 2 and the wiring conductor 3 are formed by a conventionally known thin film forming method such as a vapor deposition method, a sputtering method, a CVD method, or a plating method, and then a conventionally known photolithography method, etching method, lift-off method, or the like. Is processed into a predetermined pattern. The mounting portion 2 may be formed using the surface of the insulating substrate 1, or may be formed using a part of the wiring conductor 3 formed on the surface of the circuit substrate 14.

また、搭載部2、配線導体3は、例えば密着金属層、拡散防止層および主導体層が順次積層された3層構造の導体層から成るのがよい。   Moreover, the mounting part 2 and the wiring conductor 3 are preferably composed of a conductor layer having a three-layer structure in which an adhesion metal layer, a diffusion prevention layer, and a main conductor layer are sequentially laminated, for example.

密着金属層は、セラミックス等から成る絶縁基板1との密着性を良好とするという観点からは、チタン(Ti),クロム(Cr),タンタル(Ta),ニオブ(Nb),ニッケル−クロム(Ni−Cr)合金,窒化タンタル(TaN)等の熱膨張率がセラミックスと近い金属のうち少なくとも1種より成るのが好ましく、その厚みは0.01〜0.2μm程度が好ましい。密着金属層の厚みが0.01μm未満では、密着金属層を絶縁基板1に強固に密着することが困難となる傾向があり、0.2μmを超えると、成膜時の内部応力によって密着金属層が絶縁基板1から剥離し易くなる傾向がある。 From the viewpoint of improving the adhesion with the insulating substrate 1 made of ceramics or the like, the adhesion metal layer is made of titanium (Ti), chromium (Cr), tantalum (Ta), niobium (Nb), nickel-chromium (Ni —Cr) alloy, tantalum nitride (Ta 2 N), or the like, preferably made of at least one metal having a thermal expansion coefficient close to that of ceramics, and the thickness is preferably about 0.01 to 0.2 μm. If the thickness of the adhesion metal layer is less than 0.01 μm, it tends to be difficult to firmly adhere the adhesion metal layer to the insulating substrate 1. If the thickness exceeds 0.2 μm, the adhesion metal layer is caused by internal stress during film formation. Tends to peel from the insulating substrate 1.

また、拡散防止層は、密着金属層と主導体層との相互拡散を防ぐという観点からは、白金(Pt),パラジウム(Pd),ロジウム(Rh),ニッケル(Ni),タングステン(W),Ni−Cr合金,Ti−W合金等の熱伝導性の良好な金属のうち少なくとも1種より成ることが好ましく、その厚みは0.05〜1μm程度が好ましい。拡散防止層の厚みが0.05μm未満では、ピンホール等の欠陥が発生して拡散防止層としての機能を果たしにくくなる傾向があり、1μmを超えると、成膜時の内部応力により拡散防止層が密着金属層から剥離し易く成る傾向がある。なお、拡散防止層にNi−Cr合金を用いる場合は、Ni−Cr合金は絶縁基板1との密着性が良好なため、密着金属層を省くことも可能である。   In addition, the diffusion preventing layer is made of platinum (Pt), palladium (Pd), rhodium (Rh), nickel (Ni), tungsten (W), from the viewpoint of preventing mutual diffusion between the adhesion metal layer and the main conductor layer. It is preferably made of at least one metal having good thermal conductivity such as Ni—Cr alloy or Ti—W alloy, and its thickness is preferably about 0.05 to 1 μm. If the thickness of the diffusion prevention layer is less than 0.05 μm, defects such as pinholes tend to occur and it becomes difficult to perform the function as the diffusion prevention layer. If the thickness exceeds 1 μm, the diffusion prevention layer is caused by internal stress during film formation. Tends to be easily peeled off from the adhesive metal layer. When a Ni—Cr alloy is used for the diffusion preventing layer, the Ni—Cr alloy has good adhesion to the insulating substrate 1, and therefore the adhesion metal layer can be omitted.

さらに、主導体層は、搭載部2、配線導体3の電気抵抗を小さくするという観点からは、電気抵抗の小さい金(Au),Cu,Ni,銀(Ag)の少なくとも1種より成ることが好ましく、その厚みは0.1〜5μm程度が好ましい。主導体層の厚みが0.1μm未満では、電気抵抗が大きなものとなり配線導体3に要求される電気抵抗を満足できなくなる傾向があり、5μmを超えると、成膜時の内部応力により主導体層が拡散防止層から剥離し易く成る傾向がある。なお、Auは貴金属で高価であることから、低コスト化の点でなるべく薄く形成することが好ましい。また、Cuは酸化し易いので、その上にNiおよびAuからなる保護層を被覆してもよい。   Further, the main conductor layer may be made of at least one of gold (Au), Cu, Ni, and silver (Ag) having a low electric resistance from the viewpoint of reducing the electric resistance of the mounting portion 2 and the wiring conductor 3. The thickness is preferably about 0.1 to 5 μm. If the thickness of the main conductor layer is less than 0.1 μm, the electric resistance tends to be large and the electric resistance required for the wiring conductor 3 tends not to be satisfied. If the thickness exceeds 5 μm, the main conductor layer is caused by internal stress during film formation. Tends to be easily peeled off from the diffusion preventing layer. Since Au is a noble metal and expensive, it is preferably formed as thin as possible in terms of cost reduction. Further, since Cu is easily oxidized, a protective layer made of Ni and Au may be coated thereon.

第1のろう材からなる接合パッド4は、絶縁基板1の搭載部2に従来周知の蒸着法やスパッタリング法,CVD法,めっき法等の薄膜形成法により形成された後、従来周知のフォトリソグラフィ法やエッチング法,リフトオフ法等によって所定パターンで設けられる。このような第1のろう材は、Au−Ge合金(融点約356℃)、Au−Si合金(融点約370℃)、鉛−錫(PbーSn)合金(融点約183℃)、Au−Sn合金(融点約280℃)、Ag−Sn合金(融点約220℃)、In−Pb合金(融点約172℃)、In(融点約157℃)等から成り、中でも特にAu−Sn合金からなるのが好ましい。なぜなら、一般的に電子素子は約400℃程度の耐熱性を有しており、上述のAu−Ge合金およびAu−Si合金で実装する際の実装温度は400℃以上となり、電子素子が熱劣化する可能性がある。また、上述のIn−Pb合金およびInの低融点ろう材は電子素子との接合強度が弱い傾向がある。よって、AuーSn合金からなるろう材を用いることにより、電子素子を搭載時に第1のろう材を溶融しても熱劣化させることなく実装することができ、且つ、接合強度を強いものとすることができる。   The bonding pad 4 made of the first brazing material is formed on the mounting portion 2 of the insulating substrate 1 by a conventionally known thin film forming method such as a vapor deposition method, a sputtering method, a CVD method, or a plating method, and then a conventionally known photolithography. It is provided in a predetermined pattern by a method, an etching method, a lift-off method, or the like. Such a first brazing material includes an Au—Ge alloy (melting point: about 356 ° C.), an Au—Si alloy (melting point: about 370 ° C.), a lead-tin (Pb—Sn) alloy (melting point: about 183 ° C.), Au— Sn alloy (melting point: about 280 ° C), Ag-Sn alloy (melting point: about 220 ° C), In-Pb alloy (melting point: about 172 ° C), In (melting point: about 157 ° C), etc., especially Au-Sn alloy. Is preferred. This is because electronic devices generally have a heat resistance of about 400 ° C., and the mounting temperature when mounting with the above-described Au—Ge alloy and Au—Si alloy is 400 ° C. or more, and the electronic devices are thermally deteriorated. there's a possibility that. In addition, the above-described In—Pb alloy and In low melting point brazing filler metal tend to have low bonding strength with electronic devices. Therefore, by using a brazing material made of an Au—Sn alloy, the electronic element can be mounted without being thermally deteriorated even when the first brazing material is melted at the time of mounting, and the bonding strength is increased. be able to.

また、接合パッド4の厚みは2μm〜10μmが好ましい。2μm未満の場合、搭載された電子素子と搭載部2間の第1のろう材中に空洞ができ、電子素子の接合強度(ダイシェア強度)が低下し易くなる。また、10μmを超える場合、溶融した第1のろう材が回路基板14に搭載された電子素子を這い上がり、電子素子に形成された回路を短絡させてしまう可能性がある。   Further, the thickness of the bonding pad 4 is preferably 2 μm to 10 μm. When the thickness is less than 2 μm, a void is formed in the first brazing material between the mounted electronic device and the mounting portion 2, and the bonding strength (die shear strength) of the electronic device is likely to decrease. When the thickness exceeds 10 μm, the melted first brazing material scoops up the electronic element mounted on the circuit board 14 and may short circuit the circuit formed on the electronic element.

標識部6は、絶縁基板1の搭載部2を除く領域に設けられており、絶縁基板1の一部を用いて形成されていてもよく、配線導体3の一部を用いて形成されていてもよい。また、図1に示すように絶縁基板1の上に設けられた導電膜から形成されていてもよい。標識部6が例えば、W等から成る導電膜で形成されている場合、導電膜と上述のW等からなる絶縁基板1とは接合性が高いため、標識部6を絶縁基板2に直接形成するよりも剥離を抑制することができ好ましい。このような導電膜からなる標識部6は、従来周知のスクリーン印刷法のような厚膜形成法や蒸着法やスパッタリング法,CVD法,めっき法等の薄膜形成法により形成された後、従来周知のフォトリソグラフィ法やエッチング法,リフトオフ法等によって所定パターンに加工される。   The marking portion 6 is provided in a region excluding the mounting portion 2 of the insulating substrate 1 and may be formed using a part of the insulating substrate 1 or formed using a part of the wiring conductor 3. Also good. Moreover, as shown in FIG. 1, you may form from the electrically conductive film provided on the insulating substrate 1. FIG. For example, when the marking portion 6 is formed of a conductive film made of W or the like, since the conductive film and the insulating substrate 1 made of W or the like have high bonding properties, the marking portion 6 is formed directly on the insulating substrate 2. It is preferable because it can suppress peeling. The marker portion 6 made of such a conductive film is formed by a thick film forming method such as a conventionally known screen printing method or a thin film forming method such as a vapor deposition method, a sputtering method, a CVD method, or a plating method, and then conventionally known. These are processed into a predetermined pattern by the photolithography method, the etching method, the lift-off method or the like.

標識部6に被着された第2のろう材5は、接合パッド4と同様の方法で標識部6に形成されており、Au−Ge合金(融点約356℃)、Au−Si合金(融点約370℃)、Pb−Sn合金(融点約183℃)、Au−Sn合金(融点約280℃)、Ag−Sn合金(融点約220℃)、In−Pb合金(約172℃)、In(融点約157℃)等から成る。このような第2のろう材5が被着された標識部6は、溶融状態推定用のパターンとして機能しており、標識部6に被着された第2のろう材5の溶融状態が観察されることによって、接合パッド4を形成する第1のろう材の溶融状態が推定できる。よって、第1のろう材が十分に溶融していない、あるいは、第1のろう材が搭載部2からはみ出して溶融し、回路基板14に形成された他の電子素子とショートする等の第1のろう材の溶融状態の不良に起因する電子素子と回路基板14との接続不良が生じることを抑制し、所望の状態で電子素子を回路基板14の搭載部2に搭載することができる。ここで、第2のろう材は、第1のろう材と融点が同等かあるいは第1のろう材の融点より低い融点を有する材料から成るのが好ましく、その融点の差は10℃以下であるのがよい。仮に第1のろう材の融点が第2のろう材5の融点に比べて10℃より高いと、第1のろう材が溶融するよりも相当早い段階で第2のろう材5が溶融してしまい、第1のろう材の溶融状態を推定する機能を十分になし難い。   The second brazing material 5 deposited on the marking portion 6 is formed on the marking portion 6 in the same manner as the bonding pad 4, and is composed of an Au—Ge alloy (melting point: about 356 ° C.), an Au—Si alloy (melting point). About 370 ° C.), Pb—Sn alloy (melting point: about 183 ° C.), Au—Sn alloy (melting point: about 280 ° C.), Ag—Sn alloy (melting point: about 220 ° C.), In—Pb alloy (about 172 ° C.), In ( The melting point is about 157 ° C.). The marking part 6 to which the second brazing material 5 is adhered functions as a pattern for estimating the molten state, and the molten state of the second brazing material 5 adhered to the marking part 6 is observed. As a result, the molten state of the first brazing material forming the bonding pad 4 can be estimated. Therefore, the first brazing material is not sufficiently melted, or the first brazing material protrudes from the mounting portion 2 and melts to short-circuit with other electronic elements formed on the circuit board 14. It is possible to suppress the occurrence of poor connection between the electronic element and the circuit board 14 due to the defective melting state of the brazing material, and to mount the electronic element on the mounting portion 2 of the circuit board 14 in a desired state. Here, the second brazing material is preferably made of a material having a melting point equal to or lower than the melting point of the first brazing material, and the difference between the melting points is 10 ° C. or less. It is good. If the melting point of the first brazing material is higher than 10 ° C. compared to the melting point of the second brazing material 5, the second brazing material 5 is melted at a much earlier stage than the first brazing material is melted. Therefore, it is difficult to sufficiently perform the function of estimating the molten state of the first brazing material.

なお、第2のろう材5が被着された標識部6は、電子部品を絶縁基板1に搭載する際に視認可能な位置(例えば回路基板の上方から見える位置等)に形成されている。また、第2のろう材5の溶融状態を確認する際に、第2のろう材5の表面には、他の部品が接合されていない状態である。   In addition, the label | marker part 6 to which the 2nd brazing material 5 was adhere | attached is formed in the position (for example, position visible from the upper direction of a circuit board etc.) visible when mounting an electronic component on the insulated substrate 1. FIG. Further, when the melting state of the second brazing material 5 is confirmed, no other parts are bonded to the surface of the second brazing material 5.

また、上述のように標識部6に被着された第2のろう材5の溶融状態が観察されることによって、電子素子を絶縁基板に安定して搭載することができるため、第1のろう材と第2のろう材5との組成は溶融状態が近似する組成であるのが好ましい。このような組成としては、例えば第1のろう材としてSnが96.5%、Agが3.5%で構成されており、第2のろう材5としてSnが96.5%、Agが3.0%、Cuが0.5%で構成されている場合等が考えられる。   Moreover, since the molten state of the second brazing material 5 attached to the marking portion 6 is observed as described above, the electronic element can be stably mounted on the insulating substrate, so that the first brazing The composition of the material and the second brazing material 5 is preferably a composition that approximates the molten state. As such a composition, for example, the first brazing material is composed of 96.5% Sn and 3.5% Ag, and the second brazing material 5 is composed of 96.5% Sn and 3% Ag. The case where 0.0% and Cu are comprised with 0.5% is considered.

また、さらに好ましくは、第2のろう材5が接合パッド4を形成する第1のろう材と同一組成のろう材から成るのがよい。なぜなら、同一成分からなることによって接合パッド4を形成する第1のろう材の溶融状態と標識部6に被着された第2のろう材5の溶融状態とがさらに近似するため、第2のろう材5の状態を確認することで電子素子が搭載される接合パッド4の状態がよりわかり易くなるからである。そして、標識部6に被着された第2のろう材5の厚みは接合パッド4と同じ厚みであるのが好ましい。なぜなら、このような厚みで形成されることによって、第1のろう材の溶融状態と第2のろう材5の溶融状態とがさらに近似するからである。   More preferably, the second brazing material 5 is made of a brazing material having the same composition as the first brazing material forming the bonding pad 4. This is because the molten state of the first brazing material forming the bonding pad 4 and the molten state of the second brazing material 5 attached to the marking portion 6 are further approximated by being composed of the same component. This is because checking the state of the brazing material 5 makes it easier to understand the state of the bonding pad 4 on which the electronic element is mounted. And it is preferable that the thickness of the 2nd brazing material 5 adhere | attached on the label | marker part 6 is the same thickness as the joining pad 4. FIG. This is because by forming with such a thickness, the molten state of the first brazing material and the molten state of the second brazing material 5 are further approximated.

また、好ましくは、平面視で第2のろう材5の外周部に角部が形成されているのがよい。なぜなら、電子素子搭載時に標識部6に被着された第2のろう材5が溶融を開始すると、角部付近で第2のろう材5の形状に変化があらわれ、その動きを確認することで電子素子が搭載される接合パッドの状態がよりわかり易くなり、電子素子をより最適な条件で接合することが可能となるからである。   In addition, it is preferable that corners are formed on the outer peripheral portion of the second brazing material 5 in plan view. This is because when the second brazing material 5 attached to the marking portion 6 starts to melt when the electronic element is mounted, the shape of the second brazing material 5 changes in the vicinity of the corner, and the movement is confirmed. This is because the state of the bonding pad on which the electronic element is mounted becomes easier to understand, and the electronic element can be bonded under more optimal conditions.

また、さらに好ましくは標識部6の第2のろう材5が被着された部位の表面の算術平均粗さRaをR1、搭載部2の表面の算術平均粗さRaをR2としたとき、R1≦R2の関係を有するのがよい。このような表面状態を得る方法として、例えばまず、標識部6の第2のろう材5が被着される部位に、従来周知のフォトリソグラフィ法等によってレジスト膜を形成する。その後、サンドブラストをかけて表面を荒らし、絶縁基板1に上述の方法で搭載部2を形成した後、レジストを剥離し接合パッド4と標識部6とを形成することによってR1≦R2の関係を有する表面状態とする方法等が考えられる。一般的に滑らかな表面に形成されたろう材は、粗く形成された表面に形成されたろう材よりも濡れ性が悪く、大きく形状を変えて溶融する。よって、第2のろう材5が被着される部位の標識部6の表面が、電子素子の搭載部2の表面と比べて滑らかに形成された回路基板14は、第2のろう材5の溶融開始時の動きがより大きくなり視認し易くなるため好ましい。   More preferably, R1 represents the arithmetic average roughness Ra of the surface of the portion 6 to which the second brazing material 5 of the marking portion 6 is attached, and R2 represents the arithmetic average roughness Ra of the surface of the mounting portion 2. It is preferable to have a relationship of ≦ R2. As a method for obtaining such a surface state, for example, first, a resist film is formed on a portion of the marking portion 6 where the second brazing material 5 is adhered by a conventionally known photolithography method or the like. Thereafter, sandblasting is performed to roughen the surface, and after the mounting portion 2 is formed on the insulating substrate 1 by the above-described method, the resist is peeled off to form the bonding pad 4 and the marker portion 6 so that R1 ≦ R2 is satisfied. A method for obtaining a surface state is conceivable. In general, a brazing material formed on a smooth surface has lower wettability than a brazing material formed on a rough surface, and melts with a greatly changed shape. Therefore, the circuit board 14 in which the surface of the marking portion 6 where the second brazing material 5 is attached is formed more smoothly than the surface of the mounting portion 2 of the electronic element is the second brazing material 5. It is preferable because the movement at the start of melting becomes larger and the visual recognition becomes easier.

また、標識部6の第2のろう材5が被着された部位の表面の算術平均粗さR1は、一部が異なる値を持つのが好ましい。このような回路基板14は、例えば、レジスト膜で標識部6の一部を覆うように形成し、サンドブラストをかけてレジスト膜を削除した後、第2のろう材5を被着させることで形成される。前述のように算術平均粗さRaの異なる部位に形成されたものの動きは一般的に異なるため、一部が滑らかな面上に形成された標識部6の第2のろう材5の動きを確認することにより接合パッド4を形成する第1のろう材の溶融開始時の動きがより視認しやすくなり、電子素子をより適切に接合しやすくなるため好ましい。   Further, it is preferable that the arithmetic average roughness R1 of the surface of the portion where the second brazing material 5 of the marking portion 6 is attached has a partly different value. Such a circuit board 14 is formed, for example, by covering a part of the marking portion 6 with a resist film, removing the resist film by sandblasting, and then depositing the second brazing material 5. Is done. As described above, since the movement of parts formed at different parts of the arithmetic average roughness Ra is generally different, the movement of the second brazing material 5 of the marking part 6 formed on a partly smooth surface is confirmed. By doing so, the movement at the start of melting of the first brazing material forming the bonding pad 4 becomes easier to visually recognize, and it is preferable to bond the electronic elements more appropriately.

また、第2のろう材5と接合パッド4とが平面視で同じ形状に形成されると、標識部6に被着された第2のろう材5における熱の伝わり方と、接合パッド2を形成する第1のろう材における熱の伝わり方とがより近似され、第1、第2のろう材5の溶融状態をより近い状態とすることができる。このため、電子素子をさらに最適な条件で接合することができ、好ましい。   Further, when the second brazing material 5 and the bonding pad 4 are formed in the same shape in plan view, the heat transfer in the second brazing material 5 attached to the marker portion 6 and the bonding pad 2 are determined. The way of heat transfer in the first brazing material to be formed is more approximate, and the molten state of the first and second brazing materials 5 can be made closer. For this reason, an electronic element can be joined on more optimal conditions, and it is preferable.

また、回路基板14上に電気抵抗確認用のモニターパターン、膜厚確認用のモニターパターンや位置あわせ用のターゲットパターン等のモニターが設けられている場合、このようなモニターを標識部6とすると、回路基板14表面に標識部6を別に設ける必要がなくなり、回路基板14の表面を有効に利用できるため好ましい。また、例えば、モニターとしてターゲットパターンが回路基板14上に形成されている場合、このようなターゲットパターンは電子素子の位置あわせ時に当然光学的画像認識等によってモニタリングされているため、ターゲットパターンと標識部6に被着された第2のろう材5とを観察するカメラを別途設ける必要がなくなる。またさらに、第2のろう材5によりターゲットパターンの高さが高くなるため、その陰影によりターゲットパターンをより認識し易くなる。   Further, when a monitor such as a monitor pattern for confirming electrical resistance, a monitor pattern for confirming film thickness, or a target pattern for alignment is provided on the circuit board 14, such a monitor is assumed to be the marking unit 6. This is preferable because it is not necessary to separately provide the marking portion 6 on the surface of the circuit board 14 and the surface of the circuit board 14 can be used effectively. Further, for example, when a target pattern is formed on the circuit board 14 as a monitor, such a target pattern is naturally monitored by optical image recognition or the like when aligning the electronic elements. Therefore, it is not necessary to separately provide a camera for observing the second brazing material 5 attached to 6. Furthermore, since the height of the target pattern is increased by the second brazing material 5, it becomes easier to recognize the target pattern due to the shadow.

次に、本発明の電子装置を添付の図面に基づいて詳細に説明する。図2は、本発明の電子装置の実施の形態の一例を示す断面図である。以下の説明において、電子素子の一例として光半導体素子を用いて説明するが、光半導体素子に限られるものではない。   Next, an electronic device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a cross-sectional view showing an example of an embodiment of an electronic device of the present invention. In the following description, an optical semiconductor element is used as an example of an electronic element, but the present invention is not limited to the optical semiconductor element.

図2において電子装置101は、光半導体素子103と、ろう材を介して光半導体素子103が搭載された回路基板14から主に成っており、基体105の上面に回路基板14を取り囲むようにAgロウ合金やAuSn合金等のロウ材や接着材を介して枠体109が接合されている。このような枠体109は、上面にAgロウ合金やAuSn合金等のロウ材や接着材を介して蓋体110が取着されており、レンズ107を介して光半導体素子103と対向する側部に光ファイバ108を挿入するための貫通孔109aが形成されている。そして、貫通孔109aには光ファイバ108を固定するための筒状の固定部材111が挿着されており、基体105上面に搭載された回路基板14は、TEC(サーモエレクトリッククーラー)106を介して載置されている。   In FIG. 2, an electronic device 101 mainly includes an optical semiconductor element 103 and a circuit board 14 on which the optical semiconductor element 103 is mounted via a brazing material, and Ag is formed so as to surround the circuit board 14 on the upper surface of the base 105. The frame body 109 is joined via a brazing material such as a brazing alloy or an AuSn alloy or an adhesive. In such a frame 109, a lid 110 is attached to the upper surface via a brazing material or adhesive such as Ag brazing alloy or AuSn alloy, and the side portion facing the optical semiconductor element 103 via the lens 107. A through hole 109a for inserting the optical fiber 108 is formed in the optical fiber 108. A cylindrical fixing member 111 for fixing the optical fiber 108 is inserted into the through hole 109 a, and the circuit board 14 mounted on the upper surface of the base 105 is interposed via a TEC (thermoelectric cooler) 106. It is placed.

また、固定部材111には、光ファイバ108の端部に取着されたステンレススチール等から成るフランジ(図示せず)がYAGレーザ等の照射によるレーザ溶接によって接合されており、光ファイバ108が枠体109に固定されることによって電子装置101となる。このような電子装置101は、本発明の回路基板14と、回路基板14に搭載された電子部品103とを具備していることによって、電子素子103を安定に接合できる、動作信頼性の高いものとすることができる。   Further, a flange (not shown) made of stainless steel or the like attached to the end of the optical fiber 108 is joined to the fixing member 111 by laser welding by irradiation with a YAG laser or the like, and the optical fiber 108 is framed. The electronic device 101 is obtained by being fixed to the body 109. Such an electronic device 101 includes the circuit board 14 of the present invention and the electronic component 103 mounted on the circuit board 14 so that the electronic element 103 can be stably bonded and has high operation reliability. It can be.

ここで、上述の電子装置101を製造する方法は、標識5に被着された第2のろう材5の溶融状態を観察して、電子素子を絶縁基板1に搭載する工程を具備している。このような工程を具備することにより、たとえ電子素子を絶縁基板1に搭載する際に電子素子が平面視で搭載部に重なって第1のろう材の溶融状態が確認できなくても、第2のろう材5の溶融状態を代わりに確認することで、電子素子を安定に接続搭載した高信頼の電子装置を製造することができる。   Here, the method of manufacturing the electronic device 101 described above includes a step of observing the molten state of the second brazing material 5 attached to the marker 5 and mounting the electronic element on the insulating substrate 1. . By providing such a process, even when the electronic element is mounted on the insulating substrate 1, even if the electronic element overlaps the mounting portion in a plan view and the molten state of the first brazing material cannot be confirmed, the second By confirming the molten state of the brazing material 5 instead, a highly reliable electronic device in which electronic elements are stably connected and mounted can be manufactured.

なお、本発明は上述の実施の最良の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更を施すことは何等差し支えない。   It should be noted that the present invention is not limited to the best mode described above, and various modifications may be made without departing from the gist of the present invention.

本発明の回路基板の実施の形態の一例を示す斜視図である。It is a perspective view which shows an example of embodiment of the circuit board of this invention. 本発明の電子装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the electronic device of this invention. 従来の回路基板の斜視図である。It is a perspective view of the conventional circuit board.

符号の説明Explanation of symbols

1:絶縁基板
2:搭載部
3:配線導体
4:第1のろう材からなる接合パッド
5:第2のろう材
6:標識部
14:回路基板
1: Insulating substrate 2: Mounting portion 3: Wiring conductor 4: Bonding pad 5 made of first brazing material 5: Second brazing material 6: Marking portion 14: Circuit board

Claims (8)

表面に電子素子の搭載部を有するとともに、該搭載部に第1のろう材からなる接合パッドが形成され、前記搭載部を除く前記表面に第2のろう材が被着された標識部を有する絶縁基板を具備することを特徴とする回路基板。 It has an electronic element mounting portion on the surface, a bonding pad made of a first brazing material is formed on the mounting portion, and a marking portion on which the second brazing material is attached on the surface excluding the mounting portion. A circuit board comprising an insulating substrate. 前記第2のろう材は、前記第1のろう材と同一組成のろう材から成ることを特徴とする請求項1に記載の回路基板。 The circuit board according to claim 1, wherein the second brazing material is made of a brazing material having the same composition as the first brazing material. 前記第2のろう材は平面視で外周部に角部を有することを特徴とする請求項1または請求項2に記載の回路基板。 The circuit board according to claim 1, wherein the second brazing material has a corner portion on an outer peripheral portion in a plan view. 前記標識部の前記第2のろう材が被着された部位の表面の算術平均粗さRaをR1、前記搭載部の表面の算術平均粗さRaをR2としたとき、R1≦R2の関係を有することを特徴とする請求項1乃至請求項3のいずれかに記載の回路基板。 When the arithmetic average roughness Ra of the surface of the portion where the second brazing material of the labeling part is attached is R1, and the arithmetic average roughness Ra of the surface of the mounting part is R2, the relationship of R1 ≦ R2 is established. The circuit board according to claim 1, wherein the circuit board is provided. 前記第2のろう材と前記接合パッドとが平面視で同じ形状であることを特徴とする請求項1乃至請求項4のいずれかに記載の回路基板。 5. The circuit board according to claim 1, wherein the second brazing material and the bonding pad have the same shape in a plan view. 請求項1乃至請求項5のいずれかに記載の回路基板と、該回路基板に搭載された電子部品とを具備していることを特徴とする電子装置。 An electronic device comprising: the circuit board according to claim 1; and an electronic component mounted on the circuit board. 請求項6に記載の電子装置の製造方法であって、前記第2のろう材の状態を観察して、前記電子素子を前記絶縁基板に搭載する工程を具備することを特徴とする電子装置の製造方法。 7. The method of manufacturing an electronic device according to claim 6, further comprising a step of observing a state of the second brazing material and mounting the electronic element on the insulating substrate. Production method. 表面にろう材を介して電子素子が接合され、前記電子素子が搭載される部位を除く前記絶縁基板に前記ろう材の溶融状態推定用のパターンが設けられた絶縁基板を有することを特徴とする電子装置。 An electronic element is bonded to the surface via a brazing material, and the insulating substrate excluding a portion on which the electronic element is mounted has an insulating substrate provided with a pattern for estimating the melting state of the brazing material. Electronic equipment.
JP2005282622A 2005-09-28 2005-09-28 Circuit board, electronic equipment using it, and manufacturing method thereof Pending JP2007095954A (en)

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