JP2007086683A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently impress overdrive pulses. <P>SOLUTION: Each pixel has a holding capacity 114 to which a video voltage taken in from a data line DL is written and a liquid crystal element 112 to which the voltage held by the holding capacity 114 is applied. Then, immediately after the end start of video voltage write to the holding capacity 114, capacity lines SC-A and SC-B are shifted by the overdrive pulses and the voltage applied to a liquid crystal is made larger than the voltage desired to be actually applied to the liquid crystal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a device that overdrives a voltage applied to liquid crystal.

  Conventionally, a liquid crystal display (LCD) has been widely used as a typical flat panel display. This liquid crystal display device includes a passive type and an active matrix type, and an active matrix type in which each pixel has an individual pixel electrode and voltage supply to the pixel electrode is controlled by an individual pixel circuit is mainly used. It has become.

  In an active matrix liquid crystal display device, each pixel arranged in a matrix is provided with a switch transistor for controlling the video voltage (video signal) taken from the data line. Then, by this switch transistor, the taken video voltage is written into the storage capacitor and applied to the pixel electrode. Such a pixel circuit and each pixel electrode are provided on a pixel substrate. A counter substrate provided with a counter electrode common to all the pixels is disposed facing the pixel substrate, and liquid crystal is sealed between the pixel substrate and the counter substrate. Therefore, display according to the video voltage is performed by applying a video voltage to each pixel electrode.

  Further, if the voltage application to the liquid crystal is always in one direction, image sticking occurs. For this reason, AC driving that periodically reverses the voltage to the liquid crystal is employed. This AC drive may be performed by periodically inverting the voltage applied to the liquid crystal, for example, by inverting the polarity of the video voltage with respect to the voltage of the counter electrode (the + -direction with respect to the counter electrode) for each frame. .

  Also, if the direction of voltage application to the entire liquid crystal is periodically reversed, the display tends to be adversely affected. Therefore, a dot inversion method is also known in which the voltage application direction by AC driving is set in the opposite direction for each dot.

  On the other hand, the liquid crystal display device has a problem that the response speed in display is slower than that of a CRT (cathode ray tube) or the like. Therefore, an overdrive driving method has been proposed in which video data is corrected and the change is made larger than actual when the gradation changes, thereby improving the response (Patent Document 1).

JP-A 64-10299

  Here, in order to perform the overdrive process, it is necessary to shift the video signal supplied to the liquid crystal panel as a whole. Therefore, there is a problem that the power supply capability for outputting the video signal has to be increased and the power consumption is increased. In addition, in the dot inversion, if the overdrive method is adopted, there is a problem that a circuit for that is complicated.

  The present invention relates to a liquid crystal display device in which liquid crystal is sealed between a first substrate and a second substrate, and display is performed by controlling a voltage of liquid crystal for each pixel arranged in a matrix. Each pixel has a data line A storage capacitor to which the video voltage taken in is written, a pixel electrode connected to the storage capacitor, to which a voltage held in the storage capacitor is applied, and for applying a voltage to the liquid crystal, A capacitor line is connected to the side opposite to the side connected to the pixel electrode, and the voltage applied to the liquid crystal is higher than the voltage that is actually desired to be applied to the liquid crystal immediately after the video voltage writing is completed. An overdrive pulse for shifting the voltage of the storage capacitor is applied to the capacitor.

  The height of the overdrive pulse is preferably determined according to the video voltage.

  Further, two capacitor lines are provided for each row of the pixels, and the capacitors of the pixels in the row direction are alternately connected to the two capacitor lines, and the polarity of the voltage applied to the liquid crystal is inverted in the data line of each column. The video voltage is alternately supplied, the voltage supplied to the two capacitor lines is set so that the voltage applied to the corresponding liquid crystal has the opposite polarity in each pixel in the row direction, and is supplied to each capacitor line The polarity of the overdrive pulse is preferably set in accordance with the voltage supplied to the capacitor line.

  Thus, according to the present invention, an overdrive pulse is applied to the capacitor line. Therefore, it is not necessary to shift the video voltage itself as a whole. Therefore, compared to shifting the video voltage, the configuration is simple and power saving can be achieved.

  FIG. 1 shows a configuration of a signal processing circuit that creates various signals to be supplied to a liquid crystal panel based on a video signal and a synchronization signal from a microcomputer. This signal processing circuit is usually composed of an IC (semiconductor integrated circuit) separate from the liquid crystal panel.

  RGB digital video signals are supplied from the microcomputer. In this example, each RGB signal is a 6-bit [5: 0] 64-gradation digital video signal, which is input to the video signal processing circuit 10. The video signal processing circuit 10 performs signal processing such as γ correction, and supplies the processed signal to a D / A (digital / analog) conversion circuit 12. The D / A conversion circuit 12 converts each RGB signal into a corresponding analog signal. The analog signal thus obtained is supplied to the liquid crystal panel via the amplifier 14.

  Further, the dot clock Dotclk, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync indicating the timing for each display dot of the video signal supplied from the microcomputer are supplied to the timing controller (T / C) 16. Based on these signals, the processing timing in the video signal processing circuit 10 and the D / A conversion circuit 12 is controlled. Further, the control pulse necessary for the liquid crystal panel is boosted by the level shifter 18 and then supplied to the liquid crystal.

  Further, the digital video signal is also supplied to the D / A conversion circuit 20 for the SC line. The D / A conversion circuit 20 generates two types of voltage signals VSCH and VSCL for the capacitance line in the liquid crystal panel, and amplifies them in the amplifier 22 and outputs them. VSCH and VSCL are signals having opposite polarities and are alternately switched between H level (voltage higher than the common electrode voltage VCOM) and L level (voltage lower than the common electrode voltage VCOM) at every predetermined polarity conversion timing. As will be described later, in this embodiment, two capacitor lines SC-A and SC-B are prepared for one row of pixels, and the voltages VSCH and VSCL are sequentially switched for each frame. It is because it supplies. Then, dot inversion is enabled by alternately connecting the capacitance of each pixel in one row to two capacitance lines SC-A and SC-B.

  The D / A conversion circuit 20 is also supplied with a digital video signal, and an overdrive pulse is added to the voltage signals VSCH and VSCL by D / A converting the digital video signal. The signal switching timing in the D / A conversion circuit 20 is controlled by a signal from the timing controller 16.

  That is, as shown in FIG. 2, the polarity of the video signal supplied to one pixel of the liquid crystal panel is inverted every predetermined frame (for example, several frames to several tens frames). In addition, when the polarity is + (when a voltage higher than VCOM is applied to the pixel electrode), a positive voltage VSCH (a voltage higher than VCOM) is supplied to the capacitor line to which the capacitor of the pixel is connected. A voltage VSCL having a polarity of-at the time of-is supplied.

  Although not shown in FIG. 2, when a video signal is written to the storage capacitor, the capacitor line is set to substantially the same voltage as VCOM, and then shifted to a voltage higher or lower than VCOM. .

  The voltage signals VSCH and VSCL are added with an overdrive pulse of one frame period, for example, at the timing of switching the polarity of the video signal. The direction of this overdrive pulse is the + direction for the voltage signal VSCH and the-direction for the VSCL. As a result, a voltage larger than the video voltage is actually applied to the liquid crystal of the pixel during the first one frame period.

  The voltage signals VSCH and VSCL output from the amplifier 22 are provided with overdrive pulses at the timing of polarity inversion of the video signal. That is, the video signal supplied to each pixel is inverted every predetermined frame. Therefore, an overdrive pulse is added to both voltage signals VSCH and VSCL in accordance with the inversion timing.

  In this embodiment, the voltage value of the overdrive pulse can be obtained by D / A converting the digital video signal. For example, when the black level is about 1.0V and the white level is about 3.5V, the overdrive pulse voltage is preferably about 0.2 to 0.8V. The voltage value of the overdrive pulse is large when the luminance is high according to the value (luminance value) of the video signal at that time, and the voltage value of the overdrive pulse is small when the luminance is low. Generally, it is considered that the overdrive pulse is preferably set to several tens of percent with respect to the luminance at that time, and a suitable overdrive pulse voltage can be set by using a video signal. In addition, the use of the video signal eliminates the need for special voltage signal generation data. The voltage value of the overdrive pulse can be obtained by other than D / A conversion.

  FIGS. 3 and 4 show graphs of experimental examples regarding changes in response speed due to application of overdrive pulses. The relationship between the voltage applied to the liquid crystal and the display is 1.0 V: black, 2.5 V: halftone 1, 3.0 V: halftone 2, 3.5 V: white. The triangle (a) changes the applied voltage from 1.0 V to 3.5 V, the square (b) changes the applied voltage from 1.0 V to 3.0 V, and the circle (c) changes the applied voltage from 1.0 V to 2.5 V. Shows the response speed. The response time is a value written for each measurement point, and the three characteristics are written apart for easy understanding. The interval between the horizontal lines is 20 ms (milliseconds).

  As can be seen from the figure, the response speed is greatly improved by using the overdrive pulse.

  Further, it can be understood from the figure that the response speed is increased by increasing the overdrive voltage. In particular, the improvement in response speed from black to white is significant. Therefore, an appropriate response speed can be improved by the present embodiment in which the voltage value of the overdrive pulse is determined according to the magnitude of the video signal. In addition, 1.0V: white, 2.5V: halftone 1, 3.0V: halftone 2, 3.5V: black may be sufficient, and these numerical values are examples.

  FIG. 5 shows the luminance when the video voltage changes when the overdrive pulse is not used. On the other hand, FIG. 6 shows the luminance when using the overdrive pulse in this embodiment (adding the overdrive pulse to VSCH). In this way, the luminance response can be improved by using the overdrive pulse.

"Pixel circuit and dot inversion"
Here, in the present embodiment, two capacitor lines are provided for one row, and the voltages of the two capacitor lines are inverted for each frame with opposite polarities. This configuration will be described below.

  FIG. 7 shows a schematic configuration of a pixel circuit provided with two capacitor lines. The pixel circuit 1 is arranged in a matrix over the entire display area. The matrix arrangement may be a zigzag shape instead of a perfect lattice shape. The display may be monochrome or full color, and in the case of full color, the normal pixels are three colors of RGB, but it is also preferable to add pixels of a specific color including white as necessary.

  As shown in the drawing, one pixel circuit 1 has an n-channel pixel TFT 110 whose source is connected to the data line DL, a liquid crystal element 112 and a storage capacitor 114 connected to the drain of the pixel TFT 110. . A gate line GL arranged for each horizontal scanning line is connected to the gate of the pixel TFT 110.

  The liquid crystal element 112 is configured such that a pixel electrode individually provided for each pixel is connected to the drain of the pixel TFT 110, and a common electrode common to all the pixels is disposed opposite to the pixel electrode with the liquid crystal interposed therebetween. The common electrode is connected to the common electrode power source VCOM.

  In the storage capacitor 114, the extended portion of the semiconductor layer constituting the drain of the pixel TFT 110 is directly used as one electrode, and a part of the capacitor line SC formed so as to face the oxide film is a counter electrode. Note that the portion that becomes the electrode of the storage capacitor 114 may be separated from the portion of the pixel TFT 110 as another semiconductor layer, and both may be connected by metal wiring.

  Here, there are two capacitance lines SC, SC-A and SC-B, for one row (horizontal scanning line), and the storage capacitance of each pixel circuit is SC-A and SC-B in the horizontal scanning direction. Are connected alternately. In the pixel circuit shown in this figure, the storage capacitor 114 is connected to the capacitor line SC-A, and the storage capacitor 114 of the adjacent pixel is connected to the capacitor line SC-B.

  A vertical driver 120 is connected to the gate line GL, and the vertical driver 120 sequentially selects the gate lines GL one by one for each horizontal period and sets them to the H level. The vertical driver 120 has a shift register, receives a signal STV indicating the start of one vertical scanning period, sets the first stage of the shift register to the H level, and then shifts the H level one by one by a clock signal, for example. Thus, the gate lines GL of each horizontal scanning line are sequentially selected one by one and set to the H level. Here, for example, the H level of the gate line GL is the VDD potential, the L level is the VSS potential, and these power supply voltages VDD and VSS are supplied to the vertical driver 120, thereby the gate line GL as the output of the vertical driver. H level and L level are set.

  The SC driver 122 outputs two voltage levels to the two storage capacitor lines SC-A and SC-B.

  Although not shown, the display device is also provided with, for example, a horizontal driver, and controls line-sequential supply of the input video signal to the data line DL. That is, in this example, the horizontal driver outputs a sampling clock for each pixel in accordance with the clock of the video signal for each pixel, and the video signal (data signal) for one horizontal scanning line is turned on / off by this sampling clock. Latch. Then, a data signal for each pixel of one latched horizontal scanning line is output to the data line DL over one horizontal scanning period.

  Actually, there are three types of video signals, RGB, and each pixel in the vertical direction is one of the same color pixels of R, G, and B. Therefore, a data signal of any one of RGB is set in the data line DL.

  In the apparatus of this embodiment, a dot inversion AC application method is employed. That is, in each pixel (dot) in the horizontal scanning direction, a voltage applied to the pixel electrode of the liquid crystal element 112 is applied as a data signal having a polarity opposite to the voltage VCOM of the common electrode.

  The left side of FIG. 8 shows a data signal having the first polarity, and the hypotenuse of the triangle written as Vvideo indicates a data signal (write voltage) corresponding to the luminance. The data signal has a potential difference (dynamic range) of Vb from the black level to the white level, and the voltage applied to the pixel electrode after the voltage shift is white when the voltage is separated from VCOM, and is black when the voltage is close. It has become. Therefore, in this example, the black level is VCOM−Vb / 2 and the white level is VCOM + Vb / 2. In the adjacent pixels, as shown on the right side of FIG. 12, the second polarity is opposite to the first polarity, the black level is VCOM + Vb / 2, and the white level is VCOM−Vb / 2. ing.

  Then, after the ON period to the pixel TFT 110 ends and data writing ends, the capacitance lines SC-A and SC-B shift by the predetermined voltage ΔVsc. In this example, a normally black vertical alignment (VA) type liquid crystal is used as the liquid crystal. For the pixel on the left side of FIG. 8, the capacitor line SC-A is connected, and Vsc is shifted in the higher voltage direction by ΔVsc. Further, for the pixel on the right side of FIG. 8, the capacitor line SC-B is connected, and Vsc is shifted in the lower direction by ΔVsc.

  As a result, the data signal applied to the pixel electrode is shifted by a voltage corresponding to ΔVsc, and this is applied to VCOM. Here, ΔVsc is set to a voltage corresponding to the threshold voltage Vath at which the change in transmittance according to the applied voltage of the liquid crystal starts, and display by the liquid crystal element 112 is possible by the voltage after the shift. Become. The dynamic range of the data signal is set so that the shifted dynamic range is a potential difference from the black level to the white level in the display.

  In FIG. 8, Va (W) is the shift amount of the white level data signal, Va (B) is the shift amount of the black level data signal, and these shift amounts are determined by ΔVsc. Vb is the potential difference (dynamic range) between the black level and the white level of the data signal, and Vb 'is the dynamic range after the shift.

  In the present embodiment, as described above, overdrive pulses are added to the voltage signals VSCH and VSCL supplied to the capacitance lines SC-A and SC-B. Accordingly, during this overdrive pulse period, the voltage shift amount ΔVSC is increased by the overhead pulse voltage, and a large voltage is applied to the liquid crystal.

It is a block diagram which shows the structure of the signal processing circuit which produces | generates the signal supplied to a liquid crystal panel. It is a figure which shows the waveform of the various signals supplied to a pixel. It is a figure which shows the relationship between an overdrive pulse and a response speed. It is a figure which shows the relationship between an overdrive pulse and a response speed. It is a figure which shows the relationship between a video voltage and a brightness | luminance. It is a figure which shows the relationship between a video voltage and a brightness | luminance. It is a figure which shows schematic structure of a structure of the pixel circuit which provides two capacity | capacitance lines. It is a figure for demonstrating the voltage application state with respect to a liquid crystal.

Explanation of symbols

  10 Video signal processing circuit, 12, 20 D / A conversion circuit, 14, 22 amplifier, 18 level shifter.

Claims (3)

A liquid crystal display device that performs display by enclosing liquid crystal between a first substrate and a second substrate and controlling a voltage of liquid crystal for each pixel arranged in a matrix,
Each pixel is
A storage capacitor to which the video voltage taken from the data line is written;
A pixel electrode connected to the holding capacitor, applied with a voltage held in the holding capacitor, and applying a voltage to the liquid crystal;
Have
A capacitor line is connected to the side opposite to the side connected to the pixel electrode of the storage capacitor, and the voltage applied to the liquid crystal is applied to the capacitor line immediately after the video voltage writing is finished. An overdrive pulse for shifting the voltage of the storage capacitor so as to be larger is applied. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the height of the overdrive pulse is determined according to a video voltage. The liquid crystal display device according to claim 1 or 2,
Two capacitance lines are provided for each row of pixels, and the capacitance of each pixel in the row direction is alternately connected to the two capacitance lines,
The video voltage that reverses the polarity of the applied voltage to the liquid crystal is alternately supplied to the data line of each column,
The voltage supplied to the two capacitor lines is set so that the voltage applied to the corresponding liquid crystal has the opposite polarity in each pixel in the row direction,
The polarity of the overdrive pulse supplied to each capacitor line is set in accordance with the voltage supplied to the capacitor line.