JP2007081266A - Method for repairing semiconductor device - Google Patents

Method for repairing semiconductor device Download PDF

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JP2007081266A
JP2007081266A JP2005269665A JP2005269665A JP2007081266A JP 2007081266 A JP2007081266 A JP 2007081266A JP 2005269665 A JP2005269665 A JP 2005269665A JP 2005269665 A JP2005269665 A JP 2005269665A JP 2007081266 A JP2007081266 A JP 2007081266A
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Prior art keywords
semiconductor device
resin
wiring board
sealing resin
plate
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JP2005269665A
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JP5175431B2 (en
Inventor
Akira Ouchi
明 大内
Asao Murakami
朝夫 村上
Masahiro Kubo
雅洋 久保
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To remove a semiconductor chip resin-sealed by underfill from a wiring board, leaving little resin residue and without damaging the substrate surface. <P>SOLUTION: In the method for repairing a semiconductor device, a separating plate 12 is inserted, while the adhesion strength of sealing resin 9 is made reduced by heating, into a gap between a wiring board 10 and a semiconductor chip 1 (Fig. (b)) to peel off the sealing resin 9 from the wiring board 10, thus removing the semiconductor chip 1 (Fig. (c)). It is desirable that the adhesion strength of the sealing resin 9 be 3.43 N/mm<SP>2</SP>or less when inserting the peeling plate into the gap between the semiconductor device and the wiring board. Further, it is desirable that particles with a multilayer structure having a siloxane framework be added to the sealing resin. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、配線基板上に複数の半導体デバイスがフリップチップ接続により搭載され、それぞれの半導体デバイスがアンダーフィルにより樹脂封止されている半導体装置のリペア方法に関し、不良となった半導体デバイスのみを選択的に除去することができ、半導体デバイス除去時に配線基板上に残る封止樹脂残渣が少なく、かつ短時間でリペアが可能な半導体装置のリペア方法に関する。   The present invention relates to a repair method of a semiconductor device in which a plurality of semiconductor devices are mounted on a wiring board by flip-chip connection, and each semiconductor device is resin-sealed by underfill, and only defective semiconductor devices are selected. The present invention relates to a method for repairing a semiconductor device, which can be removed in an effective manner, has a small amount of sealing resin residue left on a wiring board when a semiconductor device is removed, and can be repaired in a short time.

電子機器の急速な発達に伴い、LSIなどの半導体デバイスにはこれまで以上に高機能化が求められるようになった。半導体デバイスの多機能化に伴い半導体デバイスの入出力端子数は増加し、また半導体デバイスを高速動作させるための配線長は短縮化が求められている。こうした要求を実現するために開発された接続工法としてフリップチップ接続がある。フリップチップ接続は半導体チップの配線面にエリア上に接続パッドを設けることができるため多ピン化に適している。また、ワイヤボンディングやテープオートメイティッドボンディング(TAB)のような他の半導体チップ接続工法と比較し、引き出し線を必要としないため配線長の短縮化が可能である。一般にフリップチップ接続される高機能半導体デバイスの多くは高付加価値のものであり、またこれらの半導体デバイスが搭載される微細配線基板は高多層なものが必要となるため非常に高価であり、実装歩留まりを向上させるための要求は非常に強いものがある。   With the rapid development of electronic equipment, semiconductor devices such as LSIs are required to have higher functionality than ever. As the number of functions of a semiconductor device increases, the number of input / output terminals of the semiconductor device increases, and the wiring length for operating the semiconductor device at high speed is required to be shortened. As a connection method developed to realize such a requirement, there is a flip chip connection. Flip chip connection is suitable for increasing the number of pins because a connection pad can be provided on the wiring surface of the semiconductor chip on the area. Further, compared with other semiconductor chip connection methods such as wire bonding and tape automated bonding (TAB), the lead length is not required, so that the wiring length can be shortened. In general, many of the high-functional semiconductor devices that are flip-chip connected are high-value-added, and the fine wiring board on which these semiconductor devices are mounted is very expensive because it requires a multi-layered substrate. There is a very strong demand for improving the yield.

以上のように高付加価値の電子機器に用いられる半導体デバイスの実装には、フリップチップ接続を使用したものが増加している。一方、フリップチップ接続される半導体デバイスの多くは、半導体デバイス−配線基板間の熱膨張差を緩和するため、接続部に封止樹脂とよばれる液状の封止剤を注入し硬化させることにより接続信頼性を確保する必要がある。この樹脂封止により、耐落下衝撃性、耐熱衝撃性、耐振動性、耐埃性、耐水性を向上させることができる。   As described above, an increasing number of semiconductor devices used in high value-added electronic devices use flip chip connection. On the other hand, many flip-chip connected semiconductor devices are connected by injecting and curing a liquid sealant called sealing resin in the connection part to alleviate the difference in thermal expansion between the semiconductor device and the wiring board. It is necessary to ensure reliability. By this resin sealing, it is possible to improve the drop impact resistance, thermal shock resistance, vibration resistance, dust resistance, and water resistance.

樹脂封止に用いられる材料にはエポキシ樹脂、シリコーン樹脂、フェノール樹脂、ジアリルフタレート樹脂、ポリイミド樹脂、アクリル樹脂、ウレタン樹脂等があるが、耐熱性、耐湿性、耐薬品性、接着性、コスト等の面で優れているエポキシ樹脂が広く使用されている。エポキシ樹脂を含む多くの封止樹脂はその接着強度の高さのため、高い実装信頼性が確保できる反面、一度熱処理を施して樹脂を硬化させてしまうと、その高い樹脂強度、接着強度のため除去することが非常に困難となってしまう。したがって半導体デバイスあるいは配線基板の不良発生時に不良部品を交換することが非常に困難となり、実装コストが高くなるという問題がある。特にハイエンドサーバー、ハイエンドコンピュータ等、高付加価値な装置については、1枚の微細配線基板上に搭載される半導体デバイスが数十個に及ぶこともあり、1個の半導体デバイスの不良によりその他の良品部品全てが廃棄となってしまうことは非常に多額のコスト損失を招くことになる。   Materials used for resin sealing include epoxy resin, silicone resin, phenolic resin, diallyl phthalate resin, polyimide resin, acrylic resin, urethane resin, etc., but heat resistance, moisture resistance, chemical resistance, adhesion, cost, etc. Epoxy resin, which is superior in terms of the above, is widely used. Many sealing resins including epoxy resins have high adhesive strength, so high mounting reliability can be ensured. On the other hand, once the resin is cured by heat treatment, its high resin strength and adhesive strength. It will be very difficult to remove. Therefore, it is very difficult to replace a defective part when a semiconductor device or a wiring board is defective, and there is a problem that the mounting cost is increased. Especially for high-value servers such as high-end servers and high-end computers, several tens of semiconductor devices may be mounted on a single fine wiring board. If all parts are discarded, a very large cost loss is incurred.

半導体デバイスを実装する基板には主にセラミックを用いたものと有機材料を用いたものの2種類がある。高密度実装に用いられる配線基板の多くは、狭ピッチ化に優れ、軽量、低コストであることから有機材料を用いたものである。高密度配線基板の多くはビルドアップと呼ばれる積層構造をとっている(図1参照)。ビルドアップ配線基板はコア層とビルドアップ層の2つの部分からなっている。コア層は配線基板の反りを低減し、実装歩留まりを向上させる構造上の支持体としての役割と、電源層などの配線密度の低い層を受け持つことで高密度配線層を低い密度で使用することを可能ならしめ、配線密度のバランスをとる役割を果たしている。   There are mainly two types of substrates on which semiconductor devices are mounted, those using ceramics and those using organic materials. Many of the wiring boards used for high-density mounting use organic materials because they are excellent in narrowing the pitch, are lightweight, and are low in cost. Many high-density wiring boards have a laminated structure called build-up (see FIG. 1). The build-up wiring board is composed of two parts, a core layer and a build-up layer. The core layer serves as a structural support that reduces the warping of the wiring board and improves the mounting yield, and uses a high-density wiring layer at a low density by taking charge of the low-density wiring layer such as the power supply layer. It plays a role to balance the wiring density.

狭ピッチの配線を描くことのできる点で有利な有機基板材料には、アクリル、ポリオレフィン、ポリウレタン、ポリカーボネート、ポリスチレン、ポリエーテル、ポリアミド、ポリイミド、フッ素を含むポリマー、ポリエステル、フェノール樹脂、フルオレン樹脂、ベンゾシクロブテン、シリコ−ン系ポリマー等様々な材料があるが、コスト、低熱膨張、低誘電損失、耐熱性等の面に優れるエポキシ樹脂が一般に用いられている。また配線基板の最外層には、はんだ流れ防止を目的としてソルダーレジストが塗布されている。このソルダーレジストの多くも基板材料や封止樹脂と同様にエポキシ樹脂であり、現在の有機配線基板の多くはエポキシ樹脂により形成されているといえる。   Organic substrates that are advantageous in that they can draw narrow pitch wiring include acrylic, polyolefin, polyurethane, polycarbonate, polystyrene, polyether, polyamide, polyimide, fluorine-containing polymer, polyester, phenolic resin, fluorene resin, benzoic acid. Although there are various materials such as cyclobutene and silicone-based polymers, epoxy resins that are excellent in terms of cost, low thermal expansion, low dielectric loss, heat resistance and the like are generally used. Also, a solder resist is applied to the outermost layer of the wiring board for the purpose of preventing solder flow. Many of the solder resists are epoxy resins as well as the substrate material and the sealing resin, and it can be said that many of the current organic wiring boards are formed of an epoxy resin.

次に、リペアを可能にする封止樹脂の従来技術について述べる。第1の方法として、封止樹脂に熱可塑性の成分を添加し、高温下にさらすことで樹脂の密着強度、あるいは樹脂強度を低下させ、半導体チップを取り外す工程と、基板上に残された残渣樹脂を高温下における可塑性を利用することにより除去する工程を含むコンセプトが考案されている(例えば、特許文献1〜3参照)。
しかし一般的な熱可塑性成分の添加に関しては、増粘やチキソ性(揺変性)発現による狭ギャップへの充填性の悪化、線膨張係数の増大による接続信頼性低下、耐マイグレーション性の低下等の性能劣化を招く場合が多く、充填性、接続信頼性、リペア性を同時に満足させることは困難である。
Next, the prior art of the sealing resin that enables repair will be described. As a first method, a thermoplastic component is added to the sealing resin, and the adhesion strength of the resin or the resin strength is reduced by exposing to a high temperature to remove the semiconductor chip, and the residue left on the substrate The concept including the process of removing resin by utilizing the plasticity under high temperature is devised (for example, refer patent documents 1-3).
However, with regard to the addition of general thermoplastic components, such as deterioration of filling properties in narrow gaps due to thickening and thixotropy (thixotropy) expression, reduced connection reliability due to increased linear expansion coefficient, reduced migration resistance, etc. In many cases, the performance is deteriorated, and it is difficult to satisfy the filling property, the connection reliability, and the repair property at the same time.

その他の取り外し方法として、有機溶剤を用い、封止樹脂を膨潤させることで封止樹脂と配線基板の間の密着強度、樹脂強度を低下させ、半導体チップの取り外し、残渣樹脂の除去を行う方法が考案されている(例えば、特許文献2、4、5参照)。しかし現在用いられている封止樹脂および配線基板の多くは共にエポキシ樹脂であるため、樹脂残渣除去用の溶剤が封止樹脂のみでなく配線基板も膨潤させ、ビルドアップ基板の層間剥離を起こす恐れがある。さらに配線基板表面の状態が樹脂残渣除去用の溶剤により変化し、配線基板を再利用する際に封止樹脂の再充填性を悪化させる恐れがある。以上のように溶剤を用いた場合に配線基板に影響を与えずに封止樹脂のみを選択的に除去することは一般的には困難である。   Other removal methods include using an organic solvent and swelling the sealing resin to reduce the adhesion strength between the sealing resin and the wiring board, the resin strength, removing the semiconductor chip, and removing the residual resin. It has been devised (for example, see Patent Documents 2, 4, and 5). However, since many of the sealing resins and wiring boards that are currently used are epoxy resins, the solvent for removing resin residues can swell not only the sealing resin but also the wiring board, causing delamination of the build-up board There is. Furthermore, the state of the surface of the wiring board changes depending on the solvent for removing the resin residue, and there is a possibility that the refillability of the sealing resin is deteriorated when the wiring board is reused. As described above, when the solvent is used, it is generally difficult to selectively remove only the sealing resin without affecting the wiring board.

上記のような懸念から不良発生時に備えて、実装形態自体を再利用可能な構造とする方法も考案されている。この例として、半導体チップ実装時にインターポーザ構造を取り、不良発生時にははんだリフローによってインターポーザごと取り外してしまう方法が考案されている(例えば、特許文献6参照)。
しかし、インターポーザを用いた実装方法は、配線長が長くなるため一般的には信号の高速伝搬に不利であり、またインピーダンス整合をとるのが困難であるという欠点がある。また、インタポーザ構造をとることで実装面積、実装高さが増大し、小型化、高密度化との両立ができないという欠点がある。以上のようにインターポーザ構造をとることによる半導体デバイスのリペアは根本的な問題解決の手段としては不十分である。
溶剤を必要としない封止樹脂除去方法として、樹脂残渣に電磁波を照射することにより樹脂残渣を除去する方法(例えば、特許文献7参照)、レーザ光が透過する配線基板を実装時に用い、半導体チップの実装されている裏面からレーザ光を照射し、封止樹脂の密着力を弱める方法(例えば、特許文献8参照)等が考案されている。
しかし、現在用いられている封止樹脂および配線基板の基板材料の多くは共にエポキシ樹脂であるため、封止樹脂のみを選択的に加工することは難しく、また封止樹脂除去を可能にする程度の強度でレーザ光照射を行うと、配線基板の損傷および配線基板表面状態の変化により配線基板再利用時の封止樹脂再充填性を悪化させる恐れがある。また現在使用されている配線基板の多くはレーザ透過性を持っておらず、特許文献9の方法による問題解決は困難である。以上のように非接触のエネルギーを用いた方法による封止樹脂のみの選択的加工は困難である。
特開2000−323193号公報 特開平11−274376号公報 特開平9−221650号公報 特開平10−67916号公報 特開平7−102225号公報 特開平4−124845号公報 特開平6−77264号公報 特開平4−257240号公報
In view of the above concerns, a method of making the mounting form itself reusable structure has been devised in preparation for occurrence of defects. As an example of this, a method has been devised in which an interposer structure is taken when a semiconductor chip is mounted and the interposer is removed by solder reflow when a defect occurs (for example, see Patent Document 6).
However, the mounting method using an interposer is generally disadvantageous for high-speed signal propagation because of the long wiring length, and has a drawback that it is difficult to achieve impedance matching. In addition, the interposer structure increases the mounting area and mounting height, and there is a disadvantage that it is impossible to achieve both miniaturization and high density. As described above, the repair of the semiconductor device by adopting the interposer structure is not sufficient as a fundamental problem solving means.
As a sealing resin removing method that does not require a solvent, a method of removing a resin residue by irradiating the resin residue with an electromagnetic wave (see, for example, Patent Document 7), a wiring board that transmits laser light is used for mounting, and a semiconductor chip. Has been devised, such as a method of irradiating laser light from the back surface where the sealing resin is mounted to weaken the adhesion of the sealing resin (see, for example, Patent Document 8).
However, since most of the sealing resin currently used and the substrate material of the wiring board are both epoxy resin, it is difficult to selectively process only the sealing resin, and it is possible to remove the sealing resin. When the laser beam is irradiated with the intensity of 1, the sealing resin refillability at the time of reuse of the wiring board may be deteriorated due to the damage of the wiring board and the change of the wiring board surface state. Also, many of the wiring boards currently used do not have laser transparency, and it is difficult to solve the problem by the method of Patent Document 9. As described above, it is difficult to selectively process only the sealing resin by a method using non-contact energy.
JP 2000-323193 A Japanese Patent Laid-Open No. 11-274376 Japanese Patent Laid-Open No. 9-221650 Japanese Patent Laid-Open No. 10-67916 JP-A-7-102225 Japanese Patent Laid-Open No. 4-124845 JP-A-6-77264 JP-A-4-257240

以上述べたように、従来技術では配線基板に損傷を与えることなく半導体デバイスならびに封止樹脂を選択的に除去し、充填性、接続信頼性、リペア性のいずれをも同時に満足させることはできない。また、樹脂封止された半導体デバイスのリペアを困難にしている大きな原因の一つにリペア部品除去後に基板等の再生したい面に残った樹脂組成物を取り除くクリーニング工程での課題が挙げられる。一つ目の課題は、クリーニング作業中に再生面である基板表面を損傷してしまって再利用ができなくなることである。2つ目の課題は、たとえ再生面をきれいにできた場合でも、クリーニング時に生じた樹脂組成物の微細なカスが再生面の電極部に入り込んでしまい、部品再実装の際に電極部に入り込んだ樹脂組成物のカスの影響で接続不良を起こしてしまう問題である。3つ目の課題はクリーニング工程に多大な時間を要することである。樹脂組成物の除去についても、再生面を損傷しないように注意深い作業が要求されることは勿論であるが、前記の微細な電極部に入り込んだ樹脂組成物のカスを取り除く必要が生じた場合は、数多くの電極についてそれぞれ除去作業を実施する必要があり、その手間は莫大なものとなる。   As described above, according to the prior art, the semiconductor device and the sealing resin are selectively removed without damaging the wiring board, and none of the filling property, connection reliability, and repair property can be satisfied at the same time. Further, one of the major causes that makes it difficult to repair a resin-encapsulated semiconductor device is a problem in a cleaning process of removing a resin composition remaining on a surface to be regenerated such as a substrate after removing a repair component. The first problem is that the substrate surface which is the reproduction surface is damaged during the cleaning operation and cannot be reused. The second problem is that even if the reproduction surface can be cleaned, the fine residue of the resin composition generated during cleaning enters the electrode portion of the reproduction surface and enters the electrode portion during component remounting. This is a problem that causes poor connection due to the residue of the resin composition. The third problem is that the cleaning process takes a lot of time. As for the removal of the resin composition, it is a matter of course that careful work is required so as not to damage the reproduction surface, but when it is necessary to remove the residue of the resin composition that has entered the fine electrode portion. Therefore, it is necessary to carry out the removal work for each of the many electrodes, and the effort is enormous.

本発明の課題は、上述した従来技術の問題点を解決することであって、その目的は、リペアしたい半導体デバイスを除去する際、半導体デバイスや配線基板を損傷することなく、リペアしたい箇所の樹脂組成物の大部分を再利用する基板等の界面から剥離させることで樹脂残りを最小限に抑え、クリーニング工程を簡単確実に行うことが可能となるリペア方法を提供することである。さらに複数の半導体デバイスが隣接して実装された場合においても、リペアしたいデバイスのみを確実に除去可能なリペア方法を提供することである。   An object of the present invention is to solve the above-described problems of the prior art, and the purpose thereof is to remove a resin to be repaired without damaging the semiconductor device or the wiring board when removing the semiconductor device to be repaired. It is an object of the present invention to provide a repair method in which most of the composition is peeled off from the interface of a reused substrate or the like to minimize the resin residue, and the cleaning process can be performed easily and reliably. It is another object of the present invention to provide a repair method capable of reliably removing only a device to be repaired even when a plurality of semiconductor devices are mounted adjacent to each other.

上記の目的を達成するため、本発明によれば、配線基板に1ないし複数の半導体デバイスが、配線基板上の基板側パッドに半導体デバイスのパッドが導電性バンプを介して接続される態様にて、実装され、前記半導体デバイスと前記配線基板との隙間が封止樹脂により充填されている半導体装置のリペア方法であって、少なくともリペア対象の半導体デバイスを加熱して封止樹脂の密着強度を低下させ、前記半導体デバイスと前記配線基板との隙間より薄いプレートを前記半導体デバイスと前記配線基板との隙間に挿入することにより、前記半導体デバイスを前記配線基板から分離することを特徴とする半導体装置のリペア方法、が提供される。   In order to achieve the above object, according to the present invention, one or more semiconductor devices are connected to a wiring board, and pads of the semiconductor device are connected to substrate-side pads on the wiring board via conductive bumps. A method for repairing a semiconductor device, wherein a gap between the semiconductor device and the wiring board is filled with a sealing resin, and at least the semiconductor device to be repaired is heated to reduce the adhesion strength of the sealing resin And the semiconductor device is separated from the wiring board by inserting a plate thinner than the gap between the semiconductor device and the wiring board into the gap between the semiconductor device and the wiring board. A repair method is provided.

そして、好ましくは、封止樹脂にはシロキサン骨格を有する多層構造の粒子が添加される。あるいは封止樹脂にはコア部がシエル部よりも硬度が低い多層構造の粒子が添加される。また、好ましくは、多層構造の粒子のコア部が線状ポリマーによって構成され、シエル部が3次元ポリマーによって構成される。あるいは多層構造の粒子のコア部がシリコーンゴムであり、シエル部がシリコーンレジンである。更に、好ましくは、プレートを半導体デバイスと配線基板との隙間に挿入する際の封止樹脂の密着強度は3.43N/mm(350gf/mm)以下である。 Preferably, particles having a multilayer structure having a siloxane skeleton are added to the sealing resin. Or the particle | grains of a multilayer structure whose core part has lower hardness than a shell part are added to sealing resin. Preferably, the core portion of the multi-layered particle is composed of a linear polymer, and the shell portion is composed of a three-dimensional polymer. Or the core part of the particle | grains of a multilayer structure is a silicone rubber, and a shell part is a silicone resin. Further, preferably, the adhesion strength of sealing resin at the time of inserting the plate into the gap between the semiconductor device and the wiring board is less than 3.43N / mm 2 (350gf / mm 2).

加熱されて密着強度が低下した封止樹脂では、金属製などの剥離用プレートを挿入することが可能になり、これにより封止樹脂の配線基板からの剥離が可能となり樹脂封止された半導体デバイスを容易に配線基板から分離することが可能になる。また、配線基板上での樹脂残渣を少なくすることができる。そして、エポキシ樹脂を主体とする封止樹脂に多層シロキサン骨格を有する粒子を添加した封止樹脂を使用することにより、加熱により容易に封止樹脂の密着強度を低下させることが可能になり、プレ−トを使用した半導体デバイスの除去作業時に封止樹脂は基板面より容易に剥離されるようになり、半導体デバイスの分離後に基板上の再生したい面に残存する樹脂成分をほとんど無くすことが可能になる。したがって、半導体デバイス除去に続く基板面のクリーニングが容易になり、基板面の再生を確実にすることができ、リペア作業を短時間で簡単にかつ確実に行なうことが可能になる。   With a sealing resin whose adhesion strength has been reduced by heating, it becomes possible to insert a metal-made peeling plate, which enables the sealing resin to be peeled from the wiring board, and a resin-sealed semiconductor device Can be easily separated from the wiring board. Moreover, the resin residue on a wiring board can be decreased. Further, by using a sealing resin in which particles having a multilayer siloxane skeleton are added to a sealing resin mainly composed of an epoxy resin, it becomes possible to easily reduce the adhesion strength of the sealing resin by heating. -The sealing resin can be easily peeled off from the substrate surface when removing the semiconductor device using the substrate, making it possible to eliminate almost any resin component remaining on the surface to be regenerated on the substrate after separation of the semiconductor device. Become. Therefore, the cleaning of the substrate surface following the removal of the semiconductor device is facilitated, the regeneration of the substrate surface can be ensured, and the repair operation can be performed easily and reliably in a short time.

図1に、本発明のリペア方法を実施する半導体装置の一例として、LSIなどの複数の半導体デバイスを1枚のビルドアップ配線基板にフリップチップ実装したモジュール(MCM)の例を示す(但し、図1にはフリップチップ実装された半導体チップの内一個のみを示す)。ビルドアップ配線基板3には、感光性樹脂層、プリプレグ硬化層等からなる絶縁層4が1ないし複数層(図示した例では2層)形成されており、絶縁層4上には配線5が形成されている。ビルドアップ配線基板3の表面にはソルダーレジスト7が形成されており、最上層の配線5のソルダーレジスト7に被覆されない領域は、基板側パッド6となっている。半導体チップ1にはチップ側パッド2が形成されており、チップ側パッド2と基板側パッド6とははんだバンプ8により電気的に接続されている。そして、半導体チップ1とビルドアップ配線基板3の隙間には、封止樹脂9が充填されている。図1には、半導体デバイスとしてフリップチップが示されているが、本発明においてリペアの対象となる半導体デバイスは、フリップチップに限定されず、配線基板上に導電性バンプを介して接続されるデバイスであれば、ベアチップ、CSP(chip size package)、BGA(ball grid array)等でいずれであってもよい。
半導体チップなどのデバイスとビルドアップ配線基板の間の電気接続を取る材料ははんだ材料のみに限るものではなく、導電性を有する材料であれば特に限定されない。例えば導電粒子を分散させた導電性樹脂による接続、あるいは金バンプの導電性塗料ないしはんだによる接続等であってもよい。なお、本明細書においてバンプとは、はんだボールのような導電性ボールをも含むものである。
ビルドアップ配線基板の表面を覆っているソルダーレジスト、コア材等の配線基板を構成している有機ならびに無機材料については、金属配線、接続パッド等に対し、腐食性等の悪影響を及ぼさない材料を選択する必要があり、また半導体デバイスのリペア工程に耐える耐熱性を有することが望ましい。例えば一般的に使用される鉛フリーはんだのリフロー温度250℃のプロセスにおいて、配線基板、半導体デバイス、電子部品等に対して悪影響を及ぼさないものが望ましい。
FIG. 1 shows an example of a module (MCM) in which a plurality of semiconductor devices such as LSIs are flip-chip mounted on one build-up wiring board as an example of a semiconductor device that implements the repair method of the present invention (however, FIG. 1 shows only one of the flip-chip mounted semiconductor chips). The build-up wiring board 3 has one or more insulating layers 4 (two layers in the illustrated example) formed of a photosensitive resin layer, a prepreg cured layer, etc., and the wiring 5 is formed on the insulating layer 4. Has been. A solder resist 7 is formed on the surface of the build-up wiring board 3, and a region of the uppermost wiring 5 that is not covered with the solder resist 7 is a board-side pad 6. A chip-side pad 2 is formed on the semiconductor chip 1, and the chip-side pad 2 and the substrate-side pad 6 are electrically connected by solder bumps 8. A gap between the semiconductor chip 1 and the buildup wiring board 3 is filled with a sealing resin 9. FIG. 1 shows a flip chip as a semiconductor device. However, the semiconductor device to be repaired in the present invention is not limited to a flip chip, and is a device connected to a wiring substrate via a conductive bump. If so, any of a bare chip, a CSP (chip size package), a BGA (ball grid array), etc. may be used.
The material that establishes electrical connection between a device such as a semiconductor chip and the buildup wiring board is not limited to a solder material, and is not particularly limited as long as it is a conductive material. For example, it may be a connection using a conductive resin in which conductive particles are dispersed, or a connection of a gold bump using a conductive paint or solder. In the present specification, the bump includes a conductive ball such as a solder ball.
For the organic and inorganic materials that make up the wiring board such as solder resist and core material that cover the surface of the build-up wiring board, use materials that do not adversely affect the metal wiring, connection pads, etc. It is necessary to select it, and it is desirable to have heat resistance that can withstand the repair process of the semiconductor device. For example, in a generally used process of lead-free solder having a reflow temperature of 250 ° C., it is desirable to have no adverse effect on a wiring board, a semiconductor device, an electronic component, or the like.

封止樹脂の基材となる材料には、アクリル樹脂、メラミン樹脂、エポキシ樹脂、ポリオレフィン樹脂、ポリウレタン樹脂、ポリカーボネート樹脂、ポリスチレン樹脂、ポリエーテル樹脂、ポリアミド樹脂、ポリイミド樹脂、フッ素樹脂、ポリエステル樹脂、フェノール樹脂、フルオレン樹脂、ベンゾシクロブテン樹脂、シリコーン樹脂等様々な材料があるが、特に限定されるものではなく、これらを1種あるいは2種以上組み合わせて用いることもできる。粘度、コスト、耐熱性等の面に優れるエポキシ樹脂が一般に用いられるが、25℃の室温において液状である樹脂が望ましい。   The base material of the sealing resin includes acrylic resin, melamine resin, epoxy resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluororesin, polyester resin, phenol There are various materials such as a resin, a fluorene resin, a benzocyclobutene resin, and a silicone resin, but there is no particular limitation, and these can be used alone or in combination of two or more. Epoxy resins that are excellent in terms of viscosity, cost, heat resistance, and the like are generally used, but resins that are liquid at room temperature of 25 ° C. are desirable.

半導体デバイスを取り外すための加熱温度(以下、リペア温度)での封止樹脂の密着性を低下させるための手段の1例として、封止樹脂にシロキサン骨格を有する多層粒子を添加することが有効であるが、多層粒子についてさらに詳細に説明すると、コア部分の硬度がシエル部分の硬度よりも低くなるように設計されている。たとえば2層の粒子を用いる場合、好適なコア部の硬度は75未満であり(スプリング式硬さ計JIS-A形JISK6301)、シエル部の硬度は75以上であるが、より好適にはコア部の硬度を40以下に設定することが望ましい。コア部の硬度を小さく設計した場合、低弾性化の効果が大きくなる。この効果により、リペア温度における樹脂密着性を低下させることができる。
封止樹脂に添加するシロキサン骨格を有する多層粒子は、コア部の体積比率がシエル部分の体積比率よりも高い構造となっている。具体的にはコア部の体積比率がシエル部の体積比率の1.5倍以上、より好ましくは2倍以上大きい場合に、低弾性化効果と線膨張を抑える効果がより強く現れる。
封止樹脂に添加するシロキサン骨格を有する多層粒子は、シエル部のガラス転移温度がコア部のガラス転移温度よりも高い構造となっている。具体例の一つとしてコア部のガラス転移温度が−80℃、封止樹脂母材が110℃、シエル部のガラス転移温度が260℃の構成で用いた場合、封止樹脂充填時の増粘がなく、また180℃を超えるリペア温度域において配線基板に損傷を与えることなく封止樹脂のクリーニングができた。現行のLSIチップの動作温度105℃を想定した場合の信頼性への影響、リペア時の作業性から、コア部のガラス転移温度は100℃未満かつシエル部のガラス転移温度が125℃以上であることが望ましい。コア部分のガラス転移温度点がこれ以上に高い場合にはリペア性が損なわれる傾向が強く、またシエル部分のこれ以上のガラス転移温度低下は半導体デバイスの熱サイクル試験に用いられる温度上限を下回るからである。こうした設計により、リペア性と信頼性の両立が実現できる。
As an example of means for reducing the adhesion of the sealing resin at a heating temperature (hereinafter referred to as a repair temperature) for removing the semiconductor device, it is effective to add multilayer particles having a siloxane skeleton to the sealing resin. However, the multilayer particles will be described in more detail. The hardness of the core portion is designed to be lower than the hardness of the shell portion. For example, when two layers of particles are used, the preferred core has a hardness of less than 75 (spring type hardness tester JIS-A type JISK6301) and the shell has a hardness of 75 or more, more preferably the core It is desirable to set the hardness to 40 or less. When the hardness of the core part is designed to be small, the effect of reducing elasticity becomes large. This effect can reduce the resin adhesion at the repair temperature.
The multilayer particles having a siloxane skeleton added to the sealing resin have a structure in which the volume ratio of the core portion is higher than the volume ratio of the shell portion. Specifically, when the volume ratio of the core part is 1.5 times or more, more preferably 2 times or more larger than the volume ratio of the shell part, the effect of reducing the elasticity and suppressing the linear expansion appears more strongly.
The multilayer particle having a siloxane skeleton added to the sealing resin has a structure in which the glass transition temperature of the shell portion is higher than the glass transition temperature of the core portion. As one specific example, when the glass transition temperature of the core part is −80 ° C., the sealing resin base material is 110 ° C., and the glass transition temperature of the shell part is 260 ° C., the viscosity increases when the sealing resin is filled. In addition, the sealing resin could be cleaned without damaging the wiring board in a repair temperature range exceeding 180 ° C. The glass transition temperature of the core portion is less than 100 ° C. and the glass transition temperature of the shell portion is 125 ° C. or higher due to the influence on reliability when the operating temperature of the current LSI chip is assumed to be 105 ° C. and workability during repair. It is desirable. When the glass transition temperature point of the core part is higher than this, the repair property tends to be impaired, and the further glass transition temperature decrease of the shell part is lower than the upper temperature limit used for the thermal cycle test of the semiconductor device. It is. This design makes it possible to achieve both repairability and reliability.

封止樹脂に加えるシロキサン骨格を有する多層粒子は球状であることが望ましく、添加量としては1〜30vol%程度が望ましい。より好ましくは15〜25vol%程度の添加が望ましい。球状以外の粒子添加は増粘等傾向が強く、またこれ以上の添加は粘度増加、チキソ性発現による充填性の悪化が見られる場合が多いため、半導体デバイスと配線基板の間の狭ギャップに対する充填性を損なうことになる。
封止樹脂に添加されるシロキサン骨格を有する多層粒子の平均粒子径は、充填される半導体デバイス−配線基板間ギャップの1/10以下のサイズのものが好適であり、平均粒径が0.1〜30μm程度の範囲にあることが望ましい。また、シリコーン粒子の粒径、硬度等のパラメータにより低線膨張化に与える効果は異なる。たとえば同種のシリコーン原料を用いてシロキサン骨格を有する多層粒子を形成し、平均粒径0.5μmの粒度分布を有する粒子、平均粒径3μmの粒度分布を有する粒子、平均粒径5μmの粒度分布を有する粒子を封止樹脂に添加した場合の線膨張係数に与える影響においては、粒子径5μmのものに、より強く線膨張係数の増大を抑える効果が見られた。
The multilayer particles having a siloxane skeleton added to the sealing resin are preferably spherical, and the addition amount is preferably about 1 to 30 vol%. More preferably, addition of about 15 to 25 vol% is desirable. Addition of particles other than spheres has a strong tendency to increase viscosity, and addition of more than this often increases viscosity and deteriorates filling properties due to thixotropy, so filling for narrow gaps between semiconductor devices and wiring boards It will damage the sex.
The average particle diameter of the multilayer particles having a siloxane skeleton added to the sealing resin is preferably 1/10 or less of the gap between the semiconductor device and the wiring board to be filled, and the average particle diameter is 0.1. It is desirable to be in the range of about 30 μm. Further, the effect on the low linear expansion varies depending on parameters such as the particle size and hardness of the silicone particles. For example, the same kind of silicone raw material is used to form multilayer particles having a siloxane skeleton, particles having an average particle size of 0.5 μm, particles having an average particle size of 3 μm, particles having an average particle size of 5 μm. In the influence exerted on the linear expansion coefficient when the particles having the additive are added to the sealing resin, the effect of suppressing the increase in the linear expansion coefficient more strongly was observed with the particle diameter of 5 μm.

封止樹脂に添加される無機フィラーにはシリカ、炭酸カルシウム、アルミナ、ジルコニウム、酸化チタン等様々な材料が用いられるが、コスト、真球度、低線膨張化等のメリットが最も顕著なシリカを用いることが多い。添加するシリカの平均粒子径は充填される半導体デバイス−配線基板間ギャップの1/10以下のサイズのものが好適であり、平均粒径が0.1〜30μm程度の範囲にあることが望ましい。また、これらの無機添加剤の表面には封止樹脂との濡れ性を改善し、充填性を高めるためにカップリング剤を用いてもよい。カップリング剤はシラン系、チタネート系、アルミネート系、ジルコアルミネート系、クロメート系、ボレート系、スタネート系、イソシアネート系等といった共有結合性タイプのものや、β−ジケトンカプラーのように配位結合性のものなど各種用いることができる。   Various materials such as silica, calcium carbonate, alumina, zirconium and titanium oxide are used for the inorganic filler added to the sealing resin, but silica with the most remarkable advantages such as cost, sphericity and low linear expansion is used. Often used. The average particle diameter of the silica to be added is preferably 1/10 or less of the gap between the semiconductor device and the wiring board to be filled, and the average particle diameter is preferably in the range of about 0.1 to 30 μm. Further, a coupling agent may be used on the surface of these inorganic additives in order to improve the wettability with the sealing resin and enhance the filling property. Coupling agents include silane, titanate, aluminate, zircoaluminate, chromate, borate, stunate, isocyanate, and other types of covalent bonds, and coordinate bonds such as β-diketone couplers. Various types can be used.

以上に述べた手法により、リペア温度での密着強度を低下させた樹脂を用いて封止された半導体デバイスをリペアする際のプロセス例について、図2を参照して説明する。図2(a)に示される配線基板10上に搭載された半導体チップ1を取り外すものとする。配線基板10の表面には、ソルダーレジスト7に区画されて基板側パッド6が形成されており、この基板側パッド6には、半導体チップ1に形成されたチップ側パッド2がはんだバンプ8により電気的に接続されており、そして配線基板10と半導体チップ1の隙間には封止樹脂9が充填されている。取り外しのために、まず、半導体チップ1をホットプレート(図示せず)等によりリペア温度まで加熱する。リペア温度については、はんだバンプのように金属結合している場合は、バンプが溶融する融点温度以上まで加熱する必要がある。一例を示すと、共晶はんだであれば、183℃以上、鉛フリ−はんだ(Sn−3Ag−0.5Cu)では220℃以上となるが、実際には全てのはんだバンプが確実に溶融している必要があるので、融点温度より、20℃以上高めに設定することが望ましく、その際の封止樹脂の密着強度は、350gf/mm(3.43N/mm)以下、より好ましくは345gf/mm(3.38N/mm)以下であることが望ましい。また、バンプ自体が金属結合等で一体になっているわけではなく、封止樹脂の接着力等により単に接触している場合においては、封止樹脂の密着強度が350gf/mm以下となる温度に設定すればよい。さらに導電性接着剤等をバンプとして使用している場合は、導電性樹脂バンプの密着強度および封止樹脂の密着強度が共に350gf/mm以下となる温度でリペアすることが望ましい。封止樹脂の密着強度が350gf/mm以上の場合で、350gf/mmより十分大きい場合は、半導体チップ除去時に基板を損傷する。350gf/mmよりわずかに大きい場合は、半導体チップの除去は成功するが、封止樹脂が再生したい基板表面の電極部付近にも残るため、この樹脂を後のクリーニング工程で除去しようとした場合、基板損傷が生じたり電極部に樹脂のカスが入り込むことによる再実装工程での接続不良が発生する可能性が高くなる。ここで、半導体チップを配線基板より除去する際に必要な図3に示す剥離用プレート12を準備する。図3(a)は剥離用プレート12の平面図、図3(b)はそのA−A線での断面図である。剥離用プレートの材質は、リペア温度で封止樹脂よりも十分に強いことが望ましく、一例としてはSUS等の金属が挙げられるがこれに限定されるものではない。剥離用プレート12の幅Wは、リペアする半導体チップの幅と同程度であることが目安となるが、隣接部品がない場合は半導体チップよりやや大きめの幅とし、隣接部品がある場合は半導体チップよりやや小さめの幅とすることが望ましい。剥離用プレートの厚さtについては、半導体チップと配線基板の隙間に挿入する関係上、半導体チップと配線基板の隙間より薄いことが必要である。剥離用プレートの長さLは半導体チップの長さよりも長くし、半導体チップの末端まで剥離用プレートを挿入できるようにすることが望ましい。剥離用プレート12の先端のコーナ部12aの形状は直角でもよいが、基板表面の状態等によっては剥離用プレート挿入中にプレートコーナ部にて基板表面を傷つける可能性があるため、丸みのある形状に加工しておくことが望ましい。 An example of a process for repairing a semiconductor device sealed with a resin whose adhesion strength at the repair temperature is reduced by the method described above will be described with reference to FIG. Assume that the semiconductor chip 1 mounted on the wiring substrate 10 shown in FIG. A substrate-side pad 6 is formed on the surface of the wiring substrate 10 by being partitioned by a solder resist 7. The chip-side pad 2 formed on the semiconductor chip 1 is electrically connected to the substrate-side pad 6 by solder bumps 8. The gap between the wiring substrate 10 and the semiconductor chip 1 is filled with a sealing resin 9. For removal, the semiconductor chip 1 is first heated to a repair temperature by a hot plate (not shown) or the like. As for the repair temperature, when metal bonding is performed like a solder bump, it is necessary to heat to a melting point temperature or higher at which the bump melts. For example, if it is eutectic solder, it will be 183 ° C or higher, and lead-free solder (Sn-3Ag-0.5Cu) will be 220 ° C or higher. Therefore, it is desirable to set it 20 ° C. or more higher than the melting point temperature, and the adhesion strength of the sealing resin at that time is 350 gf / mm 2 (3.43 N / mm 2 ) or less, more preferably 345 gf. / Mm 2 (3.38 N / mm 2 ) or less. In addition, the bump itself is not integrally formed by metal bonding or the like, and when the bump resin is simply in contact with the adhesive force of the sealing resin, the temperature at which the adhesion strength of the sealing resin is 350 gf / mm 2 or less. Should be set. Further, when a conductive adhesive or the like is used as a bump, it is desirable to repair at a temperature at which the adhesion strength of the conductive resin bump and the adhesion strength of the sealing resin are both 350 gf / mm 2 or less. When the adhesion strength of the sealing resin is 350 gf / mm 2 or more and is sufficiently larger than 350 gf / mm 2 , the substrate is damaged when the semiconductor chip is removed. If it is slightly larger than 350 gf / mm 2 , the removal of the semiconductor chip is successful, but the sealing resin remains in the vicinity of the electrode part on the surface of the substrate to be regenerated. In addition, there is a high possibility that a connection failure occurs in the re-mounting process due to substrate damage or resin residue entering the electrode portion. Here, the peeling plate 12 shown in FIG. 3 required for removing the semiconductor chip from the wiring board is prepared. 3A is a plan view of the peeling plate 12, and FIG. 3B is a cross-sectional view taken along the line AA. The material of the peeling plate is preferably sufficiently stronger than the sealing resin at the repair temperature, and examples thereof include metals such as SUS, but are not limited thereto. The width W of the peeling plate 12 is approximately the same as the width of the semiconductor chip to be repaired. However, if there is no adjacent component, the width W is slightly larger than the semiconductor chip, and if there is an adjacent component, the semiconductor chip A slightly smaller width is desirable. The thickness t of the peeling plate needs to be thinner than the gap between the semiconductor chip and the wiring board because of being inserted into the gap between the semiconductor chip and the wiring board. It is desirable that the length L of the peeling plate is longer than the length of the semiconductor chip so that the peeling plate can be inserted to the end of the semiconductor chip. The shape of the corner portion 12a at the tip of the peeling plate 12 may be a right angle, but depending on the state of the substrate surface, etc., the substrate surface may be damaged at the plate corner portion during insertion of the peeling plate. It is desirable to process it.

次に、図2(b)に示すように、半導体チップ1と配線基板10の隙間を封止している樹脂の側面に対して、配線基板表面に沿って剥離用プレート12を挿入していく。挿入直後は、側面外周の封止樹脂を破壊することとなるが、さらに少しずつ剥離用プレートを挿入するとすぐに樹脂が破壊された際に生じた樹脂クラックは封止樹脂9と基板の界面剥離に進展するため、その後は剥離プレート12先端を利用してさらに界面剥離を進行させ、最終的には剥離用プレート先端を挿入辺の反対側の辺まで到達させることにより、リペアしたい半導体チップを配線基板から除去することができる。
この際、図2(c)に示すように、配線基板上には半導体チップの搭載エリア外周にわずかに樹脂残渣13が残るが、基板表面の他の部分には樹脂の残渣なく、表面から封止樹脂をきれいに剥離することができる。このとき、基板側パッド6上には残留はんだ14が薄く残る。
最後に、図2(d)に示すように、半導体チップの搭載エリア外周にわずかに残った樹脂をクリーニングにより除去するが、その方法の一例として、常温にてDMF(ジメチルホルムアミド)等の溶剤を用いながら、綿棒等でこすり落とすことにより、基板上に残った樹脂を完全に除去することができる。この状態で半導体チップの再搭載が可能となるが、基板側パッドを含めた基板表面は、DMF(ジメチルホルムアミド)アルコール等で表面をふき取ると微細な汚れ等が落ち、安定した再実装を行うために効果的である。
Next, as shown in FIG. 2B, a peeling plate 12 is inserted along the surface of the wiring board into the side surface of the resin sealing the gap between the semiconductor chip 1 and the wiring board 10. . Immediately after the insertion, the sealing resin on the outer periphery of the side surface is destroyed. However, when the peeling plate is inserted little by little, the resin crack generated when the resin is destroyed is the interface peeling between the sealing resin 9 and the substrate. Then, the interface peeling is further advanced using the tip of the peeling plate 12, and finally the tip of the peeling plate reaches the side opposite to the insertion side, thereby wiring the semiconductor chip to be repaired. It can be removed from the substrate.
At this time, as shown in FIG. 2C, the resin residue 13 remains slightly on the periphery of the mounting area of the semiconductor chip on the wiring board, but there is no resin residue on the other part of the substrate surface and the resin chip 13 is sealed from the surface. Stop resin can be peeled cleanly. At this time, the residual solder 14 remains thin on the board-side pad 6.
Finally, as shown in FIG. 2D, the resin slightly remaining on the outer periphery of the mounting area of the semiconductor chip is removed by cleaning. As an example of the method, a solvent such as DMF (dimethylformamide) is used at room temperature. While being used, the resin remaining on the substrate can be completely removed by scraping with a cotton swab or the like. In this state, the semiconductor chip can be remounted. However, if the surface of the substrate including the pad on the substrate side is wiped off with DMF (dimethylformamide) alcohol or the like, fine dirt is removed and stable remounting is performed. It is effective.

なお、剥離用プレートを挿入する際、挿入開始時は封止樹脂表面を破壊し、樹脂内部へプレート先端を侵入させる必要があるため、プレート先端は鋭利な形状で材質は金属製である方が作業性がよいが樹脂と基板界面の剥離が発生した後は、場合によっては基板表面の凹凸等のある個所で基板を傷つける可能性があるので、図3(b)に示すように、剥離用プレート12の先端部12bは丸く加工しておくことが望ましく、またプレートの材質も可能な限りやわらかい方がよい。そこで挿入開始時はプレート先端が鋭利なものを使用し、樹脂表面を破壊した後は剥離用プレートを交換し、先端が丸く材質も基板材質と同等のものを使用すると効果的である。また、金属プレートの先端部に耐熱性のある樹脂、例えばポリイミド等のコーティングやテープを貼る等も基板表面の保護に効果がある。   In addition, when inserting the peeling plate, it is necessary to destroy the sealing resin surface at the start of insertion and allow the plate tip to penetrate into the resin, so the plate tip should be sharp and made of metal. Although workability is good, after peeling of the interface between the resin and the substrate occurs, there is a possibility that the substrate may be damaged in some places with irregularities on the surface of the substrate. As shown in FIG. It is desirable that the end portion 12b of the plate 12 be rounded, and the material of the plate should be as soft as possible. Therefore, it is effective to use a plate with a sharp tip at the start of insertion, replace the peeling plate after destroying the resin surface, and use a material with a round tip and the same material as the substrate material. In addition, applying a heat-resistant resin such as polyimide coating or tape to the tip of the metal plate is also effective for protecting the substrate surface.

次に、複数の半導体チップが搭載された基板で不良の半導体チップのみをリペアしたい場合の方法について述べる。全体を加熱ながらリペアしたい半導体チップのみを除去してもよいが、部品の耐熱性等の問題で必要以上に加熱したくない場合、リペアしたい半導体チップのみを局部加熱することが有効である。例えば、図4に示すように、リペア対象の半導体チップ11にのみエアノズル15よりホットエア16を噴射して、局部加熱を行う。この方法により、リペアしたい半導体チップが所定の温度に達した後、前述した方法によって、リペア対象の半導体チップ11を取り外すことで他部品の熱ストレスを低減することができる。   Next, a method for repairing only defective semiconductor chips on a substrate on which a plurality of semiconductor chips are mounted will be described. Although only the semiconductor chip to be repaired may be removed while heating the whole, it is effective to locally heat only the semiconductor chip to be repaired when it is not desired to heat it more than necessary due to problems such as heat resistance of components. For example, as shown in FIG. 4, hot air 16 is sprayed from the air nozzle 15 only to the semiconductor chip 11 to be repaired to perform local heating. By this method, after the semiconductor chip to be repaired reaches a predetermined temperature, the semiconductor chip 11 to be repaired can be removed by the above-described method to reduce the thermal stress of other components.

また、図5に示すように、リペア対象の半導体チップ11にのみヒータブロック17を接触させて、局部加熱を行ってもよい。
なお、図4、図5に示した加熱方法は、チップ取り外し時のみでなく半導体チップの再実装にも利用することで、他部品の熱ストレスを低減することができる。
また、リペアしたい半導体チップに局部加熱を施すとともに近接する部品を冷却するのも、他の部品の熱ストレスを低下させるのに効果がある。例えば、図6に示すように、リペア対象の半導体チップ11にのみエアノズル15よりホットエア16を放射すると共に、近隣の半導体チップ1には金属製の冷却ブロック18を接触させる。この例では冷却の際に冷却ブロックを接触させるものであるが、他の例としてゲル状の材料を接触させたり、室温以下のエアを吹きつける方法等であってもよい。
Further, as shown in FIG. 5, local heating may be performed by bringing the heater block 17 into contact only with the semiconductor chip 11 to be repaired.
Note that the heating method shown in FIGS. 4 and 5 can be used not only when the chip is removed but also when the semiconductor chip is remounted, thereby reducing the thermal stress of other components.
In addition, applying local heating to a semiconductor chip to be repaired and cooling adjacent components is effective in reducing the thermal stress of other components. For example, as shown in FIG. 6, hot air 16 is radiated from the air nozzle 15 only to the semiconductor chip 11 to be repaired, and a metal cooling block 18 is brought into contact with the neighboring semiconductor chip 1. In this example, the cooling block is brought into contact with the cooling. However, as another example, a method in which a gel-like material is brought into contact or air at room temperature or lower is blown may be used.

複数の半導体チップが近接配置された場合、それぞれの半導体チップを封止している樹脂がつながってしまうことがある。図7(a)は、リペア対象の半導体チップ11の封止樹脂9と隣接する半導体チップ1の封止樹脂9とが連結した場合を示したものである。この場合、不良側の半導体チップ11の封止樹脂の基板界面をきれいに剥離させることができても、封止樹脂がつながっているためにリペア対象でない良品の半導体チップ1側に樹脂剥離等の損傷を与えてしまう可能性がある。これを回避するには、図7(b)に示すように、連結した封止樹脂間に切り込み19を入れるのがよい。このようにすることにより、チップ取り外し時の樹脂剥離の進行を切り込み箇所にて分断させ、隣接部品への悪影響を防止することができる。この際の樹脂に切れ込みを入れる手段としては、加熱した後に先端が鋭利な金属等で行ってもよいし、常温にて切り込み深さを調整可能な電動カッター等を用いてもよい。切り込みの深さについては、樹脂厚さの半分以上であることが望ましく、さらには基板表面ぎりぎりであればより効果的である。
以下に本発明をさらに具体的に説明するが、本発明はその要旨を越えない限り、以下の実施例に限定されるものではない。
When a plurality of semiconductor chips are arranged close to each other, a resin sealing each semiconductor chip may be connected. FIG. 7A shows a case where the sealing resin 9 of the semiconductor chip 11 to be repaired and the sealing resin 9 of the adjacent semiconductor chip 1 are connected. In this case, even if the substrate interface of the sealing resin of the semiconductor chip 11 on the defective side can be peeled cleanly, the sealing resin is connected so that the non-repairable semiconductor chip 1 side is damaged such as resin peeling. May be given. In order to avoid this, as shown in FIG. 7B, it is preferable to make a notch 19 between the connected sealing resins. By doing so, it is possible to divide the progress of the resin peeling at the time of removing the chip at the cut portion, and to prevent an adverse effect on the adjacent parts. As a means for making a cut in the resin at this time, a metal having a sharp tip after heating may be used, or an electric cutter or the like whose depth of cut can be adjusted at room temperature may be used. The depth of the cut is desirably half or more of the resin thickness, and more effective if it is just below the substrate surface.
The present invention will be described more specifically below, but the present invention is not limited to the following examples unless it exceeds the gist.

まず、エポキシ樹脂のリペア温度における密着性を低下させるための検討を実施した。エポキシ樹脂母材に対し、異なる種別の粒子を添加した封止樹脂組成物を試作した。多層シロキサン骨格を有する粒子を添加した組成A、ポリブタジエン系粒子を添加した組成B、アクリル系粒子を添加した組成C、前記の有機粒子未添加の組成Dを下記表に示す割合で混合し、その線膨張係数、弾性率を測定した。結果を表1に示す。なお、表1において、α1はガラス転位温度以下の温度での線膨張係数、α2はガラス転位温度以上の温度での線膨張係数である(表5においても同じ)。本発明の多層シロキサン骨格を有する粒子を添加した組成Aは、組成B、組成Cと比較し、多量の有機フィラー添加にもかかわらず、線膨張係数を増加させることがない。また、有機フィラーは添加せず無機フィラーのみ他と同量添加した組成Dと比較し、リペア時に必要となる弾性率を低くすることができた。すなわち、本発明の方法により、耐ヒートサイクル性確保に必要な低線膨張係数と、リペア時に必要な低弾性を両立させることができた。なお、表1に示す線膨張係数のデータは3回以上の繰り返し測定を行い、平均した値を記載したものである。   First, investigations were made to reduce the adhesion of the epoxy resin at the repair temperature. A sealing resin composition in which different types of particles were added to the epoxy resin base material was made as a prototype. The composition A to which particles having a multilayer siloxane skeleton were added, the composition B to which polybutadiene particles were added, the composition C to which acrylic particles were added, and the composition D to which no organic particles were added were mixed in the ratio shown in the following table, The linear expansion coefficient and elastic modulus were measured. The results are shown in Table 1. In Table 1, α1 is a linear expansion coefficient at a temperature not higher than the glass transition temperature, and α2 is a linear expansion coefficient at a temperature not lower than the glass transition temperature (the same applies to Table 5). The composition A to which the particles having a multilayer siloxane skeleton of the present invention are added does not increase the linear expansion coefficient in spite of the addition of a large amount of organic filler, compared with the compositions B and C. Moreover, the elasticity modulus required at the time of repair was able to be made low compared with the composition D which added the same amount as the others only by adding an inorganic filler without adding an organic filler. That is, according to the method of the present invention, it was possible to achieve both a low linear expansion coefficient necessary for ensuring heat cycle resistance and a low elasticity necessary for repair. In addition, the data of the linear expansion coefficient shown in Table 1 are values obtained by averaging three or more repeated measurements.

Figure 2007081266
Figure 2007081266

エポキシ樹脂母材に対し、シリコーンフィラーを下記表2に示す割合で添加し、粘弾性測定を実施した。その結果、シリコーンフィラーの添加はガラス転移温度の大幅な低下を生じさせることなく、封止樹脂の弾性率を低下させることができた。   Silicone filler was added to the epoxy resin base material at the ratio shown in Table 2 below, and viscoelasticity measurement was performed. As a result, the addition of the silicone filler was able to reduce the elastic modulus of the sealing resin without causing a significant decrease in the glass transition temperature.

Figure 2007081266
Figure 2007081266

エポキシ母材に対し異なる種別の粒子を添加した封止樹脂組成物を試作した。多層シロキサン骨格を有する粒子を添加した組成A、多層構造を持たないシリコーンゴム粒子を添加した組成E、アクリル系粒子を添加した組成Cを下記に示す割合で混合し、その粘度、チクソトロピー指数、浸透性を測定した結果を、表3に示す。結果、多重シロキサン骨格を有する粒子を用いることにより、低粘度、低チクソトロピー指数で、浸透性を向上させることができた。   A sealing resin composition in which different types of particles were added to the epoxy base material was made as a prototype. The composition A to which particles having a multilayer siloxane skeleton were added, the composition E to which silicone rubber particles having no multilayer structure were added, and the composition C to which acrylic particles were added were mixed at the following ratios, and their viscosity, thixotropy index, penetration The results of measuring the properties are shown in Table 3. As a result, by using particles having a multiple siloxane skeleton, the permeability could be improved with a low viscosity and a low thixotropy index.

Figure 2007081266
Figure 2007081266

樹脂のリペア温度における密着強度の測定を行った。評価方法は、利昌工業(株)製ガラスエポキシ材CS−3357sの表面に太陽インキ製造(株)製のソルダーレジストPSR−4000CC02をコートした基板材料を準備した。この基板材料を2mm角に切断し、同様の基板材料の上に評価対象となるエポキシ樹脂にて接着し、エポキシ樹脂を十分に硬化した試料を用いた。評価に使用した樹脂は、ビフェニル系エポキシ樹脂に多層シロキサン骨格を有する粒子を25vol%添加したものを組成F、有機粒子未添加のビフェニル系エポキシ樹脂を組成G、有機粒子未添加のナフタレン系エポキシ樹脂を組成Hとした。これらの試験片を25℃及びはんだ溶融温度に合わせたリペア温度である240℃にてシェア(shear)試験により、各樹脂の密着強度測定を行った。試験数は各温度について9としたが、組成Fの240℃に関しては、3倍の27とした。結果を表4に示す。   The adhesion strength at the repair temperature of the resin was measured. The evaluation method prepared the board | substrate material which coat | covered the solder resist PSR-4000CC02 made by Taiyo Ink Manufacturing Co., Ltd. on the surface of the glass epoxy material CS-3357s made by Risho Kogyo Co., Ltd. This substrate material was cut into 2 mm square, adhered to the same substrate material with an epoxy resin to be evaluated, and a sample in which the epoxy resin was sufficiently cured was used. The resin used in the evaluation is a composition F obtained by adding 25 vol% of particles having a multi-layered siloxane skeleton to a biphenyl epoxy resin, a composition G of a biphenyl epoxy resin without addition of organic particles, and a naphthalene epoxy resin without addition of organic particles The composition H. These test pieces were measured for adhesion strength of each resin by a shear test at 25 ° C. and a repair temperature of 240 ° C. adjusted to the solder melting temperature. The number of tests was 9 for each temperature, but for 240 ° C. of composition F, it was tripled to 27. The results are shown in Table 4.

Figure 2007081266
(単位:N)
Figure 2007081266
(Unit: N)

結果の中で数字の後に以上と記載があるものは、測定器の上限値を超えても剥離しなかったものであり、正確な密着強度を測定することはできなかったものである。
結果は、ナフタレン系エポキシ樹脂の組成Hとビフェニル系エポキシ樹脂の組成Gを比較した場合、25℃、240℃ともにナフタレン系エポキシ樹脂の組成Hの密着強度が強いことが確認できた。ビフェニル系エポキシ樹脂に多層シロキサン骨格を有する粒子を25vol%添加した組成Fと有機粒子未添加のビフェニル系エポキシ樹脂である組成Gを比較した場合、リペア温度での密着強度の平均値が70%程度となっており、多層シロキサン骨格を有する粒子を添加することにより、リペア温度での密着性を低下させる効果があることを確認した。なお、組成Fの240℃における単位面積あたりの密着強度の最大値は、353gf/mmであった。
In the results, what is described above after the number is the one that did not peel even when the upper limit value of the measuring instrument was exceeded, and the accurate adhesion strength could not be measured.
As a result, when the composition H of the naphthalene epoxy resin and the composition G of the biphenyl epoxy resin were compared, it was confirmed that the adhesion strength of the composition H of the naphthalene epoxy resin was strong at 25 ° C. and 240 ° C. When comparing composition F, in which 25 vol% of particles having a multi-layer siloxane skeleton are added to a biphenyl-based epoxy resin, and composition G, which is a biphenyl-based epoxy resin to which no organic particles are added, the average value of the adhesion strength at the repair temperature is about 70%. It was confirmed that the addition of particles having a multilayer siloxane skeleton has the effect of reducing the adhesion at the repair temperature. In addition, the maximum value of the adhesion strength per unit area of the composition F at 240 ° C. was 353 gf / mm 2 .

以下に、実際に半導体チップを使用したリペアの実施例を示す。なお、リペア実験に使用したビフェニル系エポキシ樹脂に多層シロキサン骨格を有する粒子を添加した樹脂の詳細を表5に示す。   Hereinafter, an example of repair actually using a semiconductor chip will be described. Table 5 shows details of a resin obtained by adding particles having a multilayer siloxane skeleton to the biphenyl epoxy resin used in the repair experiment.

Figure 2007081266
Figure 2007081266

実験に使用した半導体チップはサイズが13mm×18mm、ピッチは0.8mm、電極数は66である。半導体チップのバンプは、Sn−3Ag−0.5Cuの鉛フリーはんだを使用した。次に、半導体チップをビルドアップ配線基板上に実装する方法について述べる。フラックスを均一に薄く塗布したガラス板上に半導体チップのはんだバンプ先端を押しつけた状態で所定の荷重でのせた後に剥がし、半導体チップのはんだバンプ先端にフラックスを転写する。引き続きビルドアップ配線基板上に、半導体チップをフリップチップマウンタにて位置あわせし、搭載した後ピーク温度240℃のリフロー炉にてはんだリフローを行い、ビルドアップ配線基板と半導体チップを接続することができた。なお、半導体チップとビルドアップ配線基板との隙間は約250μmである。
得られた半導体チップ搭載済みのビルドアップ配線基板をアルコール中で揺動し、半導体チップとビルドアップ配線基板間の隙間に残るフラックス残渣を洗浄した。得られた洗浄済みの実装品を125℃のオーブン中で2時間ベーキングし、フラックス洗浄に用いたアルコールを乾燥させた。
さらに乾燥済みパッケージをホットプレート上で加温し、ビルドアップ配線基板の表面温度が100℃であることを確認した後、樹脂塗布装置を用いて半導体チップの側面より樹脂組成物を供給した。この際、封止樹脂組成物は毛細管現象により半導体チップの下面を流動し、約250μmのギャップにボイドが発生することなく充填することができた。
The semiconductor chip used in the experiment has a size of 13 mm × 18 mm, a pitch of 0.8 mm, and 66 electrodes. The bump of the semiconductor chip was Sn-3Ag-0.5Cu lead-free solder. Next, a method for mounting a semiconductor chip on a build-up wiring board will be described. The solder bump tip of the semiconductor chip is pressed onto a glass plate on which the flux is uniformly and thinly applied and then peeled off with a predetermined load, and the flux is transferred to the solder bump tip of the semiconductor chip. The semiconductor chip can then be aligned on the build-up wiring board using a flip chip mounter, and after mounting, solder reflow can be performed in a reflow furnace with a peak temperature of 240 ° C to connect the build-up wiring board and the semiconductor chip. It was. The gap between the semiconductor chip and the build-up wiring board is about 250 μm.
The obtained build-up wiring board on which the semiconductor chip was mounted was swung in alcohol, and the flux residue remaining in the gap between the semiconductor chip and the build-up wiring board was cleaned. The obtained mounted product was baked in an oven at 125 ° C. for 2 hours to dry the alcohol used for flux cleaning.
Further, the dried package was heated on a hot plate, and after confirming that the surface temperature of the build-up wiring board was 100 ° C., the resin composition was supplied from the side surface of the semiconductor chip using a resin coating apparatus. At this time, the sealing resin composition flowed on the lower surface of the semiconductor chip by capillary action, and was able to be filled without generating voids in a gap of about 250 μm.

樹脂の充填が完了した実装品を150℃大気雰囲気中で約1時間硬化させることで、半導体チップの実装を完了した。
このようにして得られた半導体装置を用いて、半導体チップをビルドアップ配線基板よりリペアする実験を試みた。
ホットプレート上に半導体チップ実装面を上にして置き、基板表面がはんだバンプの溶融温度である240℃になるように加熱した。まず、リペア方法として本発明の剥離用プレートを使用する方法にて、リペア実験を行なった。
リペア実験に使用した剥離用プレートは、幅22mm、長さ130mm、厚さが0.15mmで材質はSUS420である。ビルドアップ配線基板が動かないように押さえながら、半導体チップの幅13mmの辺の封止樹脂フィレット部に剥離用プレート幅22mmの先端を当てて配線基板表面に沿って押し込み、封止樹脂側面を破壊して、さらに剥離用プレートを少しずつ挿入した。剥離用プレートを挿入すると樹脂が破壊された際に生じた樹脂クラックは封止樹脂と基板の界面剥離に進展し、そのまま剥離用プレートを挿入し続けてさらに界面剥離を進展させ、最終的には剥離用プレート先端を挿入辺の反対側の辺まで到達させることにより、半導体チップをビルドアップ配線基板から除去することができた。この段階でビルドアップ配線基板上を観察してみると、基板上の樹脂残渣は半導体チップ周辺の樹脂フィレット部でわずかに残る程度で、電極パッド部では基板界面からきれいに剥離していることが確認された。わずかに残った樹脂残渣は、常温でDMF(ジメチルホルムアミド)を用いながら綿棒にてこする等のクリーニングを施すことにより、基板表面から除去することができた。再生したビルドアップ配線基板に新たな半導体チップを前述した方法により、再実装してみたが問題なく実装することができた。以上の結果から、剥離用プレートを使用した本発明のリペア方法により、リペアが可能であることを確認した。
また、前記リペア評価はホットエアによる局部加熱方式も含め、5個実験を行ったが、いずれの試料についても全て同様に基板界面から半導体チップを除去することができた。
The mounting of the semiconductor chip was completed by curing the mounting of the resin filled with the resin in an air atmosphere at 150 ° C. for about 1 hour.
Using the semiconductor device thus obtained, an experiment was attempted to repair the semiconductor chip from the build-up wiring board.
The semiconductor chip mounting surface was placed on a hot plate, and the substrate surface was heated to 240 ° C., which is the melting temperature of the solder bumps. First, a repair experiment was performed by a method using the peeling plate of the present invention as a repair method.
The peeling plate used in the repair experiment has a width of 22 mm, a length of 130 mm, a thickness of 0.15 mm and a material of SUS420. While holding the build-up wiring board so as not to move, the tip of the peeling plate width 22 mm is applied to the sealing resin fillet on the side of the semiconductor chip 13 mm wide and pushed along the surface of the wiring board to destroy the side surface of the sealing resin Then, a peeling plate was inserted little by little. When the peeling plate is inserted, the resin crack that occurs when the resin is destroyed progresses to the interface peeling between the sealing resin and the substrate, and continues to insert the peeling plate as it is, further progressing the interface peeling. The semiconductor chip could be removed from the build-up wiring board by causing the tip of the peeling plate to reach the side opposite to the insertion side. When observing the build-up wiring board at this stage, it is confirmed that the resin residue on the board remains slightly in the resin fillet part around the semiconductor chip, and that the electrode pad part is cleanly separated from the board interface It was done. The resin residue that remained slightly could be removed from the substrate surface by cleaning such as rubbing with a cotton swab while using DMF (dimethylformamide) at room temperature. Although a new semiconductor chip was re-mounted on the regenerated build-up wiring board by the method described above, it could be mounted without any problem. From the above results, it was confirmed that repair was possible by the repair method of the present invention using a peeling plate.
In addition, the repair evaluation was conducted for five samples including a local heating method using hot air, and all the samples were able to remove the semiconductor chip from the substrate interface in the same manner.

次に、ピンセットを用いた取り外し実験を行なった。前述した方法と同様に実装品を240℃まで加熱した後、ピンセット先端を半導体チップの側面に引っ掛けた後、半導体チップを持ち上げるようにして基板から引き剥がした。するとビルドアップ配線基板上には、多数の電極エリアも含め、面積比で50%以上樹脂が残っており、基板界面で樹脂剥離させることはできなかった。
また、前述の樹脂密着強度試験に使用した有機粒子未添加のビフェニル系エポキシ樹脂と有機粒子未添加のナフタレン系エポキシ樹脂を用いて、前述した剥離用プレートを用いたリペア実験と同様の条件でリペア実験を実施した。まず、密着強度が強いナフタレン系エポキシ樹脂の場合では、剥離用プレートを樹脂側面に押し当てた後の樹脂破壊が困難であったが、さらに強い力で剥離用プレートを挿入したところ、ビルドアップ基板表面の大部分のソルダーレジストが剥離する基板破壊が発生した。
Next, a removal experiment using tweezers was performed. After the mounted product was heated to 240 ° C. in the same manner as described above, the tip of the tweezers was hooked on the side surface of the semiconductor chip, and then the semiconductor chip was lifted and peeled off from the substrate. Then, 50% or more of the resin remained in the area ratio including many electrode areas on the build-up wiring board, and the resin could not be peeled off at the board interface.
In addition, using the biphenyl epoxy resin without addition of organic particles and the naphthalene epoxy resin without addition of organic particles used in the resin adhesion strength test described above, repair was performed under the same conditions as in the repair experiment using the peeling plate described above. Experiments were performed. First, in the case of naphthalene-based epoxy resin with strong adhesion strength, it was difficult to break the resin after pressing the release plate against the resin side, but when the release plate was inserted with a stronger force, the build-up board Substrate destruction occurred where most of the solder resist on the surface peeled off.

次に、有機粒子未添加のビフェニル系エポキシ樹脂で剥離用プレートを用いたリペア実験を実施した結果は、基板を破壊することなく、半導体チップを取り外すことができたが、基板上に50%程度の面積比で樹脂残渣が発生し、さらに樹脂除去を試みたところ、部分的にビルドアップ基板表面のソルダーレジストが剥離する基板破壊が発生した。この結果に関しては、有機粒子未添加のビフェニル系エポキシ樹脂の場合、240℃における樹脂の密着強度とリペア性を比較した場合、非常に微妙な関係にあることと、前記した樹脂密着強度測定結果からもわかるように密着強度に多少のバラツキが生じるためにこのような結果になったと考えることができる。つまり、密着強度が低い箇所では基板界面から樹脂が剥離するが、密着強度が高い箇所では樹脂が基板に残り、樹脂除去時のソルダーレジスト剥離に至ったのである。   Next, as a result of carrying out a repair experiment using a peeling plate with a biphenyl epoxy resin to which no organic particles were added, the semiconductor chip could be removed without destroying the substrate, but about 50% on the substrate. Resin residue was generated at an area ratio of, and further resin removal was attempted. As a result, substrate destruction occurred in which the solder resist on the build-up substrate surface was partially peeled off. Regarding this result, in the case of biphenyl-based epoxy resin to which no organic particles are added, when the adhesion strength and repairability of the resin at 240 ° C. are compared, there is a very delicate relationship, and from the measurement result of the resin adhesion strength described above. It can be considered that this result was obtained because there was some variation in the adhesion strength. That is, the resin peels off from the substrate interface at a location where the adhesion strength is low, but the resin remains on the substrate at a location where the adhesion strength is high, leading to solder resist peeling at the time of resin removal.

以上の結果より、ビフェニル系エポキシ樹脂に多層シロキサン骨格を有する粒子を添加した樹脂が、リペアに対して効果的であることと、樹脂の密着強度が350gf/mm以下となる条件で剥離用プレートを用いたリペアを行なうことで、基板界面から封止樹脂を剥離させることが可能であることを確認した。
ビフェニル系エポキシ樹脂に多層シロキサン骨格を有する粒子を添加した樹脂による信頼性評価を行なった。封止なし、封止あり(リペアなし)、封止あり(リペアあり)の3種のパッケージを、それぞれ10セット(10p)ずつ作製した。得られたパッケージを−25℃〜125℃の温度条件(各槽10分保持、中間保持なし)の温度サイクル試験槽に投入し、電気抵抗をモニターした結果、封止なしの試料は50〜400サイクルでパッケージ全数に高抵抗化不良が検出されたのに対し、封止ありのサンプル20試料については、半導体チップをリペアし、再搭載したパッケージについても1500サイクルを超える耐熱サイクル信頼性を確認することができた。
From the above results, the release plate is obtained under the condition that the resin in which the particles having a multilayer siloxane skeleton are added to the biphenyl-based epoxy resin is effective for repair and the adhesive strength of the resin is 350 gf / mm 2 or less. It was confirmed that the sealing resin can be peeled off from the substrate interface by performing repair using.
Reliability evaluation was performed using a resin in which particles having a multilayer siloxane skeleton were added to a biphenyl epoxy resin. Ten sets (10p) of three types of packages each without sealing, with sealing (without repair), and with sealing (with repair) were produced. The obtained package was put into a temperature cycle test bath under a temperature condition of −25 ° C. to 125 ° C. (holding for 10 minutes in each bath, no intermediate holding), and the electrical resistance was monitored. While high resistance failure was detected in the total number of packages in the cycle, for the 20 samples with sealing, the semiconductor chip was repaired, and the heat cycle reliability exceeding 1500 cycles was confirmed for the remounted package I was able to.

Figure 2007081266
Figure 2007081266

信頼性試験完了後の半導体装置を断面観察し、はんだ接続部周辺の封止樹脂の充填状態を観察した。その結果、シロキサン骨格を2層以上有する多層構造となる粒子は、封止樹脂硬化後においても球形を維持していることが確認できた。シロキサン骨格を2層以上有する多層構造となる粒子は、封止樹脂の硬化温度において溶融せず、また封止樹脂の母材となるエポキシ樹脂と相溶していないことを確認した。   A cross section of the semiconductor device after the completion of the reliability test was observed, and the filling state of the sealing resin around the solder connection portion was observed. As a result, it was confirmed that the particles having a multilayer structure having two or more siloxane skeletons maintained a spherical shape even after the sealing resin was cured. It was confirmed that the particles having a multilayer structure having two or more siloxane skeletons did not melt at the curing temperature of the sealing resin and were not compatible with the epoxy resin serving as the base material of the sealing resin.

半導体チップをビルドアップ配線基板上にフリップチップ接続し、封止樹脂を充填した半導体装置の断面図。Sectional drawing of the semiconductor device which carried out the flip chip connection of the semiconductor chip on the buildup wiring board, and was filled with sealing resin. 本発明のリペア方法を示す工程順の断面図。Sectional drawing of the process order which shows the repair method of this invention. 本発明のリペア方法に用いる剥離用プレートの平面図と部分断面図。The top view and fragmentary sectional view of the plate for peeling used for the repair method of this invention. 配線基板上に複数の半導体チップが搭載された場合において、ホットエアにより局部加熱する様子を示す模式図。The schematic diagram which shows a mode that a local heating is carried out with hot air, when a several semiconductor chip is mounted on a wiring board. 配線基板上に複数の半導体チップが搭載された場合において、ヒータブロックにより局部加熱する様子を示す模式図。The schematic diagram which shows a mode that it heats locally with a heater block, when a several semiconductor chip is mounted on a wiring board. 配線基板上に複数の半導体チップが搭載された場合において、ホットエアにより局部加熱しながら、隣接チップを冷却ブロックにより局部冷却する様子を示す模式図。The schematic diagram which shows a mode that an adjacent chip | tip is locally cooled by a cooling block, when a some semiconductor chip is mounted on a wiring board, heating locally by hot air. 配線基板上に複数の半導体チップが搭載された場合において、隣接する半導体チップを封止する樹脂が連結した場合のリペアを説明する模式図。The schematic diagram explaining the repair when the resin which seals an adjacent semiconductor chip has connected in the case where a plurality of semiconductor chips are mounted on a wiring board.

符号の説明Explanation of symbols

1 半導体チップ
2 チップ側パッド
3 ビルドアップ配線基板
4 絶縁層
5 配線
6 基板側パッド
7 ソルダーレジスト
8 はんだバンプ
9 封止樹脂
10 配線基板
11 リペア対象の半導体チップ
12 剥離用プレ−ト
13 樹脂残渣
14 残留はんだ
15 エアノズル
16 ホットエア
17 ヒータブロック
18 冷却ブロック
19 切り込み
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Chip side pad 3 Build-up wiring board 4 Insulation layer 5 Wiring 6 Board side pad 7 Solder resist 8 Solder bump 9 Sealing resin 10 Wiring board 11 Repair target semiconductor chip 12 Peeling plate 13 Resin residue 14 Residual solder 15 Air nozzle 16 Hot air 17 Heater block 18 Cooling block 19 Notch

Claims (16)

配線基板に1ないし複数の半導体デバイスが、それぞれに形成されたパッド同士が導電性バンプを介して接続される態様にて、実装され、前記半導体デバイスと前記配線基板との隙間が封止樹脂により充填されている半導体装置のリペア方法であって、少なくともリペア対象の半導体デバイスを加熱して封止樹脂の密着強度を低下させ、前記半導体デバイスと前記配線基板との隙間より薄いプレートを前記半導体デバイスと前記配線基板との隙間に挿入することにより、前記半導体デバイスを前記配線基板から分離することを特徴とする半導体装置のリペア方法。 One or a plurality of semiconductor devices are mounted on a wiring board in such a manner that pads formed on each are connected via conductive bumps, and a gap between the semiconductor device and the wiring board is formed by a sealing resin. A method of repairing a filled semiconductor device, wherein at least a semiconductor device to be repaired is heated to reduce an adhesion strength of a sealing resin, and a plate thinner than a gap between the semiconductor device and the wiring board is formed on the semiconductor device A semiconductor device repairing method, wherein the semiconductor device is separated from the wiring board by being inserted into a gap between the wiring board and the wiring board. 前記封止樹脂にはシロキサン骨格を有する多層構造の粒子が添加されていることを特徴とする請求項1に記載の半導体装置のリペア方法。 The method for repairing a semiconductor device according to claim 1, wherein particles having a multilayer structure having a siloxane skeleton are added to the sealing resin. 前記封止樹脂にはコア部がシエル部よりも硬度が低い多層構造の粒子が添加されていることを特徴とする請求項1に記載の半導体装置のリペア方法。 The method of repairing a semiconductor device according to claim 1, wherein particles having a multilayer structure with a core portion having a hardness lower than that of the shell portion are added to the sealing resin. 前記多層構造の粒子のコア部が線状ポリマーによって構成され、シエル部が3次元ポリマーによって構成されていることを特徴とする請求項2または3に記載の半導体装置のリペア方法。 4. The method of repairing a semiconductor device according to claim 2, wherein the core portion of the multi-layered particle is made of a linear polymer, and the shell portion is made of a three-dimensional polymer. 前記多層構造の粒子のコア部がシリコーンゴムであり、シエル部がシリコーンレジンであることを特徴とする請求項2または3に記載の半導体装置のリペア方法。 4. The method of repairing a semiconductor device according to claim 2, wherein the core portion of the particles having the multilayer structure is made of silicone rubber and the shell portion is made of silicone resin. 前記プレートを前記半導体デバイスと前記配線基板との隙間に挿入する際の前記封止樹脂の密着強度は3.43N/mm(350gf/mm)以下であることを特徴とする請求項1から5のいずれかに記載の半導体装置のリペア方法。 The adhesion strength of the sealing resin when the plate is inserted into a gap between the semiconductor device and the wiring board is 3.43 N / mm 2 (350 gf / mm 2 ) or less. 6. The method for repairing a semiconductor device according to any one of 5 above. リペア対象の半導体デバイスのみを局部的に加熱することを特徴とする請求項1から6のいずれかに記載の半導体装置のリペア方法。 7. The method of repairing a semiconductor device according to claim 1, wherein only the semiconductor device to be repaired is locally heated. リペア対象の半導体デバイスのみを局部的に加熱するとともにリペア対象ではない周囲のデバイスを選択的に冷却することを特徴とする請求項1から7のいずれかに記載の半導体装置のリペア方法。 8. The method of repairing a semiconductor device according to claim 1, wherein only a semiconductor device to be repaired is locally heated and peripheral devices not to be repaired are selectively cooled. リペア対象の半導体デバイスの封止樹脂とリペア対象の半導体デバイスに隣接する半導体デバイスの封止樹脂とが連結している場合にその封止樹脂の連結部の少なくとも一部に切り込みを施した後、リペア対象の半導体デバイスを選択的に除去することを特徴とする請求項1から8のいずれかに記載の半導体装置のリペア方法。 When the sealing resin of the semiconductor device to be repaired and the sealing resin of the semiconductor device adjacent to the semiconductor device to be repaired are connected, after cutting at least part of the connecting portion of the sealing resin, 9. The method of repairing a semiconductor device according to claim 1, wherein a semiconductor device to be repaired is selectively removed. 前記プレートの挿入により、前記導電性バンプを配線基板側根元にて配線基板側のパッドより分離することを特徴とする請求項1から9のいずれかに記載の半導体装置のリペア方法。 10. The method of repairing a semiconductor device according to claim 1, wherein the conductive bumps are separated from the pads on the wiring board side at the base of the wiring board by inserting the plate. 前記プレートの前記封止樹脂への挿入が、前記封止樹脂を前記配線基板の表面より剥離しつつ進行することを特徴とする請求項1から10のいずれかに記載の半導体装置のリペア方法。 11. The method of repairing a semiconductor device according to claim 1, wherein the insertion of the plate into the sealing resin proceeds while peeling the sealing resin from the surface of the wiring board. リペア対象の半導体デバイスを分離・除去するに際し、最初に封止樹脂の表面を破壊するプレート(以下、第1プレート)と、リペア対象の半導体デバイスを配線基板から分離する際のプレート(以下、第2プレート)とが異なることを特徴とする請求項1から11のいずれかに記載の半導体装置のリペア方法。 When separating / removing the semiconductor device to be repaired, a plate (hereinafter referred to as the first plate) that first destroys the surface of the sealing resin and a plate (hereinafter referred to as the first plate) for separating the semiconductor device to be repaired from the wiring board. 12. The method for repairing a semiconductor device according to claim 1, wherein the two plates are different from each other. 前記第1プレートは、前記第2プレートより薄いことを特徴とする請求項12に記載の半導体装置のリペア方法。 The method of claim 12, wherein the first plate is thinner than the second plate. 前記第1プレートの先端部は、前記第2プレートの先端部より鋭利であることを特徴とする請求項12または13に記載の半導体装置のリペア方法。 14. The method of repairing a semiconductor device according to claim 12, wherein a tip portion of the first plate is sharper than a tip portion of the second plate. 前記プレートまたは前記第2プレートの先端部の断面形状は丸みを有していることを特徴とする請求項1から14のいずれかに記載の半導体装置のリペア方法。 15. The method of repairing a semiconductor device according to claim 1, wherein a cross-sectional shape of a tip portion of the plate or the second plate has a round shape. 前記プレートまたは前記第2プレートには耐熱性樹脂のコーティングが施されていることを特徴とする請求項1から15のいずれかに記載の半導体装置のリペア方法。
16. The method of repairing a semiconductor device according to claim 1, wherein the plate or the second plate is coated with a heat resistant resin.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5556808B2 (en) * 2009-03-24 2014-07-23 日本電気株式会社 Electronic device, substrate, and method of manufacturing electronic device
WO2020129487A1 (en) * 2018-12-21 2020-06-25 豊田合成株式会社 Light-emitting device and manufacturing method therefor
CN112703583A (en) * 2018-10-30 2021-04-23 昭和电工材料株式会社 Semiconductor device and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04154861A (en) * 1990-10-19 1992-05-27 Toshiba Silicone Co Ltd Resin composition
JPH10204259A (en) * 1997-01-17 1998-08-04 Loctite Corp Thermosetting resin composition
JP2004179552A (en) * 2002-11-28 2004-06-24 Nec Corp Mounting structure and mounting method for semiconductor device, and reworking method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04154861A (en) * 1990-10-19 1992-05-27 Toshiba Silicone Co Ltd Resin composition
JPH10204259A (en) * 1997-01-17 1998-08-04 Loctite Corp Thermosetting resin composition
JP2004179552A (en) * 2002-11-28 2004-06-24 Nec Corp Mounting structure and mounting method for semiconductor device, and reworking method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5556808B2 (en) * 2009-03-24 2014-07-23 日本電気株式会社 Electronic device, substrate, and method of manufacturing electronic device
CN112703583A (en) * 2018-10-30 2021-04-23 昭和电工材料株式会社 Semiconductor device and method for manufacturing the same
WO2020129487A1 (en) * 2018-12-21 2020-06-25 豊田合成株式会社 Light-emitting device and manufacturing method therefor

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