JP2007074705A - Signal transmission device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transmission device in which jitter occurring in a clock signal is eliminated. <P>SOLUTION: A signal transmission device 10 has a construction in which a transmission end IC (Integrated Circuit) chip 22 provided with a transmission part 24 of a data signal and a reception end IC chip 50 provided with a reception part 52 of the data signal, the transmission part 24 and the reception part 52 are connected via a data signal transmission line 40, an oscillator 26 that outputs a clock signal to the transmission part 24 is connected with the transmission end IC chip 22, a clock signal transmission line 42 is provided which leads the clock signal outputted from the oscillator 26 to the reception part 52, and a SAW (Surface Acoustic Wave) filter 44 is arranged in the clock signal transmission line 42. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal transmission device, and more particularly to a signal transmission device that transmits a signal between IC chips.

  In the signal transmission device that transmits the data signal from the transmission side to the reception side, the data signal is transmitted from the transmission side to the reception side in synchronization with the clock signal, and the data signal “0”, There is a configuration that performs the determination of “1”. Since such a signal transmission apparatus reads a data signal based on a clock signal on the receiving side, there is a problem that the data signal cannot be read accurately when noise occurs in the clock signal and jitter occurs.

In optical communication that performs high-distance transmission at high speed, the jitter of the clock signal causes a data transmission error, and therefore it is desired that the jitter of the clock signal is sufficiently small. Therefore, in the optical transceiver module for the optical network, the jitter of the clock signal is eliminated as follows. That is, the optical transceiver module has a configuration in which a clock conversion circuit is configured by a phase-locked loop (PLL) circuit using a voltage-controlled surface acoustic wave oscillator (VCSO), and this is provided inside. The optical transceiver module converts a low-frequency clock with a lot of jitter into a high-frequency clock signal with reduced jitter by a clock conversion circuit, and a reference for multiplexing a plurality of transmission data into a single transmission data. Used as a clock signal. The clock conversion circuit connects the first bandpass filter to the output terminal for the PLL feedback loop of the VCSO and connects the second bandpass filter to the output terminal of the feedback buffer differential amplifier in the VCSO. , The generation of jitter in the signal output from the VCSO is suppressed (see, for example, Patent Document 1).
JP 2004-120352 A

  Some signal transmission apparatuses that transmit data signals from a transmission side to a reception side perform data signal transmission among a plurality of IC chips mounted on a substrate mounted on an electronic device such as a computer. In this case, the transmission side IC chip and the reception side IC chip are mounted on the substrate, and the data signal transmission line for transmitting the data signal and the clock signal transmission line for transmitting the clock signal are connected to these IC chips. Yes.

  By the way, on the substrate on which the data signal transmission line and the clock signal transmission line are routed, in addition to the transmission side IC chip and the reception side IC chip involved in the transmission of the data signal, the circuit operates at high speed. Many IC chips (other IC chips) are mounted. For this reason, noise generated in other IC chips enters the clock signal transmitted through the clock signal transmission line, and jitter is generated in the clock signal.

  In recent years, since the data transmission speed has increased, the amount of data processed by the IC chip has increased, and the amount of data transmitted from the transmission side IC chip to the reception side IC chip has also increased. Further, since the clock signal is accelerated, the cycle of the clock pulse becomes shorter and shorter. For this reason, as the signal transmission distance becomes longer or the clock signal speeds up, the influence of jitter due to noise increases, and data transmission is hindered. That is, the problem of erroneous determination of the data signal even with a little noise has become prominent.

An apparatus that eliminates jitter using the above-described PLL circuit is very expensive. For this reason, in a signal transmission device that transmits and receives data between a plurality of IC chips, there is a problem that it is too costly to use a device that eliminates jitter using a PLL circuit.
An object of this invention is to provide the signal transmission apparatus which eliminated the jitter which arises in a clock signal.

  In one embodiment of the present invention, the signal transmission device is a signal transmission device having a clock signal transmission line through which a clock signal is transmitted and a data signal transmission line through which a data signal synchronized with the clock signal is transmitted. In addition, a bandpass filter is provided on the clock signal transmission line. Although the clock signal transmitted through the clock signal transmission line may have noise due to external influences, only the clock signal is passed through the bandpass filter, and the noise is removed from the clock signal. For this reason, the signal transmission apparatus can transmit the clock signal from which noise has been removed. As a result, erroneous determination of the data signal can be prevented.

  In one embodiment of the present invention, the bandpass filter is a SAW filter. In this case, even a signal transmission device using a high-frequency clock signal can remove noise from the clock signal.

  In one embodiment of the present invention, the clock signal is a spread spectrum clock signal spread in a predetermined frequency band, and the SAW filter is a band filter that passes the frequency band. To do. As a result, the signal transmission device can use the spread spectrum clock signal, so that it is possible to prevent the occurrence of electromagnetic interference (EMI) in the electronic device in which the signal transmission device is mounted.

  In one embodiment of the present invention, the signal transmission device includes an oscillator that outputs a clock signal, a transmission unit that converts parallel data into serial data, and outputs the serial data in synchronization with the clock signal; A signal transmission device having a receiving unit for receiving serial data and converting the serial data into parallel data based on the clock signal, wherein a bandpass filter is provided on a clock signal transmission line for supplying the clock signal to the receiving unit. It is provided. Although the clock signal transmitted through the clock signal transmission line may have noise due to external influences, only the clock signal is passed through the bandpass filter, and the noise is removed from the clock signal. For this reason, the signal transmission apparatus can input the clock signal from which noise has been removed to the receiving unit.

  In one embodiment of the present invention, the bandpass filter is a SAW filter. By using the SAW filter, even a high-frequency clock signal can be passed. Therefore, even if the clock signal of the signal transmission device has a high frequency, the noise of the clock signal can be removed, and erroneous determination of the data signal can be prevented.

  Also, in one embodiment of the present invention, the clock signal transmitted from the oscillator to the receiving unit is a spread spectrum clock signal spread in a predetermined frequency band, and the band filter has the frequency band. It is a band pass filter to be passed. As a result, the signal transmission device can use a spread spectrum clock, so that an electromagnetic interference (EMI) can be prevented from occurring in an electronic device in which the signal transmission device is mounted.

  In one embodiment of the present invention, the signal transmission device includes an oscillator that outputs a clock signal, and a transmission-side IC chip that includes a transmission unit that is connected to the oscillator and outputs a data signal in synchronization with the clock signal. A receiving side IC chip including the data signal receiving unit, a data signal transmission line for connecting the transmitting unit and the receiving unit and transmitting the data signal, and the clock signal output from the oscillator Is provided with a clock signal transmission line for transmitting the signal to the receiving side IC chip, and a SAW filter is provided on the clock signal transmission line.

  Even if noise enters the clock signal transmitted through the clock signal transmission line, the noise can be removed by the SAW filter that passes only the band corresponding to the frequency of the clock signal. Therefore, jitter caused by noise does not occur in the clock signal. Since the signal transmission device reads the data signal based on the clock signal without jitter by the receiving unit, it can accurately determine “0” and “1” of the data signal. Since only the SAW filter is used to remove noise from the clock signal, noise can be removed with a small and inexpensive system configuration.

  In one embodiment of the present invention, the signal transmission device includes a plurality of the transmission units in the transmission-side IC chip, and the reception-side IC chip includes the same number of reception units as the plurality of transmission units. The transmitting unit and the receiving unit are connected one-to-one with the data signal transmission line. Thereby, a plurality of data signals can be transmitted in parallel from the transmission side IC chip to the reception side IC chip.

  In one embodiment of the present invention, the clock signal transmission line connects the transmission-side IC chip and the reception-side IC chip, and transmits the clock signal supplied to the transmission-side IC chip to the clock. It supplies to a signal transmission line, It is characterized by the above-mentioned. In one embodiment of the present invention, the clock signal transmission line connects the oscillator and the receiving IC chip. According to these embodiments, the receiving IC chip can be supplied with a clock signal from the oscillator via the transmitting IC chip or directly.

  In one embodiment of the present invention, the signal transmission device includes a phase synchronization circuit for increasing the frequency of the clock signal in the transmission side IC chip, and the clock signal transmission line is connected to an output of the phase synchronization circuit. It is characterized by that. As a result, the frequency of the clock signal can be increased, and the data signal can be transmitted from the transmission side IC chip to the reception side IC chip at high speed. In addition, since the phase synchronization circuit may be provided in the transmission side IC chip, the circuit configuration of the reception side IC chip can be simplified.

  In one embodiment of the present invention, the signal transmission device is characterized in that a phase synchronization circuit for increasing the frequency of the clock signal is provided in the transmission side IC chip and the reception side IC chip. As a result, the frequency of the clock signal can be increased, and the data signal can be transmitted from the transmission side IC chip to the reception side IC chip at high speed.

  In one embodiment of the present invention, the SAW filter is provided close to the receiving-side IC chip. That is, since the SAW filter is provided near the reception side IC chip in the clock signal transmission line, the distance from the SAW filter to the reception side IC chip is extremely shorter than the distance from the transmission side IC chip to the SAW filter. ing. For this reason, since it is possible to prevent noise from entering the clock signal transmitted through the clock signal transmission line, it is possible to input a clock signal free from jitter due to noise to the receiving side IC chip.

  The best embodiment of the signal transmission apparatus according to the present invention will be described below. First, the first embodiment will be described. FIG. 1 is a block diagram of a signal transmission apparatus according to the first embodiment. The signal transmission apparatus 10 includes a transmission-side integrated circuit (IC) chip 22 that transmits a data signal. An oscillator 26 for outputting a clock signal is connected to the transmission side IC chip 22, and the transmission stage 20 is configured by the transmission side IC chip 22 and the oscillator 26. The transmission-side IC chip 22 includes a data signal transmission unit 24 and a first phase synchronization (PLL) circuit 30 that increases the frequency of the clock signal.

  FIG. 2 shows a block diagram of the first PLL circuit. The first PLL circuit 30 has a phase comparator 33 connected to the oscillator 26 via an input terminal 31 and connected to a feedback loop 32. The phase comparator 33 outputs a difference signal voltage based on the clock signal input from the oscillator 26 and the clock signal input from the feedback loop 32. The subsequent stage of the phase comparator 33 is connected to a low-pass filter (LPF) 34. The LPF 34 removes harmonic components and the like of the difference signal voltage. The subsequent stage of the LPF 34 is connected to a voltage controlled oscillator (VCO) 35. The VCO 35 outputs a clock signal having a frequency corresponding to the difference signal voltage input from the LPF 34. The subsequent stage of the VCO 35 is connected to the feedback loop 32 and the output terminal 36 of the first PLL circuit 30. The feedback loop 32 is provided with a frequency dividing circuit 37 that divides the clock signal output from the VCO 35 by a set frequency dividing ratio.

  The transmitter 24 shown in FIG. 1 is connected to the output of the first PLL circuit 30. That is, the transmission unit 24 is connected to the VCO 35 through the output terminal 36. The output of the transmission unit 24 is connected to the data signal transmission line 40. The transmission unit 24 receives a data signal and a clock signal from the first PLL circuit 30 and transmits the data signal to the data signal transmission line 40 in synchronization with the clock signal.

  A clock signal transmission line 42 is connected to the transmission side IC chip 22, and the clock signal output from the oscillator 26 is branched before the input stage of the first PLL circuit 30, and the clock signal is sent to the clock signal transmission line 42. It comes to lead. The clock signal transmission line 42 may be provided side by side with the data signal transmission line 40. That is, it is preferable that the transmission distances of signals transmitted through the clock signal transmission line 42 and the data signal transmission line 40 are the same.

  The signal transmission device 10 includes a receiving side IC chip 50. The reception side IC chip 50 includes a reception unit 52 and a second PLL circuit 54. The second PLL circuit 54 has the same configuration as the first PLL circuit 30 provided in the transmission-side IC chip 22 and is connected to the clock signal transmission line 42. That is, the input of the phase comparator constituting the second PLL circuit 54 is connected to the clock signal transmission line 42 and the feedback loop. The clock signal transmission line 42 is provided with a surface acoustic wave (SAW) filter 44. The SAW filter 44 is preferably provided in the vicinity of the receiving side IC chip 50. That is, the SAW filter 44 is preferably provided immediately before the point where the clock signal transmission line 42 is connected to the receiving side IC chip 50.

  The receiving unit 52 is connected to the output of the second PLL circuit 54 and is also connected to the data signal transmission line 40. The receiving unit 52 determines “0” or “1” of the data signal input from the transmitting unit 24 via the data signal transmission line 40 based on the clock signal input from the second PLL circuit 54. is there. That is, the receiving unit 52 reads the data signal based on the clock signal. Then, the receiving unit 52 outputs the read data signal.

  Next, the operation of the signal transmission device 10 will be described. First, the oscillator 26 outputs a clock signal to the transmission side IC chip 22. The clock signal input to the transmission side IC chip 22 is supplied to the first PLL circuit 30 and the clock signal transmission line 42. The first PLL circuit 30 increases the frequency of the clock signal and outputs it to the transmission unit 24. The transmitting unit 24 converts the parallel data input from the parallel data input line 45 into serial data in synchronization with the clock signal, and transmits the serial data to the receiving-side IC chip 50 via the data signal transmission line 40.

  The clock signal supplied to the clock signal transmission line 42 is input to the SAW filter 44. The center frequency of the SAW filter 44 substantially matches the frequency of the clock signal. Therefore, the SAW filter 44 removes noise that has entered during transmission of the clock signal transmission line 42 from the clock signal. That is, while the clock signal is transmitted through the clock signal transmission line 42, noises of various frequencies are superimposed on the clock signal, but the SAW filter 44 whose center frequency substantially matches the frequency of the clock signal is clocked. By providing in the middle of the signal transmission line 42, a noise component of a signal having a frequency corresponding to the frequency of the clock signal is removed. By removing this noise, jitter is prevented from occurring in the clock signal. Further, since the SAW filter 44 has a narrow frequency passband width and the SAW filter 44 has a characteristic of significantly attenuating the signal outside the passband, jitter due to noise having a frequency close to the frequency of the clock signal. Can be suppressed. Further, the longer the transmission distance, the higher the possibility that noise will enter the clock signal. However, since the SAW filter 44 is provided close to the receiving side IC chip 50, the output from the SAW filter 44 to the receiving side IC chip 50 is increased. The distance of the clock signal transmission line 42 is extremely short, and no noise enters between them. Therefore, a clock signal with no jitter is input to the second PLL circuit 54 provided in the receiving side IC chip 50.

  Then, the second PLL circuit 54 increases the frequency of the clock signal and outputs it to the receiving unit 52. The receiving unit 52 converts the serial data input via the data signal transmission line 40 into parallel data based on the clock signal output from the second PLL circuit 54 and outputs the parallel data from the parallel data output line 46. Since the data signal transmission line 40 and the clock signal transmission line 42 have the same distance and the clock signal is transmitted in parallel with the data signal, there is no phase shift between these signals. Therefore, the receiving unit 52 can accurately determine “0” or “1” of the data signal based on the clock signal. And the receiving part 52 outputs the data signal after determination. In this way, the data signal is transmitted from the transmission side IC chip 22 to the reception side IC chip 50.

  Since such a signal transmission device 10 is provided with the SAW filter 44 in the clock signal transmission line 42, noise can be removed by passing the clock signal through the SAW filter 44. Therefore, the signal transmission device 10 can obtain a clock signal in which jitter due to noise does not occur.

Further, since the signal transmission device 10 is provided with the SAW filter 44 serving as a jitter filter immediately before the clock signal is input to the reception-side IC chip 50, a new signal is removed from the clock signal from which noise has been removed by the SAW filter 44. Therefore, only the clock signal can be input to the receiving-side IC chip 50 without any noise. That is, the signal transmission device 10 can input a clock signal with no jitter to the reception-side IC chip 50. Therefore, the receiving unit 52 of the signal transmission device 10 can accurately read the data signal based on the clock signal in which no jitter occurs.
Further, since the signal transmission device 10 uses the SAW filter 44 having a simple configuration as a jitter filter, the system can be configured with a small size and at a low cost.

  In the embodiment described above, the first PLL circuit 30 is provided in the transmission-side IC chip 22 and the second PLL circuit 54 is provided in the reception-side IC chip 50 to increase the frequency of the clock signal. The first PLL circuit 30 and the second PLL circuit 54 may be omitted. That is, the transmission unit 24 may be configured to directly input the clock signal from the oscillator 26, and the reception unit 52 may be configured to directly input the clock signal from the clock signal transmission line 42.

  A modification of the embodiment described above is shown in FIG. A signal transmission device 104 illustrated in FIG. 5 includes a transmission stage 204 including a transmission-side IC chip 224 and an oscillator 26, and a reception IC chip 504. The signal transmission device 104 connects the output of the first PLL circuit 30 provided in the transmission side IC chip 224 to the clock signal transmission line 42 provided with the SAW filter 44 in the middle, and the reception unit 52 receives the clock signal. The clock signal is directly input from the transmission line 42. With this configuration, it is not necessary to provide a PLL circuit in the reception side IC chip 504, and the circuit configuration of the reception side IC chip 504 can be simplified. In this configuration, the first PLL circuit 30 may be a spread spectrum type PLL circuit that spreads a clock signal in a predetermined frequency band. When a spread spectrum type PLL circuit is used, the SAW filter 44 is a filter that passes the spread frequency band.

  Next, a second embodiment will be described. In the second embodiment, since a modification of the signal transmission device according to the first embodiment will be described, the same components as those of the signal transmission device according to the first embodiment are denoted by the same reference numerals, and the description thereof will be given. Omitted or simplified.

FIG. 3 is a block diagram of a signal transmission apparatus according to the second embodiment. The signal transmission device 102 includes a transmission side IC chip 222 including the transmission unit 24 and the first PLL circuit 30. The transmission-side IC chip 222 and the oscillator 26 constitute a transmission stage 202. An oscillator 26 is connected to the transmission side IC chip 222, and a clock signal is input from the oscillator 26. Further, the signal transmission device 102 includes a reception side IC chip 50 including a reception unit 52 and a second PLL circuit 54. The transmitter 24 and the receiver 52 are connected by a data signal transmission line 40. In the connection between the oscillator 26 and the transmission side IC chip 222, the clock signal transmission line 42 is connected before the clock signal output from the oscillator 26 is input to the transmission side IC chip 222. That is, the clock signal output from the oscillator 26 is branched in a previous stage input to the transmission side IC chip 222 and supplied to the clock signal transmission line 42 and the transmission side IC chip 222. A SAW filter 44 is provided on the clock signal transmission line 42. The SAW filter 44 is provided immediately before the clock signal is input to the receiving-side IC chip 50.
Even such a signal transmission device 102 can perform the same operation as the signal transmission device described in the first embodiment, and can obtain the same effect.

  Next, a third embodiment will be described. In the third embodiment, since a modification of the signal transmission device according to the first and second embodiments will be described, the same components as those of the signal transmission device according to the first and second embodiments are denoted by the same reference numerals. The description is omitted or simplified.

  FIG. 4 is a block diagram of a signal transmission apparatus according to the third embodiment. The signal transmission device 103 includes a transmission stage 203 including an oscillator 26 and a transmission-side IC chip 223 to which the oscillator 26 is connected. The transmission-side IC chip 223 includes a first PLL circuit 30 and a plurality of transmission units 24, and each transmission unit 24 is connected to the first PLL circuit 30. The input of the first PLL circuit 30 is connected to the oscillator 26. The signal transmission device 103 includes a reception-side IC chip 503 that includes a second PLL circuit 54 and a plurality of reception units 52, and each reception unit 52 is connected to the second PLL circuit 54. The transmission unit 24 is connected to the reception unit 52 on a one-to-one basis by the data signal transmission line 40. The input of the second PLL circuit 54 is connected to the oscillator 26 through the transmission side IC chip 223 by the clock signal transmission line 42. A SAW filter 44 is provided on the clock signal transmission line 42, and the SAW filter 44 is provided immediately before the clock signal is input to the reception-side IC chip 503 and in the vicinity of the reception-side IC chip 503.

  Such a signal transmission device 103 can transmit a plurality of data signals from the transmission side IC chip 223 to the reception side IC chip 503. And this signal transmission apparatus 103 can acquire the effect similar to the signal transmission apparatus demonstrated in 1st Embodiment.

  In FIG. 4, the clock signal transmission line 42 is connected to the transmission side IC chip 223 and the reception side IC chip 503 in the same manner as the signal transmission device according to the first embodiment, and the oscillator 26 is connected via the transmission side IC chip 223. A configuration for transmitting a clock signal to the reception-side IC chip 503 is shown. However, in this embodiment, the clock signal transmission line 42 is connected to the oscillator 26 and the reception-side IC chip 503 as in the signal transmission apparatus according to the second embodiment, and the clock signal is directly transmitted from the oscillator 26 to the reception-side IC chip 503. It may be configured to transmit.

In addition to the configuration of the signal transmission device described in the first to third embodiments, the signal transmission device is provided with a transmission unit in the reception-side IC chip, and a reception unit is provided in the transmission-side IC chip, which is used as a data signal. Connected by a transmission line, connected to an oscillator that outputs a clock signal to a transmission unit provided in the reception side IC chip, and provided a clock signal transmission line that guides this clock signal to the reception unit provided in the transmission side IC chip, In this clock signal transmission line, a SAW filter may be provided immediately before the clock signal is input to the transmission side IC chip. As a result, the transmission side IC chip and the reception side IC chip can transmit data signals to each other.
In the first to third embodiments, the oscillator 26 arranged near the transmitting IC chip is used as the clock signal source. However, a clock signal transmitted from another device is used instead of the oscillator 26. You can also.

1 is a block diagram of a signal transmission device according to a first embodiment. The block diagram of a 1st PLL circuit is shown. It is a block diagram of the signal transmission apparatus which concerns on 2nd Embodiment. It is a block diagram of the signal transmission apparatus which concerns on 3rd Embodiment. It is a block diagram which shows the modification of a signal transmission apparatus.

Explanation of symbols

10, 102, 103, 104 ............ signal transmission device 22, 222, 223, 224 ............ transmission side IC chip, 24 ............ transmission unit, 26 ............ oscillator, 30 ............ first PLL circuit, 40 ......... Data signal transmission line, 42 ......... Clock signal transmission line, 44 ......... SAW filter, 50, 503, 504 ......... Reception side IC chip, 52 ......... Reception unit, 54 ......... No. 2 PLL circuit.

Claims (13)

A clock signal transmission line through which the clock signal is transmitted;
A signal transmission device having a data signal transmission line through which a data signal synchronized with the clock signal is transmitted,
A signal transmission apparatus comprising a bandpass filter in the clock signal transmission line.   The signal transmission apparatus according to claim 1, wherein the band filter is a SAW filter.   3. The signal according to claim 1, wherein the clock signal is a spread spectrum clock signal spread in a predetermined frequency band, and the SAW filter is a band filter that passes the frequency band. Transmission equipment. An oscillator that outputs a clock signal;
A transmitter that converts parallel data into serial data and outputs the serial data in synchronization with the clock signal;
A signal transmission device having a receiving unit that receives the serial data and converts the serial data into parallel data based on the clock signal;
A signal transmission device comprising a bandpass filter in a clock signal transmission line for supplying the clock signal to the receiving unit.   The signal transmission apparatus according to claim 4, wherein the band filter is a SAW filter.   The clock signal transmitted from the oscillator to the receiving unit is a spread spectrum clock signal spread in a predetermined frequency band, and the band filter is a band filter that passes the frequency band. The signal transmission device according to claim 4 or 5. An oscillator that outputs a clock signal;
A transmission-side IC chip including a transmission unit connected to the oscillator and outputting a data signal in synchronization with the clock signal;
A receiving-side IC chip including a receiving unit for the data signal;
A data signal transmission line for connecting the transmitter and the receiver and transmitting the data signal;
A clock signal transmission line for transmitting the clock signal output from the oscillator to the receiving IC chip is provided,
A signal transmission apparatus comprising a SAW filter provided on the clock signal transmission line. A plurality of the transmission units are provided in the transmission side IC chip, and the reception units of the same number as the plurality of transmission units are provided in the reception side IC chip,
8. The signal transmission apparatus according to claim 7, wherein the transmission unit and the reception unit are connected one-to-one with the data signal transmission line. The clock signal transmission line connects between the transmission side IC chip and the reception side IC chip,
9. The signal transmission device according to claim 7, wherein the clock signal supplied to the transmission side IC chip is supplied to the clock signal transmission line.   The signal transmission device according to claim 7, wherein the clock signal transmission line connects the oscillator and the reception-side IC chip.   10. The phase synchronization circuit for increasing the frequency of the clock signal is provided in the transmission side IC chip, and the clock signal transmission line is connected to the output of the phase synchronization circuit. Signal transmission equipment.   11. The signal transmission device according to claim 7, wherein a phase synchronization circuit for increasing the frequency of the clock signal is provided in the transmission side IC chip and the reception side IC chip.   13. The signal transmission device according to claim 7, wherein the SAW filter is provided in the vicinity of the reception-side IC chip.

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