JP2007067473A - Quadrature error automatic compensating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defect in feedback control, even if there is deviation in the input signal, and to satisfy predetermined quadrature error compensating characteristics, using a simple circuit. <P>SOLUTION: The circuit is provided with a sum of squares calculating means for calculating sum of squares of an in-phase signal and a quadrature signal to be output from a quadrature error compensating means; a code inverting means for applying code inversion on an output of the square sum calculating means; a selecting means for outputting a first input, when a third input is the same code and outputting a second input when it is a different code, where the first input is the output of the square sum calculating means, the second input is the output of the code-inverting means, a third input is code information of the output of the quadrature error compensating means; an accumulative processing means for accumulating the output of the selecting means, stopping the accumulating adding processing, if the absolute value thereof exceeds the absolute value of the threshold, and outputting an addition signal/subtraction signal according to positive/negative state of an accumulated addition value; and an accumulator for outputting a value, increased by increment according to the addition signal/subtraction signal as a control signal to the quadrature error compensating means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is an automatic quadrature error compensating quadrature error in a quadrature detector that demodulates a digital modulation signal such as quadrature phase shift keying (QPSK) or multi-level QAM (quadrature amplitude modulation). The present invention relates to a compensation circuit.

  In a receiver of a digital modulation signal such as QPSK or multilevel QAM, a quadrature detector is used for separating the received signal into two in-phase and quadrature signal components and outputting them as baseband signals.

  In an ideal quadrature detector, the signal space diagram is a circle as shown by the solid line in FIG. However, in general, orthogonality between in-phase / quadrature channels is lost due to incompleteness of the quadrature detector such as quadrature error / gain error and DC offset, and the signal space diagram becomes an ellipse as shown by a broken line in FIG. Patent Document 1). For this reason, Patent Document 1 proposes a quadrature error detection circuit for an all-digital quadrature detector. Note that in the state where carrier synchronization and timing error are not established, phase rotation and intersymbol interference exist, and therefore the quadrature detector output is randomly distributed within the ellipse. Therefore, in the orthogonal error compensation circuit, control (orthogonal error compensation) is performed so that the existence probabilities of the received signals in each quadrant on the signal space diagram are equal.

  FIG. 4 shows a configuration example of a conventional orthogonal error automatic compensation circuit shown in Patent Document 1. In the figure, the in-phase signal input terminal 10 and the quadrature signal input terminal 20 are inputted with the quadrature detector output after removing unnecessary harmonics. The in-phase signal and the quadrature signal are input to the quadrature error compensation circuit 100, and are output to the in-phase signal output terminal 30 and the quadrature signal output terminal 40, respectively, as the in-phase signal and the quadrature signal compensated for the quadrature error. The orthogonal error compensation control in the orthogonal error compensation circuit 100 is performed as follows.

  The square operation circuits 110 and 120 and the adder circuit 130 receive the in-phase signal and the quadrature signal output from the quadrature error compensation circuit 100 and calculate the sum of squares (power). The sign inversion circuit 140 inverts the sign of the output of the addition circuit 130. The selection circuit 150 inputs the code bits of the in-phase signal and the quadrature signal output from the quadrature error compensation circuit 100, and the same code (when the arrangement on the signal space diagram of the received signal is in the first quadrant and the third quadrant). ), The output signal of the adder circuit 130 is selected, and the output signal of the sign inverting circuit 140 is selected and output if the different sign (if the arrangement of the received signal on the signal space diagram is in the second quadrant and the fourth quadrant). . The output signal of the selection circuit 150 is cumulatively added by the cumulative addition circuit 160. Here, since the transmission signal sequence is random, the bias of the signal points on the signal space diagram is detected by cumulatively adding the output signal of the selection circuit 150 to a certain number of received symbols. The output signal of the cumulative conversion circuit 160 is smoothed by a low-pass filter (LPF) 170 and used as a control signal for the orthogonal error compensation circuit 100. By such feedback control, orthogonal error compensation can be automatically performed.

The shape of the signal space diagram is independent of carrier synchronization and timing synchronization. Accordingly, the conventional orthogonal error automatic compensation circuit operates without deterioration even if carrier synchronization and timing synchronization are not established.
JP 2004-248115 A Hiroshi Suzuki, Hitoshi Yoshino, “Affine Transform Linear Distortion Compensation-Application to Linear Signal Transmission including Equalization in Mobile Radio Communications”, IEICE Transactions B-II, Vol. J75-B-II, No. 1, pp.1-9, January 1992

  In the conventional orthogonal error automatic compensation circuit shown in FIG. 4, the value accumulated by the accumulation adding circuit 160 is not cleared other than being initialized when the apparatus is turned on. For this reason, there is a bias in the transmission signal that occurs during long-time operation, that is, a situation in which the signal point arrangement of the received signal appears only in a specific quadrant, for example, “0” or “1” continues. Alternatively, in a situation where a “01” alternation or the like occurs, the value of the cumulative addition circuit 160 may increase.

  If an overflow occurs in the cumulative addition circuit 160 due to such a reason, the monotonous increase (or monotonic decrease) of the control signal to the orthogonal error compensation circuit 100 is lost, and feedback control for orthogonal error correction fails. . For this reason, when designing the cumulative addition circuit 160, it is necessary to provide a sufficient margin so as not to overflow. However, this margin depends on the deterministic pattern itself that makes up the frame of the system, its length, error correction used in the data section, scrambler design parameters, etc., so accurate estimation is difficult and more than necessary. A margin will be taken.

  An object of the present invention is to provide an automatic quadrature error compensation circuit that can prevent failure of feedback control even when an input signal is biased and can satisfy a predetermined quadrature error compensation characteristic with a simple circuit.

  1st invention inputs the in-phase signal and quadrature signal which removed the unnecessary harmonic from the output of a quadrature detector, and outputs the in-phase signal and quadrature signal which compensated the quadrature error according to the control signal A square sum operation means for inputting the in-phase signal and the quadrature signal output from the quadrature error compensation means and calculating a sum of squares thereof; a sign inversion means for inverting the sign of the output of the square sum operation means; and a sum of squares The output of the computing means is the first input, the output of the sign inverting means is the second input, the in-phase signal and the quadrature signal code information output from the quadrature error compensation means are the third input, When the input is the same sign, the first input is output, and when the third input is a different sign, the selection means for outputting the second input and the absolute value of the threshold value are input from the outside, and the output of the selection means And the absolute value of the cumulative addition value is the threshold value. The cumulative addition process is stopped when the absolute value exceeds the absolute value, and an addition signal is output if the cumulative addition value is positive, and a subtraction signal is output if the cumulative addition value is negative. When a step size is input and an addition signal is input from the accumulation processing means, a value obtained by increasing the step size to the previous value is output to the orthogonal error compensation means as a control signal, and a subtraction signal is input from the accumulation processing means And an accumulator that outputs a value obtained by reducing the step size to the immediately preceding value to the orthogonal error compensation means as a control signal.

  In the first invention, the cumulative processing means cumulatively adds the outputs of the selection means, and stops the cumulative addition processing when the absolute value of the cumulative addition value exceeds the absolute value of the threshold value set from outside, If the addition value is a positive value, an addition signal is output to the subsequent accumulator, and if it is a negative value, a subtraction signal is output. The accumulator performs a process of increasing / decreasing a control signal given to the orthogonal error compensation means in units of a predetermined step based on the addition signal or the subtraction signal. As a result, the quadrature error compensation means guarantees monotonic increase or monotonic decrease of the compensation signal output for the quadrature error, and even if the input signal is biased, the circuit operation does not fail and avoids performance degradation. be able to.

  In the second invention, as the accumulation processing means in the first invention, the absolute value of the threshold value is inputted from the outside, the output of the selection means is cumulatively added, and the absolute value of the cumulative addition value exceeds the absolute value of the threshold value The cumulative addition circuit stops the cumulative addition process and outputs + (threshold) if the cumulative addition value is positive, and-(threshold) if the cumulative addition value is negative, and the absolute value of the threshold from the outside. When the output of the cumulative addition circuit is + (threshold), an addition signal is output. When the output is-(threshold), a threshold comparison circuit that outputs a subtraction signal is used.

  According to a third invention, as the accumulation processing means in the first invention, an absolute value of the threshold value is inputted from the outside, and a count operation of +1 or −1 is performed according to the sign bit of the output of the selection means. An up / down counter that stops the counting operation when the absolute value exceeds the absolute value of the threshold value, and outputs + (threshold value) if the count value is a positive value, and-(threshold value) if the count value is a negative value; A configuration using a threshold comparison circuit that inputs an absolute value of a threshold value from the outside, outputs an addition signal if the output of the up / down counter is + (threshold value), and outputs a subtraction signal if the output value is-(threshold value). is there.

  The accumulation processing means (cumulative addition circuit or up / down counter and threshold comparison circuit) and accumulator function as a loop filter in feedback control of the orthogonal error automatic compensation circuit as a whole. The threshold value set from the outside and the step size of the accumulator are parameters that affect the frequency characteristics and delay characteristics of the low-pass filter. Therefore, the values of these parameters are designed to be optimum values as a loop filter.

  The fourth invention is a quadrature error compensation for inputting an in-phase signal and a quadrature signal from which unnecessary harmonics are removed from the output of the quadrature detector, and outputting the in-phase signal and the quadrature signal in which the quadrature error is compensated according to the control signal. The absolute value of the threshold value is inputted from the outside and the sign signal of the in-phase signal and the quadrature signal outputted from the quadrature error compensation means, and +1 or -1 depending on whether each signal is the same sign or different sign When the absolute value of the count value exceeds the absolute value of the threshold value, the count operation is stopped, and if the count value is a positive value, + (threshold), and if the count value is negative, − An up / down counter that outputs (threshold) and an absolute value of the threshold from the outside are input. If the output of the up / down counter is + (threshold), an addition signal is output, and if it is − (threshold), a subtraction signal is output. Output threshold comparison times When a step size is input from the outside and an addition signal is input from the threshold comparison circuit, a value obtained by increasing the step size to the previous value is output as a control signal to be supplied to the orthogonal error compensation means, and subtracted from the threshold comparison circuit. And an accumulator that outputs, as a control signal, to the orthogonal error compensator, a value obtained by decreasing the step size to the previous value when the signal is input.

  In the fourth aspect of the invention, it is possible to detect the quadrature error only by determining the quadrant on the signal point arrangement of the input signal, and count it to generate a control signal to be supplied to the quadrature error compensation means as in the third aspect. . As a result, the configuration of the orthogonal error automatic compensation circuit can be greatly simplified.

  The quadrature error automatic compensation circuit of the present invention can prevent failure of feedback control due to overflow in the accumulation processing means even if the input signal is biased with a simple circuit configuration, and satisfies a predetermined quadrature error compensation characteristic. be able to.

(First embodiment)
FIG. 1 shows a first embodiment of the present invention. In the figure, the in-phase signal input terminal 10 and the quadrature signal input terminal 20 are inputted with the quadrature detector output after removing unnecessary harmonics. The in-phase signal and the quadrature signal are input to the quadrature error compensation circuit 100, and output to the in-phase signal output terminal 30 and the quadrature signal output terminal 40, respectively, as the in-phase signal and the quadrature signal in which the quadrature error is compensated. The orthogonal error compensation control in the orthogonal error compensation circuit 100 is performed as follows.

  The sum-of-squares calculation means comprising the square calculation circuits 110 and 120 and the addition circuit 130 inputs the in-phase signal and the quadrature signal output from the quadrature error compensation circuit 100 and calculates the sum of squares (power). The sign inversion circuit 140 inverts the sign of the output of the addition circuit 130. The selection circuit 150 receives the sign bits of the in-phase signal and the quadrature signal output from the quadrature error compensation circuit 100. If the sign is the same, the selection circuit 150 outputs the output signal of the adder circuit 130. Select the output signal and output it. The output signal of the selection circuit 150 is cumulatively added by the cumulative addition circuit 200.

  The cumulative addition circuit 200 inputs the absolute value of the threshold value from the outside, stops the cumulative addition process when the absolute value of the cumulative addition value exceeds the absolute value of the threshold value, and if the cumulative addition value is a positive value. For example, + (threshold) is output to the threshold comparison circuit 210. The threshold value comparison circuit 210 inputs the absolute value of the threshold value from the outside, and outputs an addition signal to the accumulator 220 if the output of the cumulative addition circuit 200 is + (threshold value) or-(threshold value). The accumulator 220 receives a step size from the outside, and based on the addition signal or the subtraction signal input from the threshold comparison circuit 210, performs a process of increasing / decreasing the control signal given to the orthogonal error compensation circuit 100 from the current value in increments of the step size. Do. In the orthogonal error compensation circuit 100, feedback control is performed by the control signal that is increased or decreased in increments of increments in this way, and compensation for the orthogonal error of the orthogonal detector can be automatically performed.

  In the cumulative addition circuit 200, the cumulative addition value may be cleared at the timing when the subsequent-stage threshold comparison circuit 210 outputs the addition signal or the subtraction signal.

(Second Embodiment)
FIG. 2 shows a second embodiment of the present invention. The feature of this embodiment is that the cumulative addition circuit 200 in the first embodiment is replaced with an up / down counter 205, and the count operation is performed on the sign bit of the output signal of the selection circuit 150. Other configurations are the same as those of the first embodiment.

  The up / down counter 205 performs a count operation of +1 or −1 according to the sign bit of the output of the selection circuit 150, and stops the count operation when the absolute value of the count value exceeds the absolute value of the threshold, If the value is a positive value, + (threshold value) is output to the threshold value comparison circuit 210, and if the value is negative,-(threshold value) is output. The operations of the threshold comparison circuit 210 and the accumulator 220 are the same as those in the first embodiment. By using such an up / down counter 205, an orthogonal error compensation operation equivalent to that of the first embodiment can be realized with a simple configuration.

(Third embodiment)
FIG. 3 shows a third embodiment of the present invention. The feature of this embodiment is that the square operation circuits 110 and 120, the adder circuit 130, the sign inversion circuit 140, and the selection circuit 150 in the second embodiment are omitted, and the in-phase signal and the quadrature signal output from the quadrature error compensation circuit 100 are omitted. Is directly input to the up / down counter 207. Other configurations are the same as those of the second embodiment.

  The up / down counter 207 inputs the in-phase signal output from the quadrature error compensation circuit 100 and the sign bit of the quadrature signal, performs a count operation of +1 or −1 depending on whether each signal is the same sign or different sign, When the absolute value of the count value exceeds the absolute value of the threshold value, the count operation is stopped, and if the count value is a positive value, + (threshold value), and if the count value is a negative value,-(threshold value) is compared with the threshold value. Output to the circuit 210. The operations of the threshold comparison circuit 210 and the accumulator 220 are the same as those in the second embodiment (first embodiment). That is, in the configuration of the present embodiment, the orthogonal error is detected only by the quadrant determination on the signal point arrangement of the input signal, so that it is equivalent to the first embodiment and the second embodiment with a simple configuration. An orthogonal error compensation operation can be realized.

  In the case of burst transmission, the characteristics of the quadrature detector on the receiving side do not change even if the transmission partner is different. Therefore, in any configuration of the first to third embodiments, the circuit is operated only during the period when the signal arrives. It can respond by doing.

The figure which shows the structural example of the 1st Embodiment of this invention. The figure which shows the structural example of the 2nd Embodiment of this invention. The figure which shows the structural example of the 3rd Embodiment of this invention. The figure which shows the structural example of the conventional orthogonal error automatic compensation circuit. The figure which shows a signal space diagram.

Explanation of symbols

10 In-phase signal (in-phase channel output of quadrature detector) input terminal 20 Quadrature signal (orthogonal channel output of quadrature detector) input terminal 30 In-phase signal (in-phase channel output of quadrature error compensation circuit) output terminal 40 Quadrature signal (quadrature) Orthogonal channel output of error compensation circuit) Output terminal 100 Orthogonal error compensation circuit 110, 120 Square operation circuit 130 Addition circuit 140 Sign inversion circuit 150 Selection circuit 160 Cumulative addition circuit 170 Low-pass filter (LPF)
200 Cumulative addition circuit 205, 207 Up / down counter 210 Threshold comparison circuit 220 Accumulator

Claims (4)

Quadrature error compensation means for inputting an in-phase signal and a quadrature signal from which unnecessary harmonics have been removed from the output of the quadrature detector, and outputting an in-phase signal and a quadrature signal in which quadrature error is compensated according to the control signal;
A sum-of-squares calculation means for inputting the in-phase signal and the quadrature signal output from the quadrature error compensation means and calculating the sum of squares thereof;
Sign inverting means for inverting the output of the sum of squares calculating means;
The output of the sum of squares computing means is a first input, the output of the sign inverting means is a second input, and the code information of the in-phase signal and quadrature signal output from the quadrature error compensation means is a third input. Selecting means for outputting the first input when the third input has the same sign, and outputting the second input when the third input has a different sign;
The absolute value of the threshold value is input from the outside, and the output of the selection means is cumulatively added. When the absolute value of the cumulative added value exceeds the absolute value of the threshold value, the cumulative addition process is stopped and the cumulative added value is correct. A cumulative processing means for outputting an addition signal if the value is negative, and outputting a subtraction signal if the value is negative;
When the step size is input from the outside and the addition signal is input from the accumulation processing unit, a value obtained by increasing the step size to the previous value is output to the orthogonal error compensation unit as the control signal, and the accumulation processing unit And an accumulator that outputs, as the control signal, a value obtained by reducing the step size to the previous value when the subtraction signal is input to the orthogonal error compensation means. In the orthogonal error automatic compensation circuit according to claim 1,
The cumulative processing means includes
The absolute value of the threshold value is input from the outside, and the output of the selection means is cumulatively added. When the absolute value of the cumulative added value exceeds the absolute value of the threshold value, the cumulative addition process is stopped and the cumulative added value is correct. A cumulative addition circuit that outputs + (threshold value) if the value is negative, and-(threshold value) if the value is negative;
A threshold comparison circuit for inputting an absolute value of the threshold from the outside, outputting an addition signal if the output of the cumulative addition circuit is + (threshold), and outputting a subtraction signal if the output is-(threshold). An automatic orthogonal error compensation circuit characterized by the above. In the orthogonal error automatic compensation circuit according to claim 1,
The cumulative processing means includes
An absolute value of the threshold value is input from the outside, and a count operation of +1 or -1 is performed according to the sign bit of the output of the selection means, and the count operation is stopped when the absolute value of the count value exceeds the absolute value of the threshold value And an up / down counter that outputs + (threshold value) if the count value is a positive value, and-(threshold value) if the count value is a negative value,
A threshold comparison circuit for inputting an absolute value of the threshold value from the outside, outputting an addition signal if the output of the up / down counter is + (threshold value), and outputting a subtraction signal if the output value is-(threshold value). An automatic orthogonal error compensation circuit characterized by the above. Quadrature error compensation means for inputting an in-phase signal and a quadrature signal from which unnecessary harmonics have been removed from the output of the quadrature detector, and outputting an in-phase signal and a quadrature signal in which quadrature error is compensated according to the control signal;
The absolute value of the threshold is input from the outside, the in-phase signal output from the quadrature error compensation means and the sign bit of the quadrature signal are input, and a count of +1 or −1 is made depending on whether each signal is the same sign or different sign When the absolute value of the count value exceeds the absolute value of the threshold value, the count operation is stopped, and if the count value is a positive value, + (threshold value), if the count value is a negative value,-(threshold value) ) Output up / down counter,
A threshold comparison circuit for inputting an absolute value of the threshold from the outside, outputting an addition signal if the output of the up / down counter is + (threshold), and outputting a subtraction signal if-(threshold);
When the step size is input from the outside and the addition signal is input from the threshold value comparison circuit, a value obtained by increasing the step size to the previous value is output as the control signal to be supplied to the orthogonal error compensation unit, and the threshold value comparison is performed. An accumulator that outputs an accumulator as a control signal that gives a value obtained by decreasing the step size to the previous value when the subtraction signal is input from the circuit to the quadrature error compensation means. .

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