JP3360691B2 - Detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a π / 4 shift QPSK.
The present invention relates to a detection circuit suitable for detecting a wave.

[0002]

2. Description of the Related Art In order to detect a π / 4 shift QPSK signal, it is necessary to set the frequency of a signal input to a detection circuit to a predetermined frequency. As described above, as an AFC (automatic frequency control circuit) that automatically controls the frequency, a tank input / output phase difference detection type AFC, a baseband beat signal detection type AFC, a reference signal comparison type AFC, and the like are known.

In these conventional devices, the oscillation frequency of a local oscillator used to generate an intermediate frequency (IF) is controlled in accordance with a frequency error so that the intermediate frequency (IF) becomes a predetermined frequency. Like that.

[0004]

In the conventional apparatus, the frequency of the local oscillator in the IF signal generation stage is controlled as described above. Therefore, noise tends to be applied to a control signal line for controlling the local oscillator. , S / N deteriorated.

[0005] The present invention has been made in view of such a situation, and suppresses deterioration of S / N.

[0006]

A detection circuit according to the present invention comprises delay detection circuits 41 and 42 as first detection means for detecting an input signal by delaying one symbol, and delay detection circuits 41 and 42.
The ternary decision circuits 15 and 18 as first level decision means for deciding the level of the output of 42,
18, a phase difference determination circuit 25 as first phase determination means for determining the phase of the output, and a delay detection circuit 4 as second detection means for detecting the input signal by delaying a plurality of symbols by a plurality of symbols.
Ternary judgment circuit 1 as second level judgment means for judging the output level of delay detection circuits 43 and 44
6, 19, and a phase difference determination circuit 24 as second phase determination means for determining the phase of the output of the ternary determination circuits 16, 19.
And binary decision circuits 14 and 17 as third level decision means for determining the output levels of the delay detection circuits 41 and 42
A phase difference judging circuit 20 as a third phase judging means for judging the phases of the outputs of the binary judging circuits 14 and 17, and an input signal from the output of the phase difference judging circuit 24 and the output of the phase difference judging circuit 20. And a detection circuit 45 as detection means for detecting a frequency shift of the signal.

In the ternary decision circuits 15 and 18, the output levels of the delay detection circuits 41 and 42 can be decided into three values. In this determination, a first level larger than the reference level and a second level smaller than the reference level are provided, and the outputs of the delay detection circuits 41 and 42 are set to a value larger than the first level, which is higher than the first level. The determination can be made based on which of three values, that is, a value that is smaller and larger than the second level and a value that is smaller than the second level.

A correction circuit 27 as correction means for correcting the output of the phase difference determination circuit 25 in accordance with the output of the detection circuit 45 can be further provided. The detection circuit 45
, A control circuit 32 may be further provided as control means for controlling the delay time of the delay detection circuits 41 and 42.

[0009]

In the detection circuit having the above configuration, the input signal is set to 1
A frequency shift is detected from the determination results corresponding to the outputs of the delay detection circuits 41 and 42 that detect with a symbol delay and the determination results corresponding to the outputs of the delay detection circuits 43 and 44 that detect with a delay of a plurality of symbols. Is done. Therefore, the configuration is simplified, the frequency can be estimated in the baseband, and the deterioration of the S / N is suppressed.

[0010]

FIG. 1 is a block diagram showing a configuration of an embodiment of a .pi. / 4 shift QPSK wave detection circuit according to the present invention. I
The F amplifier 1 saturates and amplifies the input intermediate frequency (IF) signal, and outputs the signal to the delay detection circuits 41 and 42. The delay detection circuit 41 includes a delay circuit 2 that delays the input signal by one symbol and outputs the signal, an exclusive OR circuit 3 that calculates an exclusive OR of a signal delayed by the delay circuit 2 and a signal that is not delayed. And a low-pass filter 4 for removing unnecessary high-frequency components of the output of the exclusive OR circuit 3. The delay detection circuit 41 delay-detects the I component.

On the other hand, the delay detection circuit 42 calculates the exclusive OR of the delay circuit 8 for delaying the input signal by one symbol and outputting the signal, the signal delayed by the delay circuit 8, and the signal not delayed. Exclusive OR circuit 9
And a low-pass filter 10 for removing unnecessary high-frequency components from the output of the exclusive OR circuit 9. The delay detection circuit 42 delay-detects the Q component.

The output of the delay circuit 2 is also supplied to a delay circuit 5, and after being further delayed by one symbol, is supplied to an exclusive OR circuit 6.
The exclusive OR circuit 6 calculates the exclusive OR of the signal input from the delay circuit 5 and the signal input from the IF amplifier 1 and outputs the result to the low-pass filter 7. The delay circuits 2 and 5 and the exclusive OR circuit 6
The low-pass filter 7 constitutes a delay detection circuit 43 that delays the input signal by two symbols and delay-detects the I component.

Similarly, a delay circuit 11 is connected to the subsequent stage of the delay circuit 8, and a signal delayed by one symbol by the delay circuit 11 is supplied to an exclusive OR circuit 12. The exclusive OR circuit 12 calculates the exclusive OR of the signal input from the delay circuit 11 and the signal input from the IF amplifier 1, and outputs the result to the low-pass filter 13. The delay circuits 8, 1
1. The exclusive OR circuit 12 and the low-pass filter 13 constitute a delay detection circuit 44 for delaying the input signal by two symbols and delay-detecting the Q component.

The output of the low-pass filter 4 is supplied to a ternary decision circuit 15 so that its level is ternary decided. Then, the determination result is supplied to the phase difference determination circuit 25. Further, the output of the low-pass filter 10 is supplied to a ternary determination circuit 18 where ternary determination is performed, and the determination result is supplied to a phase difference determination circuit 25. The output of the low-pass filter 7 is supplied to a ternary decision circuit 16 where ternary decision is made, and the decision result is output to a phase difference decision circuit 24.
Supplied to The output of the low-pass filter 13 is
The ternary data is supplied to the ternary determination circuit 19 where the ternary value is determined. The result of the determination is supplied to the phase difference determination circuit 24. further,
The output of the low-pass filter 4 is supplied to a binary determination circuit 14, and after the binary determination, the determination result is supplied to a phase difference determination circuit 20. The low-pass filter 10
Is supplied to the binary decision circuit 17, and after the binary decision, the decision result is supplied to the phase difference decision circuit 20.

The output of the phase difference judging circuit 20 is
, And after being delayed by one symbol by a one-symbol delay circuit 21, is supplied to an adder 22,
The signal is added to the signal supplied from the phase difference determination circuit 20. Then, the output of the adder 22 is supplied to a subtractor 23, and is subtracted from the output of the phase difference determination circuit 24. The output of the subtracter 23 is supplied to an integrating circuit 26. The integrating circuit 26 integrates a signal supplied from the subtractor 23 in synchronization with an integrating timing signal supplied from a CPU (not shown) or the like.

This delay circuit 21, adder 22, subtractor 2
A detection circuit 45 for detecting a frequency shift is constituted by the 3 and the integrating circuit 26.

The preamble detecting circuit 29 detects a preamble from the output of the phase difference judging circuit 24, supplies the detection signal as a reset signal to the integrating circuit 26, and as a high-speed symbol synchronization signal for resetting the PLL (not shown). It is supplied to a PLL.
The preamble detection circuit 29 is supplied with a synchronization establishment signal output from the CPU as a disable signal.

The correction circuit 27 generates a correction signal corresponding to the output of the phase difference determination circuit 25 and the output of the integration circuit 26,
It is output to the adder 28. The adder 28 adds the output of the phase difference determination circuit 25 and the output of the correction circuit 27, and outputs the result to the phase data conversion circuit 31. The phase data conversion circuit 31 converts the signal supplied from the adder 28 into demodulated data and outputs the demodulated data to a CPU (not shown).

The output of the integrating circuit 26 is supplied to a latch circuit 30. After being latched, the output is supplied to a circuit (not shown) as a signal representing a frequency shift, and is also supplied to a control circuit 32. . The control circuit 32 controls the delay times of the delay circuits 2, 5, 8, and 11 in accordance with the output of the latch circuit 30.

Next, the operation will be described. The signal saturated and amplified by the IF amplifier 1 is input by a delay detection circuit 41 including a one-symbol delay circuit 2, an exclusive OR circuit 3, and a low-pass filter 4.
The components are differentially detected. The signal output from the low-pass filter 4 is supplied to a ternary determination circuit 15 where the ternary determination is performed.

As shown in FIG. 2, the ternary determination circuit 15
A level I ₁ that is greater than a zero level as a reference level,
It has a level I ₂ smaller than the 0 level as a threshold. Then, the level of the signal input from the low-pass filter 4 is compared with the levels I ₁ and I _2, and when the level of the signal input from the low-pass filter 4 is higher than the level I ₁ , the level is lower than H and I _1. The ternary determination result of M when it is larger than I ₂ and L when it is smaller than I ₂ is output to the phase difference determination circuit 25 as 2-bit data.

On the other hand, the Q component signal delayed and detected by the delay detection circuit 42 including the one-symbol delay circuit 8, the exclusive OR circuit 9, and the low-pass filter 10 is supplied to the ternary decision circuit 18, Is determined.

That is, as shown in FIG. 2, the ternary determination circuit 18 outputs a level Q higher than the 0 level as a reference level.
_1, a small level Q ₂ from 0 level, has as a threshold, compares the level of the input signal from the low pass filter 10, and the level Q _1, Q _2. The level of the signal input from the low-pass filter 10 is the level Q ₁
The ternary determination result of H when it is larger, M smaller than Q ₁ and M when it is larger than Q ₂ , and L when it is smaller than Q ₂ is output to the phase difference determination circuit 25 as 2-bit data.

As described above, the phase difference determination circuit 25
The three-valued determination result of H, M, and L in the component and the three-valued determination result of H, M, and L in the Q component are input. As shown in FIG. 2, when the I component is plotted on the horizontal axis, the Q component is plotted on the vertical axis, points on the I axis are set to 0, and positions 45 degrees apart in a counterclockwise direction are set to 1 to 7, respectively. The position of the phase of the π / 4 shift QPSK signal is one of 1, 3, 5, and 7.

When the ternary decision result of the I component is H, the phase position of the signal is one of 0, 1, and 7. When the determination result of the I component is M, the phase position is 2 or 6. When the determination result is L, the phase position is 3, 4, or 5. Similarly,
When the ternary determination result of the Q component is H, the phase position of the signal is one of 1 to 3, and when the determination result of the I component is M, the phase position is 0 or 4, and the determination result is Is L, the phase position is one of 5 to 7. Therefore, the phase difference determination circuit 25 can make the determination shown in FIG. 3 from the three-value determination results of the I and Q components.

That is, when the determination result of the I component is H, M, L and the determination result of the Q component is H, the phase position is
1, 2, or 3. The judgment result of the I component is H or L
When the determination result of the Q component is M, the phase position is 0 or 4. Also, if the determination result of the I component is H,
In the case of M and L, if the determination result of the Q component is L, the phase position is 7, 6, or 5.

The phase difference determination circuit 25 outputs the result of this determination to the adder 28 and the correction circuit 27. The signal input to the adder 28 is added (corrected) to the signal output from the correction circuit 27 and supplied to the phase data conversion circuit 31 as a final determination result.

Next, the operation of this correction will be described. The output detected by the delay detection circuit 43 including the one-symbol delay circuits 2 and 5, the exclusive OR circuit 6, and the low-pass filter 7 is supplied to the ternary decision circuit 16. The ternary determination is performed, and the determination result is supplied to the phase difference determination circuit 24. Similarly, one-symbol delay circuits 8, 1
1. The output delayed and detected by the delay detection circuit 44 composed of the exclusive OR circuit 12 and the low-pass filter 13 is supplied to the ternary determination circuit 19, and the ternary determination is performed. It is supplied to the judgment circuit 24.

The phase difference judging circuit 24 comprises a phase difference judging circuit 2
As in the case of 5, the phase positions 0 to 7 of the π / 4 shift QPSK signal are determined from the three-value determination results of the I component and the Q component, and the determination result is output to the subtractor 23. The difference between the determination results in the phase difference determination circuit 24 and the phase difference determination circuit 25 is determined by the phase difference determination circuit 25 determining the phase position from the outputs of the delay detection circuits 41 and 42 that detect the input signal by delaying one symbol. The phase difference determination circuit 2
Reference numeral 4 indicates that the phase position is determined in accordance with the outputs of the delay detection circuits 43 and 44 which detect the input signal with a delay of two symbols.

On the other hand, the binary decision circuit 14 makes a binary decision on the output of the delay detection circuit 41 for detecting the input signal of the I component with one symbol delay, as shown in FIG. That is, the binary determination circuit 14 determines whether the level of the signal input from the low-pass filter 4 is greater than or less than the 0 level as a threshold value. Output to the judgment circuit 20.

Similarly, the binary decision circuit 17 makes a binary decision on the signal level of the Q component output from the low-pass filter 10, and when the level is larger than the zero level as a threshold, the decision result is L when the level is smaller. To the phase difference determination circuit 20
Output to

The binary judgments H and L of the I component and the binary judgments H and L of the Q component are input to the phase difference judgment circuit 20 in this way. As shown in FIG. 4, when it is determined that the I component is H, the phase position of the input signal is 0, 1, or 7, and when it is L, it is one of 3 to 5. When the Q component is H, the phase position of the input signal is one of 1 to 3, and when it is L, it is one of 5 to 7. Therefore, as shown in FIG. 5, when both the I component and the Q component are H, the phase position is determined to be 1, and when the I component is L and the Q component is H, the phase position is 3
Is determined. Similarly, if the I component is H and Q
When the component is L, the phase position is determined to be 7. When both the I component and the Q component are L, the phase position is determined to be 5. The phase difference determination circuit 20 outputs the determination result of the phase position of 1, 3, 5, or 7.

The output of the phase difference judging circuit 20 is delayed by one symbol by the one-symbol delay circuit 21;
Those not delayed are added in the adder 22. The adder 22 performs modulo 8 addition.

That is, the delay circuit 21 and the adder 22 generate a signal having the same level as that obtained when the phase difference determination circuit 24 determines a signal obtained by detecting the input signal by delaying two symbols. This signal is used as the subtractor 23
And is subtracted from the signal output by the phase difference determination circuit 24. The signal output from the phase difference determination circuit 24 is generated based on the signal delayed by two symbols in the delay detection circuits 43 and 44. On the other hand, the adder 22
Are generated based on signals detected by the delay detection circuits 41 and 42 with one symbol delay. In general, as the number of delay symbols in the delay detection circuit increases, the detection performance against frequency fluctuations deteriorates accordingly. In other words, the delay detection circuit that performs detection by delaying one symbol has a 1 / n deterioration in detection performance compared to the delay detection circuit that detects by delaying n symbols.

Therefore, the signal output from the subtractor 23 is 1
When both the symbol delay detection circuits 41 and 42 and the two-symbol delay detection circuits 43 and 44 are demodulating correct data, the value becomes 0, and it can be estimated that there is no frequency error. In other words, the output of the subtracter 23 is positive (+1) when the frequency of the signal input from the IF amplifier 1 is shifted to the higher side, and is negative (-1) when the frequency is shifted to the lower side. Become.

The integrating circuit 26 integrates the signal output from the subtractor 23 in synchronization with the input integration timing.
The preamble detection circuit 29 detects a preamble (the preamble is periodically arranged at a predetermined position of a time slot of a signal detected by the present apparatus) from a signal output from the phase difference determination circuit 24. The integration circuit 26 resets the integrated value when the detection signal is input from the preamble detection circuit 29. In this way, the integrating circuit 26 outputs the integrated value of the output of the subtractor 23 during a predetermined period.

The correction circuit 27 monitors the polarity (positive or negative) of the integrated value of the integration circuit 26 and the output (phase positions 0 to 7) of the phase difference determination circuit 25, and generates a correction signal. This correction signal is set to 0 when the phase position output from the phase difference determination circuit 25 is 1, 3, 5, or 7. That is, at this time, the signal of the phase position output from the phase difference determination circuit 25 is supplied to the phase data conversion circuit 31 via the adder 28 as it is.

On the other hand, when the phase position output from the phase difference determination circuit 25 is 0, 2, 4, or 6, if the integrated value in the integration circuit 26 is positive, the correction signal is set to plus one. , If negative, it is set to -1. Since this correction signal is added to the output of the phase difference determination circuit 25 in the adder 28, the output of the adder 28
Is 0, 2, 4 or 6, when the integrated value of the integrating circuit 26 is positive, they are 1, 3, 5 or 7, respectively. When the integrated value is negative, 7, 1 or , 3 or 5.

As described above, the output of the adder 28 is any one of the four phase positions 1, 3, 5, and 7 in FIG. That is, it is determined here which of the four phase positions of the π / 4 shift QPSK is. Then, the phase position data is input to the phase data conversion circuit 31 and is converted into demodulated data.

On the other hand, the integrated value of the integrating circuit 26 is latched by the latch circuit 30 immediately before being reset by the reset signal output from the preamble detecting circuit 29,
The control circuit 32 controls the delay amounts of the delay circuits 2, 5, 8 and 11 according to the latch result. That is, when the value latched by the latch circuit 30 is positive, the frequency of the IF signal is shifted to the higher side, so that the control circuit 32 reduces the delay amount of the delay circuit 2, 5, 8, or 11 so that the delay amount becomes small. Control. Conversely, when the value latched by the latch circuit 30 is negative, the frequency of the IF signal is shifted to the lower side, so that the delay time in each delay circuit is switched to be longer.

Each of the delay circuits 2, 5, 8 or 11 has a built-in shift register of, for example, 100 stages, and the delay time is controlled by changing the number of stages. When the frequency of the intermediate frequency signal input to the IF amplifier 1 is 1.2 MHz and the clocks of the delay circuits 2, 5, 8, and 11 are 19.2 MHz, each symbol is processed in each delay circuit at a rate of 192 Ksps. Will be.

As described above, in this embodiment, it is possible to detect a frequency shift in the baseband and make correction accompanying it.

In the above embodiment, the delay detection circuits 43 and 44 delay two symbols.
It is possible to delay by n (n ≧ 3) symbols.

[0044]

As described above, according to the detection circuit of the present invention,
A frequency shift of the input signal is detected by using an output of the first detection means for detecting the input signal with one symbol delay and an output of the second detection means for detecting the input signal with a delay of a plurality of symbols. Therefore, the processing can be completed inside the demodulation circuit that demodulates the intermediate frequency, and the deterioration of the S / N can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a detection circuit according to an embodiment of the present invention.

FIG. 2 is a ternary decision circuit 15, 1 in the embodiment of FIG.
It is a figure explaining operation | movement of 6,18,19.

FIG. 3 is a diagram illustrating a phase difference determination circuit according to the embodiment of FIG. 1;
FIG. 9 is a diagram illustrating a determination operation of No. 5;

FIG. 4 is a diagram showing binary decision circuits 14 and 17 in the embodiment of FIG. 1;
It is a figure explaining operation of.

FIG. 5 is a diagram illustrating a determination operation of a phase difference determination circuit 20 in the embodiment of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 IF amplifier 2 delay circuit 3 exclusive OR circuit 5, 8 delay circuit 9 exclusive OR circuit 11 delay circuit 12 exclusive OR circuit 14 binary decision circuit 15, 16 ternary decision circuit 17 binary decision circuit 18 , 19 ternary judgment circuit 20 phase difference judgment circuit 21 delay circuit 22 adder 23 subtractor 24, 25 phase difference judgment circuit 26 integration circuit 27 correction circuit 28 adder 32 control circuits 41 to 44 delay detection circuit 45 detection circuit

Claims (5)

(57) [Claims] 1. A first detector for detecting an input signal by delaying one symbol, a first level determiner for determining an output level of the first detector, and a first level determiner. To determine the phase of the output of
Phase detecting means, second detecting means for detecting an input signal by delaying a plurality of symbols, second level determining means for determining an output level of the second detecting means, and second level determining means Second to determine the phase of the output of the means
Phase determining means, third level determining means for determining the level of the output of the first detecting means, and third level determining means for determining the phase of the output of the third level determining means.
A detection circuit for detecting a frequency shift of an input signal from an output of the second phase determination device and an output of the third phase determination device. 2. The method according to claim 1, wherein the first level determination unit is configured to output the first level determination signal.
2. The detection circuit according to claim 1, further comprising a ternary determination unit that determines an output level of said detection unit into three values. 3. The ternary determination means has a first level higher than a reference level and a second level lower than the reference level, and the output of the first detector is the first level. It is determined which of the following three values, a larger value, a value smaller than the first level and larger than the second level, and a value smaller than the second level. Item 3. The detection circuit according to item 2. 4. The detection circuit according to claim 1, further comprising correction means for correcting an output of said first phase determination means in response to an output of said detection means. 5. The apparatus according to claim 1, further comprising control means for controlling a delay time of said first detection means and said second detection means in accordance with an output of said detection means. The detection circuit according to any of the above.