JP3943474B2 - Automatic frequency control device and automatic frequency control method - Google Patents

Automatic frequency control device and automatic frequency control method Download PDF

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JP3943474B2
JP3943474B2 JP2002290119A JP2002290119A JP3943474B2 JP 3943474 B2 JP3943474 B2 JP 3943474B2 JP 2002290119 A JP2002290119 A JP 2002290119A JP 2002290119 A JP2002290119 A JP 2002290119A JP 3943474 B2 JP3943474 B2 JP 3943474B2
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JP2004128877A (en
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史洋 山下
好典 中須賀
仁 三次
正純 上羽
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Nippon Telegraph and Telephone Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、４相位相変調方式の受信信号の周波数誤差を推定して除去する際に、相関回路を用いて受信信号の周波数オフセット領域を推定して周波数誤差を補償する自動周波数制御装置および自動周波数制御方法に関する。
【０００２】
【従来の技術】
４相位相変調方式（ＱＰＳＫ）の変調信号を復調する復調回路では、位相平面をπ／２ずつ４つの領域（以下、第１象限〜第４象限という）に分割し、受信シンボルが存在する象限を判定することによりビット列に変換する。ここで、受信信号がドップラーシフトなどの影響により周波数オフセットされる場合には、受信シンボルは位相平面上を一定方向に回転することになる。例えばシンボルレートをfsとしたときに、１／fs時間に受信シンボルの位相が位相平面上で２π回転することは、周波数軸上で受信信号の周波数が割り当てられた設定周波数よりfsだけ周波数オフセットしていることになる。すなわち、１／fs時間あたり±π／４の位相回転であれば、受信信号が周波数軸上で割り当てられた設定周波数より±fs／８だけ周波数オフセットしていることになる。
【０００３】
したがって、受信信号が設定周波数から大きな周波数オフセットを受ける場合、例えば１／fs時間にｋπ／２＋α（ｋは０以外の整数）のようなπ／２を越える大きなシンボル回転が想定される場合に、第１象限に設定したシンボル位相点からαだけオフセットしたシンボルが観測されたときに、本来第１象限のシンボルがαだけ周波数オフセットしているのか、本来第２象限のシンボルがα−π／２オフセットしているのか、区別がつかない。しかし、このような不確定な場合に、位相回転量をαと判断して周波数制御を行い、受信シンボルの位相が１／fs時間にα−π／２回転する場合でも、各象限でのシンボルは設定位相からαだけ位相回転した位相となるため、シンボル同期をとることは可能である。ただし、本来の象限とは異なる象限と領域判定されるため、変換されたビット列は誤ったものになる。以下、これを「誤同期」という。
【０００４】
この誤同期の問題を解決するために、従来提案された相関回路を用いた自動周波数制御装置の構成例を図６に示す。本構成は、非特許文献１から従来技術として考えられる箇所を抜粋したものであり、３つの相関回路を用いることにより、１／fs時間に受信シンボルの位相が±π／４以上回転しても、周波数誤差を補償することができる特徴を有する。
【０００５】
図６において、受信信号と発振回路６９の出力信号が乗算回路６１で乗算され、周波数変換された信号が遅延検波回路６２に入力される。遅延検波回路６２では、乗算回路６１の出力信号を２分岐回路６２１で２分岐し、その一方の信号と遅延回路６２２を介して遅延させた他方の信号を直交検波回路６２３に入力して遅延検波し、その検波信号がクロック再生回路６２４に入力されてタイミング再生される。クロック再生回路６２４から出力される再生信号は２分岐回路６２５で２分岐され、検出回路６２６はその一方の再生信号を領域判定してデータビット列を出力する。
【０００６】
２分岐回路６２５で２分岐された他方の再生信号を入力する自動周波数制御回路６３は、再生信号から推定された周波数誤差量を示す周波数誤差信号と、この周波数誤差量を再生信号から除去した信号（以下「復調信号」という）を出力する。この復調信号は３分岐回路７０で３分岐され、それぞれ第１の相関回路６４、第２の相関回路６５、第３の相関回路６６に入力され、各相関結果が判定回路６７に出力される。判定回路６７は３つの相関結果に応じて、自動周波数制御回路６３から出力される周波数誤差信号の補正量Δθを判定し、その補正信号を出力する。加算回路６８は、周波数誤差信号と補正信号を加算して発振回路６９に与え、その発振周波数を制御する。
【０００７】
以上示した遅延検波回路６２は一般的な構成である（非特許文献２）。また、自動周波数制御回路６３は例えば逓倍法を用いて構成でき、その出力信号により発振周波数を制御する発振回路６９は、電圧制御発振器（ＶＣＯ）を用いて容易に構成できる（非特許文献３、非特許文献４）。
【０００８】
本自動周波数制御装置の特徴は、３つの相関回路を用いて周波数誤差領域を推定する機能にある。以下、第１の相関回路６４、第２の相関回路６５、第３の相関回路６６および判定回路６７の設計方法および動作原理について説明する。
【０００９】
本自動周波数制御装置は遅延検波方式に対応する構成であり、受信信号を遅延検波するために送信側で情報ビットを差動符号化している。一般に、通信フレームには、同期をとるためにユニークワード（ＵＷ）と呼ばれる固定ビットパターンが挿入されるが、上記のように送信側でＵＷも差動符号化されるために、受信側に差動符号化されたＵＷが固定ビットパターンとして受信される。周波数誤差がない状態におけるこの差動符号化されたＵＷの固定ビットパターンを（Ｓi ，Ｓq ）とする。以下に説明する従来例では、信号はグレイ符号化されていることを想定している。この（Ｓi ，Ｓq ）の固定ビットパターンを第１の相関回路６４の相関係数として設定した場合、第１の相関回路６４のビット数は、差動符号化されたＵＷのビット数分だけ存在することになる。
【００１０】
ここで、自動周波数制御回路６３から出力される復調信号を第１の相関回路６４に入力して相関を調べ、雑音等の影響によりビット誤りを起こす可能性があることから閾値を設け、あらかじめ設定された閾値以上のビット数が一致する相関結果が得られたならば（本明細書ではこの状況を「相関がとれる」または「相関する」と表現し、図中では「相関回路が相関」と表現する）、受信信号の周波数誤差量は±fs／８以下であり、受信シンボルの１／fs時間あたりの位相回転量は±π／４以下であるという情報が得られる。
【００１１】
一方、単位１／fs時間に、受信シンボルの位相がπ／４〜３π／４回転するような状況では、自動周波数制御回路６３から出力される復調信号は、第１の相関回路６４で相関がとれない。この状況では、受信信号の周波数は設定周波数よりfs／８〜３fs／８だけ周波数オフセットしており、受信信号の固定ビットパターンは、第１の相関回路６４の値をπだけ＋方向にオフセットした（−Ｓq ，Ｓi ）の固定ビットパターンと一致する。ただし、符号の「−」はビット反転を意味する。そこで、この（−Ｓq ，Ｓi ）の固定ビットパターンを第２の相関回路６５の相関係数に設定し、第２の相関回路６５で相関がとれた場合、受信信号が設定周波数からfs／８〜３fs／８だけ周波数オフセットしており、受信シンボルの位相が１／fs時間にπ／４〜３π／４回転しているという情報が得られる。
【００１２】
同様に、１／fs時間に、受信シンボルの位相が−π／４〜−３π／４回転するような、受信信号の周波数が設定周波数より−fs／８〜−３fs／８だけ周波数オフセットしている状況では、自動周波数制御回路６３から出力される復調信号は、第１の相関回路６４および第２の相関回路６５で相関がとれない。この状況では、受信信号の固定ビットパターンは、第１の相関回路６４の値をπだけ、−方向にオフセットした（Ｓq ，−Ｓi ）となる。そこで、この（Ｓq ，−Ｓi ）の固定ビットパターンを第３の相関回路６６の相関係数に設定し、第３の相関回路６６で相関がとれた場合、受信信号が設定周波数から−fs／８〜−３fs／８だけ周波数オフセットしており、受信シンボルの位相が１／fs時間に−π／４〜−３π／４回転しているという情報が得られる。
【００１３】
次に、判定回路６７の動作について説明する。
判定回路６７は、第１の相関回路６４、第２の相関回路６５、第３の相関回路６６の相関結果を入力し、その３つの相関を調べて推定された１／fs時間あたりの受信シンボルの位相回転量に関する情報を用い、自動周波数制御回路６３から出力される周波数誤差信号の補正量Δθを判定する。
【００１４】
ここで、第１の相関回路６４で相関がとれた場合、受信シンボルの位相回転量は１／fs時間あたり±π／４以下である。この場合は、正常な象限で同期がとれていると判断する。したがって、自動周波数制御回路６３で検出される周波数誤差量は正常な象限で推定されている値であることから、補正する必要がないために判定回路６７の出力（周波数誤差信号の補正量）Δθは０である。
【００１５】
第２の相関回路６５で相関がとれた場合、受信シンボルの位相回転量は１／fs時間あたりπ／４〜３π／４である。したがって、正常な象限で周波数誤差を除去するためには、受信シンボルの位相回転量が１／fs時間あたり±π／４以下になるように、自動周波数制御回路６３から出力される周波数誤差信号の補正量を設定する必要がある。すなわち、第２の相関回路６５で相関がとれた場合、判定回路６７の出力Δθを−π／２とし、受信シンボルの位相回転量に１／fs時間あたり−π／２を加えてやればよい。この１／fs時間あたりに与える位相シフト量−π／２は、周波数誤差の判別値としてはシンボルレートの−１／４である。
【００１６】
第３の相関回路６６で相関がとれた場合、受信シンボルの位相回転量は１／fs時間あたり−３π／４〜−π／４である。したがって、同様に判定回路６７の出力Δθを＋π／２とし、受信シンボルの位相回転量に１／fs時間あたりπ／２を加えてやればよい。この１／fs時間あたりに与える位相シフト量＋π／２は、周波数誤差の判別値としてはシンボルレートの１／４となる。
【００１７】
図７は、従来の自動周波数制御装置の判定回路６７の判定アルゴリズムを示す。
判定回路６７は、第１の相関回路６４で相関を調べて相関がとれた場合には、判定回路出力Δθとして０を出力して処理を終了する。次に、第１の相関回路６５で相関がとれず、第２の相関回路６５で相関を調べて相関がとれた場合には、判定回路出力Δθとして−π／２を出力し、第１の相関回路６４の相関を調べる手順に戻る。また、第１の相関回路６４および第２の相関回路６５で相関がとれず、第３の相関回路６６で相関を調べて相関がとれた場合には、判定回路出力Δθとして＋π／２を出力し、第１の相関回路６４の相関を調べる手順に戻る。なお、従来の自動周波数制御装置では、第３の相関回路６６で相関がとれない場合については特に考慮されておらず、処理を終了する。
【００１８】
すなわち、第１の相関回路６４で相関がとれた場合には、自動周波数制御回路６３から出力される周波数誤差信号をそのまま発振回路６９にフィードバックして処理を終了する。また、第２の相関回路６５で相関がとれた場合には、周波数誤差信号に−π／２を加算して発振回路６９にフィードバックすることにより、第１の相関回路６４で相関がとれる状態になり処理を終了する。
【００１９】
以上のように、判定回路６７は、第１の相関回路６４で相関がとれた場合には０、第２の相関回路６５で相関がとれた場合には−π／２、第３の相関回路６６で相関がとれた場合には＋π／２を加算回路６８に出力し、自動周波数制御回路６３から出力される周波数誤差信号に加算し、発振回路６９の発振周波数を制御する。このようにして制御された周波数の信号を乗算回路６１に入力し、受信信号と乗算することにより、受信信号が割り当てられた設定周波数から周波数オフセットしている周波数誤差成分を除去することができる。
【００２０】
【非特許文献１】
五十嵐、外５名、「複数の相関器を用いたＡＦＣ方法に関する一検討」、1994年電子情報通信学会秋季大会、Ｂ−290
【非特許文献２】
藤野忠著「ディジタル移動通信」昭晃堂、第１版、2000年６月10日発行、pp.52-78、pp.122-152
【非特許文献３】
飯田尚志著「衛星通信」オーム社、第１版、平成10年５月30日発行、pp.301-333
【非特許文献４】
山本平一、加藤修三共著「ＴＤＭＡ通信」電子情報通信学会、第１版、平成９年５月１日発行、pp.76-89
【００２１】
【発明が解決しようとする課題】
ところで、従来の自動周波数制御装置は、図６に示すように３つの相関回路を用い、図７に示すように第３の相関回路６６で相関がとれない場合については考慮していないので、補償できる最大周波数誤差は、位相面では１／fs時間あたり受信シンボル位相が最大±３π／４の回転量、周波数軸上では±３fs／８の周波数誤差量となる。
【００２２】
また、図７に示す従来の判定アルゴリズムでは周波数誤差を補正できない（受信シンボルの同期がとれない）場合があり、以下この現象について図８を参照して説明する。図８は、自動周波数制御回路６３の入力信号の１／fs時間あたりの周波数誤差によるシンボルの位相回転量を位相面で表す。
【００２３】
まず、送信側の送信シンボル位置を位相面で♯０とする。図８は、周波数誤差によるシンボルの位相回転量を表すので、周波数誤差がなければ、受信シンボルの位相回転量は♯０となり（以下「受信シンボル♯０」または「♯０」という）、送信シンボル位置と一致する。この前提において、受信シンボルは周波数誤差の影響を受け、雑音がなければ１／fs時間あたりπ／４よりやや小さい位相量で回転している状況を仮定し、図８に受信シンボル♯１として表す。雑音がなければ、受信シンボル♯１は第１の相関回路６４で相関がとれる。したがって、自動周波数制御回路６３で周波数誤差成分が除去され、受信シンボル♯１の位相回転量を補正して送信シンボル♯０を推定することができる。
【００２４】
しかし、一般に受信信号には、伝搬路や変復調回路において雑音が付加されるので、以下のような状況が一例として想定される。雑音が付加された状況では、受信シンボル♯１は、１／fs時間あたりπ／４より大きく回転することがある。このとき、受信シンボル♯１は位相面において♯２の位置に動き、受信シンボル♯２は第２の相関回路６５で相関がとれる。ここで、判定回路６７が出力する−π／２を自動周波数制御回路６３が出力する周波数誤差信号に加算して発振回路６９の発振周波数を制御すれば、次に自動周波数制御回路６３に入力する受信シンボルは♯３となる。
【００２５】
この受信シンボル♯３は、雑音が付加されることで♯４の位置に動くことがある。このとき、受信シンボル♯４は第３の相関回路６６で相関がとれる。ここで、判定回路６７が出力する＋π／２を自動周波数制御回路６３が出力する周波数誤差信号に加算して発振回路６９の発振周波数を制御すれば、次に自動周波数制御回路６３に入力する受信シンボルは♯５となり、受信シンボル♯１の近傍になる。
【００２６】
このように、受信シンボル♯１が雑音付加により受信シンボル♯２に遷移し、−π／２のシンボル位相量の回転後に受信シンボル♯３になるが、雑音付加により受信シンボル♯４に遷移したために＋π／２のシンボル位相量の回転が行われ、受信シンボル♯１の近傍の受信シンボル♯５になると、再び雑音の付加により受信シンボル♯２に遷移する状況が想定される。このようなシンボル遷移が繰り返し起こった場合には、図６の自動周波数制御回路６３は推定する周波数誤差量が雑音の影響で時間とともに大きく変動し、正確に周波数誤差量を推定することができない。すなわち、受信開始後に受信信号の同期が長時間とれず、回線品質が大幅に劣化する状況になる。
【００２７】
また、別の例として、自動周波数制御回路６３に入力されるシンボルが♯１と♯２の間を雑音の影響によりふらつく場合には、相関結果が閾値を越えないために、第１の相関回路６４および第２の相関回路６５でともに相関がとれない状態になる。この場合も同様に図６の自動周波数制御回路６３は正確に周波数誤差量を推定することができず、受信信号の同期が長時間とれないために回線品質が大幅に劣化する状況になる。
【００２８】
このように、雑音の影響により、自動周波数制御回路６３へ入力される受信シンボルの１／fs時間あたりの位相回転量が変わり、時間とともに相関がとれる相関回路が異なる場合や、相関がとれる相関回路がない場合には、判定回路６７において周波数誤差領域の推定ができないために、受信信号の回線品質が大幅に劣化する。このような状況は、具体的には１／fs時間あたりの受信シンボルの位相回転量が±π／４近傍または±３π／４近傍であり、周波数軸上では±fs／８近傍、または±３fs／８近傍の周波数オフセットを受けている場合に生じる。以下この±fs／８および±３fs／８近傍の周波数誤差領域を「自動周波数制御不安定領域」という。
【００２９】
本発明は、相関回路を用いて周波数誤差量を推定して除去する自動周波数制御装置において、±３fs／８以上の周波数誤差量を推定して除去することができるとともに、受信信号が設定周波数より±fs／８近傍または±３fs／８近傍の周波数誤差を受けている場合に雑音の影響を受けずに周波数誤差量を推定して除去し、回線品質の劣化を抑えることができる自動周波数制御装置を提供することを目的とする。
【００３０】
【課題を解決するための手段】
本発明の自動周波数制御装置は、設定周波数より±３fs／８を越える周波数オフセットした信号を検出するために第４の相関回路を設けることを特徴とする。従来技術では、周波数誤差の制御範囲の上限が±３fs／８であったのに対して、本発明により制御範囲が±３fs／８を越える広範囲な周波数誤差量を推定して除去することができる。
【００３１】
また、本発明の自動周波数制御装置は、すべての相関回路で相関がとれない場合には、周波数誤差信号の補正量としてα（ただし、αはシンボルレートのｎ／４（ｎは整数）とは異なる値）を出力する判定回路を設けることを特徴とする。
【００３２】
【発明の実施の形態】
（第１の実施形態）
図１は、本発明の第１の実施形態の全体構成を示す。
【００３３】
図において、受信信号と発振回路８の出力信号が乗算回路１で乗算され、周波数変換された信号が復調回路２に入力される。復調回路２は、入力信号から推定した周波数誤差量を示す周波数誤差信号と、この周波数誤差量を入力信号から除去した復調信号と、この復調信号から検出されたデータを出力する。 復調信号は４分岐回路１０で４分岐され、それぞれ第１の相関回路３、第２の相関回路４、第３の相関回路５、第４の相関回路６に入力され、各相関結果が判定回路７に出力される。判定回路７は４つの相関結果に応じて、復調回路２から出力される周波数誤差信号の補正量Δθを判定し、その補正信号を出力する。加算回路９は、周波数誤差信号と補正信号を加算して発振回路８に与え、その発振周波数を制御する。
【００３４】
第１の相関回路３、第２の相関回路４、第３の相関回路５は、図６に示す従来の構成の相関回路６４，６５，６６と同様の構成である。以下、本実施形態の特徴である第４の相関回路６の回路設計法、判定回路７で第４の相関回路６を追加することにより新しく付け加わった制御機能について説明する。
【００３５】
図６に示す従来の構成では、設定周波数から最大±３fs／８の周波数誤差を補正することは可能であったが、まずこの最大周波数誤差以上の周波数誤差量として、受信信号に３fs／８〜５fs／８の周波数誤差がある状況を想定する。
【００３６】
３fs／８〜５fs／８の周波数誤差がある状況では、復調回路２から出力される復調信号は、受信信号が設定周波数からfs／８〜３fs／８オフセットしている状況から、さらにシンボル位相が１／fs時間あたり＋π／２回転している。結果として±fs／８以下の周波数オフセットを受けた場合から、シンボル位相が１／fs時間あたり＋π回転していることになる。±fs／８以下の周波数オフセットを有する信号が相関する第１の相関回路の固定ビットパターンは、従来技術の欄で説明したように（Ｓi ，Ｓq ）である。したがって、この場合よりさらに、シンボル位相が１／fs時間あたり＋π回転している場合、入力信号と相関がとれる固定ビットパターンは、第１の相関回路の固定ビットパターンを＋π回転させた（−Ｓi ，−Ｓq ）となる。
【００３７】
一方、−５fs／８〜−３fs／８の周波数誤差がある状況では、復調回路２から出力される復調信号は、受信信号が設定周波数から−３fs／８〜−fs／８オフセットしている状況から、さらにシンボル位相が１／fs時間あたり−π／２回転している。結果として±fs／８以下の周波数オフセットを受けた場合から、シンボル位相が１／fs時間あたり−π回転していることになる。±fs／８以下の周波数オフセットを有する信号が相関する第１の相関回路の固定ビットパターンは、従来技術の欄で説明したように（Ｓi ，Ｓq ）である。したがって、この場合よりさらに、シンボル位相が１／fs時間あたり−π回転している場合、入力信号と相関がとれる固定ビットパターンは、第１の相関回路の固定ビットパターンを−π回転させた（−Ｓi ，−Ｓq ）となる。
【００３８】
以上により、（−Ｓi ，−Ｓq ）の固定ビットパターンを第４の相関回路６に設定し、入力信号と相関がとれた場合には、受信信号の周波数誤差量が３fs／８〜５fs／８または−５fs／８〜−３fs／８の範囲にあることを推定することができる。
【００３９】
ここで、設定周波数から３fs／８〜５fs／８の周波数誤差領域に受信信号が存在すれば、シンボルの位相回転量は１／fs時間に３π／４〜５π／４になる。この場合、シンボルの位相を１／fs時間に−π／２回転させることにより、１／fs時間あたりのシンボルの位相回転量はπ／４〜３π／４になり、第２の相関回路４で相関がとれる。第２の相関回路４で相関がとれた場合、受信シンボルの位相は−π／２回転されるので、シンボルの位相回転量は１／fs時間あたり、最終的に±π／４以下まで補正される。これにより、復調回路２内に存在する自動周波数制御回路において周波数誤差の除去が可能となる。したがって、第４の相関回路６で相関がとれた場合、設定周波数から３fs／８〜５fs／８の周波数誤差領域に受信信号が存在すれば、判定回路７から出力する周波数誤差信号の補正量は−π／２とすればよい。
【００４０】
一方、設定周波数から−５fs／８〜−３fs／８の周波数誤差領域に受信信号が存在すれば、シンボルの位相回転量は１／fs時間に−５π／４〜−３π／４になる。この場合、シンボルの位相を１／fs時間にπ／２回転させることにより、１／fs時間あたりのシンボルの位相回転量は−３π／４〜−π／４になり、第３の相関回路５で相関がとれる。第３の相関回路５で相関がとれた場合、受信シンボルの位相はπ／２回転されるので、シンボルの位相回転量は１／fs時間あたり、最終的に±π／４以下まで補正される。これにより、復調回路２内に存在する自動周波数制御回路において周波数誤差の除去が可能となる。したがって、第４の相関回路６で相関がとれた場合、設定周波数から−５fs／８〜−３fs／８の周波数誤差領域に受信信号が存在すれば、判定回路７から出力する周波数誤差信号の補正量はπ／２とすればよい。
【００４１】
しかし、第４の相関回路６で相関がとれた場合、受信信号の周波数誤差量が３fs／８〜５fs／８、または−５fs／８〜−３fs／８の範囲にあることを推定することができるが、いずれの周波数誤差領域にあっても同じように相関結果が出力されるので、どちらの周波数誤差領域なのかを特定することができない。すなわち、判定回路７から出力する周波数誤差信号の補正量Δθが−π／２かπ／２かを決定することができない。そこで、第４の相関回路６で相関がとれた後に判定回路７の出力を制御する手順について、以下に図２を参照して説明する。
【００４２】
第４の相関回路６で相関がとれたときに、判定回路７は、設定周波数から３fs／８〜５fs／８の周波数誤差領域に受信信号が存在すると仮定し、その出力を−π／２とする。これにより、発振回路８は周波数誤差信号に−π／２加算して制御されるので、仮定が正しければ第２の相関回路４で相関がとれる状態になる。したがって、第２の相関回路４で相関がとれた場合には、判定回路７の出力は最終的に−π／２と確定できる。
【００４３】
一方、上記の仮定が誤っていれば、判定回路７の出力が−π／２とされたために、１／fs時間あたりのシンボルの位相回転量が−７π／４〜−５π／４となる。この場合には、受信信号は設定周波数よりさらに大きく周波数オフセットするため、いずれの相関回路でも相関しない状態になる。したがって、判定回路７の出力を−π／２とした後に、第２の相関回路４の相関結果に着目し、第２の相関回路４で相関しなければ仮定に誤りがあると判断し、受信信号は設定周波数から−５fs／８〜−３fs／８の周波数誤差領域に存在すると判断する。
【００４４】
この周波数誤差の場合、本来は判定回路７の出力がπ／２でなければならないが、先に誤った仮定で−π／２が判定回路７の出力として発振回路８を制御しているので、それを打ち消してさらに出力を＋π／２とするには、判定回路７の出力を＋πとする必要がある。これにより、誤った仮定に基づく発振回路８の周波数制御は相殺され、第３の相関回路５で相関がとれる状態になる。したがって、第３の相関回路５で相関がとれた場合には、判定回路７の出力は最終的に＋π／２と確定できる。
【００４５】
以上のように第４の相関回路６および判定回路７を構成することにより、設定周波数から最大±５fs／８までの周波数誤差を除去することができる。
【００４６】
（判定回路７の判定アルゴリズム）
図３および図４は、第１の実施形態における判定回路７の判定アルゴリズムを示す。
【００４７】
図３において、判定回路７は、第１の相関回路３で相関を調べて相関がとれた場合には、判定回路出力Δθとして０を出力して処理を終了する。次に、第１の相関回路３で相関がとれず、第２の相関回路４で相関を調べて相関がとれた場合には、判定回路出力Δθとして−π／２を出力し、第１の相関回路３の相関を調べる手順に戻る。また、第１の相関回路３および第２の相関回路４で相関がとれず、第３の相関回路５で相関を調べて相関がとれた場合には、判定回路出力Δθとして＋π／２を出力し、第１の相関回路３の相関を調べる手順に戻る。以上の手順(a) は、図７に示す従来構成のものと同じである。
【００４８】
本実施形態の自動周波数制御装置では、第３の相関回路５で相関がとれない場合に第４の相関回路６に移行し、第４の相関回路６で相関を調べて相関がとれた場合に、上述したように判定回路出力Δθとして−π／２を出力し、第２の相関回路４で相関を調べる。第２の相関回路４で相関がとれた場合には、判定回路出力Δθとして−π／２を確定し、第１の相関回路３の相関を調べる手順に戻る。一方、第２の相関回路４で相関がとれない場合には、判定回路出力Δθとして＋πを出力し、第３の相関回路５で相関を調べる。第３の相関回路５で相関がとれた場合には、判定回路出力Δθとして＋π／２を確定し、第１の相関回路３の相関を調べる手順に戻る。
【００４９】
なお、第４の相関回路６で相関がとれない場合には処理を終了する。ただし、ここで待機状態になるか、または各相関回路から判定回路７への入力を再開するかを含めて、ここでは処理終了としている。
【００５０】
図４に示す判定回路７の判定アルゴリズムは、第４の相関回路６で相関がとれた場合に、図２および図３の場合の上記仮定を逆にして判定回路出力Δθとして＋π／２を出力する。この場合には、第３の相関回路５で相関を調べ、第３の相関回路５で相関がとれた場合には、判定回路出力Δθとして＋π／２を確定し、第１の相関回路３の相関を調べる手順に戻る。一方、第３の相関回路５で相関がとれない場合には、判定回路出力Δθとして−πを出力し、第２の相関回路４で相関を調べる。第２の相関回路４で相関がとれた場合には、判定回路出力Δθとして−π／２を確定し、第１の相関回路３の相関を調べる手順に戻る。
【００５１】
また、本実施形態の説明では、判定回路７の出力を±π／２および±πとしたが、これらの値は厳密なものではなく、例えば±0.49πというように多少の誤差を許容している。
【００５２】
また、第４の相関回路で相関がとれた場合に判定回路の出力として±π／２を出力するのではなく、受信シンボルの位相を正常に同期がとれる象限が存在する方向の象限に遷移できるような出力値を設定してもよい。例えば、図３の判定アルゴリズムでは、「第４の相関回路−［−π／２位相操作］−第２の相関回路−［−π／２位相操作］−第１の相関回路」、あるいは「第４の相関回路−［−π／２位相操作］−第２の相関回路−［＋π位相操作］−第３の相関回路−［＋π／２位相操作］−第１の相関回路」というように、２段階または３段階で同期がとれる象限にシンボルが遷移するように位相量を順次制御しており、図４の判定アルゴリズムでも同様であるが、第４の相関回路で相関がとれた場合の位相操作量を例えば−πとして「第４の相関回路−［−π位相操作］−第１の相関回路」というように、１段階で同期をとるようなアルゴリズムとしてもよい。ただし、このとき第１の相関回路で相関がとれない場合には、判定回路の出力を＋２πとし、「第４の相関回路−［−π位相操作］−第１の相関回路−［＋２π位相操作］−第１の相関回路」というように、２段階で同期をとるようなアルゴリズムになる。
【００５３】
また、図３および図４（後述する図１１および図１２）の判定アルゴリズムにおいて、第２の相関回路と第３の相関回路の順番を入れ替えて入力信号との相関を調べる手順としてもよい。
【００５４】
（復調回路２の構成例）
復調回路２の検波方式として遅延検波方式を採用する場合には、図６に示す遅延検波回路６２と自動周波数制御回路６３により復調回路２とすることができる。すなわち、クロック再生回路６２４から出力される再生信号を入力する自動周波数制御回路６３から、推定された周波数誤差量を示す周波数誤差信号と、この周波数誤差量を再生信号から除去した復調信号を出力し、この復調信号を４分岐して各相関回路に入力する。
【００５５】
図５は、復調回路２の他の構成例を示す。図５(1) の構成例は、検波方式として絶対同期検波方式を採用した場合であり、図５(2) の構成例は、検波方式として差動符号同期検波方式を採用した場合である。
【００５６】
図５(1) において、復調回路２の入力信号（乗算回路１の出力信号）を直交検波回路２１に入力して直交検波し、その検波信号がクロック再生回路２２に入力されてタイミング再生される。クロック再生回路２２から出力される再生信号を入力する自動周波数制御回路２３は、再生信号から推定された周波数誤差量を示す周波数誤差信号と、この周波数誤差量を再生信号から除去した信号を出力する。周波数誤差信号は、復調回路２の出力として図１に示す加算回路９に入力される。周波数誤差量が除去された信号は搬送波再生回路２４に入力され、位相オフセット成分が除去された信号となる。この信号は２分岐回路２５で２分岐され、検出回路２６はその一方の信号領域判定してデータビット列を出力する。
【００５７】
２分岐回路２４で２分岐された他方の信号は１シンボル差分回路２７に入力され、入力信号とそれを１シンボル時間遅延させた信号との差分信号が生成される。この差分信号は、復調回路２の復調信号として図１に示す４分岐回路１０を介して各相関回路（３〜６）に入力される。
【００５８】
ここで、１シンボル分の差分値をとる理由は、差動符号化されたＵＷの固定ビットパターンを（Ｓi ，Ｓq ）とし、そのパターンをもとに各相関回路の相関係数を設定しているためである。絶対同期検波方式は、送信側で差動符号化しないため、相関回路の相関係数を上記パターンに設定するために、受信側で差動符号化する必要がある。また、絶対同期検波方式では、自動周波数制御回路２３で±fs／８以下の周波数誤差を補償することができるので、自動周波数制御回路２３で検出した周波数誤差信号を加算回路９に出力しない場合もある。
【００５９】
図５(2) に示す復調回路２は、基本的な構成は図５(1) に示す絶対同期検波方式のものと同じであるが、差動符号同期検波方式をとるために送信側で情報ビットを差動符号化しており、１シンボル差分回路２７が不要になるところが異なる。また、差動符号同期検波方式では、自動周波数制御回路２３で±fs／８以下の周波数誤差を補償することができるので、自動周波数制御回路２３で検出した周波数誤差信号を加算回路９に出力しない場合もある。
【００６０】
なお、本発明の自動周波数制御装置に用いる復調回路２は、上記のように検波方式として、遅延検波方式、絶対同期検波方式、差動符号同期検波方式などを採用した構成例を示したが、各回路構成に限定されるものではない。また、本実施形態では、入力信号の符号化方式としてグレイ符号を想定したが、他の符号化方式にも同様に本発明の原理を適用することができる。
【００６１】
（第２の実施形態）
第２の実施形態は、従来の自動周波数制御装置における判定回路６７の判定アルゴリズムの改良例を示す。従来構成では、図８を用いて説明したように、設定周波数より±fs／８近傍または±３fs／８近傍の周波数誤差がある場合に、雑音の影響により周波数誤差の除去ができないことにより回線品質が劣化する問題があったが、本実施形態はこれを解決するものである。
【００６２】
図９は、第２の実施形態における判定回路６７の判定アルゴリズムを示す。本実施形態における自動周波数制御装置は図６に示す従来構成を例に説明するが、例えば遅延検波回路６２と自動周波数制御回路６３の部分は、図５に示すような他の復調回路の構成をとることもできる。
【００６３】
判定回路６７は、第１の相関回路６４で相関を調べて相関がとれた場合には、判定回路出力Δθとして０を出力して処理を終了する。次に、第１の相関回路６５で相関がとれず、第２の相関回路６５で相関を調べて相関がとれた場合には、判定回路出力Δθとして−π／２を出力し、第１の相関回路６４の相関を調べる手順に戻る。また、第１の相関回路６４および第２の相関回路６５で相関がとれず、第３の相関回路６６で相関を調べて相関がとれた場合には、判定回路出力Δθとして＋π／２を出力し、第１の相関回路６４の相関を調べる手順に戻る。以上の手順は、図７に示す従来構成のものと同じである。
【００６４】
本実施形態では、第１の相関回路６４、第２の相関回路６５、第３の相関回路６６のいずれでも相関がとれない場合に、判定回路６７は周波数誤差信号の補正量としてα（ただし、αはｎπ／２（ｎは整数）とは異なる値）を出力し、第１の相関回路６４の相関を調べる手順に戻る。
【００６５】
このような判定アルゴリズムにより、雑音の影響により周波数誤差の除去ができない状態を回避できる例について図１０を参照して説明する。図１０は、図８と同様に、自動周波数制御回路６３の入力信号の１／fs時間あたりの周波数誤差によるシンボルの位相回転量を位相面で表す。
【００６６】
まず、αの一例としてπ／４と設定し、受信シンボルが１／fs時間あたり−７π／32回転している状況を想定する。この状況において大きな雑音が信号に加わると、同期がとれない自動周波数制御不安定領域（図中ハッチングで示す領域）と想定する。例えば雑音の影響により、受信シンボルが第１の相関回路の相関周波数誤差領域と第３の相関回路の相関周波数誤差領域の間でふらつくと、すべての相関回路の相関値が設定閾値を越えない状況になる。このとき、判定回路６７は、図９の判定アルゴリズムに従い、α（＝π／４）を出力する。
【００６７】
図１０では、送信シンボルが♯０であるのに対して、受信シンボルが♯１であることを想定している。この想定では、受信シンボル♯１の位相量は１／fs時間あたり−７π／32回転しているため、判定回路６７の出力としてα（＝π／４）を設定すると、受信シンボルの位相は差し引き１／fs時間あたりπ／32回転し、受信シンボル♯２の位置に遷移する。この回転量は、上記のように自動周波数制御回路６３で除去可能な１／fs時間あたり±π／４以内の回転量であるので、容易に自動周波数制御回路６３で除去することができる。その結果、第１の相関回路６４で相関がとれ、判定回路６７の出力は０となり、図９の処理が終了する。
【００６８】
（第３の実施形態）
第３の実施形態は、図１の第１の実施形態における判定回路７の判定アルゴリズムの改良例を示す。図３に示す判定アルゴリズムの改良例を図１１に示し、図４に示す判定アルゴリズムの改良例を図１２に示す。
【００６９】
いずれも、第１の相関回路３、第２の相関回路４、第３の相関回路５、第４の相関回路６のいずれでも相関がとれない場合に、判定回路７は周波数誤差信号の補正量としてα（ただし、αはｎπ／２（ｎは整数）とは異なる値）を出力し、第１の相関回路３の相関を調べる手順に戻る。αを出力した後の動作は、第２の実施形態で示した動作と同じである。
【００７０】
【発明の効果】
以上説明したように、本発明の自動周波数制御装置は、設定周波数より±３fs／８を越える周波数誤差を補正することができるので、高速に移動している移動体でドップラーシフトにより生じる大きな周波数誤差を補正できることになり、移動体通信の利用範囲を拡大することができる。
【００７１】
また、安価で小型であるが周波数安定性の悪い発振器を利用することにより生じる大きな周波数誤差を補正することができるので、端末のコスト低減を図ることができる。
【００７２】
また、受信信号が設定周波数より±fs／８近傍または±３fs／８近傍の周波数オフセットを受けている場合に、雑音を受けた場合でも安定して周波数誤差量を推定して除去することができるので、回線品質の劣化を抑えることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態の全体構成を示すブロック図。
【図２】第１の実施形態の判定回路７の判定アルゴリズムの主要部を示すフローチャート。
【図３】第１の実施形態の判定回路７の判定アルゴリズムを示すフローチャート。
【図４】第１の実施形態の判定回路７の判定アルゴリズムを示すフローチャート。
【図５】第１の実施形態の復調回路２の他の構成例を示すブロック図。
【図６】従来の自動周波数制御装置の構成例を示すブロック図。
【図７】従来の自動周波数制御装置の判定回路６７の判定アルゴリズムを示すフローチャート。
【図８】従来の判定アルゴリズムで受信シンボルの同期がとれない例を説明する図。
【図９】第２の実施形態における判定回路６７の判定アルゴリズムを示すフローチャート。
【図１０】第２の実施形態における判定アルゴリズムの改善例を説明する図。
【図１１】図３に示す判定アルゴリズムの改良例を示すフローチャート。
【図１２】図４に示す判定アルゴリズムの改良例を示すフローチャート。
【符号の説明】
１ 乗算回路
２ 復調回路
２１ 直交検波回路
２２ クロック再生回路
２３ 自動周波数制御回路
２４ 搬送波再生回路
２５ ２分岐回路
２６ 検出回路
２７ １シンボル差分回路
３ 第１の相関回路
４ 第２の相関回路
５ 第３の相関回路
６ 第４の相関回路
７ 判定回路
８ 発振回路
９ 加算回路
１０ ４分岐回路
６１ 乗算回路
６２ 遅延検波回路
６２１ ２分岐回路
６２２ 遅延回路
６２３ 直交検波回路
６２４ クロック再生回路
６２５ ２分岐回路
６２６ 検出回路
６３ 自動周波数制御回路
６４ 第１の相関回路
６５ 第２の相関回路
６６ 第３の相関回路
６７ 判定回路
６８ 加算回路
６９ 発振回路
７０ ３分岐回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an automatic frequency control apparatus and an automatic frequency controller that compensates a frequency error by estimating a frequency offset region of a received signal using a correlation circuit when estimating and removing a frequency error of a received signal of a four-phase phase modulation method. The present invention relates to a frequency control method.
[0002]
[Prior art]
In a demodulation circuit that demodulates a four-phase phase modulation (QPSK) modulation signal, the phase plane is divided into four regions by π / 2 (hereinafter referred to as first to fourth quadrants), and a quadrant in which a received symbol exists. Is converted into a bit string. Here, when the received signal is frequency offset due to the influence of Doppler shift or the like, the received symbol rotates on the phase plane in a certain direction. For example, when the symbol rate is fs, the phase of the received symbol rotates by 2π on the phase plane at 1 / fs time is offset by fs from the set frequency to which the frequency of the received signal is assigned on the frequency axis. Will be. That is, if the phase rotation is ± π / 4 per 1 / fs time, the received signal is offset by ± fs / 8 from the set frequency assigned on the frequency axis.
[0003]
Therefore, when the received signal receives a large frequency offset from the set frequency, for example, when a large symbol rotation exceeding π / 2 such as kπ / 2 + α (k is an integer other than 0) is assumed in 1 / fs time, When a symbol offset by α from the symbol phase point set in the first quadrant is observed, whether the symbol in the first quadrant is originally frequency offset by α or the symbol in the second quadrant is α−π / 2. I cannot tell if it is offset. However, in such an uncertain case, even when the phase control amount is determined to be α and frequency control is performed and the phase of the received symbol rotates α−π / 2 in 1 / fs time, the symbol in each quadrant Since the phase is a phase rotated by α from the set phase, symbol synchronization is possible. However, since the region is determined to be a quadrant different from the original quadrant, the converted bit string is incorrect. Hereinafter, this is referred to as “false synchronization”.
[0004]
FIG. 6 shows a configuration example of an automatic frequency control apparatus using a conventionally proposed correlation circuit in order to solve the problem of erroneous synchronization. This configuration is an excerpt from the non-patent document 1 that can be considered as a conventional technique. By using three correlation circuits, even if the phase of the received symbol rotates ± π / 4 or more in 1 / fs time, The frequency error can be compensated.
[0005]
In FIG. 6, the reception signal and the output signal of the oscillation circuit 69 are multiplied by the multiplication circuit 61, and the frequency-converted signal is input to the delay detection circuit 62. In the delay detection circuit 62, the output signal of the multiplication circuit 61 is branched into two by the two-branch circuit 621, and one signal and the other signal delayed through the delay circuit 622 are input to the quadrature detection circuit 623 for delay detection. The detected signal is input to the clock recovery circuit 624 and the timing is recovered. The reproduction signal output from the clock reproduction circuit 624 is branched into two by a two-branch circuit 625, and the detection circuit 626 determines one of the reproduction signals and outputs a data bit string.
[0006]
The automatic frequency control circuit 63 for inputting the other reproduction signal branched into two by the two-branch circuit 625 includes a frequency error signal indicating a frequency error amount estimated from the reproduction signal and a signal obtained by removing this frequency error amount from the reproduction signal. (Hereinafter referred to as “demodulated signal”). The demodulated signal is branched into three by a three-branch circuit 70 and is input to the first correlation circuit 64, the second correlation circuit 65, and the third correlation circuit 66, respectively, and each correlation result is output to the determination circuit 67. The determination circuit 67 determines the correction amount Δθ of the frequency error signal output from the automatic frequency control circuit 63 according to the three correlation results, and outputs the correction signal. The adder circuit 68 adds the frequency error signal and the correction signal to the oscillation circuit 69 and controls the oscillation frequency.
[0007]
The delay detection circuit 62 shown above has a general configuration (Non-Patent Document 2). The automatic frequency control circuit 63 can be configured using, for example, a multiplication method, and the oscillation circuit 69 that controls the oscillation frequency based on the output signal can be easily configured using a voltage controlled oscillator (VCO) (Non-Patent Document 3, Non-patent document 4).
[0008]
A feature of the automatic frequency control device is a function of estimating a frequency error region using three correlation circuits. Hereinafter, a design method and an operation principle of the first correlation circuit 64, the second correlation circuit 65, the third correlation circuit 66, and the determination circuit 67 will be described.
[0009]
This automatic frequency control apparatus has a configuration corresponding to the delay detection method, and information bits are differentially encoded on the transmission side in order to delay-detect the received signal. In general, a fixed bit pattern called a unique word (UW) is inserted into a communication frame in order to synchronize. However, since UW is also differentially encoded on the transmission side as described above, there is a difference between the reception side and the reception side. The dynamically encoded UW is received as a fixed bit pattern. This differentially encoded UW fixed bit pattern in a state where there is no frequency error is defined as (Si, Sq). In the conventional example described below, it is assumed that the signal is gray-coded. When the fixed bit pattern of (Si, Sq) is set as the correlation coefficient of the first correlation circuit 64, the number of bits of the first correlation circuit 64 is the same as the number of differentially encoded UW bits. Will do.
[0010]
Here, the demodulated signal output from the automatic frequency control circuit 63 is input to the first correlation circuit 64, the correlation is examined, and a bit error may occur due to the influence of noise or the like, so that a threshold value is provided and set in advance. If a correlation result is obtained that matches the number of bits equal to or greater than the threshold value (in this specification, this situation is expressed as “correlation is possible” or “correlation”, and “correlation circuit is correlation” in the figure) The frequency error amount of the received signal is ± fs / 8 or less, and the information that the phase rotation amount per 1 / fs time of the received symbol is ± π / 4 or less is obtained.
[0011]
On the other hand, in a situation where the phase of the received symbol rotates by π / 4 to 3π / 4 in the unit 1 / fs time, the demodulated signal output from the automatic frequency control circuit 63 is correlated by the first correlation circuit 64. Can not be removes. In this situation, the frequency of the received signal is offset by fs / 8 to 3 fs / 8 from the set frequency, and the fixed bit pattern of the received signal is offset in the + direction by the value of the first correlation circuit 64 by π. It matches the fixed bit pattern of (-Sq, Si). However, the sign “−” means bit inversion. Therefore, when the fixed bit pattern of (-Sq, Si) is set as the correlation coefficient of the second correlation circuit 65, and the correlation is obtained by the second correlation circuit 65, the received signal is fs / 8 from the set frequency. Information is obtained that the frequency is offset by ˜3 fs / 8 and the phase of the received symbol is rotated by π / 4 to 3π / 4 in 1 / fs time.
[0012]
Similarly, the frequency of the received signal is offset by −fs / 8 to −3 fs / 8 from the set frequency so that the phase of the received symbol rotates by −π / 4 to −3π / 4 in 1 / fs time. In this situation, the demodulated signal output from the automatic frequency control circuit 63 cannot be correlated by the first correlation circuit 64 and the second correlation circuit 65. In this situation, the fixed bit pattern of the received signal is (Sq, -Si) in which the value of the first correlation circuit 64 is offset in the-direction by π. Therefore, when the fixed bit pattern of (Sq, -Si) is set as the correlation coefficient of the third correlation circuit 66, and the correlation is obtained by the third correlation circuit 66, the received signal is -fs / Information is obtained that the frequency is offset by 8 to −3 fs / 8 and the phase of the received symbol is rotated by −π / 4 to −3π / 4 in 1 / fs time.
[0013]
Next, the operation of the determination circuit 67 will be described.
The determination circuit 67 receives the correlation results of the first correlation circuit 64, the second correlation circuit 65, and the third correlation circuit 66, and examines the three correlations to estimate the received symbols per 1 / fs time. Is used to determine the correction amount Δθ of the frequency error signal output from the automatic frequency control circuit 63.
[0014]
Here, when the correlation is obtained by the first correlation circuit 64, the phase rotation amount of the received symbol is ± π / 4 or less per 1 / fs time. In this case, it is determined that synchronization is established in a normal quadrant. Therefore, since the frequency error amount detected by the automatic frequency control circuit 63 is a value estimated in a normal quadrant, there is no need to correct it, and therefore the output of the determination circuit 67 (correction amount of the frequency error signal) Δθ. Is 0.
[0015]
When the correlation is obtained by the second correlation circuit 65, the phase rotation amount of the received symbol is π / 4 to 3π / 4 per 1 / fs time. Therefore, in order to remove the frequency error in the normal quadrant, the frequency error signal output from the automatic frequency control circuit 63 is set so that the phase rotation amount of the received symbol is ± π / 4 or less per 1 / fs time. It is necessary to set a correction amount. That is, when the correlation is obtained by the second correlation circuit 65, the output Δθ of the determination circuit 67 is set to −π / 2, and −π / 2 per 1 / fs time is added to the phase rotation amount of the received symbol. . The phase shift amount −π / 2 given per 1 / fs time is −1/4 of the symbol rate as a discriminating value of the frequency error.
[0016]
When the correlation is obtained by the third correlation circuit 66, the phase rotation amount of the received symbol is −3π / 4 to −π / 4 per 1 / fs time. Therefore, similarly, the output Δθ of the determination circuit 67 may be set to + π / 2, and π / 2 per 1 / fs time may be added to the phase rotation amount of the received symbol. The phase shift amount + π / 2 given per 1 / fs time is 1/4 of the symbol rate as a discriminating value of the frequency error.
[0017]
FIG. 7 shows a determination algorithm of the determination circuit 67 of the conventional automatic frequency control device.
When the first correlation circuit 64 checks the correlation and finds a correlation, the determination circuit 67 outputs 0 as the determination circuit output Δθ and ends the process. Next, when the correlation is not obtained by the first correlation circuit 65 and the correlation is obtained by examining the correlation by the second correlation circuit 65, −π / 2 is output as the determination circuit output Δθ, and the first correlation circuit 65 The procedure returns to the procedure for examining the correlation of the correlation circuit 64. If the correlation is not obtained by the first correlation circuit 64 and the second correlation circuit 65 but the correlation is obtained by examining the correlation by the third correlation circuit 66, + π / 2 is output as the determination circuit output Δθ. Then, the procedure returns to the procedure for examining the correlation of the first correlation circuit 64. In the conventional automatic frequency control device, the case where the correlation is not obtained by the third correlation circuit 66 is not particularly taken into consideration, and the processing is terminated.
[0018]
That is, when the correlation is obtained by the first correlation circuit 64, the frequency error signal output from the automatic frequency control circuit 63 is fed back to the oscillation circuit 69 as it is, and the process is terminated. When the correlation is obtained by the second correlation circuit 65, −π / 2 is added to the frequency error signal and fed back to the oscillation circuit 69, so that the correlation can be obtained by the first correlation circuit 64. The process ends.
[0019]
As described above, the determination circuit 67 is 0 when the correlation is obtained by the first correlation circuit 64, -π / 2 when the correlation is obtained by the second correlation circuit 65, and the third correlation circuit. When the correlation is obtained at 66, + π / 2 is output to the adder circuit 68 and added to the frequency error signal output from the automatic frequency control circuit 63 to control the oscillation frequency of the oscillation circuit 69. By inputting the signal of the frequency controlled in this way to the multiplication circuit 61 and multiplying the received signal, the frequency error component that is frequency offset from the set frequency to which the received signal is assigned can be removed.
[0020]
[Non-Patent Document 1]
Igarashi, 5 others, “A study on AFC method using multiple correlators”, 1994 Autumn Meeting of IEICE, B-290
[Non-Patent Document 2]
Fujino Tadashi "Digital Mobile Communications" Shosho-do, 1st edition, published on June 10, 2000, pp.52-78, pp.122-152
[Non-Patent Document 3]
Naoshi Iida "Satellite Communications" Ohmsha, 1st edition, published on May 30, 1998, pp.301-333
[Non-Patent Document 4]
Heiichi Yamamoto and Shuzo Kato “TDMA Communication” The Institute of Electronics, Information and Communication Engineers, 1st edition, published on May 1, 1997, pp.76-89
[0021]
[Problems to be solved by the invention]
By the way, the conventional automatic frequency control apparatus uses three correlation circuits as shown in FIG. 6, and does not consider the case where the correlation cannot be obtained by the third correlation circuit 66 as shown in FIG. The maximum frequency error that can be performed is a rotation amount of a maximum of ± 3π / 4 of the received symbol phase per 1 / fs time on the phase plane, and a frequency error amount of ± 3 fs / 8 on the frequency axis.
[0022]
Further, there are cases where the conventional determination algorithm shown in FIG. 7 cannot correct the frequency error (the received symbol cannot be synchronized), and this phenomenon will be described below with reference to FIG. FIG. 8 shows the phase rotation amount of the symbol due to the frequency error per 1 / fs time of the input signal of the automatic frequency control circuit 63 on the phase plane.
[0023]
First, the transmission symbol position on the transmission side is set to # 0 on the phase plane. FIG. 8 shows the phase rotation amount of the symbol due to the frequency error. If there is no frequency error, the phase rotation amount of the reception symbol is # 0 (hereinafter referred to as “reception symbol # 0” or “# 0”), and the transmission symbol Match the position. Under this assumption, it is assumed that the received symbol is affected by the frequency error, and if there is no noise, the received symbol is rotated by a phase amount slightly smaller than π / 4 per 1 / fs time, and is represented as received symbol # 1 in FIG. . If there is no noise, the received symbol # 1 can be correlated by the first correlation circuit 64. Accordingly, the frequency error component is removed by the automatic frequency control circuit 63, and the transmission symbol # 0 can be estimated by correcting the phase rotation amount of the reception symbol # 1.
[0024]
However, since noise is generally added to a received signal in a propagation path or a modem circuit, the following situation is assumed as an example. In a situation where noise is added, received symbol # 1 may rotate more than π / 4 per 1 / fs time. At this time, the received symbol # 1 moves to the position of # 2 in the phase plane, and the received symbol # 2 is correlated by the second correlation circuit 65. Here, if −π / 2 output from the determination circuit 67 is added to the frequency error signal output from the automatic frequency control circuit 63 to control the oscillation frequency of the oscillation circuit 69, then it is input to the automatic frequency control circuit 63. The received symbol is # 3.
[0025]
This received symbol # 3 may move to the position of # 4 due to the addition of noise. At this time, the received symbol # 4 is correlated by the third correlation circuit 66. Here, if + π / 2 output from the determination circuit 67 is added to the frequency error signal output from the automatic frequency control circuit 63 to control the oscillation frequency of the oscillation circuit 69, the next reception input to the automatic frequency control circuit 63 is performed. The symbol is # 5 and is in the vicinity of the reception symbol # 1.
[0026]
Thus, reception symbol # 1 transitions to reception symbol # 2 by adding noise and becomes reception symbol # 3 after rotation of the symbol phase amount of −π / 2, but has transitioned to reception symbol # 4 by adding noise. When a symbol phase amount of + π / 2 is rotated and the received symbol # 5 is in the vicinity of the received symbol # 1, it is assumed that a transition to the received symbol # 2 occurs again due to the addition of noise. When such symbol transitions occur repeatedly, the automatic frequency control circuit 63 of FIG. 6 cannot estimate the frequency error amount accurately because the frequency error amount to be estimated varies greatly with time due to the influence of noise. In other words, the reception signal cannot be synchronized for a long time after the start of reception, and the line quality is greatly deteriorated.
[0027]
As another example, when the symbol input to the automatic frequency control circuit 63 fluctuates between # 1 and # 2 due to the influence of noise, the correlation result does not exceed the threshold value. 64 and the second correlation circuit 65 cannot be correlated. In this case as well, the automatic frequency control circuit 63 of FIG. 6 cannot accurately estimate the frequency error amount, and the received signal cannot be synchronized for a long time, so that the line quality is greatly deteriorated.
[0028]
In this way, the phase rotation amount per 1 / fs time of the received symbol input to the automatic frequency control circuit 63 changes due to the influence of noise, and the correlation circuit that can be correlated with time is different, or the correlation circuit that can be correlated When there is no signal, the determination circuit 67 cannot estimate the frequency error region, so that the line quality of the received signal is greatly deteriorated. Specifically, in this situation, the phase rotation amount of the received symbol per 1 / fs time is near ± π / 4 or ± 3π / 4, and on the frequency axis, near ± fs / 8, or ± 3 fs. This occurs when a frequency offset in the vicinity of / 8 is received. Hereinafter, the frequency error region in the vicinity of ± fs / 8 and ± 3 fs / 8 is referred to as “automatic frequency control unstable region”.
[0029]
The present invention can estimate and remove a frequency error amount of ± 3 fs / 8 or more in an automatic frequency control apparatus that estimates and removes a frequency error amount using a correlation circuit, and receives a received signal from a set frequency. An automatic frequency control device that estimates and removes the frequency error amount without being affected by noise when it receives a frequency error in the vicinity of ± fs / 8 or ± 3 fs / 8, and suppresses deterioration in line quality. The purpose is to provide.
[0030]
[Means for Solving the Problems]
The automatic frequency control apparatus according to the present invention is characterized in that a fourth correlation circuit is provided to detect a signal that is offset from the set frequency by more than ± 3 fs / 8. In the prior art, the upper limit of the control range of the frequency error was ± 3 fs / 8, but a wide range of frequency error amounts exceeding ± 3 fs / 8 can be estimated and removed by the present invention. .
[0031]
Further, in the automatic frequency control device of the present invention, when correlation cannot be obtained in all the correlation circuits, the correction amount of the frequency error signal is α (where α is the symbol rate n / 4 (n is an integer)). It is characterized in that a determination circuit for outputting (different values) is provided.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows the overall configuration of the first embodiment of the present invention.
[0033]
In the figure, the received signal and the output signal of the oscillation circuit 8 are multiplied by the multiplication circuit 1, and the frequency-converted signal is input to the demodulation circuit 2. The demodulating circuit 2 outputs a frequency error signal indicating a frequency error amount estimated from the input signal, a demodulated signal obtained by removing the frequency error amount from the input signal, and data detected from the demodulated signal. The demodulated signal is branched into four by the four-branch circuit 10 and input to the first correlation circuit 3, the second correlation circuit 4, the third correlation circuit 5, and the fourth correlation circuit 6, respectively, and each correlation result is determined by the determination circuit. 7 is output. The determination circuit 7 determines the correction amount Δθ of the frequency error signal output from the demodulation circuit 2 according to the four correlation results, and outputs the correction signal. The adder circuit 9 adds the frequency error signal and the correction signal to the oscillation circuit 8 and controls the oscillation frequency.
[0034]
The first correlation circuit 3, the second correlation circuit 4, and the third correlation circuit 5 have the same configuration as the correlation circuits 64, 65, and 66 having the conventional configuration shown in FIG. Hereinafter, a circuit design method for the fourth correlation circuit 6 which is a feature of the present embodiment, and a control function newly added by adding the fourth correlation circuit 6 in the determination circuit 7 will be described.
[0035]
In the conventional configuration shown in FIG. 6, it was possible to correct a maximum frequency error of ± 3 fs / 8 from the set frequency. First, as a frequency error amount equal to or greater than the maximum frequency error, 3 fs / 8˜ Assume a situation where there is a frequency error of 5 fs / 8.
[0036]
In a situation where there is a frequency error of 3 fs / 8 to 5 fs / 8, the demodulated signal output from the demodulation circuit 2 has a symbol phase further from the situation where the received signal is offset by fs / 8 to 3 fs / 8 from the set frequency. The rotation is + π / 2 per 1 / fs time. As a result, when a frequency offset of ± fs / 8 or less is received, the symbol phase is rotated by + π per 1 / fs time. The fixed bit pattern of the first correlation circuit that correlates signals having a frequency offset of ± fs / 8 or less is (Si, Sq) as described in the section of the prior art. Therefore, when the symbol phase is further rotated by + π per 1 / fs time than in this case, the fixed bit pattern that can be correlated with the input signal is rotated by the fixed bit pattern of the first correlation circuit by + π (−Si). , -Sq).
[0037]
On the other hand, in a situation where there is a frequency error of −5 fs / 8 to −3 fs / 8, the demodulated signal output from the demodulation circuit 2 is a situation where the received signal is offset from the set frequency by −3 fs / 8 to −fs / 8. Therefore, the symbol phase is further rotated by −π / 2 per 1 / fs time. As a result, since a frequency offset of ± fs / 8 or less is received, the symbol phase is rotated by −π per 1 / fs time. The fixed bit pattern of the first correlation circuit that correlates signals having a frequency offset of ± fs / 8 or less is (Si, Sq) as described in the section of the prior art. Therefore, when the symbol phase is further rotated by −π per 1 / fs time than in this case, the fixed bit pattern that can be correlated with the input signal is obtained by rotating the fixed bit pattern of the first correlation circuit by −π ( -Si, -Sq).
[0038]
As described above, when the fixed bit pattern of (-Si, -Sq) is set in the fourth correlation circuit 6 and correlation is established with the input signal, the frequency error amount of the received signal is 3 fs / 8 to 5 fs / 8. Alternatively, it can be estimated that it is in the range of −5 fs / 8 to −3 fs / 8.
[0039]
Here, if the received signal exists in the frequency error region of 3 fs / 8 to 5 fs / 8 from the set frequency, the phase rotation amount of the symbol becomes 3π / 4 to 5π / 4 in 1 / fs time. In this case, by rotating the symbol phase by −π / 2 in 1 / fs time, the symbol phase rotation amount per 1 / fs time becomes π / 4 to 3π / 4. Correlation can be taken. When the correlation is obtained by the second correlation circuit 4, the phase of the received symbol is rotated by −π / 2, so that the phase rotation amount of the symbol is finally corrected to ± π / 4 or less per 1 / fs time. The As a result, the frequency error can be removed in the automatic frequency control circuit existing in the demodulation circuit 2. Therefore, when the correlation is obtained by the fourth correlation circuit 6, if the received signal exists in the frequency error region of 3 fs / 8 to 5 fs / 8 from the set frequency, the correction amount of the frequency error signal output from the determination circuit 7 is It may be set to −π / 2.
[0040]
On the other hand, if the received signal exists in the frequency error region of −5 fs / 8 to −3 fs / 8 from the set frequency, the phase rotation amount of the symbol becomes −5π / 4 to −3π / 4 in 1 / fs time. In this case, by rotating the symbol phase by π / 2 in 1 / fs time, the symbol phase rotation amount per 1 / fs time becomes −3π / 4 to −π / 4, and the third correlation circuit 5 Can be correlated. When the correlation is obtained by the third correlation circuit 5, the phase of the received symbol is rotated by π / 2, so that the amount of phase rotation of the symbol is finally corrected to ± π / 4 or less per 1 / fs time. . As a result, the frequency error can be removed in the automatic frequency control circuit existing in the demodulation circuit 2. Therefore, when the correlation is obtained by the fourth correlation circuit 6, if the received signal exists in the frequency error region of −5 fs / 8 to −3 fs / 8 from the set frequency, the frequency error signal output from the determination circuit 7 is corrected. The amount may be π / 2.
[0041]
However, when the correlation is obtained by the fourth correlation circuit 6, it is estimated that the frequency error amount of the received signal is in the range of 3 fs / 8 to 5 fs / 8 or −5 fs / 8 to −3 fs / 8. However, since the correlation result is output in the same manner in any frequency error region, it cannot be specified which frequency error region. That is, it cannot be determined whether the correction amount Δθ of the frequency error signal output from the determination circuit 7 is −π / 2 or π / 2. A procedure for controlling the output of the determination circuit 7 after the correlation is obtained by the fourth correlation circuit 6 will be described below with reference to FIG.
[0042]
When the correlation is obtained by the fourth correlation circuit 6, the determination circuit 7 assumes that the received signal exists in the frequency error region of 3 fs / 8 to 5 fs / 8 from the set frequency, and outputs the output as −π / 2. To do. As a result, the oscillation circuit 8 is controlled by adding −π / 2 to the frequency error signal. Therefore, if the assumption is correct, the second correlation circuit 4 can be correlated. Therefore, when the correlation is obtained in the second correlation circuit 4, the output of the determination circuit 7 can be finally determined as -π / 2.
[0043]
On the other hand, if the above assumption is incorrect, the output of the determination circuit 7 is set to −π / 2, and the amount of symbol phase rotation per 1 / fs time is −7π / 4 to −5π / 4. In this case, the received signal is offset by a frequency larger than the set frequency, so that no correlation circuit is correlated. Therefore, after setting the output of the determination circuit 7 to −π / 2, paying attention to the correlation result of the second correlation circuit 4, if there is no correlation in the second correlation circuit 4, it is determined that there is an error in the assumption, and reception It is determined that the signal exists in the frequency error region of −5 fs / 8 to −3 fs / 8 from the set frequency.
[0044]
In the case of this frequency error, the output of the determination circuit 7 should originally be π / 2, but because −π / 2 controls the oscillation circuit 8 as the output of the determination circuit 7 under the wrong assumption, In order to cancel this and further increase the output to + π / 2, the output of the determination circuit 7 needs to be + π. As a result, the frequency control of the oscillation circuit 8 based on an erroneous assumption is canceled, and the third correlation circuit 5 is in a state of being correlated. Therefore, when the correlation is obtained by the third correlation circuit 5, the output of the determination circuit 7 can be finally determined as + π / 2.
[0045]
By configuring the fourth correlation circuit 6 and the determination circuit 7 as described above, it is possible to remove frequency errors from the set frequency up to ± 5 fs / 8.
[0046]
(Judgment algorithm of judgment circuit 7)
3 and 4 show a determination algorithm of the determination circuit 7 in the first embodiment.
[0047]
In FIG. 3, when the correlation is obtained by examining the correlation in the first correlation circuit 3, the determination circuit 7 outputs 0 as the determination circuit output Δθ and ends the process. Next, when the correlation is not obtained in the first correlation circuit 3 and the correlation is obtained by examining the correlation in the second correlation circuit 4, −π / 2 is output as the determination circuit output Δθ, and the first The procedure returns to the procedure for examining the correlation of the correlation circuit 3. Further, when the correlation is not obtained by the first correlation circuit 3 and the second correlation circuit 4 and the correlation is obtained by examining the correlation by the third correlation circuit 5, + π / 2 is output as the determination circuit output Δθ. Then, the procedure returns to the procedure for examining the correlation of the first correlation circuit 3. The above procedure (a) is the same as that of the conventional configuration shown in FIG.
[0048]
In the automatic frequency control device according to the present embodiment, when the correlation cannot be obtained by the third correlation circuit 5, the process proceeds to the fourth correlation circuit 6, and when the correlation is examined by the fourth correlation circuit 6, the correlation is obtained. As described above, -π / 2 is output as the determination circuit output Δθ, and the correlation is examined by the second correlation circuit 4. When the correlation is obtained by the second correlation circuit 4, −π / 2 is determined as the determination circuit output Δθ, and the procedure returns to the procedure for examining the correlation of the first correlation circuit 3. On the other hand, when the correlation cannot be obtained by the second correlation circuit 4, + π is output as the determination circuit output Δθ, and the correlation is examined by the third correlation circuit 5. When the correlation is obtained by the third correlation circuit 5, + π / 2 is determined as the determination circuit output Δθ, and the procedure returns to the procedure for examining the correlation of the first correlation circuit 3.
[0049]
If the correlation cannot be obtained by the fourth correlation circuit 6, the process is terminated. However, the processing is ended here, including whether to enter a standby state or to restart the input from each correlation circuit to the determination circuit 7.
[0050]
The determination algorithm of the determination circuit 7 shown in FIG. 4 outputs + π / 2 as the determination circuit output Δθ by reversing the above assumption in the case of FIGS. 2 and 3 when the correlation is obtained by the fourth correlation circuit 6. To do. In this case, the correlation is examined by the third correlation circuit 5, and when the correlation is obtained by the third correlation circuit 5, + π / 2 is determined as the determination circuit output Δθ, and the first correlation circuit 3 Return to the procedure to check the correlation. On the other hand, when the third correlation circuit 5 cannot obtain the correlation, -π is output as the determination circuit output Δθ, and the second correlation circuit 4 checks the correlation. When the correlation is obtained by the second correlation circuit 4, −π / 2 is determined as the determination circuit output Δθ, and the procedure returns to the procedure for examining the correlation of the first correlation circuit 3.
[0051]
In the description of this embodiment, the output of the determination circuit 7 is set to ± π / 2 and ± π. However, these values are not exact, and allow for some errors such as ± 0.49π. Yes.
[0052]
In addition, when the correlation is obtained by the fourth correlation circuit, instead of outputting ± π / 2 as the output of the determination circuit, the phase of the received symbol can be shifted to a quadrant in a direction where there is a quadrant that can be normally synchronized. Such an output value may be set. For example, in the determination algorithm of FIG. 3, “fourth correlation circuit — [− π / 2 phase operation] —second correlation circuit — [− π / 2 phase operation] —first correlation circuit” or “first correlation circuit” 4 correlation circuits-[-π / 2 phase operation]-second correlation circuit-[+ π phase operation]-third correlation circuit-[+ π / 2 phase operation]-first correlation circuit " The phase amount is sequentially controlled so that the symbols transition to quadrants that can be synchronized in two or three stages, and the same applies to the determination algorithm of FIG. 4, but the phase when the correlation is obtained in the fourth correlation circuit. For example, an operation amount may be set to −π, and an algorithm that performs synchronization in one stage, such as “fourth correlation circuit — [− π phase operation] —first correlation circuit” may be used. However, if the correlation cannot be obtained in the first correlation circuit at this time, the output of the determination circuit is set to + 2π, and “fourth correlation circuit − [− π phase operation] −first correlation circuit − [+ 2π phase operation” is set. ] —First correlation circuit ”, the algorithm is synchronized in two stages.
[0053]
Further, in the determination algorithm of FIGS. 3 and 4 (FIGS. 11 and 12 to be described later), the order of the second correlation circuit and the third correlation circuit may be switched to check the correlation with the input signal.
[0054]
(Configuration example of demodulation circuit 2)
When the delay detection method is adopted as the detection method of the demodulation circuit 2, the demodulation circuit 2 can be formed by the delay detection circuit 62 and the automatic frequency control circuit 63 shown in FIG. 6. That is, a frequency error signal indicating the estimated frequency error amount and a demodulated signal obtained by removing the frequency error amount from the reproduction signal are output from the automatic frequency control circuit 63 that inputs the reproduction signal output from the clock recovery circuit 624. The demodulated signal is branched into four and input to each correlation circuit.
[0055]
FIG. 5 shows another configuration example of the demodulation circuit 2. The configuration example of FIG. 5 (1) is a case where the absolute synchronous detection method is adopted as the detection method, and the configuration example of FIG. 5 (2) is a case where the differential code synchronous detection method is adopted as the detection method.
[0056]
In FIG. 5 (1), the input signal of the demodulation circuit 2 (the output signal of the multiplication circuit 1) is input to the quadrature detection circuit 21 for quadrature detection, and the detected signal is input to the clock recovery circuit 22 for timing recovery. . An automatic frequency control circuit 23 that inputs a reproduction signal output from the clock reproduction circuit 22 outputs a frequency error signal indicating a frequency error amount estimated from the reproduction signal and a signal obtained by removing the frequency error amount from the reproduction signal. . The frequency error signal is input to the adder circuit 9 shown in FIG. The signal from which the frequency error amount has been removed is input to the carrier wave recovery circuit 24 and becomes a signal from which the phase offset component has been removed. This signal is branched into two by a two-branch circuit 25, and the detection circuit 26 determines one of the signal areas and outputs a data bit string.
[0057]
The other signal branched into two by the two-branch circuit 24 is input to the 1-symbol difference circuit 27, and a difference signal between the input signal and a signal obtained by delaying it by one symbol time is generated. This differential signal is input as a demodulated signal of the demodulating circuit 2 to each correlation circuit (3 to 6) via the four-branch circuit 10 shown in FIG.
[0058]
Here, the reason for taking the difference value for one symbol is that the differentially encoded UW fixed bit pattern is (Si, Sq), and the correlation coefficient of each correlation circuit is set based on the pattern. Because it is. Since the absolute synchronous detection method does not perform differential encoding on the transmission side, it is necessary to perform differential encoding on the reception side in order to set the correlation coefficient of the correlation circuit to the above pattern. In the absolute synchronous detection method, since the frequency error of ± fs / 8 or less can be compensated for by the automatic frequency control circuit 23, the frequency error signal detected by the automatic frequency control circuit 23 may not be output to the adder circuit 9. is there.
[0059]
The basic configuration of the demodulation circuit 2 shown in FIG. 5 (2) is the same as that of the absolute synchronous detection method shown in FIG. 5 (1), but information is transmitted on the transmission side in order to adopt the differential code synchronous detection method. The difference is that the bits are differentially encoded and the one-symbol difference circuit 27 is not required. Further, in the differential code synchronous detection method, since the frequency error of ± fs / 8 or less can be compensated for by the automatic frequency control circuit 23, the frequency error signal detected by the automatic frequency control circuit 23 is not output to the adder circuit 9. In some cases.
[0060]
The demodulating circuit 2 used in the automatic frequency control device of the present invention has shown a configuration example in which a delay detection method, an absolute synchronous detection method, a differential code synchronous detection method, etc. are adopted as a detection method as described above. It is not limited to each circuit configuration. In this embodiment, the Gray code is assumed as the encoding method of the input signal. However, the principle of the present invention can be applied to other encoding methods as well.
[0061]
(Second Embodiment)
The second embodiment shows an improved example of the determination algorithm of the determination circuit 67 in the conventional automatic frequency control device. In the conventional configuration, as described with reference to FIG. 8, when there is a frequency error in the vicinity of ± fs / 8 or ± 3 fs / 8 from the set frequency, the line quality cannot be removed due to the influence of noise. However, the present embodiment solves this problem.
[0062]
FIG. 9 shows a determination algorithm of the determination circuit 67 in the second embodiment. The automatic frequency control apparatus according to the present embodiment will be described by taking the conventional configuration shown in FIG. 6 as an example. For example, the delay detection circuit 62 and the automatic frequency control circuit 63 have the configuration of another demodulation circuit as shown in FIG. It can also be taken.
[0063]
When the first correlation circuit 64 checks the correlation and finds a correlation, the determination circuit 67 outputs 0 as the determination circuit output Δθ and ends the process. Next, when the correlation is not obtained by the first correlation circuit 65 and the correlation is obtained by examining the correlation by the second correlation circuit 65, −π / 2 is output as the determination circuit output Δθ, and the first correlation circuit 65 The procedure returns to the procedure for examining the correlation of the correlation circuit 64. If the correlation is not obtained by the first correlation circuit 64 and the second correlation circuit 65 but the correlation is obtained by examining the correlation by the third correlation circuit 66, + π / 2 is output as the determination circuit output Δθ. Then, the procedure returns to the procedure for examining the correlation of the first correlation circuit 64. The above procedure is the same as that of the conventional configuration shown in FIG.
[0064]
In this embodiment, when no correlation is obtained in any of the first correlation circuit 64, the second correlation circuit 65, and the third correlation circuit 66, the determination circuit 67 uses α (however, α is a value different from nπ / 2 (n is an integer), and the procedure returns to the procedure for examining the correlation of the first correlation circuit 64.
[0065]
An example in which such a determination algorithm can avoid a state in which the frequency error cannot be removed due to the influence of noise will be described with reference to FIG. FIG. 10 shows the phase rotation amount of the symbol due to the frequency error per 1 / fs time of the input signal of the automatic frequency control circuit 63 in the same manner as FIG.
[0066]
First, π / 4 is set as an example of α, and a situation is assumed in which the received symbol is rotated by −7π / 32 per 1 / fs time. When a large noise is added to the signal in this situation, it is assumed that the automatic frequency control is unstable (the area indicated by hatching in the figure) that cannot be synchronized. For example, when the received symbol fluctuates between the correlation frequency error region of the first correlation circuit and the correlation frequency error region of the third correlation circuit due to noise, the correlation values of all the correlation circuits do not exceed the set threshold value become. At this time, the determination circuit 67 outputs α (= π / 4) according to the determination algorithm of FIG.
[0067]
In FIG. 10, it is assumed that the transmission symbol is # 0 while the reception symbol is # 1. In this assumption, the phase amount of the received symbol # 1 is rotated by −7π / 32 per 1 / fs time. Therefore, if α (= π / 4) is set as the output of the determination circuit 67, the phase of the received symbol is subtracted. It rotates by π / 32 per 1 / fs time and transitions to the position of received symbol # 2. Since the rotation amount is within ± π / 4 per 1 / fs time that can be removed by the automatic frequency control circuit 63 as described above, it can be easily removed by the automatic frequency control circuit 63. As a result, the correlation is obtained by the first correlation circuit 64, the output of the determination circuit 67 becomes 0, and the processing of FIG.
[0068]
(Third embodiment)
The third embodiment shows an improved example of the determination algorithm of the determination circuit 7 in the first embodiment of FIG. An improved example of the determination algorithm shown in FIG. 3 is shown in FIG. 11, and an improved example of the determination algorithm shown in FIG. 4 is shown in FIG.
[0069]
In any case, when any of the first correlation circuit 3, the second correlation circuit 4, the third correlation circuit 5, and the fourth correlation circuit 6 cannot be correlated, the determination circuit 7 determines the correction amount of the frequency error signal. As α (where α is a value different from nπ / 2 (n is an integer)), and the procedure returns to the procedure for examining the correlation of the first correlation circuit 3. The operation after outputting α is the same as the operation shown in the second embodiment.
[0070]
【The invention's effect】
As described above, since the automatic frequency control apparatus of the present invention can correct a frequency error exceeding ± 3 fs / 8 from the set frequency, a large frequency error caused by Doppler shift in a moving body moving at high speed. Can be corrected, and the use range of mobile communication can be expanded.
[0071]
In addition, since a large frequency error caused by using an oscillator that is inexpensive and small but has poor frequency stability can be corrected, the cost of the terminal can be reduced.
[0072]
Further, when the received signal receives a frequency offset in the vicinity of ± fs / 8 or ± 3 fs / 8 from the set frequency, the frequency error amount can be estimated and removed stably even when receiving noise. Therefore, it is possible to suppress deterioration of the line quality.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of a first embodiment of the present invention.
FIG. 2 is a flowchart illustrating a main part of a determination algorithm of a determination circuit 7 according to the first embodiment.
FIG. 3 is a flowchart illustrating a determination algorithm of the determination circuit 7 according to the first embodiment.
FIG. 4 is a flowchart showing a determination algorithm of the determination circuit 7 according to the first embodiment.
FIG. 5 is a block diagram showing another configuration example of the demodulation circuit 2 of the first embodiment.
FIG. 6 is a block diagram showing a configuration example of a conventional automatic frequency control device.
FIG. 7 is a flowchart showing a determination algorithm of a determination circuit 67 of a conventional automatic frequency control device.
FIG. 8 is a diagram for explaining an example in which received symbols cannot be synchronized by a conventional determination algorithm;
FIG. 9 is a flowchart showing a determination algorithm of a determination circuit 67 in the second embodiment.
FIG. 10 is a diagram illustrating an improvement example of a determination algorithm according to the second embodiment.
FIG. 11 is a flowchart showing an improved example of the determination algorithm shown in FIG. 3;
12 is a flowchart showing an improved example of the determination algorithm shown in FIG. 4;
[Explanation of symbols]
1 Multiplier circuit
2 Demodulator circuit
21 Quadrature detection circuit
22 Clock recovery circuit
23 Automatic frequency control circuit
24 Carrier recovery circuit
25 2-branch circuit
26 Detection circuit
27 1-symbol difference circuit
3 First correlation circuit
4 Second correlation circuit
5 Third correlation circuit
6 Fourth correlation circuit
7 Judgment circuit
8 Oscillator circuit
9 Adder circuit
10 4-branch circuit
61 Multiplier circuit
62 Delay detection circuit
621 2-branch circuit
622 delay circuit
623 Quadrature detection circuit
624 clock recovery circuit
625 2-branch circuit
626 detection circuit
63 Automatic frequency control circuit
64 First correlation circuit
65 Second correlation circuit
66 Third correlation circuit
67 Judgment circuit
68 Adder circuit
69 Oscillator circuit
70 3-branch circuit

Claims (9)

発振周波数制御端子に入力する制御信号に応じて発振周波数の制御が可能な発振回路と、
４相位相変調された受信信号と前記発振回路の出力信号を乗算して周波数変換する乗算回路と、
前記周波数変換された信号を入力し、その入力信号から推定した周波数誤差量を示す周波数誤差信号と、この周波数誤差量を入力信号から除去した復調信号と、この復調信号から検出されたデータを出力する復調回路と、
前記復調信号を４分岐する４分岐回路と、
４分岐された前記復調信号をそれぞれ入力し、それぞれ所定の相関係数との相関をとる４つの相関回路と、
前記４つの相関回路の各相関結果に応じて、前記周波数誤差信号の補正量を判定する判定回路と、
前記周波数誤差信号と前記補正量を加算し、前記発振回路の発振周波数制御端子に与える加算回路とを備え、
前記４つの相関回路を第１の相関回路、第２の相関回路、第３の相関回路、第４の相関回路としたときに、それぞれの相関係数として、前記受信信号の周波数誤差量がシンボルレートの０，−１／４，１／４，１／２で伝送されたときのビットパターンを設定し、
前記判定回路は、前記周波数誤差信号の補正量として、前記第１の相関回路で入力信号と相関がとれた場合に０を出力し、前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力し、前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力し、前記第１の相関回路、前記第２の相関回路および前記第３の相関回路で相関がとれず、前記第４の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力してさらに前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力し、または前記第４の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力してさらに前記第２の相関回路で入力信号と相関がとれない場合にシンボルレートの１／２を出力してさらに前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力する構成である
ことを特徴とする自動周波数制御装置。An oscillation circuit capable of controlling the oscillation frequency in accordance with a control signal input to the oscillation frequency control terminal;
A multiplying circuit that multiplies the received signal that has undergone four-phase phase modulation and the output signal of the oscillation circuit to convert the frequency;
The frequency-converted signal is input, and a frequency error signal indicating a frequency error amount estimated from the input signal, a demodulated signal obtained by removing the frequency error amount from the input signal, and data detected from the demodulated signal are output. A demodulation circuit to
A four-branch circuit for four-branching the demodulated signal;
Each of the four-branched demodulated signals is input, and four correlation circuits each for correlating with a predetermined correlation coefficient;
A determination circuit for determining a correction amount of the frequency error signal according to each correlation result of the four correlation circuits;
An addition circuit that adds the frequency error signal and the correction amount and gives the oscillation error control terminal to the oscillation circuit;
When the four correlation circuits are a first correlation circuit, a second correlation circuit, a third correlation circuit, and a fourth correlation circuit, the frequency error amount of the received signal is a symbol as a correlation coefficient. Set the bit pattern when transmitted at 0, -1/4, 1/4, 1/2 of the rate,
When the first correlation circuit correlates with the input signal, the determination circuit outputs 0 as the correction amount of the frequency error signal, and when the second correlation circuit correlates with the input signal -1/4 of the symbol rate is output to the first correlation circuit, and when the third correlation circuit correlates with the input signal, 1/4 of the symbol rate is output, and the first correlation circuit and the second correlation When the correlation is not obtained in the circuit and the third correlation circuit and the input signal is correlated in the fourth correlation circuit, -1/4 of the symbol rate is output and input in the second correlation circuit. When the correlation with the signal is obtained , -1/4 of the symbol rate is output, or when the correlation with the input signal is obtained with the fourth correlation circuit, -1/4 of the symbol rate is output, and further, When the correlation circuit of 2 cannot correlate with the input signal, Automatic frequency control device which is a configuration for outputting a quarter of the symbol rate in the case where the correlation between the input signal caught by further said third correlation circuit outputs 1/2 of Borureto. 発振周波数制御端子に入力する制御信号に応じて発振周波数の制御が可能な発振回路と、
４相位相変調された受信信号と前記発振回路の出力信号を乗算して周波数変換する乗算回路と、
前記周波数変換された信号を入力し、その入力信号から推定した周波数誤差量を示す周波数誤差信号と、この周波数誤差量を入力信号から除去した復調信号と、この復調信号から検出されたデータを出力する復調回路と、
前記復調信号を４分岐する４分岐回路と、
４分岐された前記復調信号をそれぞれ入力し、それぞれ所定の相関係数との相関をとる４つの相関回路と、
前記４つの相関回路の各相関結果に応じて、前記周波数誤差信号の補正量を判定する判定回路と、
前記周波数誤差信号と前記補正量を加算し、前記発振回路の発振周波数制御端子に与える加算回路とを備え、
前記４つの相関回路を第１の相関回路、第２の相関回路、第３の相関回路、第４の相関回路としたときに、それぞれの相関係数として、前記受信信号の周波数誤差量がシンボルレートの０，−１／４，１／４，１／２で伝送されたときのビットパターンを設定し、
前記判定回路は、前記周波数誤差信号の補正量として、前記第１の相関回路で入力信号と相関がとれた場合に０を出力し、前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力し、前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力し、前記第１の相関回路、前記第２の相関回路および前 記第３の相関回路で相関がとれず、前記第４の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力してさらに前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力し、または前記第４の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力してさらに前記第３の相関回路で入力信号と相関がとれない場合にシンボルレートの−１／２を出力してさらに前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力する構成である
ことを特徴とする自動周波数制御装置。An oscillation circuit capable of controlling the oscillation frequency in accordance with a control signal input to the oscillation frequency control terminal;
A multiplying circuit that multiplies the received signal that has undergone four-phase phase modulation and the output signal of the oscillation circuit to convert the frequency;
The frequency-converted signal is input, and a frequency error signal indicating a frequency error amount estimated from the input signal, a demodulated signal obtained by removing the frequency error amount from the input signal, and data detected from the demodulated signal are output. A demodulation circuit to
A four-branch circuit for four-branching the demodulated signal;
Each of the four-branched demodulated signals is input, and four correlation circuits each for correlating with a predetermined correlation coefficient;
A determination circuit for determining a correction amount of the frequency error signal according to each correlation result of the four correlation circuits;
An addition circuit that adds the frequency error signal and the correction amount and gives the oscillation error control terminal to the oscillation circuit;
When the four correlation circuits are a first correlation circuit, a second correlation circuit, a third correlation circuit, and a fourth correlation circuit, the frequency error amount of the received signal is a symbol as a correlation coefficient. Set the bit pattern when transmitted at 0, -1/4, 1/4, 1/2 of the rate,
When the first correlation circuit correlates with the input signal, the determination circuit outputs 0 as the correction amount of the frequency error signal, and when the second correlation circuit correlates with the input signal -1/4 of the symbol rate is output to the first correlation circuit, and when the third correlation circuit correlates with the input signal, 1/4 of the symbol rate is output, and the first correlation circuit and the second correlation circuits and pre-symbol third correlation in the correlation circuit Torezu, input in the fourth further said third correlation circuit outputs 1/4 of the symbol rate in the case where the correlation between the input signal caught by the correlation circuit When the correlation with the signal is obtained , 1/4 of the symbol rate is output, or when the correlation with the input signal is obtained with the fourth correlation circuit, 1/4 of the symbol rate is output and further the third rate is output. Symbol when the correlation circuit cannot correlate with the input signal Automatic frequency control device which is a configuration for outputting a -1/4 symbol rate when correlated with the input signal caught by further said second correlation circuit outputs a -1/2 over preparative . 発振周波数制御端子に入力する制御信号に応じて発振周波数の制御が可能な発振回路と、
４相位相変調された受信信号と前記発振回路の出力信号を乗算して周波数変換する乗算回路と、
前記周波数変換された信号を入力し、その入力信号から推定した周波数誤差量を示す周波数誤差信号と、この周波数誤差量を入力信号から除去した復調信号と、この復調信号から検出されたデータを出力する復調回路と、
前記復調信号を３分岐する３分岐回路と、
３分岐された前記復調信号をそれぞれ入力し、それぞれ所定の相関係数との相関をとる３つの相関回路と、
前記３つの相関回路の各相関結果に応じて、前記周波数誤差信号の補正量を判定する判定回路と、
前記周波数誤差信号と前記補正量を加算し、前記発振回路の発振周波数制御端子に与える加算回路とを備え、
前記３つの相関回路を第１の相関回路、第２の相関回路、第３の相関回路としたときに、それぞれの相関係数として、前記受信信号の周波数誤差量がシンボルレートの０，−１／４，１／４で伝送されたときのビットパターンを設定し、
前記判定回路は、前記周波数誤差信号の補正量として、前記第１の相関回路で入力信号と相関がとれた場合に０を出力し、前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力し、前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力し、いずれの相関回路でも入力信号と相関がとれない場合にα（ただし、αはシンボルレートのｎ／４（ｎは整数）とは異なる値）を出力する構成である
ことを特徴とする自動周波数制御装置。An oscillation circuit capable of controlling the oscillation frequency in accordance with a control signal input to the oscillation frequency control terminal;
A multiplying circuit that multiplies the received signal that has undergone four-phase phase modulation and the output signal of the oscillation circuit to convert the frequency;
The frequency-converted signal is input, and a frequency error signal indicating a frequency error amount estimated from the input signal, a demodulated signal obtained by removing the frequency error amount from the input signal, and data detected from the demodulated signal are output. A demodulation circuit to
A three-branch circuit that branches the demodulated signal into three branches;
Three correlation circuits that respectively input the three-branch demodulated signals and correlate with predetermined correlation coefficients;
A determination circuit for determining a correction amount of the frequency error signal according to each correlation result of the three correlation circuits;
An addition circuit that adds the frequency error signal and the correction amount and gives the oscillation error control terminal to the oscillation circuit;
When the three correlation circuits are a first correlation circuit, a second correlation circuit, and a third correlation circuit, the frequency error amount of the received signal is 0 or −1 of the symbol rate as a correlation coefficient. Set the bit pattern when transmitted at / 4, 1/4,
When the first correlation circuit correlates with the input signal, the determination circuit outputs 0 as the correction amount of the frequency error signal, and when the second correlation circuit correlates with the input signal Is output -1/4 of the symbol rate, and when the third correlation circuit correlates with the input signal, it outputs 1/4 of the symbol rate, and none of the correlation circuits correlates with the input signal. In this case, the automatic frequency control apparatus is characterized in that α is output (where α is a value different from n / 4 (n is an integer) of the symbol rate). 請求項１または請求項２に記載の自動周波数制御装置において、
前記判定回路は、前記周波数誤差信号の補正量として、いずれの相関回路でも入力信号と相関がとれない場合にα（ただし、αはシンボルレートのｎ／４（ｎは整数）とは異なる値）を出力する構成である
ことを特徴とする自動周波数制御装置。In the automatic frequency control device according to claim 1 or 2 ,
The determination circuit uses α as a correction amount of the frequency error signal when any correlation circuit cannot correlate with the input signal (where α is a value different from n / 4 of the symbol rate (n is an integer)). The automatic frequency control apparatus characterized by the above-mentioned. 請求項１に記載の自動周波数制御装置の判定回路が行う自動周波数制御方法において、
前記第１の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力として０を出力して処理を終了し、
前記第１の相関回路で相関がとれないときに、前記第２の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの−１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路および前記第２の相関回路で入力信号との相関がとれないときに、前記第３の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路、前記第２の相関回路および前記第３の相関回路で入力信号との相関がとれないときに、前記第４の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの−１／４を出力し、さらに前記第２の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの−１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、逆に前記第２の相関回路で入力信号との相関を調べて相関がとれない場合に判定回路出力としてシンボルレートの１／２を出力し、さらに前記第３の相関回路で入力信号と相関がとれた場合にシンボルレートの１／４を出力し、前記第１の相関回路の相関を調べる手順に戻る
ことを特徴とする自動周波数制御方法。 In the automatic frequency control method performed by the determination circuit of the automatic frequency control device according to claim 1 ,
When the correlation with the input signal is examined by the first correlation circuit and a correlation is obtained, 0 is output as the determination circuit output and the process is terminated.
When the correlation is not obtained by the first correlation circuit, the correlation with the input signal is examined by the second correlation circuit, and when the correlation is obtained, -1/4 of the symbol rate is output as the determination circuit output, Returning to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit and the second correlation circuit cannot correlate with the input signal, the third correlation circuit examines the correlation with the input signal and obtains a correlation. Output 1/4 of the symbol rate, and return to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit, the second correlation circuit, and the third correlation circuit cannot correlate with the input signal, the fourth correlation circuit checks the correlation with the input signal to obtain the correlation. Is output as a determination circuit output, and -1/4 of the symbol rate is output as a determination circuit output. Further, when the correlation with the input signal is examined by the second correlation circuit, the correlation is obtained. 4 is returned to the procedure for examining the correlation of the first correlation circuit. Conversely, when the correlation with the input signal is examined by the second correlation circuit and the correlation cannot be obtained, 1 of the symbol rate is output as the determination circuit output. / 2, and when the third correlation circuit correlates with the input signal, outputs 1/4 of the symbol rate, and returns to the procedure for examining the correlation of the first correlation circuit. Automatic frequency control method. 請求項２に記載の自動周波数制御装置の判定回路が行う自動周波数制御方法において、
前記第１の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力として０を出力して処理を終了し、
前記第１の相関回路で相関がとれないときに、前記第２の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの−１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路および前記第２の相関回路で入力信号との相関がとれないときに、前記第３の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路、前記第２の相関回路および前記第３の相関回路で入力信号との相関がとれないときに、前記第４の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの１／４を出力し、さらに前記第３の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、逆に前記第３の相関回路で入力信号との相関を調べて相関がとれない場合に判定回路出力としてシンボルレートの−１／２を出力し、さらに前記第２の相関回路で入力信号と相関がとれた場合にシンボルレートの−１／４を出力し、前記第１の相関回路の相関を調べる手順に戻る
ことを特徴とする自動周波数制御方法。 In the automatic frequency control method performed by the determination circuit of the automatic frequency control device according to claim 2 ,
When the correlation with the input signal is examined by the first correlation circuit and a correlation is obtained, 0 is output as the determination circuit output and the process is terminated.
When the correlation is not obtained by the first correlation circuit, the correlation with the input signal is examined by the second correlation circuit, and when the correlation is obtained, -1/4 of the symbol rate is output as the determination circuit output, Returning to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit and the second correlation circuit cannot correlate with the input signal, the third correlation circuit examines the correlation with the input signal and obtains a correlation. Output 1/4 of the symbol rate, and return to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit, the second correlation circuit, and the third correlation circuit cannot correlate with the input signal, the fourth correlation circuit checks the correlation with the input signal to obtain the correlation. Is output as a determination circuit output, and 1/4 of the symbol rate is output as the determination circuit output when the correlation with the input signal is further checked by the third correlation circuit. Returning to the procedure for examining the correlation of the first correlation circuit, conversely, if the correlation with the input signal is examined by the third correlation circuit and the correlation cannot be obtained, the symbol rate -1 / 2 is output, and when the second correlation circuit correlates with the input signal, -1/4 of the symbol rate is output, and the procedure returns to the procedure for examining the correlation of the first correlation circuit. Automatic frequency control method. 請求項３に記載の自動周波数制御装置の判定回路が行う自動周波数制御方法において、
前記第１の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力として０を出力して処理を終了し、
前記第１の相関回路で相関がとれないときに、前記第２の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの−１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路および前記第２の相関回路で入力信号との相関がとれないときに、前記第３の相関回路で入力信号との相関を調べて相関がとれた場合に判定回路出力としてシンボルレートの１／４を出力し、前記第１の相関回路の相関を調べる手順に戻り、
前記第１の相関回路、前記第２の相関回路および前記第３の相関回路で入力信号との相関がとれないときに、判定回路出力としてα（ただし、αはシンボルレートのｎ／４（ｎは整数）とは異なる値）を出力し、前記第１の相関回路の相関を調べる手順に戻る
ことを特徴とする自動周波数制御方法。 In the automatic frequency control method performed by the determination circuit of the automatic frequency control device according to claim 3 ,
When the correlation with the input signal is examined by the first correlation circuit and a correlation is obtained, 0 is output as the determination circuit output and the process is terminated.
When the correlation is not obtained by the first correlation circuit, the correlation with the input signal is examined by the second correlation circuit, and when the correlation is obtained, -1/4 of the symbol rate is output as the determination circuit output, Returning to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit and the second correlation circuit cannot correlate with the input signal, the third correlation circuit examines the correlation with the input signal and obtains a correlation. Output 1/4 of the symbol rate, and return to the procedure for examining the correlation of the first correlation circuit,
When the first correlation circuit, the second correlation circuit, and the third correlation circuit cannot correlate with an input signal, α is output as a determination circuit output, where α is n / 4 (n Is a value different from an integer), and the procedure returns to the procedure for examining the correlation of the first correlation circuit. 請求項５または請求項６に記載の自動周波数制御方法において、
前記第１の相関回路、前記第２の相関回路、前記第３の相関回路および前記第４の相関回路で入力信号との相関がとれないときに、判定回路出力としてα（ただし、αはシンボルレートのｎ／４（ｎは整数）とは異なる値）を出力し、前記第１の相関回路の相関を調べる手順に戻る
ことを特徴とする自動周波数制御方法。 In the automatic frequency control method according to claim 5 or 6 ,
When the first correlation circuit, the second correlation circuit, the third correlation circuit, and the fourth correlation circuit cannot correlate with the input signal, α is a decision circuit output (where α is a symbol) An automatic frequency control method characterized by outputting a rate n / 4 (a value different from an integer) and returning to the procedure of examining the correlation of the first correlation circuit. 請求項５〜７のいずれかに記載の自動周波数制御方法において、
前記第２の相関回路と前記第３の相関回路の順番を入れ替えて入力信号との相関を調べる手順とする
ことを特徴とする自動周波数制御方法。 In the automatic frequency control method in any one of Claims 5-7 ,
An automatic frequency control method characterized in that the order of the second correlation circuit and the third correlation circuit is changed to check the correlation with the input signal.
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