JP2007059666A - Manufacturing method and apparatus for semiconductor device, control program, and computer memory medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device, etc. whereby a time required for manufacturing the semiconductor device can be shortened in comparison with a conventional one. <P>SOLUTION: The manufacturing method for the semiconductor device has a process for forming a via hole 110 first by plasma-etching an insulating layer 103 in a treatment chamber by using a hard mask 105 for a via hole as a mask; a process for removing next therefrom the residual resist mask 105 for the via hole by ashing; a process for so depositing next a protective film 111 having an organic material as to leave the protective film 111 present in the via hole 110, and as to remove by ashing therefrom the protective film 111 present in a portion other than the via hole 110; and a process for so forming a trench 112 next by plasma etching by using a hard mask 104 for a trenche as a mask as to remove by ashing thereafter the protective film 111 left in the via hole 110. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor device manufacturing apparatus, a control program, and a computer storage medium.

  In recent years, in a manufacturing process of a semiconductor device, a dual damascene process in which a via hole and a trench are formed in a semiconductor substrate and a metal such as copper is embedded in the semiconductor substrate to form a via contact and a wiring simultaneously has come to be used. ing.

  As a dual damascene process as described above, for example, a method of forming a via contact and a wiring by the following process is known (see, for example, Patent Document 1). In this method, first, an insulating film is etched by etching or the like through a via resist mask to form a via hole. Next, the remaining resist mask is removed by ashing or the like. Next, a protective film for protecting the underlying layer at the bottom of the via hole is formed by CVD or the like. Next, a resist mask for trenches is formed by applying a photoresist with a coater, exposing with an exposure device, developing with a developing device, and the like. Next, a trench for wiring is formed by etching through a resist mask for trench. Then, the remaining resist mask, protective film, and the like are removed by ashing, etching, or the like.

By the above process, via holes and trenches are formed, and then a metal such as copper is buried in these via holes and trenches by a plating apparatus or the like, and the surface is polished by CMP or the like to remove metal on the surface other than the trench portions. A via contact and a wiring are formed.
JP 2004-111950 A

  In the conventional technique described above, it is necessary to perform a number of steps for performing the dual damascene process using an etching apparatus, a CVD apparatus, or an ashing apparatus. In addition, there is a problem that it is necessary to clean the semiconductor wafer between these processes, and the manufacturing process takes time.

  The present invention has been made to solve the above-described problems, and a semiconductor device manufacturing method, a semiconductor device manufacturing apparatus, a control program, and a computer capable of shortening the time required for manufacturing a semiconductor device as compared with the prior art. An object is to provide a storage medium.

  The method of manufacturing a semiconductor device according to claim 1 is a method of manufacturing a semiconductor device having a dual damascene structure, wherein a trench mask and a via hole resist mask are stacked on an insulating film. A step of accommodating a semiconductor substrate in a processing chamber; a via hole forming step of etching the insulating film through the via hole resist mask to form a via hole; and a resist mask removing step of removing the via hole resist mask by ashing; A protective film forming step of forming a protective film having an organic material for protecting a base film that is a bottom of the via hole and located under the insulating film; and etching the insulating film through the trench mask; A trench forming step of forming a trench, and the via hole in the processing chamber; Formation step, the resist mask removing step, the protective film forming step, after the trench formation step, characterized by comprising a step of unloading the semiconductor substrate from the process chamber.

  A method for manufacturing a semiconductor device according to claim 2 is the method for manufacturing a semiconductor device according to claim 1, wherein the via hole forming step, the resist mask removing step, the protective film forming step, and the trench forming step are performed. Is performed as a series of processes in the same processing chamber.

  The method for manufacturing a semiconductor device according to claim 3 is a method for manufacturing a semiconductor device having a dual damascene structure, wherein a trench mask and a via hole resist mask are stacked on an insulating film. A step of accommodating a semiconductor substrate in a processing chamber; a via hole forming step of etching the insulating film through the via hole resist mask to form a via hole; and a resist mask removing step of removing the via hole resist mask by ashing; A protective film forming step of forming a protective film having an organic material for protecting a base film that is a bottom of the via hole and located under the insulating film; and etching the insulating film through the trench mask; A trench forming process for forming a trench, and the remaining protective film is removed by ashing. After the protective film removing step and the via hole forming step, the resist mask removing step, the protective film forming step, the trench forming step, and the protective film removing step in the processing chamber, the inside of the processing chamber And a step of carrying out the semiconductor substrate.

  A method for manufacturing a semiconductor device according to claim 4 is the method for manufacturing a semiconductor device according to claim 3, wherein the via hole forming step, the resist mask removing step, the protective film forming step, and the trench forming step are performed. The protective film removing step is performed as a series of processes in the same processing chamber.

  The method for manufacturing a semiconductor device according to claim 5 is the method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the protective film forming step includes a step of depositing the protective film, and a step in the via hole. And a step of removing the protective film deposited at a site other than by ashing.

  The method for manufacturing a semiconductor device according to claim 6 is the method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the protective film is deposited using CxFy gas or CxHyFz gas. Features.

  The method for manufacturing a semiconductor device according to claim 7 is the method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein an upper electrode and a lower electrode facing the upper electrode are provided in the processing chamber. A high frequency can be applied to each of the upper electrode and the lower electrode.

  9. The semiconductor device manufacturing apparatus according to claim 8, wherein a processing chamber for accommodating a semiconductor substrate, a processing gas supply means for supplying a processing gas into the processing chamber, and the processing gas supplied from the processing gas supply means are plasma-treated. A plasma generation unit configured to perform plasma processing on the semiconductor substrate and a control unit configured to control the semiconductor device manufacturing method according to claim 1 to be performed in the processing chamber. It is characterized by that.

  A control program according to claim 9 operates on a computer and controls a semiconductor device manufacturing apparatus so that the semiconductor device manufacturing method according to any one of claims 1 to 7 is performed at the time of execution. Features.

  The computer storage medium according to claim 10 is a computer storage medium in which a control program that operates on a computer is stored, and the control program is executed by the semiconductor device according to any one of claims 1 to 7. The semiconductor device manufacturing apparatus is controlled so that the manufacturing method is performed.

  According to the present invention, it is possible to reduce the time required for manufacturing a semiconductor device as compared with the conventional case.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an enlarged cross-sectional configuration of a semiconductor wafer (semiconductor substrate) W in the semiconductor device manufacturing method according to the present embodiment, and FIG. 2 shows plasma processing as a semiconductor manufacturing apparatus according to the present embodiment. The structure of an apparatus is shown. First, the configuration of the plasma processing apparatus will be described with reference to FIG.

  The plasma processing apparatus 1 is configured as a capacitively coupled parallel plate etching apparatus in which electrode plates face each other vertically and are connected to a plasma forming power source.

  The plasma processing apparatus 1 has a processing chamber (processing container) 2 formed of, for example, aluminum whose surface is anodized and formed into a cylindrical shape, and the processing chamber 2 is grounded. A substantially cylindrical susceptor support 4 for placing an object to be processed, for example, a semiconductor wafer W, is provided at the bottom of the processing chamber 2 via an insulating plate 3 such as ceramic. Further, a susceptor 5 constituting a lower electrode is provided on the susceptor support 4. A high pass filter (HPF) 6 is connected to the susceptor 5.

  A refrigerant chamber 7 is provided inside the susceptor support 4, and a refrigerant is introduced into the refrigerant chamber 7 through a refrigerant introduction pipe 8 and circulated, and the cold heat is transmitted through the susceptor 5 to the semiconductor wafer. Heat is transferred to W, whereby the semiconductor wafer W is controlled to a desired temperature.

  The upper center portion of the susceptor 5 is formed in a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as the semiconductor wafer W is provided thereon. The electrostatic chuck 11 is configured by disposing an electrode 12 between insulating materials. Then, when a DC voltage of, for example, 1.5 kV is applied from the DC power source 13 connected to the electrode 12, the semiconductor wafer W is electrostatically attracted by, for example, Coulomb force.

  The insulating plate 3, the susceptor support 4, the susceptor 5, and the electrostatic chuck 11 are formed with a gas passage 14 for supplying a heat transfer medium (for example, He gas) on the back surface of the semiconductor wafer W. The cold heat of the susceptor 5 is transmitted to the semiconductor wafer W via the heat transfer medium so that the semiconductor wafer W is maintained at a predetermined temperature.

  An annular focus ring 15 is disposed at the upper peripheral edge of the susceptor 5 so as to surround the semiconductor wafer W placed on the electrostatic chuck 11. The focus ring 15 is made of, for example, a conductive material such as silicon, and has an effect of improving etching uniformity.

  An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel. The upper electrode 21 is supported on the upper portion of the processing chamber 2 via an insulating material 22, forms a surface facing the susceptor 5, and has a large number of discharge holes 23. For example, the surface is anodized ( The electrode plate 24 is configured by providing a quartz cover on anodized aluminum and an electrode support 25 made of a conductive material that supports the electrode plate 24. The distance between the susceptor 5 and the upper electrode 21 can be changed.

  A gas inlet 26 is provided in the center of the electrode support 25 in the upper electrode 21, and a gas supply pipe 27 is connected to the gas inlet 26. Further, a processing gas supply source 30 is connected to the gas supply pipe 27 via a valve 28 and a mass flow controller 29. A processing gas for plasma processing, for example, a processing gas for etching, a processing gas for ashing, a processing gas for depositing a protective film, or the like is supplied from the processing gas supply source 30.

  An exhaust pipe 31 is connected to the bottom of the processing chamber 2, and an exhaust device 35 is connected to the exhaust pipe 31. The exhaust device 35 includes a vacuum pump such as a turbo molecular pump, and is configured to be able to evacuate the processing chamber 2 to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa or less. Further, a gate valve 32 is provided on the side wall of the processing chamber 2 so that the semiconductor wafer W is transferred to and from an adjacent load lock chamber (not shown) with the gate valve 32 opened. It has become.

  A first high frequency power supply 40 is connected to the upper electrode 21, and a matching device 41 is inserted in the feeder line. Further, a low pass filter (LPF) 42 is connected to the upper electrode 21. The first high frequency power supply 40 has a frequency in the range of 50 to 150 MHz. By applying such a high frequency, it is possible to form a high-density plasma in a preferable dissociated state in the processing chamber 2.

  A second high-frequency power source 50 is connected to the susceptor 5 serving as a lower electrode, and a matching unit 51 is interposed in the power supply line. The second high-frequency power supply 50 has a lower frequency range than the first high-frequency power supply 40. By applying a frequency in such a range, the semiconductor wafer W that is the object to be processed is damaged. Appropriate ion action can be given without giving. The frequency of the second high frequency power supply 50 is preferably in the range of 1 to 20 MHz.

  The operation of the plasma processing apparatus 1 having the above configuration is comprehensively controlled by the control unit 60. The control unit 60 includes a process controller 61 that includes a CPU and controls each unit of the plasma processing apparatus 1, a user interface 62, and a storage unit 63.

  The user interface 62 includes a keyboard that allows a process manager to input commands to manage the plasma processing apparatus 1, a display that visualizes and displays the operating status of the plasma processing apparatus 1, and the like.

  The storage unit 63 stores a recipe that stores a control program (software), processing condition data, and the like for realizing various processes executed by the plasma processing apparatus 1 under the control of the process controller 61. Then, if desired, an arbitrary recipe is called from the storage unit 63 by an instruction from the user interface 62 and is executed by the process controller 61, so that a desired process in the plasma processing apparatus 1 is performed under the control of the process controller 61. Is performed. In addition, recipes such as control programs and processing condition data may be stored in a computer-readable computer storage medium (eg, hard disk, CD, flexible disk, semiconductor memory, etc.), or It is also possible to transmit the data from other devices as needed via a dedicated line and use it online.

  When via holes and trenches for a dual damascene structure are formed in the semiconductor wafer W by the plasma processing apparatus 1 having the above-described configuration, first, after the gate valve 32 is opened, the semiconductor wafer W is removed from a load lock chamber (not shown). It is carried into the processing chamber 2 and placed on the electrostatic chuck 11. The semiconductor wafer W is electrostatically attracted onto the electrostatic chuck 11 by applying a DC voltage from the high-voltage DC power supply 13. Next, the gate valve 32 is closed, and the processing chamber 2 is evacuated to a predetermined degree of vacuum by the exhaust device 35.

  Thereafter, the valve 28 is opened, and a predetermined processing gas from the processing gas supply source 30 is adjusted in flow rate by the mass flow controller 29, and the hollow of the upper electrode 21 passes through the processing gas supply pipe 27 and the gas inlet 26. Then, the liquid is uniformly discharged onto the semiconductor wafer W through the discharge holes 23 of the electrode plate 24 as shown by the arrows in FIG.

  Then, the pressure in the processing chamber 2 is maintained at a predetermined pressure. Thereafter, high frequency power having a predetermined frequency is applied to the upper electrode 21 from the first high frequency power supply 40. As a result, a high-frequency electric field is generated between the upper electrode 21 and the susceptor 5 as the lower electrode, and the processing gas is dissociated into plasma.

  On the other hand, high frequency power having a frequency lower than that of the first high frequency power supply 40 is applied from the second high frequency power supply 50 to the susceptor 5 serving as the lower electrode. Thereby, ions in the plasma are drawn to the susceptor 5 side, and the anisotropy of etching is enhanced by ion assist. The supply of high-frequency power to the susceptor 5 is reduced or not performed, for example, when an ion drawing effect is not required in a protective film deposition process or the like.

  Then, when a series of predetermined processes to be described later is completed, the supply of high-frequency power and the supply of process gas are stopped, and the semiconductor wafer W is unloaded from the process chamber 2 by a procedure reverse to the procedure described above.

  Next, a method for manufacturing a semiconductor device having a dual damascene structure according to the present embodiment will be described with reference to FIG. As shown in FIG. 1A, on the surface of a semiconductor wafer W as an object to be processed, a second underlayer 101 made of a metal (conductor) such as copper and a first lower layer made of SiCN or the like are sequentially formed from the lower side. A base layer 102 and an insulating layer 103 made of SiOC or the like are formed. On the insulating layer 103, a trench hard mask 104 made of TiN or the like and a via hole resist mask 105 made of a photoresist are laminated. The semiconductor wafer W is carried into the processing chamber 2 of the plasma processing apparatus 1 in this state.

  In the processing chamber 2, first, using the via hole resist mask 105 as a mask, the insulating layer 103 is plasma etched to form a via hole 110, and the state shown in FIG. In this plasma etching, various known gases for plasma etching that can plasma-etch the insulating layer 103 (for example, SiOC), such as fluorine-based gas, can be used.

  Next, ashing is performed from the state shown in FIG. 1B, and the remaining via hole resist mask 105 is removed to obtain the state shown in FIG. For this ashing, oxygen gas or a mixed gas of oxygen and argon can be used.

Next, a protective film 111 having an organic material for protecting the first underlayer 102 at the bottom of the via hole 110 is deposited to obtain the state shown in FIG. 1D. Thereafter, ashing is performed to complete the via hole. The protective film 111 in 110 is left, and the other part of the protective film 111 is removed to obtain the state shown in FIG. The formation process of the protective film 111 is constituted by the deposition process of these protective films 111 and the removal process of unnecessary portions. For the deposition of the protective film 111, various kinds of depositing gases can be used. For example, CxFy gas, CxHyFz gas, etc. (x, y, z are positive integers) can be used. Specifically, for _{example, CF 4, C 2 F 6} , C 3 F 8, C 4 F 8, C 3 F 6, C 4 F 6, C 5 F 8, CH 4, C 2 H 4, C 2 Gases such as H ₂ , CHF ₃ , C ₂ F ₅ , C ₃ F ₇ , CH ₂ F ₂ , and CH ₃ F and mixed gases of these gases with other gases can be used. For the ashing of the protective film 111, oxygen gas or a mixed gas of oxygen and argon can be used.

  Next, plasma etching is performed using the trench hard mask 104 as a mask to form a trench 112, which is in the state of FIG. At this time, the first underlayer 102 at the bottom of the via hole 110 is protected by the protective film 111 from being etched. Thereafter, ashing is performed to remove the protective film 111 remaining in the via hole 110 to obtain the state shown in FIG. In this plasma etching, various known gases for plasma etching that can plasma-etch the insulating layer 103 (for example, SiOC), such as fluorine-based gas, can be used. For the ashing of the protective film 111, oxygen gas or a mixed gas of oxygen and argon can be used.

  In the processing chamber 2, the series of steps described above are performed to form the via hole 110 and the trench 112 in the semiconductor wafer W, and then the semiconductor wafer W is unloaded from the processing chamber 2. Thereafter, a plating process, a CMP process, and the like are performed, and a conductor such as copper is embedded in the via hole 110 and the trench 112 to form a via contact and a wiring. The last remaining protective film 111 may be removed by another process after the semiconductor wafer W is unloaded from the processing chamber 2.

  As described above, in the present embodiment, the via hole 110 and the trench 112 can be formed by performing the above-described series of steps while the semiconductor wafer W is accommodated in the processing chamber 2. Therefore, the time required for manufacturing the semiconductor device can be greatly shortened as compared with the conventional method in which each process is carried separately to different devices.

  As an example, the above-described process is performed on the semiconductor wafer W (photoresist = 100 nm, TiN = 50 nm, SiOC = 400 nm, SiCN = 50 nm) having the structure shown in FIG. 1 using the plasma processing apparatus 1 shown in FIG. Was carried out according to the recipe as shown below.

  In addition, the process recipe of the Example shown below is read from the memory | storage part 63 of the control part 60, is taken in into the process controller 61, and the process controller 61 controls each part of the plasma processing apparatus 1 based on a control program. By doing so, the etching process according to the read processing recipe is executed.

(Via hole etching)
Process gas: C ₄ F ₈ / N ₂ / Ar = 6/180/500 sccm, pressure 5.33 Pa (40 mTorr), power (upper / lower) = 800/1700 W. The etching rate in this via hole etching step was 250 nm / min, and the selectivity (SiOC etching rate / SiCN etching rate) was 10.

(Ashing of resist mask for via holes)
Process gas: O ₂ = 500 sccm, pressure 2.0 Pa (15 mTorr), power (upper / lower) = 300/400 W. The ashing rate in the ashing process of this resist mask was 500 nm / min.

(Protective film deposition)
Process gas: C ₄ F ₈ / Ar = 20/300 sccm, pressure 26.6 Pa (200 mTorr), power (upper / lower) = 1000/0 W. The deposition rate of the protective film in this protective film deposition step was 200 nm / min.

(Protecting film ashing)
Process gas: O ₂ = 500 sccm, pressure 2.0 Pa (15 mTorr), power (upper / lower) = 300/400 W. The ashing rate of the protective film in this protective film ashing step was 500 nm / min.

(Trench etching)
Process gas: CF ₄ / Ar / O ₂ = 120/150/6 sccm, pressure 10.66 Pa (80 mTorr), power (upper / lower) = 300/200 W. The etching rate in this trench etching step was 250 nm / min, and the selectivity (SiOC etching rate / SiCN etching rate) was 3.

(Ashing the remaining protective film)
Process gas: O ₂ = 500 sccm, pressure 2.0 Pa (15 mTorr), power (upper / lower) = 300/400 W. The ashing rate of the protective film in this remaining protective film ashing step was 500 nm / min.

  Next, a method for manufacturing a semiconductor wafer W on which a trench hard mask and a via hole resist mask are formed will be described with reference to FIG. First, as shown in FIG. 3A, in advance from the bottom, a second base layer 101 made of a metal (conductor) such as copper, a first base layer 102 made of SiCN or the like, an insulating layer made of SiOC or the like. A hard mask material 120 such as TiN is formed on the surface of the semiconductor wafer W on which the semiconductor layer 103 is formed by CVD or the like to obtain the state shown in FIG.

  Next, as shown in FIG. 3C, a photoresist 121 is applied to the surface of the hard mask material 120, and then exposed and developed to form a resist mask 122 as shown in FIG. 3D.

  Next, the hard mask material 120 is etched using the resist mask 122 as a mask to form a trench hard mask 104 as shown in FIG. 3E. Thereafter, the remaining resist mask 122 is removed by ashing. The state shown in FIG.

  Next, as shown in FIG. 3G, a photoresist 123 is applied on the surface, and then exposed and developed to form a via hole resist mask 105 as shown in FIG. 3H. The semiconductor wafer W on which the trench hard mask 104 and the via hole resist mask 105 are formed can be manufactured through the above-described steps. Then, as described above, the semiconductor wafer W in this state is carried into the processing chamber 2.

  As described above, according to the present embodiment, the time required for manufacturing the semiconductor device can be reduced as compared with the conventional case. In addition, this invention is not limited to said embodiment, Various deformation | transformation are possible. For example, the plasma processing apparatus is not limited to the parallel plate type upper and lower high-frequency application type shown in FIG. 2, and various plasma processing apparatuses can be used. Further, the semiconductor substrate to be used is not limited to the exemplified materials of the hard mask and the insulating layer as long as the semiconductor substrate has a structure substantially similar to the structure shown in FIG. Various things can be used.

The figure which shows the cross-sectional structure of the semiconductor wafer which concerns on the etching method of embodiment of this invention. The figure which shows schematic structure of the etching apparatus which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor wafer which has a mask for trenches, and a mask for vias.

Explanation of symbols

  101 …… Second underlayer (copper), 102 …… First underlayer (SiCN), 103 …… Insulating layer (SiOC), 104 …… Trench hard mask (TiN), 105 …… Via hole resist mask, 110 ... via hole, 111 ... protective film, 112 ... trench.

Claims (10)

A method of manufacturing a semiconductor device for manufacturing a semiconductor device having a dual damascene structure,
Accommodating a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film in a processing chamber;
Etching the insulating film through the via hole resist mask to form a via hole;
A resist mask removing step of removing the resist mask for via holes by ashing;
A protective film forming step of forming a protective film having an organic material for protecting the base film serving as the bottom of the via hole, located under the insulating film;
Etching the insulating film through the trench mask to form a trench; and
And carrying out the via hole forming step, the resist mask removing step, the protective film forming step, and the trench forming step in the processing chamber, and then carrying out the semiconductor substrate from the processing chamber. A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the via hole forming step, the resist mask removing step, the protective film forming step, and the trench forming step are performed as a series of processes in the same processing chamber. A method of manufacturing a semiconductor device for manufacturing a semiconductor device having a dual damascene structure,
Accommodating a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film in a processing chamber;
Etching the insulating film through the via hole resist mask to form a via hole;
A resist mask removing step of removing the resist mask for via holes by ashing;
A protective film forming step of forming a protective film having an organic material for protecting the base film serving as the bottom of the via hole, located under the insulating film;
Etching the insulating film through the trench mask to form a trench; and
A protective film removing step of removing the remaining protective film by ashing;
A step of carrying out the semiconductor substrate from the processing chamber after performing the via hole forming step, the resist mask removing step, the protective film forming step, the trench forming step, and the protective film removing step in the processing chamber. A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 3,
The via hole forming step, the resist mask removing step, the protective film forming step, the trench forming step, and the protective film removing step are performed as a series of processes in the same processing chamber. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the protective film forming step includes a step of depositing the protective film, and a step of removing the protective film deposited in a portion other than the inside of the via hole by ashing. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the protective film is deposited using CxFy gas or CxHyFz gas. A method of manufacturing a semiconductor device according to claim 1,
An upper electrode and a lower electrode facing the upper electrode are provided in the processing chamber, and a high frequency can be applied to each of the upper electrode and the lower electrode. Production method. A processing chamber containing a semiconductor substrate;
A processing gas supply means for supplying a processing gas into the processing chamber;
Plasma generating means for converting the processing gas supplied from the processing gas supply means into plasma and plasma processing the semiconductor substrate;
A semiconductor device manufacturing apparatus, comprising: a control unit that controls the semiconductor device manufacturing method according to claim 1 to be performed in the processing chamber.   8. A control program that operates on a computer and controls a semiconductor device manufacturing apparatus so that the semiconductor device manufacturing method according to claim 1 is performed during execution. A computer storage medium storing a control program that runs on a computer,
8. A computer storage medium, wherein the control program controls a semiconductor device manufacturing apparatus so that the method of manufacturing a semiconductor device according to claim 1 is performed at the time of execution.

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