JP2007059529A - Manufacturing method of circuit board - Google Patents

Manufacturing method of circuit board Download PDF

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JP2007059529A
JP2007059529A JP2005241205A JP2005241205A JP2007059529A JP 2007059529 A JP2007059529 A JP 2007059529A JP 2005241205 A JP2005241205 A JP 2005241205A JP 2005241205 A JP2005241205 A JP 2005241205A JP 2007059529 A JP2007059529 A JP 2007059529A
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conductive
insulating resin
circuit board
metal foil
conductive projection
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JP4772424B2 (en
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Fumihiko Matsuda
文彦 松田
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Nippon Mektron KK
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board in which thermoplastic resin and thermosetting resin, which are used as interlayer insulating resin, are not peeled from a conductive projection, without depending on a temporary adhesion condition at the time of manufacturing the circuit board by connection using the conductive projection. <P>SOLUTION: For manufacturing the circuit board where a circuit substrate having metal foil in which the conductive projection is erected at least on one face, and an insulating resin layer stuck to one face of metal foil by pressure in a state where the conductive projection passes through the insulating resin layer is laminated with another circuit substrate or with a metal foil; the insulating resin layer is stuck by pressure to metal foil where the conductive projection is erected. The top of the conductive projection is pressurized, and the size of the top of the conductive projection is made larger than the hole through which the conductive projection passes in the insulating resin layer. The circuit substrate is laminated with the other circuit member or metal foil. Circuit layers are connected by the conductive projection. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、回路基板の製造方法に係り、詳しくは導電性突起で層間の接続を行う回路基板の製造方法に関する。   The present invention relates to a method for manufacturing a circuit board, and more particularly to a method for manufacturing a circuit board in which layers are connected by conductive protrusions.

近年、電子機器の小型化および高機能化は益々促進されてきており、そのために回路基板に対する高密度化の要求が高まってきている。そこで、回路基板を片面から両面や三層以上の多層回路基板とすることにより、回路基板の高密度化を図っている。   In recent years, downsizing and higher functionality of electronic devices have been promoted more and more, and therefore, there is an increasing demand for higher density of circuit boards. In view of this, the circuit board is made to be a multi-layer circuit board from one side to both sides or three or more layers to increase the density of the circuit board.

これらの回路基板においては、従来、層間接続には、レーザー、NCドリル、プラズマエッチング、化学エッチング等による開孔後、メッキ処理を行う手法が採用されている。しかし、メッキ処理工程自体の歩留まりが悪いという欠点と、絶縁樹脂層の導通をとるための工程が煩雑であるという欠点を有する。   In these circuit boards, conventionally, for interlayer connection, a technique of performing a plating process after opening by laser, NC drill, plasma etching, chemical etching or the like is employed. However, it has the disadvantage that the yield of the plating process itself is poor and the process for conducting the insulating resin layer is complicated.

そこで回路基板の層間の電気的な接続を従来のメッキ法によるビアホール接続から、所謂、導電ペーストによる印刷バンプやメッキ又はエッチングによる金属バンプなどの導電性突起を用いた接続に置き換える手法が開発されている。   Therefore, a method has been developed in which the electrical connection between the circuit board layers is replaced with a connection using a conductive protrusion such as a printing bump by a conductive paste or a metal bump by plating or etching instead of a conventional via hole connection by a plating method. Yes.

上述の導電性突起を用いた接続による回路基板の層間絶縁材は熱可塑性樹脂および熱硬化性樹脂に大別できる。熱可塑性樹脂としては例えば熱可塑性ポリイミドや液晶ポリマー等が挙げられる。熱硬化性樹脂としてはエポキシ系プリプレグが基板材料として広く用いられている。   The interlayer insulating material of the circuit board by the connection using the conductive protrusion described above can be roughly divided into a thermoplastic resin and a thermosetting resin. Examples of the thermoplastic resin include thermoplastic polyimide and liquid crystal polymer. As the thermosetting resin, an epoxy prepreg is widely used as a substrate material.

これらの層間絶縁樹脂を導電性突起が立設する銅箔面に仮接着し、特許文献1に記載されているようにロール研磨等の機械研磨・CMP等の化学研磨等により、導電性突起の頂部が層間絶縁樹脂から露出するような回路基材を形成した際に以下のような問題が生じる。   These interlayer insulating resins are temporarily bonded to the copper foil surface on which the conductive protrusions stand, and the conductive protrusions are formed by mechanical polishing such as roll polishing or chemical polishing such as CMP as described in Patent Document 1. The following problems arise when a circuit substrate is formed such that the top is exposed from the interlayer insulating resin.

熱可塑性樹脂および熱硬化性樹脂の何れを用いた場合でも、上述の仮接着の際の接着強度が弱く、次工程へのハンドリング等で導電性突起から層間絶縁樹脂が浮いたり、剥がれたりする場合があり、歩留まりに影響したり、修復可能ならばリペア等を行うために生産性を悪化させることがあった。また、工程間の検査等も困難になる。   Regardless of whether a thermoplastic resin or thermosetting resin is used, the adhesive strength at the time of temporary bonding described above is weak, and the interlayer insulating resin may float or peel off from the conductive protrusion due to handling to the next process, etc. In some cases, the yield may be affected, and if the repair is possible, the repair may be performed to deteriorate the productivity. In addition, inspection between processes becomes difficult.

そこで、仮接着力を上げようとすると、熱可塑樹脂の場合には本接着力を発現する温度、例えば熱可塑ポリイミドで約300℃、液晶ポリマーで約250℃と非常に高いプロセス温度が必要になり、生産性が損なわれる。また、接着性を発現する温度が低い場合には、基板としての耐熱性が乏しく、半田耐熱や部品実装時のリフロー等の200℃以上の高温雰囲気に晒される場合に問題が生じる。熱硬化樹脂の場合は、熱可塑樹脂に比べると低い温度で仮接着力を上げることは可能であるが、仮接着力を上げれば上げるほど、本接着力が低下してしまうため、種々の熱硬化樹脂で十分な仮接着力を得ることは困難であった。   Therefore, when trying to increase the temporary adhesive force, in the case of a thermoplastic resin, a temperature at which the actual adhesive force is exhibited, for example, a very high process temperature of about 300 ° C. for a thermoplastic polyimide and about 250 ° C. for a liquid crystal polymer is required. Thus, productivity is impaired. Further, when the temperature at which adhesiveness is manifested is low, the heat resistance as a substrate is poor, and problems arise when exposed to a high temperature atmosphere of 200 ° C. or higher such as solder heat resistance or reflow during component mounting. In the case of a thermosetting resin, it is possible to increase the temporary adhesive force at a lower temperature than the thermoplastic resin, but the higher the temporary adhesive force, the lower the actual adhesive force. It was difficult to obtain a sufficient temporary adhesive force with a cured resin.

図3及び図4は、特許文献1、2に記載の従来工法による、導電性突起を用いた接続による両面可撓性回路基板の製造工程図である。両面可撓性回路基板の製造の際に、図3(1)に示すように、特許文献1および2に記載されている銅箔21(例えば厚さ100μm)/ニッケル箔22(例えば厚さ2μm)/銅箔23(例えば厚さ18μm)の3層構造を有する金属基材24を用意する。   3 and 4 are manufacturing process diagrams of a double-sided flexible circuit board by connection using conductive protrusions according to the conventional methods described in Patent Documents 1 and 2. FIG. When manufacturing the double-sided flexible circuit board, as shown in FIG. 3 (1), the copper foil 21 (for example, 100 μm in thickness) / nickel foil 22 (for example, 2 μm in thickness) described in Patent Documents 1 and 2 ) / A metal substrate 24 having a three-layer structure of copper foil 23 (for example, 18 μm thick) is prepared.

次に図3 (2)に示すように、導電性突起25を、銅箔23上に、エッチング手法で形成する。このときのエッチング液としては特許文献1および2に記載の選択性を有するエッチング液を用いる。   Next, as shown in FIG. 3B, conductive protrusions 25 are formed on the copper foil 23 by an etching method. As the etching solution at this time, the etching solution having selectivity described in Patent Documents 1 and 2 is used.

次に図3 (3)に示すように、両面に熱可塑性ポリイミドを有するポリイミドフィルム26およびこの後の導電性突起頂部を露出させる工程の際、導電性突起を保護する保護フィルム27を導電性突起が立設された面にプレス、ラミネーター等で貼り付ける。   Next, as shown in FIG. 3 (3), in the process of exposing the polyimide film 26 having thermoplastic polyimide on both surfaces and the subsequent conductive protrusion tops, a protective film 27 for protecting the conductive protrusion is provided with the conductive protrusion. Affixed to the surface with a press or laminator.

次に図3(4)に示すように、導電性突起の頂部28をポリイミドフィルム26から露出させるために、ロール研磨等の機械研磨・CMP等の化学研磨等を行う。ポリイミドフィルムの種類によっては導電性突起25がポリイミドフィルムを貫通することが特許文献4に記載されているが、このようなポリイミドフィルムを用いたとしても、エッチングにより形成された頂部の平坦な導電性突起25においては、その頂部に必ずポリイミドフィルムが残るため、上述したような導電性突起頂部を露出させる工程が必要である。このときのポリイミドフィルム26から導電性突起の頂部28までの所謂飛び出し量は上述のようなロール研磨等の機械研磨・CMP等の化学研磨等を行った際には保護フィルム27の厚さにほぼ等しくなる。   Next, as shown in FIG. 3 (4), in order to expose the top portion 28 of the conductive protrusion from the polyimide film 26, mechanical polishing such as roll polishing or chemical polishing such as CMP is performed. Although it is described in Patent Document 4 that the conductive protrusion 25 penetrates the polyimide film depending on the type of the polyimide film, even if such a polyimide film is used, the flat conductivity at the top formed by etching is described. Since the polyimide film always remains on the top of the protrusion 25, a step of exposing the top of the conductive protrusion as described above is necessary. The so-called protrusion amount from the polyimide film 26 to the top 28 of the conductive protrusion at this time is substantially equal to the thickness of the protective film 27 when mechanical polishing such as roll polishing or chemical polishing such as CMP is performed as described above. Will be equal.

次いで、図3(5)に示すように、研磨された保護フィルム29を剥がす。ここまでの工程で、導電性突起25がポリイミドフィルム26を貫通した回路基材30を得る。   Next, as shown in FIG. 3 (5), the polished protective film 29 is peeled off. The circuit substrate 30 in which the conductive protrusion 25 penetrates the polyimide film 26 is obtained through the steps so far.

ただし、図4(1)に示すように、ポリイミドフィルム26の仮接着力があまり強くない場合などにおいては、ポリイミドフィルム26の部分的な剥がれや浮き等が生じ、この後の工程への選別を行う検査が困難になったり、この剥がれや浮きが歩留まりを低減させることもある。   However, as shown in FIG. 4 (1), in the case where the temporary adhesion force of the polyimide film 26 is not so strong, the polyimide film 26 partially peels off or floats, and the subsequent process is selected. The inspection to be performed may be difficult, and this peeling or lifting may reduce the yield.

次いで、図4(2)に示すように、銅箔31に、導電性突起25がポリイミドフィルム26を貫通した回路基材30を積層する。   Next, as shown in FIG. 4 (2), the circuit base material 30 in which the conductive protrusions 25 penetrate the polyimide film 26 is laminated on the copper foil 31.

この後、図4(3)に示すように、積層した基材の銅箔に回路パターン32を形成する。さらに定法により、カバーフィルムおよびソルダーレジスト層の形成や無電解ニッケル、金メッキ等を行い、両面可撓性回路基板33を得る。
特開2002−141629号公報 特開2003−129259号公報 特開平7−245479号公報 特許第3348004号公報
Thereafter, as shown in FIG. 4 (3), a circuit pattern 32 is formed on the laminated copper foil of the base material. Further, the cover film and the solder resist layer are formed, electroless nickel, gold plating and the like are performed by a conventional method to obtain the double-sided flexible circuit board 33.
JP 2002-141629 A JP 2003-129259 A JP-A-7-245479 Japanese Patent No. 3348004

本発明では、導電性突起を用いた接続による回路基板を製造する際に、層間絶縁樹脂として用いる熱可塑性樹脂および熱硬化性樹脂が仮接着条件によらず導電性突起から剥離することのない回路基板の製造方法を提供することを課題とする。   In the present invention, when manufacturing a circuit board by connection using conductive protrusions, a circuit in which the thermoplastic resin and thermosetting resin used as an interlayer insulating resin do not peel from the conductive protrusions regardless of temporary bonding conditions. It is an object to provide a method for manufacturing a substrate.

上記目的達成のため、本願では、次の発明を提供する。   In order to achieve the above object, the present application provides the following invention.

本発明によれば、少なくとも一面に導電性突起が立設された金属箔と、この金属箔の前記一面に前記導電性突起が貫通した状態で圧着される絶縁樹脂層とを有する回路基材と他の回路基材または金属箔とを積層する回路基板の製造方法において、前記絶縁樹脂層を前記導電性突起が立設された金属箔に圧着された後、前記導電性突起の頂部を加圧し、前記導電性突起が前記絶縁樹脂層を貫通した孔よりも前記導電性突起の頂部の径を大きく変形させた後、他の回路部材または金属箔と積層され、前記導電性突起により回路層間の接続を行う。   According to the present invention, a circuit substrate having a metal foil having conductive protrusions standing on at least one surface, and an insulating resin layer that is pressure-bonded in a state where the conductive protrusions penetrate the one surface of the metal foil; In a method of manufacturing a circuit board in which another circuit substrate or a metal foil is laminated, after the insulating resin layer is pressure-bonded to the metal foil on which the conductive protrusions are erected, the top portion of the conductive protrusions is pressurized. The conductive protrusion is deformed to have a larger diameter at the top of the conductive protrusion than the hole penetrating the insulating resin layer, and is then laminated with another circuit member or a metal foil, and the conductive protrusion is used between the circuit layers. Connect.

これらの特徴により、本発明は次のような効果を奏する。   Due to these features, the present invention has the following effects.

本発明によれば、少なくとも一面に導電性突起が立設された金属箔と、この金属箔の前記一面に前記導電性突起が貫通した状態で圧着される絶縁樹脂層とを有する回路基材と他の回路基材または金属箔とを積層する回路基板の製造方法において、前記絶縁樹脂層を前記導電性突起が立設された金属箔に圧着された後、前記導電性突起の頂部を加圧し、前記導電性突起が前記絶縁樹脂層を貫通した孔よりも前記導電性突起の頂部の径を大きく変形させることから、層間絶縁樹脂の種類や仮接着条件によらず物理的に導電性突起の頂部が層間絶縁樹脂の剥離を防止することができる。これによって、次工程へのハンドリング等で導電性突起から層間絶縁樹脂が浮いたり、剥がれたりすることなく、生産性が向上し、工程間の検査等も容易になる。   According to the present invention, a circuit substrate having a metal foil having conductive protrusions standing on at least one surface, and an insulating resin layer that is pressure-bonded in a state where the conductive protrusions penetrate the one surface of the metal foil; In a method of manufacturing a circuit board in which another circuit substrate or a metal foil is laminated, after the insulating resin layer is pressure-bonded to the metal foil on which the conductive protrusions are erected, the top portion of the conductive protrusions is pressurized. Since the conductive protrusion deforms the diameter of the top portion of the conductive protrusion larger than the hole penetrating the insulating resin layer, the conductive protrusion is physically formed regardless of the type of interlayer insulating resin and the temporary bonding condition. The top portion can prevent peeling of the interlayer insulating resin. This improves the productivity and facilitates inspection between processes without the interlayer insulating resin floating or peeling off from the conductive protrusion during handling to the next process.

この結果、本発明によれば、導電性突起を用いた接続による回路基板を製造する際に、層間絶縁樹脂として用いる熱可塑性樹脂および熱硬化性樹脂が仮接着条件によらず導電性突起から剥離することのない回路基板の製造方法およびそれに適した回路基材を安価かつ安定的に提供できる。   As a result, according to the present invention, when manufacturing a circuit board by connection using conductive protrusions, the thermoplastic resin and thermosetting resin used as the interlayer insulating resin are peeled off from the conductive protrusions regardless of the temporary bonding conditions. A circuit board manufacturing method that does not occur and a circuit base material suitable therefor can be provided inexpensively and stably.

以下、図示の実施例を参照しながら本発明をさらに説明する。   Hereinafter, the present invention will be further described with reference to the illustrated embodiments.

図1及び図2は、本発明の回路基板の製造工程図であって、先ず、図1(1)に示す様に、両面可撓性回路基板の製造の際に、特許文献2に記載されている銅箔1(例えば厚さ100μm)/ニッケル箔2(例えば厚さ2μm)/銅箔3(例えば厚さ18μm)の3層構造を有する金属基材4を用意する。   FIG. 1 and FIG. 2 are manufacturing process diagrams of a circuit board according to the present invention. First, as shown in FIG. 1 (1), it is described in Patent Document 2 when a double-sided flexible circuit board is manufactured. A metal substrate 4 having a three-layer structure of copper foil 1 (for example, thickness 100 μm) / nickel foil 2 (for example, thickness 2 μm) / copper foil 3 (for example, thickness 18 μm) is prepared.

次に図 1(2)に示すように、導電性突起5を、銅箔3上に、エッチング手法で形成する。このときのエッチング液としては特許文献3に記載の選択性を有するエッチング液を用いる。   Next, as shown in FIG. 1 (2), conductive protrusions 5 are formed on the copper foil 3 by an etching technique. As an etchant at this time, an etchant having selectivity described in Patent Document 3 is used.

次に図1(3)に示すように、両面に熱可塑性ポリイミドを有するポリイミドフィルム6およびこの後の導電性突起頂部を露出させる工程の際、導電性突起を保護する第一の保護フィルム7を導電性突起が立設された面にプレス、ラミネーター等で貼り付ける。   Next, as shown in FIG. 1 (3), a polyimide film 6 having thermoplastic polyimide on both sides and a first protective film 7 for protecting the conductive protrusions in the subsequent step of exposing the conductive protrusion tops are provided. Affixed to the surface where the conductive protrusions are erected with a press, laminator or the like.

次に図1(4)に示すように、導電性突起の頂部8をポリイミドフィルム6から露出させるために、ロール研磨等の機械研磨・CMP等の化学研磨等を行う。ポリイミドフィルムの種類によっては導電性突起5がポリイミドフィルムを貫通することが特許文献4に記載されているが、このようなポリイミドフィルムを用いたとしても、エッチングにより形成された頂部の平坦な導電性突起5においては、その頂部に必ずポリイミドフィルムが残るため、上述したような導電性突起頂部を露出させる工程が必要である。このときのポリイミドフィルム6から導電性突起の頂部8までの所謂飛び出し量は上述のようなロール研磨等の機械研磨・CMP等の化学研磨等を行った際には第一の保護フィルム7の厚さにほぼ等しくなる。   Next, as shown in FIG. 1 (4), in order to expose the top 8 of the conductive protrusion from the polyimide film 6, mechanical polishing such as roll polishing or chemical polishing such as CMP is performed. Although it is described in Patent Document 4 that the conductive protrusion 5 penetrates the polyimide film depending on the kind of the polyimide film, even if such a polyimide film is used, the flat conductivity at the top formed by etching is described. Since the polyimide film always remains on the top of the protrusion 5, a step of exposing the top of the conductive protrusion as described above is necessary. The so-called pop-out amount from the polyimide film 6 to the top 8 of the conductive protrusion at this time is the thickness of the first protective film 7 when mechanical polishing such as roll polishing or chemical polishing such as CMP is performed as described above. Almost equal to

次いで、図1(5)に示すように、研磨された第一の保護フィルム9を剥がす。ここまでの工程で、導電性突起5がポリイミドフィルム6を貫通した回路基材10を得る。   Next, as shown in FIG. 1 (5), the polished first protective film 9 is peeled off. The circuit substrate 10 in which the conductive protrusions 5 penetrate the polyimide film 6 is obtained through the steps so far.

ただし、図2(1)に示すように、回路基材10に対し、第二の保護フィルム11をラミネート法等で形成する。この第二の保護フィルム11の厚さは、前述した回路基材10の導電性突起の飛び出し量の半分程度の厚さから2倍程度の厚さまでが好ましい。第二の保護フィルム11の材質はポリイミドフィルムやペットフィルム等の合成樹脂、銅箔やアルミ箔等の金属箔、クラフト紙等の紙類等が好ましく、これらを単独、あるいは組み合わせて用いる。ここでは12.5μm厚のポリイミドフィルムを用いた。   However, as shown in FIG. 2A, the second protective film 11 is formed on the circuit substrate 10 by a laminating method or the like. The thickness of the second protective film 11 is preferably from about half the thickness of the protrusion of the conductive protrusion of the circuit substrate 10 to about twice the thickness. The material of the second protective film 11 is preferably a synthetic resin such as a polyimide film or a pet film, a metal foil such as a copper foil or an aluminum foil, or paper such as kraft paper, and these are used alone or in combination. Here, a polyimide film having a thickness of 12.5 μm was used.

次いで、図2(2)に示すように、第二の保護フィルム11の上からステンレス板等を介し平板プレス等で加圧し、導電性突起の頂部の径を絶縁樹脂層を貫通した孔よりも大きく変形させる。この時、第二の保護フィルム11の厚さが回路基材10の導電性突起の飛び出し量に比べ、厚すぎる場合には、導電性突起の変形がほとんど起きず、導電性突起の頂部の径を絶縁樹脂層を貫通した孔よりも大きく変形しない。また、第二の保護フィルム11の厚さが回路基材10の導電性突起の飛び出し量に比べ、薄すぎる場合には、導電性突起が潰れすぎてしまい、この後に銅箔や回路基材に積層した際の接続信頼性を損なう恐れがある。   Next, as shown in FIG. 2 (2), pressure is applied from above the second protective film 11 with a flat plate press or the like through a stainless steel plate or the like, so that the diameter of the top of the conductive protrusion is larger than the hole penetrating the insulating resin layer. Deform it greatly. At this time, when the thickness of the second protective film 11 is too thick compared to the protruding amount of the conductive protrusions of the circuit substrate 10, the deformation of the conductive protrusions hardly occurs, and the diameter of the top of the conductive protrusions Is not deformed to a greater extent than a hole penetrating the insulating resin layer. Moreover, when the thickness of the second protective film 11 is too thin compared to the protruding amount of the conductive protrusions of the circuit substrate 10, the conductive protrusions are crushed too much. There is a possibility that the connection reliability when laminated is impaired.

加圧時の温度としては常温から50℃付近が好ましく、この温度が高いと、導電性突起の変形は起き易いものの、第二の保護フィルム11とポリイミドフィルム6等の層間絶縁樹脂が接着してしまう恐れがある。ここでは常温で加圧した。また、第二の保護フィルム11を用いずに、第一の保護フィルム9をそのまま用いると、導電性突起の頂部がリベット状に変形し、第一の保護フィルムを剥離する際に、リベット状に変形した導電性突起の頂部がクラウン状捲れるため、好ましくない。第二の保護フィルム11を用いずに、第一の保護フィルム9を剥離した状態で加圧しても導電性突起の頂部は変形するが、その変形量の制御は困難である。   The temperature at the time of pressurization is preferably from room temperature to around 50 ° C. If this temperature is high, the conductive projections are likely to be deformed, but the second protective film 11 and the interlayer insulating resin such as the polyimide film 6 are bonded to each other. There is a risk. Here, pressurization was performed at room temperature. Further, when the first protective film 9 is used as it is without using the second protective film 11, the top of the conductive protrusion is deformed into a rivet shape, and when the first protective film is peeled off, the rivet shape is formed. Since the top part of the deformed conductive protrusion is crowned, it is not preferable. Even if it presses in the state which peeled the 1st protective film 9 without using the 2nd protective film 11, although the top part of an electroconductive protrusion deform | transforms, control of the deformation amount is difficult.

また、導電性突起を用いた接続は特許文献1、2に記載されているようなエッチング手法による導電性突起の形成法、特許文献3に記載されているような導電ペーストを印刷する手法による導電性突起の形成法とも層間絶縁樹脂から、導電性突起の頂部を露出させる際にロール研磨等の機械研磨手法・CMP等の化学研磨手法等を用いるため、導電性突起の頂部に傷が付き、後の検査工程での判断が困難になる。単なる傷であれば良品とすべきであるが、異物が付着していたり、研磨不良であれば、次工程へ流動できず、クリーニングの追加やリペア等を行わなければならないが、傷のついた導電性突起が多いとこれらの判断も膨大な負荷となり、生産性を損なうばかりか、不良品の流出にも繋がりかねない。   In addition, the connection using the conductive protrusion is conducted by the method of forming the conductive protrusion as described in Patent Documents 1 and 2, and the method of printing the conductive paste as described in Patent Document 3. In order to expose the top of the conductive protrusion from the interlayer insulating resin in the formation method of the conductive protrusion, since the mechanical polishing method such as roll polishing and the chemical polishing method such as CMP are used, the top of the conductive protrusion is scratched. Judgment in later inspection process becomes difficult. If it is a mere scratch, it should be a good product, but if foreign matter is attached or if it is poorly polished, it cannot flow to the next process and must be cleaned or repaired. If there are many conductive protrusions, these judgments also become a huge load, which not only impairs productivity but also leads to the outflow of defective products.

そこで、これまでは導電性突起の傷があまり深くならないように、研磨材の番手を上げて、傷を消したり、初めから高い番手の研磨材を使用したりしている。しかしながら、番手の高い研磨材は高価であるうえ、目詰まりが起こり易いため生産性が悪化するという欠点がある。これに対し、上述のように第二の保護フィルム11の上からステンレス板等を介し平板プレス等で加圧し、導電性突起の頂部の径を絶縁樹脂層を貫通した孔よりも大きく変形させることで、高価な番手の高い研磨材を用いることなく、研磨工程で導電性突起の頂部についた傷を平滑にするので、後の検査工程での判断が容易で、低コストで生産性を高め、不良の流出を低減できる。   So far, in order to prevent the conductive protrusions from becoming too deeply scratched, the count of the abrasive is increased to eliminate the scratches, or an abrasive with a higher count is used from the beginning. However, high count abrasives are expensive and have the disadvantage that productivity is deteriorated because clogging is likely to occur. On the other hand, as described above, pressure is applied from above the second protective film 11 with a flat plate press or the like through a stainless steel plate or the like, and the diameter of the top portion of the conductive protrusion is deformed larger than the hole penetrating the insulating resin layer. In order to smooth the scratches on the top of the conductive protrusions in the polishing process without using expensive high count abrasives, it is easy to make a decision in the subsequent inspection process, increasing productivity at a low cost, Defect outflow can be reduced.

また、図2(3)に示すように、図2(1)での導電性突起の飛び出し量と第二の保護フィルムの厚さおよび平板プレス等で加圧する際の圧力を制御することで所謂リベット状の形状に変形させることも可能である。   Further, as shown in FIG. 2 (3), the amount of protrusion of the conductive protrusions in FIG. 2 (1), the thickness of the second protective film, and the pressure when pressing with a flat plate press or the like are controlled. It is also possible to deform it into a rivet shape.

次いで、図2(4)に示すように、第二の保護フィルム11を剥離し、導電性突起の頂部がリベット状に変形した回路基材13を得る。このように導電性突起の頂部の形状が変形することで、ポリイミドフィルム6の仮接着力があまり強くない場合などにおいても、ポリイミドフィルム6の部分的な剥がれや浮き等が生じることなく、この後の工程への選別を行う検査や歩留まりを低減させるポリイミドフィルム6の剥がれや浮きが発生することはない。   Next, as shown in FIG. 2 (4), the second protective film 11 is peeled off to obtain a circuit substrate 13 in which the tops of the conductive protrusions are deformed into rivets. Since the shape of the top portion of the conductive protrusion is deformed in this way, even when the temporary adhesion force of the polyimide film 6 is not so strong, the polyimide film 6 is not partially peeled off or floated. There is no possibility that the polyimide film 6 is peeled off or lifted to reduce the inspection and the yield for selecting the process.

次いで、図2(5)に示すように、銅箔14に回路基材13を積層する。尚、図には示さないが、回路基材13を内層回路基板等にビルドアップする際には、導電性突起の飛び出し量が少ないため、特許文献4に記載されている導電性突起が立設する回路基材を内層回路基板等にビルドアップする際の課題である「内層回路基板へ与えるダメージ」が低減できるという効果もある。   Next, as shown in FIG. 2 (5), the circuit substrate 13 is laminated on the copper foil 14. Although not shown in the figure, when the circuit base 13 is built up on an inner layer circuit board or the like, the amount of protrusion of the conductive protrusion is small, so that the conductive protrusion described in Patent Document 4 is erected. There is also an effect that “damage to the inner layer circuit board”, which is a problem when building up the circuit base material to be built on the inner layer circuit board or the like, can be reduced.

この後、図2(6)に示すように、積層した基材の銅箔に回路パターン15を形成する。さらに定法により、カバーフィルムおよびソルダーレジスト層の形成や無電解ニッケル、金メッキ等を行い、両面可撓性回路基板16を得る。   Thereafter, as shown in FIG. 2 (6), a circuit pattern 15 is formed on the laminated copper foil of the base material. Further, the cover film and the solder resist layer are formed, electroless nickel, gold plating and the like are performed by a conventional method to obtain the double-sided flexible circuit board 16.

本発明の一実施例における両面可撓性回路基板の製造工程図。The manufacturing process figure of the double-sided flexible circuit board in one Example of this invention. 図1に続く製造工程図。The manufacturing process figure following FIG. 従来工法による両面可撓性回路基板の製造工程図。The manufacturing process figure of the double-sided flexible circuit board by a conventional construction method. 図3に続く製造工程図。Manufacturing process figure following FIG.

符号の説明Explanation of symbols

1 銅箔
2 ニッケル箔
3 銅箔
4 金属基材
5 導電性突起
6 ポリイミドフィルム
7 第一の保護フィルム
8 導電性突起の頂部
9 研磨された第一の保護フィルム
10 回路基材
11 第二の保護フィルム
12 絶縁樹脂層を貫通した孔よりも大きく変形した導電性突起
13 絶縁樹脂層を貫通した孔よりも大きく変形した導電性突起を有する回路基材
14 銅箔
15 回路パターン
16 本発明による両面可撓性回路基板
DESCRIPTION OF SYMBOLS 1 Copper foil 2 Nickel foil 3 Copper foil 4 Metal base material 5 Conductive protrusion 6 Polyimide film 7 First protective film 8 Top part of conductive protrusion 9 Polished first protective film 10 Circuit base material 11 Second protection Film 12 Conductive protrusion 13 deformed larger than hole penetrating insulating resin layer Circuit substrate 14 having conductive protrusion deformed larger than hole penetrating insulating resin layer Copper foil 15 Circuit pattern 16 Flexible circuit board

Claims (1)

少なくとも一面に導電性突起が立設された金属箔と、この金属箔の前記一面に前記導電性突起が貫通した状態で圧着される絶縁樹脂層とを有する回路基材と他の回路基材または金属箔とを積層する回路基板の製造方法において、前記絶縁樹脂層を前記導電性突起が立設された金属箔に圧着された後、前記導電性突起の頂部を加圧し、前記導電性突起が前記絶縁樹脂層を貫通した孔よりも前記導電性突起の頂部の径を大きく変形させた後、他の回路部材または金属箔と積層され、前記導電性突起により回路層間の接続を行うことを特徴とする回路基板の製造方法。   A circuit substrate having a metal foil with conductive protrusions standing on at least one surface, and an insulating resin layer that is pressure-bonded with the conductive protrusions penetrating on the one surface of the metal foil, and another circuit substrate or In the method of manufacturing a circuit board in which a metal foil is laminated, after the insulating resin layer is pressure-bonded to the metal foil on which the conductive protrusion is erected, the top of the conductive protrusion is pressed, and the conductive protrusion is The diameter of the top portion of the conductive protrusion is deformed larger than the hole penetrating the insulating resin layer, and then laminated with another circuit member or a metal foil, and the circuit layer is connected by the conductive protrusion. A method for manufacturing a circuit board.
JP2005241205A 2005-08-23 2005-08-23 Circuit board manufacturing method Active JP4772424B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158751A (en) * 2007-12-27 2009-07-16 Sanyo Electric Co Ltd Substrate for mounting element and method of manufacturing the same, semiconductor module and method of manufacturing the same and portable device
US8024856B2 (en) * 2007-09-28 2011-09-27 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board
US8438724B2 (en) 2007-12-27 2013-05-14 Sanyo Electric Co., Ltd. Method for producing substrate for mounting device and method for producing a semiconductor module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350258A (en) * 1993-04-16 1994-12-22 Toshiba Corp Production of printed wiring board
JP2001203430A (en) * 2000-01-18 2001-07-27 Ibiden Co Ltd Interlayer connection structure and its manufacturing method
JP2004335926A (en) * 2003-05-12 2004-11-25 North:Kk Wiring circuit board and its producing process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350258A (en) * 1993-04-16 1994-12-22 Toshiba Corp Production of printed wiring board
JP2001203430A (en) * 2000-01-18 2001-07-27 Ibiden Co Ltd Interlayer connection structure and its manufacturing method
JP2004335926A (en) * 2003-05-12 2004-11-25 North:Kk Wiring circuit board and its producing process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8024856B2 (en) * 2007-09-28 2011-09-27 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board
JP2009158751A (en) * 2007-12-27 2009-07-16 Sanyo Electric Co Ltd Substrate for mounting element and method of manufacturing the same, semiconductor module and method of manufacturing the same and portable device
US8438724B2 (en) 2007-12-27 2013-05-14 Sanyo Electric Co., Ltd. Method for producing substrate for mounting device and method for producing a semiconductor module

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