JP2007058256A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To call out a common processing program from each bank without increasing a memory space, in a quick switching system when executing a user program, while considering the situation linked to an increase of the memory space because the program used commonly such as a subroutine is required to be arranged in a memory space other than the bank, although a bank switching system is provided as a means allowing quick rewriting when executing the user program. <P>SOLUTION: A means for logical-summing up an output from a bank register and a superordinate bit of an address for a command fetch is provided to allow an access form other bank without bank-switching the one bank of a memory with bank constitution. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an address generation method and a program execution device that are changed during high-speed RUN of a programmable controller.

  In a device that executes a user-created program, when a program is being executed, another program is transferred from the peripheral device, and when the program to be executed is switched during operation, the old program execution state is changed to the new program execution state. As a technique to reduce the program halt state during the transition, there is a system that has a memory for storing programs in two or more banks, and a new program can be transferred to the other bank while one bank is running Generally used. However, it is necessary to store commonly used processing programs such as subroutines in each bank or to provide a separate memory outside the bank area.

  Japanese Patent Laid-Open No. 2000-105724 discloses an address control circuit that controls the address of a memory.

JP 2000-105724 A

  Some user program instructions include basic instructions that can be executed by the processor. However, in the case of high-function instructions, the actual processing program is registered in an area other than the user program in advance. By calling the processing program, the number of steps of the user program is saved and the transfer time is saved.

  When using memory bank switching as a means of switching user programs during operation at high speed, it is necessary to store processing programs for high-function instructions in each bank, which increases memory capacity and decreases usage efficiency. It was connected.

  In order to make one bank of a memory having a bank configuration accessible from another bank without switching the bank, means for logically summing the output of the bank register and the upper bits of the instruction fetch address is provided.

  It is possible to jump to a processing program stored in another bank without changing the value of the bank register for switching from one bank to another, which speeds up instruction execution processing and improves memory usage efficiency. I can plan.

  The best mode for carrying out the present invention will be described.

  Embodiments of a programmable controller according to the present invention will be described below with reference to the drawings.

  Embodiments of the present invention are shown in FIGS.

  FIG. 1 is a block diagram of a CPU module of the programmable controller of this embodiment.

  In FIG. 1, 1 is a CPU module, 2 is a peripheral device, 3 is a peripheral device interface, 4 is an MPU that performs arithmetic processing, 5 is a data memory, 6 is an address generator, and 7 is a user program memory.

  In FIG. 1, the MPU 4 of the CPU module 1 takes in the user program transferred from the peripheral device 2 via the peripheral device interface 3. Then, the data is written into the user program memory 7 from the MPU 4 via the address generator 6. When the MPU 4 of the CPU module 1 is RUN by the user, the program stored in the user program memory 7 is sequentially executed, and the calculation result is stored in the data memory 5.

  FIG. 2 shows a specific configuration of the address generation unit 6 of the CPU module 1 of FIG. In FIG. 2, 61 is a bank register, 62 is an OR circuit, and 63 is a selector.

  The address generation unit 6 generates addresses at the time of write access and read access from the MPU 4. At the time of reading, the output of the bank register 61 for setting the bank (here, 2 bits) and the upper bits (A9 and A8 in FIG. 2) of the address (A9-A0 and 10 bits) output from the MPU 4 The upper 2 bits are input to the OR circuit 62 and output as an upper address to the user program memory 7. As the lower address, the MPU 4 address is output as it is. Here, the address from the MPU 4 input to the OR circuit is uniquely determined depending on how many bank spaces are divided. The same applies to the number of bits of the bank register 61.

  Here, FIG. 3 shows an address map of the user program memory viewed from the MPU 4 when the bank space is divided into four. A program transferred from the peripheral device 2 is created by an address map in the logical space, thereby enabling programming without being conscious of the bank to be stored.

  At the time of writing, the bank register is invalid, and banks 0 to 3 can be accessed linearly from the MPU.

A procedure for performing a change during RUN will be described.
First, it is assumed that a user program is stored in the bank 0 in advance, and the MPU 4 is executing it. At this time, when a new user program is transferred from the peripheral device 2, the MPU 4 stores the storage destination in a bank other than the bank 0. Here, the data is stored in bank 1. Thereafter, by setting the value of the bank register 61 to “01 (binary number)”, the program stored in the bank 1 can be read from the MPU 4 thereafter.

  The user program needs to operate regardless of which bank it is stored in, and is created so as to operate in the logical address space shown in FIG. However, a jump instruction to the bank 3 in which an actual processing program is stored, such as a high function instruction, can be jumped at an absolute address indicated in the physical address space. This is the logical sum of the value set in the bank register 61 and the upper 2 bits of the output address from the MPU 4, so when the MPU 4 outputs the address for the bank 3, the value in the bank register 61 is set. This is because it is “11 (binary number)”.

  As described above, when this embodiment is used, even when the program executed by the bank register is changed at high speed, jumps between banks can be performed regardless of the value of the bank register. There is no need to store the data in each bank, and the use efficiency of the memory can be improved.

  In a programmable controller that cyclically executes a ladder program created by a user, the program is used when a program switching process is performed at a high speed when the user program is modified or changed during the program execution.

The block diagram of CPU module of this invention is shown. 2 shows an address generation unit of the CPU module of FIG. An address map of a user program when the bank space of the present invention is divided into four is shown.

Explanation of symbols

1 CPU module 2 Peripheral device 3 Peripheral device interface 4 MPU
5 Data memory 6 Address generation unit 7 User program memory 61 Bank register 62 OR circuit 63 Selector

Claims (1)

In a programmable controller having a bank register for setting a bank of a program memory and having a program address update method that allows a memory address to be changed by the value of the bank register.
A programmable controller, comprising: an address generation circuit that logically sums the bank register and a higher-order bit of a program address and uses the result as an actual program address.

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