JP2007049477A - Decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a decoder capable of detecting an error even when an odd number of edge detecting pulses are generated. <P>SOLUTION: The decoder has an edge detector 9 detecting each varying point of the rise and fall of an input encoding signal, and a clock generator 3 generating clock pulses. The decoder further has a counter 5 counting the clock pulses of the clock generator 3, imparting a count output frequency-divided up to the transmission rate of the encoding signal to the encoding signal as sampling pulses, and inputting edge detecting pulses output from the edge detector 2 as clear pulses. The decoder further has a gate circuit 4 opening a gate to the edge detecting pulses applied to the counter 5 from the edge detector 2 at constant timings, in accordance with the encoding rule of the encoding signal on the basis of a count output from the counter 5. Such a decoder has an edge counter circuit 8 inputting the edge detecting pulses and the sampling pulses as an output from the counter 5, and detecting the contravention of the encoding rule. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a decoding apparatus that converts a self-synchronized encoded signal into an NRZ encoded signal.

In general, an NRZ (Non Return Zero) system is usually used as an encoding system when a signal including information is encoded and transmitted. In this NRZ system, the code “0” is transmitted in correspondence with the low level of the voltage and the code “1” is associated with the high level, and the encoding rule is relatively simple. However, since the clock information is not included, it is necessary to synchronize the bit between the transmitting side and the receiving side when transmitting data. For this reason, a separate synchronization line must be provided, which increases costs. On the other hand, a so-called self-synchronous encoding method for transmitting data by including clock information in an encoded signal has been proposed. A decoding apparatus which is proposed as one of the self-synchronous encoding methods and converts a self-synchronized encoded signal into an NRZ encoded signal is as shown in FIG. 3 (see, for example, Permissible Document 1). .
FIG. 3 is a block diagram showing a circuit configuration of a conventional decoding device.
In FIG. 3, 1 is a low-pass filter, 2 is an edge detection circuit, 3 is a clock generator, 4 is a gate circuit, 5 is a counter, 6 is a delay circuit, and 7 is a flip-flop.
The decode circuit counts the edge detection circuit 2 that detects each change point of the falling and rising of the input encoded signal, the clock generator 3 that generates a clock pulse, and the clock pulse of the clock generator 3. The counter 5 that outputs the count output divided to the transmission speed of the encoded signal as a sampling pulse for the encoded signal and inputs the edge detection pulse output from the edge detection circuit 2 as a clear pulse, and the counter 5 And a gate circuit 4 that opens a gate with respect to an edge detection pulse applied from the edge detection circuit 2 to the counter 5 at a constant timing in accordance with the encoding rule of the encoded signal based on the count output of.
FIG. 4 is a timing chart showing the operation of the decoding apparatus of FIG.
Symbols a to f in FIG. 4 indicate waveforms corresponding to the respective points of symbols a to f in the circuit of FIG.
In such a configuration, the decoding device opens the gate signal d only in a timing period (period in which there is an edge) of the edge detection pulse according to the encoding rule, and count output of a counter that uses the signal as a clear pulse, It performs sampling of an encoded signal and error detection. Further, by ignoring the edge when the gate signal is closed, the influence of the signal change due to noise or the like during that period is eliminated.
Japanese Patent No. 2627890 (Specification, page 4, FIG. 1)

The conventional decoding apparatus only determines that the edge is not detected within the period when the gate is opened as the error detection because the least significant bit of the counter is a value of “0”. There is a problem that an error cannot be detected when an edge detection pulse is generated.
The present invention has been made in view of such problems, and an object of the present invention is to provide a decoding device capable of detecting an error even when an odd number of edge detection pulses are generated.

In order to solve the above problems, the present invention is configured as follows.
According to the first aspect of the present invention, an edge detection circuit for detecting each change point of the rising and falling of the input encoded signal, a clock generator for generating a clock pulse, and counting the clock pulses of the clock generator A counter that outputs the count output divided to the transmission speed of the encoded signal as a sampling pulse for the encoded signal, and inputs the edge detection pulse output from the edge detection circuit as a clear pulse, and the count output of this counter And a gate circuit that opens a gate with respect to an edge detection pulse applied to the counter from the edge detection circuit at a constant timing according to the encoding rule of the encoded signal based on the self-synchronous encoding such as Manchester code In the decoding device for converting a signal into an NRZ encoded signal, the clock The clock pulse of the generator is used as a clock, and an edge count circuit for detecting a code rule violation by generating an error detection signal by inputting the edge detection pulse and a sampling pulse as an output of the counter is provided. It is characterized by.
According to a second aspect of the present invention, in the decoding device according to the first aspect, when the edge count circuit detects an edge other than a prescribed number of edges during one cycle of the sampling pulse, the code rule is violated. It is characterized by setting an error detection signal.

According to the first aspect of the present invention, an edge detection circuit for detecting each change point of the rising and falling of the input encoded signal, a clock generator for generating a clock pulse, and a clock pulse of the clock generator A counter that counts and divides the encoded signal to the transmission speed is provided as a sampling pulse for the encoded signal, and an edge detection pulse output from the edge detection circuit is input as a clear pulse, and the counter And a gate circuit that opens a gate with respect to an edge detection pulse applied from the edge detection circuit to the counter at a constant timing according to a coding rule of the coded signal based on a count output of the clock signal. Edge detection using the clock pulse of the instrument as the clock An error detection signal is generated by inputting a sampling pulse that is an output of the counter and the counter, and an edge count circuit is provided to detect a code rule violation. Therefore, even if an odd number of edge detection pulses are detected, a code violation is detected. can do.
According to a second aspect of the invention, the edge count circuit sets an error detection signal as a code rule violation when an edge other than the prescribed number of edges is detected during one period of the sampling pulse. Therefore, the quality of the decoding result can be improved by detecting the signal that should be regarded as a code violation.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a decoding apparatus showing an embodiment of the present invention. Note that the description of the same constituent elements of the present invention as those of the prior art will be omitted, and different points will be described.
In FIG. 1, 8 is an edge count circuit, and 9 is a reception clock.
The components of the present invention are different from the prior art as follows.
That is, instead of the conventional configuration in which the error detection signal is generated by the counter 5, the clock pulse of the clock generator 3 is used as a clock separately from the counter 5, and the edge detection pulse and the output of the counter 5 are An edge count circuit 8 is provided for generating an error detection signal by inputting a sampling pulse to detect a code rule violation.
The edge count circuit 8 sets an error detection signal as a code rule violation when an edge other than the prescribed number of edges is detected during one cycle of the sampling pulse.

Next, the operation will be described.
In FIG. 1, an edge count circuit 8 counts the output of the edge detection circuit 2. At this time, the edge count circuit 8 is reset at the rising edge of the reception clock 9 which is an output of the counter 5 and is a sampling signal for data output. Accordingly, if the code is normal, the edge count value is [1] or [2]. If the count value remains [0], an error detection signal is set because there is no change point from the previous rising edge to that point.
Furthermore, if it is [3] or more, it means that an erroneous edge due to noise has been input. In this case as well, an error detection signal is set.

FIG. 2 is a timing chart showing the operation of the decoding apparatus of FIG.
In FIG. 2, data D1, data D2, and data D3 are correctly decoded as data outputs, but the data D4 is due to noise shown by shading even though the original value is “0”. Decoded as “1”. In the error detection in Patent Document 1 using the waveform c after passing through the gate circuit, it is not determined as an error in this case.

  By setting the number of edges that are judged to be errors by the edge count circuit to be variable, the error detection standard according to the degree of noise addition can be changed, so that the noise tolerance can be made variable according to the quality of the transmission path. It can also be used for such purposes.

The block diagram which showed the circuit structure of the decoding apparatus which shows the Example of this invention Timing chart showing the operation of the decoding device of FIG. The block diagram which showed the circuit structure of the conventional decoding apparatus Timing chart showing the operation of the decoding device of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Low pass filter 2 Edge detection circuit 3 Clock generator 4 Gate circuit 5 Counter 6 Delay circuit 7 Flip-flop 8 Edge count circuit 9 Reception clock

Claims (2)

An edge detection circuit for detecting each change point of the rising and falling of the input encoded signal;
A clock generator for generating clock pulses; and
The clock pulse of this clock generator is counted and the count output divided to the transmission speed of the encoded signal is given as a sampling pulse for the encoded signal, and the edge detection pulse output from the edge detection circuit is cleared. And a counter to enter as
A gate circuit that opens a gate with respect to an edge detection pulse applied to the counter from the edge detection circuit at a constant timing according to the encoding rule of the encoded signal based on the count output of the counter;
And a decoding device that converts a self-synchronized encoded signal such as Manchester code into an NRZ encoded signal,
An edge count circuit that uses a clock pulse of the clock generator as a clock, generates an error detection signal by inputting the edge detection pulse and a sampling pulse that is an output of the counter, and detects a code rule violation. A decoding device characterized by that.   2. The decoding apparatus according to claim 1, wherein the edge count circuit sets an error detection signal as a code rule violation when an edge other than a prescribed number of edges is detected during one cycle of the sampling pulse.

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