JP2007048317A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store a plurality of bit fields in the memory area of one address (one byte) in a RAM. <P>SOLUTION: In the case of a load instruction (BFLD) to transfer data from a memory to a general-purpose register, the logical product of data on the memory and immediate data is calculated, and the data are shifted to the right so that the least significant 1 of the immediate data can be zero, and stored in the general-purpose register. In the case of a storage instruction (BFST) to transfer data from the general-purpose register to the memory, the content of the general-purpose register is shifted to the left until the bit of the least significant 1 of the immediate data, and the immediate data at the bit position of 1 are defined as the shifted data on the general-purpose register, and the other data at the bit position of logical value "0" other than that are combined as data on the memory, and written in the memory. Thus, it is possible to improve a processing speed in comparison with the case that a bit field is used by combining a plurality of instructions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing device referred to as a microcomputer, a data processor, or a microprocessor, and more particularly to a technique that is effective for improving the program efficiency or code efficiency of a central processing unit (CPU). is there.

  A microcomputer integrated with a semiconductor integrated circuit has been attempted to expand an address space, expand an instruction set, and increase speed. Examples of realizing address space expansion and instruction set expansion while maintaining compatibility at the object level include, for example, Patent Document 1 and Patent Document 2. According to this, a 32-bit general-purpose register can be used as a 32-bit register as an address register. The data register can be selected to be used as a 32-bit register, divided and used as a 16-bit register, or further divided into a lower-order 16-bit register and used as an 8-bit register. Further, Patent Document 3 describes a processor in which a register indicating the size of an address space is provided, and the size of a general-purpose register that stores address data is variable depending on the value. In the case of a single-chip type having a built-in ROM as a program memory, the capacity of the built-in ROM is less than that of a memory that can be connected to the outside, so it is desirable to reduce the program capacity.

  In recent years, flash memories and EEPROMs (electrically erasable and erasable ROM) are often used as ROMs for single-chip microcomputers. These electrically erasable and erasable memories have a large storage element and require a high voltage generation circuit for writing and erasing, which increases the physical scale. Capacity reduction is desirable. The same applies to the built-in RAM, and it is desirable that the capacity of data to be used can be reduced.

  On the other hand, it is increasing that a microcomputer program is described in a high-level language such as C language. When written in a high-level language, the program capacity and the volume of data to be used tend to be larger than when written in assembly language.

  Examples of documents describing addressing modes such as register indirect include Patent Document 4 and Patent Document 5. Patent Document 4 describes a data processing apparatus having a register indirect addressing mode with displacement. Patent document 5 describes a data processing apparatus having a register indirect addressing mode with displacement.

JP-A-5-241826 JP-A-6-51981 JP-A-6-103063 JP-A-4-333153 JP 10-49369 A

  The present inventors have studied the reduction of program capacity and the capacity of data to be used from the following viewpoints.

The first viewpoint is the viewpoint of calculating effective addresses such as arrays. There is an addressing mode called register indirect with displacement, in which an effective address is generated by adding a displacement included in an instruction code to an address held in a general-purpose register, and this effective address is read / written. Using this, the data of the number stored in the general-purpose register (R0L) (for example, data indicating the nth) is read with respect to the array of word size data arranged in the area starting from the predetermined address (TOP). In this case, since the array number is used as an address register, the number data is zero-extended to 32 bits (8 bits to 16 bits by the instruction EXTU.W and 16 bits to 32 bits by the EXTU.L). Further, after × 2 (left 1-bit shift by the instruction SHLL) corresponding to the word size data, the instruction MOV. It is necessary to perform memory access by W. For example,
EXTU. W R0
EXTU. L ER0
SHLL. L ER0
MOV. W @ (TOP: 16, ER0), E0
It is described as follows.

  Similarly, it is conceivable to add an index to the address held in the general-purpose register.

  The second aspect relates to repetition of effective address calculation. In the case of array access, the same address may be used several times. At this time, it is inefficient to repeat the same effective address calculation many times.

  A third aspect relates to branch instructions such as program counter relative. This branch instruction is referred to as program counter relative, and has an addressing mode in which an effective address is generated by adding a displacement included in the instruction code to the contents of the program counter, and branching to this effective address. At this time, when there are a plurality of branch destinations, it is necessary to separately describe a branch instruction relative to the program counter for each branch destination.

  A fourth aspect relates to branch instructions such as memory indirection. There are cases where the same address is branched from multiple locations. In this case, it is conceivable to store the branch destination address as a table and shorten the instruction code of the branch instruction itself. This is called memory indirect, and it has 8-bit address information in a 16-bit (2 bytes) instruction code. A branch destination address table is referred to by this address information, and this branch table is read. Based on the read contents There is an addressing mode for branching. On the other hand, a branch instruction having a branch destination address (for example, 24 bits) in the instruction code has a length of 32 bits (4 bytes). Therefore, if the branch table is set to 32 bits, the branch is made to the same address. If there is a branch instruction, it is more efficient to use the memory indirect. However, this method is limited by the number and capacity of the branch tables that can be prepared, and the branch table may be used in common with the exception processing vector.

The fifth viewpoint is an efficient use of RAM. If there is data that is less than 8 bits, such as expressed in 3 bits, the use efficiency of the RAM area increases if a plurality of data can be stored in one address (byte unit). For example, 3-bit, 3-bit, and 2-bit data can be stored in one address from the lower order. These 3 bits, 3 bits, and 2 bits of data are declared in a bit field when a source program is described in C language. For example, in the above example:
struct {
unsigend char cc: 2;
unsigend char bb: 3;
unsigend char aa: 3;
} Abc;
And so on.

When this bit field data bb is manipulated, it is normally taken out to a general purpose register. This example program
MOV. B @abc, R0L
AND. B # 8'b00111000, R0L
SHLR. B # 3, R0L
And so on. In other words, the general purpose register is once read from the memory in units of bytes, the bits other than the desired bit field are cleared to 0, and a 3-bit shift is performed so that the desired bit field becomes lower-ordered. In an instruction set that supports only 1-bit shift, three SHLR instructions are required.

If you want to store in memory after the operation,
MOV. B @abc, R1L
AND. B # 8'b11000111, R1L
SHLL. B # 3, R0L
OR. B R1L, R0L
MOV. B R0L, @abc
Instruction execution is required. That is, once the memory data to be stored is read into the general-purpose register, the desired bit field is cleared to zero. On the other hand, the data to be stored is shifted so as to be in a desired bit field position. The logical sum of the two is taken and the result is stored in the memory.

  Bit fields can save memory (RAM) usage but increase program capacity. If data less than 8 bits is handled in units of bytes (for example, lower-ordered and upper-order is 0), the operation becomes easy and the program capacity does not increase, but the memory (RAM) usage increases. .

  The present invention has been made in view of the above examination contents. An object of the present invention is to make it possible to reduce the program capacity (ROM capacity to be used).

  Another object of the present invention is to make it possible to reduce the data capacity to be used (RAM capacity to be used).

  Still another object of the present invention is to minimize the increase in logical and physical scale and improve the processing speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] [Effective address calculation for arrays, etc.]
The data processing apparatus according to the present invention has an instruction execution means for reading and decoding an instruction and executing the instruction according to the decoding result, and the instruction execution means uses all or part of the storage area for information holding The general-purpose register specified by the first instruction is read according to the access size of the information when the first instruction using a part of the storage area of the general-purpose register is read. The information held in the register is shifted, and the effective result is calculated by adding the shift result to other information.

  Specifically, for example, reference address information described in an instruction, that is, a reference address (given by a displacement in the instruction, for example), and information on an index register assigned to a general-purpose register (for example, what number on the array) The effective address is calculated from the above information), and an addressing mode for accessing the memory (index register indirect addressing mode with displacement) is provided. According to the memory access size, the value of the index register (register holding the value added to the address) is x1 for bytes, x2 for words, and x4 for longwords. To shift. Independently, the size of the index register may be selectable from 32 bits, 16 bits, and 8 bits. For example, if the size of the array is 256 or less, the index register may be 8 bits, and the upper part of the same general-purpose register can be used as another data register. In short, of the data stored in the general-purpose register, only the data specified by the access size is targeted for calculation, and the upper side of the general-purpose register can hold (or maintain) the original information.

The first instruction that employs the index register indirect addressing mode with displacement is, for example, MOV. W E0, @ (d: 16, R0L)
It is a transfer written as For this addressing mode, the CPU has a function of zero-extending a general-purpose register, shifting, adding displacement, etc., and making the result available as an address.

  By including the zero extension and shift in the effective address calculation, it is possible to reduce the number of instructions and the number of execution states. Since the size of the array is smaller than the size of the address space, the upper part of the general-purpose register can be used as another data register, the amount of data that can be placed in the general-purpose register can be increased, and the number of read / write operations with the memory is reduced. As a result, the number of instructions can be further reduced, and the program capacity can be reduced. Conventionally, the processing speed can be improved as compared with the case where an array is accessed by combining a plurality of instructions.

[2] [MOVA instruction for effective address calculation such as array]
As another desirable aspect of the present invention, when the instruction execution means reads a third instruction that uses a part of the storage area of the general-purpose register, the instruction execution means shifts the information according to the access size of the information. Then, a process of storing the effective address calculated by adding the shift result with other information in another general-purpose register is executed. That is, the effective address is calculated and an effective address transfer instruction (MOVA) for storing the effective address in the general-purpose register without accessing the memory is provided. Since the data size is not known at the time of calculating the effective address, a plurality of instructions corresponding to the data size are prepared. For example, the same effective address calculation as described above and the instruction stored in the general-purpose register (ER1) is
MOVA / W @ (d: 16, R0L), ER1
Write like this. In the above description, / W is the data size when accessing the memory using the effective address, that is, in the array.

  Since the same address may be used a plurality of times, if it is stored in a general-purpose register, a displacement is not required after the second time, so that the program capacity can be reduced and the number of execution states can be reduced.

  The calculation function of the CPU is the same as that of the index register indirect addressing mode with displacement, and the general-purpose register is expanded, shifted, added, and the result is stored in the general-purpose register. This instruction is substantially an arithmetic instruction and does not directly access the memory. For this reason, even if the data used as an index is read from the memory, the instruction execution sequence is not so complicated. It can be the same operation as the effective address calculation in the index register indirect addressing mode with displacement, and even if an MOVA instruction for effective address calculation such as an array is added, the logical scale does not increase.

[3] [PC relative branch instruction]
The first instruction that employs an addressing mode such as indirect index register with displacement can also be applied as a PC relative branch instruction. That is, the index register is 8 bits, 16 bits, 32 bits, multiplied by a predetermined constant (× 2 if the instruction is in 16-bit units), and then added to the program counter (PC) to obtain the branch address To support the effective address generation of the program counter index register relative branch. When there are a plurality of branch destinations, after branch conditions are evaluated, by setting a value in the index register according to the evaluation result, one branch instruction itself can be shared.

  As the instruction execution function of the CPU, the function of expanding, shifting, adding, and making the result available as an address can be shared with the above. The other value to be added may be a displacement instead of the PC value.

  For example, by evaluating a case sentence (case) on a C source program and storing an index for calculating a branch destination address in a general-purpose register based on the evaluation result, the program capacity can be reduced.

[4] [Branch instruction in memory indirect addressing mode]
The present invention according to the second aspect has instruction execution means for reading and decoding an instruction and executing the instruction according to the result of the decoding, and the instruction execution means is offset (Hec) into a value (vec) of a predetermined field of the instruction. '80) is combined, and the number of bits is shifted in accordance with the access size of the information, and other information (VBR value) is added to the shifted value to calculate the effective address, and the calculated effective It is possible to read a memory by an address and execute a branch instruction using the read contents as a branch destination address. The shift operation is, for example, x2 or x4 corresponding to the instruction fetch size by a program counter or the like.

  If the offset value is determined so as to exceed the range of the exception processing vector table on the basis of the vector base register, it is possible to branch to the subroutine by referring to the subroutine vector table mapped to the range exceeding the range. If a branch instruction in the memory indirect addressing mode is employed, the program capacity can be reduced even if it is combined with the branch table when a short instruction code is used and there are many branch instructions that branch to the same address. Further, by adding an offset to the data (vec) in the instruction code corresponding to the size of the program counter or the address space, the information such as the vector number field of the instruction code is obtained. It can be used effectively and a large number of branch addresses can be specified. Further, in order to prevent the data (vec) in the instruction code from being shared with the number of the exception processing vector area (exception processing vector table), a predetermined amount is used before the data (vec) in the instruction code when used. Provide an offset (for example, fixed value H'80) and fill the upper side with, for example, the stored value of the vector base register (VBR), thereby excluding the area that can be specified by the data (vec) in the instruction code. It can be prevented from overlapping the processing vector area. By further adding the vector base register, relocation from the boot memory to the program memory (processing to be executed first in order to use a required program on the high-speed memory) can be easily performed.

  Instead of the vector base register, it is possible to adopt a configuration in which a first register such as a subroutine vector table register dedicated to a subroutine call is employed to enable the subroutine call. That is, the instruction execution means includes a vector base register (VBR) that can be used for referring to the exception processing vector table and a first register (TBR) that can be used for reference to the subroutine vector table. The value (disp) of a predetermined field of the instruction is shifted by the number of bits corresponding to the access size of the information, and the address is calculated by adding the value of the first register (TBR) to the shifted value. It is possible to execute a subroutine call instruction that reads the subroutine vector table by address and uses the read contents as a branch destination subroutine address.

  In optimization at the time of link when generating an object program from a source program, the branch instruction that is most frequently used may be replaced with the branch instruction of this instruction.

  As described above, the value of a predetermined field such as disp (displacement) in the instruction code is introduced by introducing the first register pointing to the head address table of the subroutine call separately from the vector base register for exception processing. In addition, a second register such as a subroutine base register is introduced, and an entry address such as 16 bits in the subroutine vector table within a range of 64 KB from the start address specified by the second register. If the branching can be performed, the size of the subroutine vector table can be reduced. In short, the instruction execution means has a vector base register that can be used for referring to the exception processing vector table, and a first register and a second register that can be used for branching to the subroutine. Is shifted by the number of bits according to the access size, the value of the first register is added to the shifted value, the address is calculated, the subroutine vector table is read with the calculated address, and the contents read The subroutine call instruction that adds the values of the two registers to obtain the branch destination subroutine address is made executable.

[5] [Bit field instruction]
In the present invention according to the third aspect, the position of the bit field on the memory is designated by the immediate data (the field in which the bit of the logical value “1” of the immediate data exists is a bit field), Enables data transfer to and from registers (lower justified). In other words, in the case of a load instruction (BFLD) for transferring from the memory to the general-purpose register, the right shift is performed so that the least significant 1 of the immediate data becomes bit 0 by taking the logical product of the data on the memory and the immediate data. After doing so, store it in a general-purpose register. In the case of a store instruction (BFST) for transferring from a general-purpose register to a memory, after shifting the contents of the general-purpose register to the least significant bit of the immediate data to the left, the data at the bit position where the immediate data is 1 is shifted as described above. The data in the general-purpose register is used, and the other data at the bit position of the logical value “0” is combined as data on the memory and written to the memory.

  Thereby, a plurality of bit fields can be stored in the storage area of one address (1 byte) of the RAM, so that the capacity of the built-in RAM can be saved without increasing the program capacity, and the program capacity for performing this processing. This is suitable for a single chip microcomputer. Conventionally, the processing speed can be improved as compared with a case where a bit field is used by combining a plurality of instructions.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, by having a function of executing an instruction corresponding to a process realized by using a plurality of instructions in the past, it is possible to improve usability, reduce the program capacity, and improve the processing speed. By reducing the program capacity, it is possible to reduce the memory capacity of the ROM for storing the program, thereby saving costs.

  FIG. 2 is a block diagram of a single chip microcomputer to which the present invention is applied.

  A single chip microcomputer 1 shown in FIG. 1 includes a CPU 2 that controls the entire system, an interrupt controller (INT) 3, a ROM 4 that is a memory that mainly stores a processing program of the CPU 2, and a work area of the CPU 2. In addition, a RAM 5 which is a memory for temporary storage of data, a timer 6, a serial communication interface (SCI) 7, an A / D converter 8, first to ninth input / output ports (IOP1 to IOP9) 9A to 9I, a clock oscillator ( CPG) 10 functional blocks or modules, which are formed on one semiconductor substrate by a known semiconductor manufacturing technique. The ROM 4 is a flash memory, an EEPROM (electrically erasable / erasable ROM), a mask ROM, or the like.

  The single-chip microcomputer 1 has, as power supply terminals, a ground level (Vss), a power supply voltage level (Vcc), an analog ground level (AVss), an analog power supply voltage level (AVcc), and other dedicated control terminals. , Reset (RES), standby (STBY), mode control (MD0, MD1), and clock input (EXTAL, XTAL) terminals.

  The single chip microcomputer 1 operates in synchronization with a reference clock (system clock) generated based on a crystal oscillator connected to the terminals EXTAL and XTAL of the CPG 10 or an external clock input to the EXTAL terminal. One cycle of this reference clock is called a state.

  The functional blocks of the single chip microcomputer 1 are connected to each other by an internal bus 11. A bus controller (not shown) that controls the bus is incorporated. The internal bus 11 includes, in addition to an address bus and a data bus, a control bus through which a bus command encoding a read signal, a write signal, and a bus size signal is transmitted.

  The functional blocks and modules are read / written by the CPU 2 via the internal bus 11. The data bus width of the internal bus 11 is 32 bits. Reading / writing of the built-in ROM 4 and RAM 5 is made possible in one state.

  The control registers included in the timer 6, the SCI 7, the A / D converter 8, the input / output ports (IOP1 to IOP9) 9A to 9I, and the CPG 11 are collectively referred to as an internal I / O register. Each of the input / output ports 9A to 9I is also used as an address bus, a data bus, a bus control signal, or an input / output terminal of the timer 6, the SCI 7, and the A / D converter 8.

  When a reset signal RES is given to the single chip microcomputer 1, the single chip microcomputer 1 including the CPU 2 is reset. When the reset is released, the CPU 2 reads a start address from a predetermined address, and performs a reset exception process that starts reading an instruction from the start address. Thereafter, the CPU sequentially reads and decodes instructions from the ROM 4 and the like, and processes data and accesses the RAM 5 based on the decoded contents.

  The states of the timer 6, SCI 7, and external signal can be transmitted to the CPU 2 as an interrupt signal 12. The interrupt signal 12 is output from the A / D converter 8, the timer 6, the SCI 7, and the input / output ports 9A to 9I. The interrupt controller 3 inputs the interrupt signal 12, and the CPU 2 based on the designation of a predetermined register or the like. Are given the interrupt request signal intf and the vector VEC corresponding to the accepted interrupt. When an interrupt factor occurs, an interrupt request is generated in the CPU 2, the CPU 2 interrupts the processing being executed, passes through the exception processing state, reads the branch destination address from the address corresponding to the vector VEC, Branches to a predetermined processing routine, performs desired processing, and clears an interrupt factor. A normal return instruction is placed at the end of the predetermined processing routine, and the interrupted process is resumed by executing this instruction.

  FIG. 3 shows a configuration example (programming model) of general-purpose registers and control registers built in the CPU 2.

  The CPU 2 has eight general-purpose registers ER0 to ER7 each having a 32-bit length. The general-purpose registers ER0 to ER7 all have the same function and can be used as an address register and a data register. The usage method will be described later. The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and is used implicitly in exception handling, subroutine branching, and the like. Exception handling includes the interrupt handling.

  The program counter PC is a 32-bit counter and indicates an address of an instruction to be executed next by the CPU 2. Although not particularly limited, since all instructions of the CPU 2 are in units of 2 bytes (words), the least significant bit is invalid, and the least significant bit is regarded as 0 when the instruction is read.

  The condition code register CCR is an 8-bit register and indicates the internal state of the CPU 2. It consists of 8 bits including interrupt mask bit (I) and half carry (H), negative (N), zero (Z), overflow (V) and carry (C) flags.

  The vector base register VBR is a 32-bit register, the lower 12 bits are set to 0, and the upper 20 bits are used as the upper address when reading the exception processing vector table and the extended memory indirect branch destination table (subroutine vector table). Is done. The subroutine vector table register (first register) TBR indicates the location of the subroutine vector table in which the entry address of the subroutine is stored.

  FIG. 4 illustrates a usage form of the general-purpose register. In the case of an address register and a 32-bit register, they are used collectively as general purpose registers ER (ER0 to ER7). As the index registers, general purpose registers ER (ER0 to ER7), general purpose registers R (R0 to R7), and general purpose registers RL (R0L to R7L) are used. Which one is used is specified by the size of the index register in the addressing mode.

  In the case of a 16-bit register, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have equivalent functions, and up to 16 16-bit registers can be used.

  In the case of an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R7H) and general-purpose registers RL (R0L to R7L). These have equivalent functions, and up to 16 8-bit registers can be used. The usage form of the general-purpose register can be selected independently for each register.

  When specifying an address in the memory, use it as an address register with a 32-bit length without shifting, or as an index register with a 32-bit, 16-bit, or 8-bit length, and shift according to the size of the data. None / 1 bit shift / 2 bit shift.

  FIG. 5 illustrates a CPU address space. It has a minimum mode with an address space of 64 kilobytes (k bytes) and a maximum mode with an address space of 4 gigabytes (G bytes).

  In the minimum mode, the entire space can be specified by a 16-bit address. The exception processing vector table and branch table (subroutine vector table) may be 16 bits.

  In the maximum mode, the entire space is specified by a 32-bit address. The vector and branch table may be 32 bits. H'00000000 to H'00007FFF and H'FFFF8000 to H'FFFFFFFF can be specified by a displacement or an absolute address of 16 bits. Although not particularly limited, by placing the internal RAM 5 in this area, a relatively short displacement and an absolute address of 16 bits can be used, so that the program capacity can be reduced.

  6 and 7 illustrate a method for calculating the effective address of the transfer / arithmetic instruction. 8, 9 and 25 illustrate a method for calculating the effective address of a branch instruction.

(1) Register direct [Rn]
In this case, a register (8 bits, 16 bits, or 32 bits) designated in the register field of the instruction code is an operand. As the 8-bit register, R0H to R7H and R0L to R7L can be designated. As the 16-bit register, R0 to R7 and E0 to E7 can be designated. ER0 to ER7 can be specified as the 32-bit register.

(2) Register indirect [@ERn]
This specifies an operand on the memory using the contents of the address register (ERn) specified in the register field of the instruction code as an address. In the advanced mode, in the branch instruction, the lower 24 bits are valid, and the upper 8 bits are all regarded as 0 (H'00).

(3) Register indirect with displacement [@ (d: 2, ERn) / @ (d: 16, ERn) / @ (d: 32, ERn)]
This designates an operand on the memory using the contents of the address register (ERn) specified in the register field of the instruction code plus the 16-bit displacement or 32-bit displacement included in the instruction code as an address. Upon addition, the 16-bit displacement is sign extended. When the data size is bytes, the short form @ (d: 2, ERn) is prepared when the displacement is 1, 2, or 3. Similarly, the shortened form @ (d: 2, ERn) is prepared when the word is 2, 4, and 6 and when the long word is 4, 8, and 12, respectively.

(4) Index register indirect with displacement [@ (d: 16/32, ERn.B / W / L)]
This means that the contents of the specified number of bits (RnL, Rn, ERn) of the address register specified in the register field of the instruction code are zero-extended to 32 bits and multiplied by 1, 2 or 4 (actually And an operand on the memory is designated with the address obtained by adding the multiplication result and the 16-bit displacement or 32-bit displacement included in the instruction code. Depending on the size of the data, the byte size is multiplied by 1, the word size is multiplied by 2, and the long word size is multiplied by 4. Upon addition, the 16-bit displacement is sign extended. In short, when using a part of the general-purpose register for holding information, the information using the part of the general-purpose register is shifted according to the size of the information to be accessed, and the shift result is added to the other information. Performs address calculation.

(5) Pre / post increment / decrement register indirect [@ERn + / @-ERn / @ + ERn / @ ERn-]
(A) Post-increment register indirect [@ ERn +] designates an operand on the memory using the contents of the address register (ERn) designated in the register field of the instruction code as an address. Thereafter, 1, 2 or 4 is added to the contents of the address register, and the addition result is stored in the address register. 1 is added for the byte size, 2 is added for the word size, and 4 is added for the long word size.
(B) Pre-decrement register indirect [@ -ERn] designates an operand on the memory using the contents obtained by subtracting 1, 2 or 4 from the contents of the address register (ERn) designated in the register field of the instruction code. . Thereafter, the subtraction result is stored in the address register. 1 is subtracted for the byte size, 2 for the word size, and 4 for the long word size.
(C) Pre-increment register indirect [@ + ERn] designates an operand on the memory with the contents obtained by adding 1, 2, or 4 from the contents of the address register (ERn) designated in the register field of the instruction code as an address. . Thereafter, the addition result is stored in the address register. 1 is added for the byte size, 2 is added for the word size, and 4 is added for the long word size.
(D) Post-decrement register indirect [@ ERn-] designates an operand on the memory using the contents of the address register (ERn) designated in the register field of the instruction code as an address. Thereafter, 1, 2 or 4 is subtracted from the contents of the address register, and the subtraction result is stored in the address register. 1 is subtracted for the byte size, 2 for the word size, and 4 for the long word size.

(6) Absolute address [@aa: 8 / @ aa: 16 / @ aa: 24 / @ aa: 32]
This is an absolute address included in the instruction code and designates an operand on the memory. The absolute address is 8 bits (@aa: 8), 16 bits (@aa: 16), 24 bits (@aa: 24), or 32 bits (@aa: 32). As the data area, 8 bits (@aa: 8), 16 bits (@aa: 16), or 32 bits (@aa: 32) are used. In the case of an 8-bit absolute address, all the upper 24 bits are 1 (H'FFFF). In the case of a 16-bit absolute address, the upper 16 bits are sign-extended. In the case of a 32-bit absolute address, the entire address space can be accessed. As a program area, 24 bits (@aa: 24) or 32 bits (@aa: 32) are used. In the case of 24 bits (@aa: 24), the upper 8 bits are all 0 (H'00).

(7) Immediate [#xx: 8 / # xx: 16 / # xx: 32]
This uses 8-bit (#xx: 8), 16-bit (#xx: 16), or 32-bit (#xx: 32) data included in the instruction code directly as an operand.

(8) Program counter relative [@ (d: 8, PC) / @ (d: 16, PC)]
This is used in instructions such as Bcc (conditional branch instruction) and BSR (subroutine branch instruction). An 8-bit or 16-bit displacement included in the instruction code is added to a 32-bit address specified by the contents of the PC to generate a 32-bit branch address. Upon addition, the displacement is sign-extended to 32 bits.

(9) Program counter index register relative [@ (ERn.B, PC) / @ (ERn.W, PC) / @ (ERn.L, PC)]
This is used in Bcc and BSR instructions. The contents of the specified number of bits (RnL, Rn, ERn) of the address register specified in the register field of the instruction code are zero-extended to 32 bits, multiplied by 2 (actually shifted), and the multiplication result Then, a 32-bit address specified by the contents of the PC is added to generate a 32-bit branch address. In short, when a part of the general-purpose register is used for holding information, the information that uses a part of the general-purpose register is shifted according to the size of the information to be accessed, and the shift result is a program count means that is other information. The effective address is calculated by adding it to the instruction address information held by, and the calculated effective address is set as the branch destination address.

(10) Memory indirect [@@ aa: 8]
This is used in instructions such as JMP (unconditional branch instruction to a specified address), JSR (subroutine branch instruction to a specified address), and the like. An operand on the memory is designated by an 8-bit absolute address included in the instruction code, and the contents are branched as a branch address. The upper bits of the 8-bit absolute address are specified by the vector base register VBR. In the minimum mode, the operand on the memory is specified by the word size, and a 16-bit branch address is generated. In the maximum mode, the operand on the memory is specified with a long word size.

(11) Extended memory indirect [@@ vec: 7]
This is a combination of data such as 7-bit data (vec) included in the instruction code and an offset, for example, a fixed value H'80, corresponding to the size of the program counter or address space, x2 (doubled). ) Or × 4 (4 times), add the start address of the branch table as specified by the register such as the vector base register VBR to the shifted value, and branch using this addition result as the address Read the table and branch the read contents as the branch destination address. Therefore, the offset value is determined so as to exceed the range of the exception processing vector table on the basis of the vector base register VBR (in short, a fixed value H′80 is added to the upper part of vec). It is possible to branch to a subroutine by referring to the subroutine vector table mapped in the range exceeding the range.

  FIG. 9 does not illustrate the process of adding the value of the vector base register VBR. FIG. 25 (6a) is a diagram that expresses this point more clearly.

  (6b) of FIG. 25 illustrates an extended memory indirect addressing mode that employs a subroutine vector table register TBR dedicated to a subroutine call instead of the vector base register VBR and enables the subroutine call. That is, the value disp of the predetermined field of the instruction is shifted by the number of bits according to the access size of information, for example, 2 bits or 4 bits, and the address is calculated by adding the value of the subroutine vector table register TBR to the shifted value. Then, the subroutine vector table is read at the calculated address, and the read content is set as a branch destination subroutine address. Although not specifically shown, it is also possible to add an addressing mode that uses the value of TBR instead of VBR in (6a) of FIG.

  The instruction in the instruction format illustrated in (6b) of FIG. 25 is, for example, a subroutine call instruction, which is a 16-bit instruction, and disp is 8 bits. FIG. 10 illustrates an instruction format of the CPU machine language. CPU instructions are in units of 2 bytes (words). Each instruction includes an operation feed (op), a register field (r), an EA extension (EA), and a condition field (cc).

  The operation field (op) represents the function of the instruction, and specifies the processing contents of the specified operand of the addressing mode. Always include the first 4 bits of the instruction. There may be two operation fields.

  The register field (r) specifies a general purpose register. The register field (r) is 3 bits for the address register and 3 bits (32 bit register) or 4 bits (8 or 16 bit register) for the data register. There may be two register fields or no register fields.

  The EA extension unit (EA) designates immediate data, an absolute address, or a displacement. It is an 8-bit, 16-bit, or 32-bit field. The condition field (cc) specifies the branch condition of the conditional branch instruction (Bcc instruction).

  FIG. 11 illustrates an instruction format related to the present invention.

[Effective address calculation for arrays, etc.]
MOV. L @ (d: 16, rs), rd is a two-word instruction that specifies the index register (rs) with bits 6-4 of the first word, the data register (rd) with bits 3-0, Two words are displacement (d). This instruction uses the index register indirect addressing mode with 16-bit displacement shown in (5) (a) of FIG. This instruction is one of the first instructions. A transfer instruction or the like using the register indirect addressing mode with displacement shown in (4) of FIG. 6 is classified as a second instruction.

[MOVA instruction for effective address calculation such as array]
MOVA / L @ (d: 16, rd), rd is a two-word instruction, and the general register (rd) common to the index register and the data register is designated by bits 2 to 0 of the first word, and the second word is Displacement (d). This instruction also uses the index register indirect addressing mode with 16-bit displacement shown in (5) (a) of FIG. This instruction is one of the third instructions.

[Branch instruction 1]
BRA rs is a one-word instruction that designates the index register (rs) with bits 6-4. This instruction uses an addressing mode relative to the program counter index register shown in (3) of FIG. This branch instruction is another example of the first instruction.

[Branch instruction 2]
JMP @@ aa: 7 is a one-word instruction and includes address information (aa) for designating a branch table in bits 7-0. This instruction uses the extended memory indirect addressing mode shown in (6) of FIG. 9 and (6a) of FIG.

[Branch instruction 3]
FIG. 26 shows an operation by a subroutine instruction in the addressing mode shown in (6b) of FIG. The format of the subroutine call instruction (16-bit instruction) described here is “JSR / N @@ (disp8, TBR)”. disp8 means 8-bit disp (displacement). The instruction code is “10000011dddddddd”, and dddddddd is an 8-bit disp (displacement). The outline of the operation is as follows. [1] The program counter PC is saved in a PR (Procedure Register) for restoration. [2] The value of TBR (subroutine vector table register) and the value of disp8 × 4 (2 bits left shift) are added to generate a 32-bit table entry address. [3] A 32-bit address is loaded into the program counter PC from the table entry of the address generated in [2]. [4] Jump to the address (covering the entire space) loaded in [3].

[Branch instruction 4]
In FIG. 27, a dedicated subroutine base register SBR indicating the start address of a subroutine call group is further introduced, and an instruction that can branch at a 16-bit table address within 64 KB is mixed to optimize the table size. An example of this will be described. An outline of the operation will be described. [1] The value of the program counter PC is saved in the PR (procedure register) as a return address. [2] The value of TBR (subroutine vector table register) and the value of disp8 × 2 are added to generate a 32-bit table entry address. [3] A 16-bit address is loaded from the table entry of the address generated in [2], zero-extended, and SBR (subroutine base address register) is added to generate an address. [4] Jump to the address (64 KB covered) generated in [3] above.

  As described above, the dedicated subroutine vector table register TBR that points to the head address table of the subroutine call is introduced separately from the vector base register VBR for exception processing. In the case of the branch instruction 3, the disp in the instruction code is used. (Displacement) allows a subroutine call by referring to the 32-bit address table with one 16-bit instruction, and further introduces a subroutine base register SBR as in the case of the branch instruction 4, and within 64 KB from there If it is possible to branch at a 16-bit table address, the size of the subroutine vector table can be reduced.

  According to the branch instructions 3 and 4, the instruction has a code size of 16 bits, has a dedicated address table area that can be freely arranged, and has no restriction on the range of jump destination addresses. As described above, the code efficiency can be improved without restricting the arrangement address of the subroutine and the address table area. In short, 1) code efficiency (size), 2) all address space within a jumpable range, and 3) easy programming by a dedicated subroutine vector table area that can be freely arranged can be satisfied.

[Bit field instruction]
BFLD # xx, @ aa: 16, rd is a 3-word instruction, the second word is an absolute address (aa), bits 7 to 0 of the third word include immediate (xx), and the third word Bits 11 to 8 designate the destination register (rd).

  BFST rd, #xx, @rs is a two-word instruction that includes an immediate (xx) in bits 7-0 of the second word, and an address register (rd) in bits 6-4 of the first word. The source register (rs) is designated by bits 11 to 8 of the word.

  FIG. 12 illustrates a data processing function by a bit field instruction.

  The BFLD (bit field load) instruction is an instruction for transferring a field (hatched field) specified in a source operand to the 8-bit register Rd in the lower order (the upper bit is 0). The bit field is designated by a bit in which 1 of 8-bit immediate data (mask data) is set. In short, the BFLD instruction reads the data on the memory, takes a logical product with the immediate data contained in the instruction code, and, for the result of the logical product, the logical value “1” on the lower bit side of the immediate data. The right shift is performed so that the first bit becomes the least significant bit, and the result of the right shift is stored in the general-purpose register.

  The BFST (bit field store) instruction transfers the contents (lower padding) of the 8-bit register Rs to the field (hatched field) designated by the immediate data in the destination operand. The bit field is designated by a bit in which 1 of 8-bit immediate data is set. In short, the BFST instruction shifts the contents of the general-purpose register to the bit of the logical value “1” on the lower bit side of the immediate data included in the instruction code, and the bit of the logical value “1” of the immediate data is The shifted contents are selected, and the bit of logical value “0” defines the process of selecting the contents of the read memory and storing the result in the memory.

  FIG. 1 illustrates details of the CPU. The CPU 2 as the instruction execution means includes a control unit 2A and an execution unit 2B.

  The control unit 2A includes an instruction register IR, an instruction change unit CHG, an instruction decoder DEC, a register selector RESL, and an interrupt control unit INTC.

  The instruction decoder DEC is configured by, for example, a micro ROM, PLA (Programmable Logic Array), or a wiring logic. Part of the output of the instruction decoder DEC is fed back to the instruction decoder DEC. This includes a stage code (TMG) used for transitions within each instruction code.

  The instruction decoder DEC controls the execution unit 2B. The control signals gbbyte, gbword, gbsft1, gbsft2, bfld, bfst, alaba, which will be described in detail later, are output for controlling the arithmetic logic unit ALU. Further, other control signals aa, aa7rd, and vecrd are output for controlling the memory address buffer AB.

  The register selector RESL outputs a register selection signal rsgb [n], wbrd [n], etc. based on an instruction from the instruction decoder DEC and information on a register field included in the instruction code, and controls input / output of the general-purpose register. To do. [N] means a number from 0 to 7 corresponding to the general-purpose register.

  The instruction register IR temporarily stores the read instruction. The instruction to be executed is output to the instruction decoder DEC. The instruction change unit CHG operates when an instruction code other than the read instruction is given to the instruction decoder DEC, and in other cases, the contents of the instruction register IR are given to the instruction decoder DEC. The instruction code other than the read instruction is used when an exception process such as an interrupt is executed according to an instruction from the interrupt control unit INTC. The interrupt control unit INTC receives the interrupt request signal intf output from the interrupt controller 3 in FIG. 2, and refers to the interrupt mask signal 21 output from the instruction decoder DEC. If the interrupt is not masked, the instruction change unit CHG An interrupt is instructed by a signal 20.

  The execution unit (EXEC) 2B includes general-purpose registers ER0 to ER7, a program counter PC, a condition code register CCR, a temporary register TR, an arithmetic logic unit ALU, an incrementer INC, a read data buffer DBR, a write data buffer DBW, an address It includes a buffer AB and vector base registers VBR and TBR. These circuit blocks are connected to each other by internal buses ab, gb, db, wb1, and wb2.

  The arithmetic and logic unit ALU is used for various operations designated by instructions and calculation of effective addresses. The incrementer INC is mainly used for addition of the program counter PC.

  Other than the general-purpose registers ER0 to ER7, the program counter PC, and the condition code register CCR shown in FIG. 3, they cannot be referred to for programming, and are used only for the operation inside the microcomputer 1. That is, the read data buffer DBR, the write data buffer DBW, the address buffer AB, and the like are used for temporary data latching and buffering in order to interface with the internal buses IAB and IDB. The temporary register TR is appropriately used for the operation inside the microcomputer 1. The internal buses IAB and IDB mean an internal address bus and an internal data bus included in the internal bus 11.

  The read data buffer DBR temporarily stores the instruction code (EA extension unit) and data read from the ROM 4, RAM 5, internal I / O register, or external memory (not shown). The write data buffer DBW temporarily stores write data to the ROM 4, RAM 5, internal I / O register, or external memory. The address buffer AB is used for buffering addresses read / written by the CPU 2 and for generating read addresses for exception processing vector tables (vector tables) and subroutine vector tables (branch tables). The address buffer AB receives a vector input from the interrupt controller, a value vec included in the instruction code, a value on the internal bus ab, and the like, and outputs an address. As described above, the value of the vector base register VBR is used as an upper address of a table reference using the vector VEC for exception processing and a table reference using the vector field value vec in the extended memory indirect.

  The logical description representing the function of the address buffer AB can be expressed as shown in FIG. The logic description in FIG. 4 is called RTL (Register Transfer Level) or HDL (Hardware Description Language) description, and can be logically expanded into a logic circuit by a known logic synthesis tool. HDL is standardized as IEEE 1364. The syntax of the logical description shown here conforms to the case statement, and when there is a change in the value or signal defined in () next to alwayss @, The description is to process. The symbol “|” represents a logical sum, and “&” represents a logical product. “2′b01” means a binary code 01 having a 2-bit length. In the logic description of FIG. 13, the mode is the maximum mode when mode = 0, the minimum mode when mode = 1, the control signal aa7rd is active when the branch table is read indirectly in the extended memory, and the control signal VECrd is active when the vector is read for exception processing. And That is, the logical description in FIG. 13 is selected according to the mode signal and the control signals aa7rd and VECrd. When all the control signals are inactive, the contents of the internal bus ab are selected.

  FIG. 14 illustrates the configuration of the main part of the arithmetic logic unit ALU. The arithmetic logic unit ALU includes an input selector 25, an arithmetic logic unit 26, a bit field operation unit 27, and an output selector 28. In addition to this, additional functions such as an ALU input selector on the internal bus db side and a bit operation instruction, which are not illustrated, are included, but detailed description thereof is omitted here.

  The input selector 25 has a zero extension function and a 1-bit shift or 2-bit shift function. FIG. 15 illustrates the function by a logical description. That is, after a resource such as a general-purpose register to be output is selected and input to the arithmetic logic unit ALU via the internal bus gb, the size of the general-purpose register (index register) to be used is specified by the signals gbbyte and gbword. The upper part is zero-extended. Thereafter, the number of shift bits is specified by the signals gbsft1 and gbsft2, and x1 / x2 / x4 is selected. For example, MOV. In the address calculation of L @ (d: 16, R1L), ER0, gbbyte = 1, gbword = 0, gbsft1 = 0, and gbsft2 = 1. The data that has been shifted and expanded by 0 is added to the displacement that is output from the read data buffer DBR and input to the arithmetic logic unit 26 via the internal bus db. The addition result is output as an address via the output selector 28 and the internal bus ab, and is also stored in the general-purpose register via the internal bus wb2. The calculation result is output to both the bus ab and the bus wb2. The input selector 25 may include logic to invert in order to subtract the contents of the internal bus gb. As the index register, it is possible to shorten the delay time by not using negative numbers and by parallelizing the logic of the input selector 25.

  The bit field load operation unit 27 inputs the internal buses gb and db and the immediate data (imm) and outputs the result to the internal bus wb2. As described above, the immediate data (imm) is bits 7 to 0 of the instruction code (xx of the BFLD instruction in FIG. 8) or the like. The calculation result output to the internal bus wb2 is stored in the general-purpose register or the write data buffer DBW. A logical description for performing the BFLD operation is illustrated in FIG. That is, the logical product of the immediate data (imm) and the internal bus gb is calculated, and the right shift is performed by the number of bits specified by the immediate data (imm) (until the lowest “1” bit becomes bit 0). Is.

  A logical description for performing the BFST operation is illustrated in FIG. That is, the internal bus db is shifted to the left by the number of bits specified by the immediate data (imm) (to the bit position of the lowest “1”), bf_in is generated, and the immediate data (imm) is 1 bit. Bf_in and other bits generate the contents of the internal bus gb (data read from the memory).

  Next, the execution timing of instructions related to the present invention will be described. As described above, the internal bus is 32 bits, but for the sake of simplicity, it is assumed that instruction read is performed 16 bits at a time. In addition, read / write of the built-in ROM 4 and RAM 5 can be read / written in one state.

  18 shows MOV. The execution timing of L @ (d: 16, R1L), ER0 is illustrated. This shows the execution timing of the instruction corresponding to the instruction format of [Effective address calculation of array etc.] described in FIG.

  At T0, the address is output from the address buffer AB of the CPU 2 to the address bus IAB. The instruction decoder DEC outputs a bus command BCMD indicating instruction fetch (if).

  At T1, the address on the internal address bus IAB of T0 and the read data according to the bus command BCMD are obtained on the internal data bus IDB. This read data is taken into the instruction register IR at T2. The above operation is performed by controlling the execution of the previous instruction.

  Although there is no particular limitation, an address is output to the internal address bus IAB, a bus command BCMD is output, and an instruction read (prefetch) is performed, even at T1, T2, T4, and T5. The displacement of this instruction is obtained on the internal data bus IDB at T2, and is taken into the read data buffer DBR at T3.

  When the execution of the immediately preceding instruction is completed, the execution of the instruction is started earliest. At T2, the read data and the instruction code are input to the instruction decoder DEC, and the contents of the instruction are decoded.

  A part of the instruction code (register designation feed) is given to the register selector RESL and decoded. In accordance with the decoding result, a control signal / register selection signal is output at T3. The signal rsgb1 is activated and the contents of the general-purpose register ER1 are output to the internal bus gb. In addition, a control signal dbrdb (output control signal from the read data buffer DBR to the bus db) (not shown) and a control signal dbrex (sign extension instruction signal for the data in the read data buffer) (not shown) are activated. The 16-bit displacement captured in the read data buffer DBR is sign-extended and output to the internal bus db. These are input to the arithmetic logic unit ALU. The signals gbbyte (byte input instruction signal from the internal bus gb) and gbsft2 (2-bit shift instruction signal for the input from the internal bus gb) are activated, and the lower 8 bits of the data input from the internal bus gb are zero-extended. Then, it is shifted by 2 bits and added to the content input from the internal bus db. The signal alaab (instruction signal for outputting the operation result of ALU to the bus ab) is activated, the addition result (ea) is output to the internal bus ab, and further to the internal address bus IAB via the address buffer AB. Is output. At the same time, a bus command BCMD indicating a long word read is output. At the same time, a data read control signal including a register selection signal is generated, and T4 and T5 are sequentially controlled. Specifically, at T4, the signal ldd (load instruction signal from IDB to DBR) is activated, and read data buffer DBR fetch control is instructed. At T5, the signal dbrrd0 (DBR read instruction signal) is activated, and the transfer of the contents of the read data buffer DBR to the general-purpose register ER0, which is the destination register, is instructed.

  The read data is obtained on the internal data bus IDB at T4, and as described above, is read into the read data buffer DBR at T5 and transferred to the general-purpose register ER0 at T6. At the same time, a predetermined flag in the condition code register CCR is updated according to the contents of the transfer data.

  FIG. 19 illustrates the execution timing of MOVA / L @ (d: 16, R1L), ER1. This indicates the execution timing of an instruction corresponding to the instruction format of [MOVA instruction for effective address calculation such as array] described in FIG.

  Similarly to the above, at T2, the instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. The displacement is taken into the read data buffer DBR at T3. A part of the instruction code (register designation feed) is given to the register selector RESL and decoded. In accordance with the decoding result, a control signal / register selection signal is output at T3. Signal rsgb1 (output instruction signal from ER1 to bus gb) is activated, and the contents of general-purpose register ER1 are output to internal bus gb. Further, the signal dbrdb (output instruction signal from the DBR to the bus db) is activated, and the displacement taken into the DBR is output to the internal bus db. These are input to the arithmetic logic unit ALU. The signals gbbyte and gbsft2 are activated, the lower 8 bits of the data input from the internal bus gb are zero-extended, shifted by 2 bits, added to the content input from the internal bus db, and the addition result is internal. It is output to the bus wb2. At the same time, the signal wbrd1 (write instruction signal from the bus wb2 to the register ER1) is activated, and the contents of the internal bus wb2 are stored in the general-purpose register ER1 that is the destination register. Although there is no particular limitation, the condition code register CCR is retained in the case of MOVA, which is an effective address transfer instruction.

  FIG. 20 illustrates the execution timing of BRA R2. This indicates the execution timing of an instruction corresponding to the instruction format of [Branch instruction 1] described in FIG.

  Similarly to the above, at T2, the instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. A part of the instruction code (register designation feed) is given to the register selector RESL and decoded. According to the decoding result, instruction reading is suppressed at T2. At T3, a control signal / register selection signal is output. The signal rsgb2 is activated and the contents of the general-purpose register ER2 are output to the internal bus gb. Further, the signal pcdb (output instruction signal of the PC value to the bus db) not shown is activated, and the value of the program counter PC is output to the internal bus db. These are input to the arithmetic logic unit ALU. The signals gbword and gbsft1 are activated, the lower 16 bits of the data input from the internal bus gb are zero-extended, shifted by 1 bit, and added to the content input from the internal bus db, and the addition result is the internal bus is output to ab. The address (target) output to the internal bus ab is output to the internal address bus IAB via the address buffer AB. At the same time, a bus command BCMD indicating an instruction read is output. Further, the content output to the internal bus ab is incremented by +2 by the incrementer and stored in the program counter PC.

  At T4, instruction read and increment of the program counter PC are performed according to the updated value of the program counter PC. At T5, the branch destination instruction code read at T3 is input to the instruction decoder DEC, and the contents of the branch destination instruction are decoded.

  FIG. 21 illustrates the execution timing of JMP @@ aa: 7. This indicates the execution timing of an instruction corresponding to the instruction format of [branch instruction 2] described in FIG.

  Similarly to the above, at T2, the instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, the control signal aa7rd is activated, and at T2, a part of the instruction code (bits 6 to 0), a fixed value (H'80) in the upper bits and the vector base register VBR are stored in the address buffer AB. Content is given. Further, according to the CPU operation mode (mode), a 1-bit shift is performed in the minimum mode, and a 2-bit shift is performed in the maximum mode, and the result is output to the internal address bus IAB. At the same time, a bus command BCMD indicating a word read in the minimum mode and a long word read in the maximum mode are output. At T3, a standby state is set. In the case of a subroutine branch instruction, the stack operation may be performed in this state.

  At T4, the read data is stored in the read data buffer DBR, and the contents are output to the internal address bus IAB via the internal bus ab and the address buffer AB. At the same time, a bus command BCMD indicating an instruction read is output. Further, the content output to the internal bus ab is incremented by +2 by the incrementer INC and stored in the program counter PC.

  At T5, instruction read and increment of the program counter PC are performed according to the updated value of the program counter PC. At T6, the branch destination instruction code read at T3 is input to the instruction decoder DEC, and the contents of the branch destination instruction are decoded.

  The number of execution states can be made equal when a branch instruction having an absolute address of 32 bits is compared with a case where the instruction code is read in units of 16 bits. If the instruction code is read in 32-bit units and the 32-bit absolute address has been read before the execution of the branch instruction with the 32-bit absolute address, the execution can be performed faster than in the extended memory indirect addressing mode. For processing that requires high-speed branching, an absolute address 32-bit branch instruction may be used. For branch instructions that have many branch instructions that share a common branch destination and do not require a high-speed branch, a branch instruction in the extended memory indirect addressing mode may be used. This specification may be specified as a C compiler option or a source program control instruction.

  FIG. 22 illustrates the execution timing of BFLD #xx, @aa: 16, R3H. This indicates the execution timing of an instruction corresponding to the instruction format of [bit field instruction] described in FIG.

  Similarly to the above, at T2, the instruction code first word (bfld-1) is input to the instruction decoder DEC, and the contents of the instruction are decoded. The absolute address (bfld-2) of the second word is taken into the read data buffer DBR at T3. At T4, the third word (bfld-3) is input to the instruction decoder DEC, and the contents of the instruction are decoded.

  In accordance with the decoding result, at T3, the signals dbrab (output instruction signal from the buffer DBR to the bus ab) and dblex (sign extension instruction signal for the information held in the buffer DBR) are activated, and the lower 16 The bit is sign-extended and output to the internal address bus IAB via the internal bus ab and the address buffer AB. At the same time, a bus command BCMD indicating a byte read is output. The read data is taken into the read data buffer DBR at T5.

  At T5, a control signal / register selection signal is output. The signal dbrgb is activated, read data is output to the internal bus gb, and immediate data as part of the instruction code is input to the arithmetic logic unit ALU. The signal bfld is activated, the arithmetic logic unit ALU performs a bit field load operation, and the operation result is output to the internal bus wb2. At the same time, the signal wbrd3h (load instruction signal from the bus wb2 to the general-purpose register R3H) is activated, and the contents of the internal bus wb2 are stored in the general-purpose register R3H which is the destination register. Although not particularly limited, the condition code register CCR is retained in the case of a BFLD instruction.

  FIG. 23 shows the execution timing of BFST R4L, #xx, @ ER3. This shows the execution timing of an instruction different from FIG. 22 corresponding to the instruction format of [bit field instruction] described in FIG.

  Similarly to the above, at T2, the instruction code first word (bfst-1) is input to the instruction decoder DEC, and the contents of the instruction are decoded. At T3, the second word (bfst-2) is input to the instruction decoder DEC, and the contents of the instruction are decoded. In accordance with the decoding result, at T2, the signal yrsab3 (not shown) is activated, and the contents of the general-purpose register ER3 are output to the internal address bus IAB via the internal bus ab and the address buffer AB. At the same time, a bus command BCMD indicating a byte read is output. The read data is taken into the read data buffer DBR at T4.

  At T4, a control signal / register selection signal is output. The signal dbrgb is activated, read data is output to the internal bus gb, the signal rddb4l is activated, the contents of the general-purpose register R4L are output to the internal bus db, and an immediate part of the instruction code Data is input to the arithmetic logic unit ALU. The signal bfst becomes active, the arithmetic logic unit ALU performs a bit field store operation, and the operation result is output to the internal bus wb2. At the same time, the signal wbdbw is activated, and the contents of the internal bus wb2 are stored in the write data buffer DBW at T5. At the same time at T4, the same contents as T2 are output to the internal address bus IAB. This is preferably held in the temporary register TR at T2 and output to the internal bus ab at T4. This was separately proposed in Japanese Patent Application No. 2000-161137. Alternatively, it may be held in the address buffer AB. Further, at T4, a bus command BCMD indicating a byte write is output. At T5, the contents of the write data buffer DBW are output to the internal data bus IDB. Although not particularly limited, in the case of a BFST instruction, the value of the condition code register CCR is retained.

  FIG. 24 shows an outline of the development environment of the CPU 2. The developer creates a program in C language or assembly language using various editors. This is usually created by dividing it into a plurality of modules.

  The C compiler 30 inputs each C language source program 31 created by the developer, and outputs an assembly language source program or an object module. As a compile-time option, a function that should be used as extended memory indirect can be specified.

  The assembler 32 inputs the assembly language source program 33 and outputs an object module.

  The linkage editor 34 inputs a plurality of object modules 35 generated by the C compiler and assembler, resolves external references and relative addresses of the modules, combines them into one program, and loads the load module 36. Output. At this time, the program is analyzed to determine the displacement and the bit length of the absolute address. In addition, an instruction with a short instruction code such as extended memory indirect is assigned to a branch instruction with a high branch destination frequency. In short, optimization is performed at the time of linking.

  The load module 36 can input to the simulator / debugger 37, simulate the operation of the CPU 2 on a system development device such as a personal computer, display the execution result, and analyze and evaluate the program. In addition, by inputting to the emulator 38 and performing so-called in-circuit emulation that operates on an actual application system or the like, it is possible to analyze and evaluate the actual operation of the entire microcomputer. Furthermore, a load module can be input to the PROM writer 39, and the created program can be loaded to the case where the built-in ROM of the microcomputer is a flash memory or the like, or to an external flash memory. If necessary, it is converted into a desired format by an object converter or the like. In addition, a general subroutine can be provided as a librarian.

  According to the microcomputer described above, the following functions and effects can be obtained.

  (1) By having a function of executing an instruction corresponding to processing that has been realized using a plurality of instructions in the past, it is possible to improve usability, reduce the program capacity, and improve the processing speed. By reducing the program capacity, it is possible to reduce the memory capacity of the ROM for storing the program, thereby saving costs.

  (2) By using the index register and the data register in the same unit, programming can be facilitated, and the upper general-purpose register can be easily used as another data register.

  (3) The effective address calculation using the contents of the general-purpose register as an index register and the instruction to store the result in the same general-purpose register should use fewer register fields, and the once-used general-purpose register should normally be used multiple times. Therefore, it is possible to shorten the instruction code length or add another instruction code without impairing the usability.

  (4) By using the index register in the lower order, it can be made the same as the number of address registers, and the instruction format can be easily made common. When adding to an existing CPU, it is easy to add.

  (5) Extended memory indirect enables mapping of a subroutine vector table to an area contiguous with an exception processing vector, thereby contributing to facilitating programming. The exception processing vector table and the subroutine vector table can be used effectively without overlapping. If the vector base register VBR is shared for exception calls and subroutine calls, it is possible to effectively use resources and improve usability.

  (6) By selecting the indirect use of the extended memory by the C compiler, the program capacity can be efficiently reduced.

  (7) By specifying the bit field as immediate, the logical configuration can be facilitated. The bit field operation unit is parallel to the arithmetic logic operation in which the arithmetic operation unit has a carry, and the delay time can be equalized to prevent an increase in the delay time.

  (8) By introducing a dedicated subroutine vector base register TBR that points to the head address table of the subroutine call separately from the vector base register VBR for exception handling, code efficiency, all address space within the jumpable range, free This makes it easy to program with a dedicated subroutine vector table area that can be placed in

  The invention made by the inventors as described above is not limited to the embodiments, and various modifications can be made without departing from the spirit of the invention.

  For example, the general-purpose registers need not be commonly used for addresses and data, and some or all of them may be dedicated to addresses or data. The data size of the general-purpose register can also be set arbitrarily. Further, although the index register is used in the lower order, the general register RH or the general register E may be usable.

  The CPU instruction system and instruction format can be arbitrarily modified. For example, the MOVA instruction designates the same general-purpose register, but other general-purpose registers or data on the memory can be used as a source (index register). The index register indirect with displacement can be applied to other operation instructions that specify a memory in addition to a transfer instruction. The zero extension and shift in the index register with displacement indirectly may be functions of the internal bus gb in addition to the functions of the ALU.

  The vector base register VBR may be omitted. It may be switched according to the operation mode. The detailed logic and execution sequence for bit field transfer can be modified. It is not essential to have both the addressing modes (6a) and (6b) in FIG. 25, and only one of them may be provided.

  Also, it is not necessary to limit the basic unit of the instruction code to 16 bits, and any bit width such as 8 bits or 32 bits can be used. A branch instruction with indirect extended memory may have a shorter instruction code length than a branch instruction with an absolute address. For simplicity, the bus width is set to 32 bits and the instruction read is set to 16 bits. However, the instruction read can be set to 32 bits to increase the speed. This was proposed in Japanese Patent Application No. 11-167812. Alternatively, the bus width may be 16 bits, and the long word read / write may be executed in two read / write operations in units of words.

  The number of bits of the program counter and the configuration of other control registers can be arbitrarily set. The VBR may be an internal I / O register as well as a register inside the CPU. The number of bits can also be arbitrarily set. Alternatively, the fixed value may be switched by an operation mode or setting of an internal I / O register.

  In the above description, the case where the invention made mainly by the present inventor is applied to the single chip microcomputer, which is the field of use behind the present invention, has been described. However, the present invention is not limited to this. The present invention can be widely applied to data processing devices such as computers, data processors, and general-purpose microprocessors. The present invention can be applied to at least a condition for decoding and processing instructions and performing arithmetic processing.

It is a block diagram which illustrates the detail of CPU to which this invention was applied. 1 is a block diagram of a single chip microcomputer to which the present invention is applied. FIG. It is explanatory drawing which illustrates the structure of the general purpose register and control register which were built in CPU. It is explanatory drawing which illustrates the usage form of a general purpose register. It is explanatory drawing which illustrates the address space of CPU. It is explanatory drawing which illustrates the calculation method of the effective address of a transfer / arithmetic instruction. It is explanatory drawing which illustrates further another calculation method of the effective address of a transfer / arithmetic instruction. It is explanatory drawing which illustrates the calculation method of the effective address of a branch instruction. It is explanatory drawing which illustrates another calculation method of the effective address of a branch instruction. It is a format figure which illustrates the instruction format of the machine language of CPU. It is explanatory drawing which illustrates the command format regarding this invention. It is explanatory drawing which illustrates the data processing function by a bit field instruction. It is explanatory drawing which illustrates the function of an address buffer with a logic description. It is a block diagram which illustrates the composition of the principal part of an arithmetic logic unit. It is explanatory drawing which illustrates the zero extension function and 1-bit shift or 2-bit shift function of an input selector by a logic description. It is explanatory drawing which illustrates a BFLD operation function with a logic description. It is explanatory drawing which illustrates a BFST operation function with a logic description. MOV. It is a timing chart which illustrates the instruction execution timing of L @ (d: 16, R1L) and ER0. It is a timing chart which illustrates the instruction execution timing of MOVA / L @ (d: 16, R1L), ER1. It is a timing chart which illustrates the instruction execution timing of BRA R2. It is a timing chart which illustrates the instruction execution timing of JMP @@ aa: 7. It is a timing chart which illustrates the instruction execution timing of BFLD #xx, @aa: 16, R3H. It is a timing chart which illustrates the instruction execution timing of BFST R4L, #xx, @ ER3. It is explanatory drawing which illustrates the outline of the development environment of CPU. It is explanatory drawing which illustrates the detail of the address calculation method of extended memory indirect addressing mode. It is explanatory drawing which shows the operation | movement by the subroutine command by the addressing mode shown by (6b) of FIG. It is explanatory drawing which shows the operation | movement by a subroutine command in the case of introduce | transducing the exclusive subroutine base register which shows the head address of a subroutine call group further.

Explanation of symbols

1 Microcomputer 2 CPU
2A Control unit 2B Execution unit IR Instruction register DEC Instruction decoder ER0 to ER7 General purpose register VBR Vector base register ALU Arithmetic logic unit INC Incrementer IDB Internal data bus IAB Internal address bus TBR Subroutine vector table register SBR Subroutine base register

Claims (5)

Having instruction execution means for reading and decoding an instruction and executing the instruction according to the decoding result;
The instruction execution means reads the data on the memory, takes a logical product with information of one or more bits included in the instruction code, and obtains the first result on the lower bit side of the information with respect to the result of the logical product. A data processing apparatus capable of executing a load instruction for right-shifting so that the bit in the state becomes the least significant bit and storing the result of the right shift in a general-purpose register.   The contents of the general-purpose register are left-shifted to the first state bit on the lower bit side of the information included in the instruction code, the first state bit in the information selects the shifted content, and the second 2. The data processing apparatus according to claim 1, wherein the status bit selects a content of the read memory, and a store instruction for storing the result in the memory can be executed.   3. The data processing apparatus according to claim 1, wherein the instruction code includes information for designating an address on a memory and information for designating a general-purpose register.   3. A data processing apparatus according to claim 1, wherein said instruction execution means is a central processing unit and is formed on one semiconductor substrate. Having instruction execution means for reading and decoding an instruction and executing the instruction according to the decoding result;
The data processing apparatus, wherein the instruction execution means decodes a predetermined instruction, selects a general-purpose register according to the result, and stores an operation result.

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