JP2007044222A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of controlling a plurality of LEDs and performing a gradation control for smoothly changing brightness of each of the LEDs even in the case of gradation-controlling the LEDs by serially outputted drive data by using fixed time timer interruption processing. <P>SOLUTION: At every fixed time timer interruption processing time, latch signals and switching signals outputted from the output port of a sub integrated board 111 are inputted to a gradation control IC, and the gradation control IC fetches the drive data serially outputted from the serial transmission part of the sub integrated board 111. Then, the gradation control IC outputs gradation drive signals to gradation lamps 49a and 49b on the basis of gradation data included in the drive data. Thus, even when gradation-controlling the LEDs by the serially outputted drive data by using the fixed time timer interruption processing, the plurality of LEDs can be controlled and the gradation control for smoothly changing the brightness of the respective LEDs can be performed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine that performs gradation control using a plurality of LEDs.

  Conventionally, lighting control of a decoration LED (light emitting diode) provided in a center accessory device or the like is simply ON / OFF control, so that it is monotonous only by repeatedly performing LED lighting / extinguishing mode. It was.

Therefore, in addition to lighting control by ON / OFF, gradation control that changes the brightness of the LED is performed to improve the visual effect and enhance the interest in the game (for example, Patent Document 1).
JP 2003-190416 A

  By the way, a fixed-time timer interrupt process can be used for this gradation control method. Within this fixed time timer interrupt process, ON / OFF data (drive data) for turning on / off the LED is serially output, and the serially output drive data is received by a shift register provided on the drive board and converted in parallel. Output to the LED. For example, when controlling the brightness of the LED in 8 steps, if the display reference period is 16 milliseconds (ms), the fixed time timer interrupt processing time is set to 2 ms, and the LED If ON / OFF data (driving data) for turning on / off the LED is serially output and updated, the lighting period in the reference period is adjusted, and as a result, the brightness of the LED can be changed in eight stages.

  However, in the gradation control of about 8 steps, for example, when changing from 2 steps to 3 steps, the brightness of the LED changes in a step shape (step shape). That's why I don't feel the smoothness of the change in brightness. In general, the change in brightness that humans perceive is felt as an exponential change, not as a linear change. Therefore, in order to make the change in brightness feel smoother, it is necessary to further refine the level at which gradation is possible.

  Therefore, for example, when considering 128 steps of adjustment by the conventional method, similarly, when 16 ms is set as the reference period of display, the fixed-time timer interruption processing time is 0.125 ms (= 16 ms). ÷ 128 steps), which is extremely short. Thus, making the gradation level fine limits the amount of information that can be serially output within the time of the fixed-time timer interrupt process. That is, the number of LEDs for gradation control is limited.

  The present invention has been made in view of such a problem in the case of performing gradation control of a plurality of LEDs. The object of the present invention is to output serially using a fixed-time timer interrupt process. It is an object of the present invention to provide a gaming machine capable of controlling a plurality of LEDs and performing gradation control for smoothly changing the brightness of each LED even when the LEDs are subjected to gradation control using drive data.

  Effective solutions for achieving the above-described object will be described below. In addition, the effect | action etc. are demonstrated as needed. In addition, for easy understanding, the corresponding configuration in the embodiment of the invention is also shown as appropriate, but is not limited at all.

(Solution 1)
A main control board, a sub-integrated board, a drive board, and a plurality of LEDs, the main control board outputs a command to the sub-integrated board based on the progress of the game, and the sub-integrated board Output driving data for gradation driving of the plurality of LEDs in a fixed-time timer interruption process based on the driving data, and the driving board performs gradation driving of the plurality of LEDs based on the driving data. The sub-integrated board includes a serial transmission unit, an output port, drive data creation means, a switching signal control means, and a latch signal control means, and the drive board includes a gradation control IC, The drive data creation means includes the drive data from gradation data for setting the luminance of the plurality of LEDs, and gradation ON / OFF data for setting ON / OFF of the plurality of LEDs, respectively. The switching signal control means outputs from the output port a switching signal for identifying either the gradation data or the gradation ON / OFF data by the gradation control IC. The latch signal control means performs control to output a latch signal from the output port when the gradation control IC captures the gradation data or the gradation ON / OFF data, and When the gradation control IC receives the gradation data and the gradation ON / OFF data output from the serial transmission unit when the latch signal and the switching signal output from the output port are input, the gradation control IC outputs the gradation control IC from the output port. When the latch signal is received, a gradation driving signal is output to the plurality of LEDs based on the gradation data.

  This gaming machine includes a main control board, a sub-integrated board, a driving board, and a plurality of LEDs. The main control board outputs a command to the sub-integrated board based on the progress of the gaming machine. The sub-integrated board to which this command is input outputs drive data for gradation driving of the plurality of LEDs in the fixed time timer interrupt process based on the command. The drive substrate to which this drive data is input drives the plurality of LEDs in gradation based on the drive data. The sub-integrated board includes a serial transmission unit, an output port, drive data generation means, a switching signal control means, and a latch signal control means, and the drive board includes a gradation control IC.

  The drive data creation means creates drive data from the gradation data for setting the brightness of each of the plurality of LEDs and the gradation ON / OFF data for setting the lighting / extinction of each of the plurality of LEDs, and sends the drive data to the serial transmission unit. The serial transmission unit that passes and receives the drive data serially outputs the drive data to the drive board. The switching signal control means controls the gradation control IC to output a switching signal for identifying either gradation data or gradation ON / OFF data from the output port, and the latch signal control means is a gradation control IC. Controls the output of the latch signal from the output port when the gray scale data or the gray scale ON / OFF data is fetched.

  The gradation control IC receives the latch signal and switching signal output from the output port, and receives the gradation data and gradation ON / OFF data serially output from the serial transmission unit, the latch signal is output from the output port. When input, the input of the latch signal triggers the output of a gradation drive signal to a plurality of LEDs based on the gradation data. Therefore, even when the LEDs are gradation-controlled by serially output drive data using the fixed-time timer interrupt process, a plurality of LEDs can be controlled, and the brightness of each LED can be changed smoothly. Key control.

  In the present embodiment, the main control board 101 in FIG. 5 corresponds to the main control board, the sub integrated board in FIG. 5 corresponds to the sub integrated board, the lamp driving board 112 in FIG. 5 corresponds to the driving board, and FIG. The production lamps 44a to 44d and the gradation lamps 49a and 49b correspond to a plurality of LEDs, the serial transmission unit 111at in FIG. 6 corresponds to a serial transmission unit, the output port 111aop in FIG. Data to be serially output (drive data DAT, which will be described later) is created and set in the transmission unit 111at, which corresponds to drive data creation means, grayscale data corresponds to grayscale data, and grayscale lamp ON / OFF data. Corresponds to the gradation ON / OFF data, and the gradation control IC 112g receives the switching signal MODE for capturing either the gradation data or the gradation lamp ON / OFF data. 6 corresponds to the switching signal control means, the switching signal MODE in FIG. 6 corresponds to the switching signal, and the gradation control IC 112g captures either gradation data or gradation lamp ON / OFF data. The output of the latch signal LAT corresponds to the latch signal output control means, and the latch signal LAT in FIG. 6 corresponds to the latch signal. The output current corresponding to the fetched gradation data corresponds to the gradation drive signal based on the gradation data.

(Solution 2)
The gaming machine according to Solution 1, wherein the gradation control IC is daisy chain connectable, the drive board includes a shift register, and the drive data creation means includes the plurality of LEDs. The shift register generates the driving data including lighting ON / OFF data for setting lighting / extinguishing of the LEDs that perform lighting control, and passes them to the serial transmission unit. When the latch signal output from the output port is input and the ON / OFF data for lighting output from the serial transmission unit is received, the lighting signal is received when the latch signal is received from the output port. A gaming machine that outputs a lighting drive signal to the plurality of LEDs based on the ON / OFF data. In this way, since the gradation control IC and the shift register can be daisy chained, a combination of gradation control by the gradation control IC and ON / OFF control by the shift register is possible.

  In the present embodiment, the shift registers 112h and 112i in FIG. 6 correspond to shift registers, the ON / OFF data for effect lamps corresponds to ON / OFF data for lighting, and serial data that is captured ON / OFF data for effect lamps. The data is converted into parallel data, and the parallel signal is used as the drive signal, and the lighting drive signal is based on the lighting ON / OFF data.

(Solution 3)
The gaming machine according to Solution 2, wherein the shift register is arranged in the first stage. When the shift register and the gradation control IC are connected in a daisy chain, when the shift register is arranged in the first stage, drive data is serially output to the gradation control IC via the first stage shift register. The drive data fetched by the shift register is composed only of ON / OFF data, that is, it is composed of data set to be turned on / off, so the drive data fetched by the shift register and the sub-integrated board are serialized. The output drive data has a one-to-one correspondence. Therefore, by arranging the shift register in the first stage, the drive data itself can be output immediately as a lighting drive signal.

(Solution 4)
4. The gaming machine according to claim 1, wherein the serial transmission unit is set to 250 kilohertz as a transfer clock. In this way, the transfer clock can be set to 250 kilohertz (kHz) and gradation control can be performed in 128 steps. With a transfer clock of 250 kHz, one cycle is 4 microseconds (μs), so the pulse width is 2 μs, and the data width of the drive data synchronized with this transfer clock is also 2 μs. Here, it has been experimentally obtained that the noise width falls within about 1 μs. That is, by setting the transfer clock to 250 kHz, the data width (2 μs) of the drive data does not approach the noise width (about 1 μs). Therefore, it is possible to serially output drive data to the gradation control IC with a transfer clock that is less susceptible to noise.

  In the present embodiment, the transfer clock CLK in FIG. 6 corresponds to the transfer clock.

(Solution 5)
The gaming machine according to Solution 1, further comprising a stepping motor, wherein the drive data creation means sets switching of excitation currents to be passed through the respective phase coils of the stepping motor that is controlled by the gradation control IC. The drive data including excitation data is generated and passed to the serial transmission unit, and the gradation control IC receives the latch signal and the switching signal output from the output port, and the output from the serial transmission unit. When the gray scale data, the excitation data, and the gray scale ON / OFF data are captured, when a latch signal is received from the output port, a gray scale drive signal is output to the plurality of LEDs based on the gray scale data. A gaming machine that outputs a drive signal to the stepping motor based on the excitation data. In this way, the gradation control IC can perform drive control of the stepping motor in addition to gradation control that smoothly changes the brightness of each LED. Here, the rated input current that can be driven by the stepping motor is set as the output current output from the gradation control IC.

  In the present embodiment, the stepping motors 120m and 120n in FIG. 9 correspond to stepping motors, and the rated input current of the drive board 120d in FIG. 9 corresponds to the driveable rated input current.

(Solution 6)
A drive board provided in the gaming machine according to any one of the solving means 1 to 5. This drive board is suitable for use as a component of the gaming machine of the present invention.

(Solution 7)
The gaming machine according to any one of solution means 1 to 6, wherein the gaming machine is a pachinko gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a pachinko gaming machine, the effects of the solving means 1 to 6 can be obtained in the pachinko gaming machine. As a basic configuration of this pachinko gaming machine, a game ball is driven into a game area (game area 12 in the present embodiment) in accordance with an operation of an operation means (operation handle 18 in the present embodiment), and the game ball that has been driven in Is displayed on the display area 42 in the effect device 40 in the present embodiment on the condition that a winning is made in the start opening provided in the game area (in this embodiment, the start winning opening 45, the electric start winning opening 46). ) Displays the variation of the symbol information and stops the display result of the symbol information. Also, when a profit granting state (a big hit gaming state) occurs, a big winning opening provided in the gaming area (this embodiment, the big winning opening 61) is opened in a predetermined manner to allow a game ball to be won, Based on the winning, a game privilege (awarding a prize ball, writing a point on a magnetic card, etc.) is given to the player.

(Solution 8)
The gaming machine according to any one of solution means 1 to 6, wherein the gaming machine is a spinning-type gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a spinning type gaming machine, the effects of the solving means 1 to 6 can be obtained in the spinning type gaming machine. As a basic configuration of this spinning machine, after a symbol information string composed of a plurality of symbol information (for example, a plurality of reel columns with a plurality of symbol information) is displayed in a variable manner, the display result of the symbol information is stopped and displayed. Fluctuation display means for starting, the fluctuation display of the symbol information is started based on the operation of the start operation means (for example, the operation lever), and the operation of the stop operation means (for example, the stop button) or the elapse of a predetermined time Based on this, the variable display of symbol information is stopped. And it is provided with the profit provision state generation | occurrence | production means which generate | occur | produces a profit provision state (big hit game state) on the condition that symbol information becomes a predetermined specific display mode.

(Solution 9)
The gaming machine according to any one of solution means 1 to 6, wherein the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a revolving gaming machine are fused.

  In the gaming machine of the present invention, since the gaming machine is a fusion gaming machine, the effects of the solving means 1 to 6 can be obtained in the fusion gaming machine. As a basic configuration of the fusion gaming machine in which the pachinko gaming machine and the revolving-type gaming machine are fused, a symbol information string composed of a plurality of symbol information (for example, a plurality of reel rows with a plurality of symbols) is variably displayed. After that, it is provided with a fluctuation display means for stopping and displaying the display result of the symbol information, and starting the fluctuation display of the symbol information based on the operation of the start operation means (for example, the operation lever), and the stop operation means (for example, The change display of the symbol information is stopped based on the operation of the stop button) or the elapse of a predetermined time. And it is provided with the profit grant state generation means which generates a profit grant state (big hit game state) on condition that the symbol information becomes a predetermined specific display mode, and by using the game ball as a game medium, A predetermined number of game balls are required at the start of the change, and a large amount of game balls are paid out when a profit granting state occurs.

(Solution 10)
An inspection system that uses a gaming machine provided with a drive board as an inspection jig when inspecting a serial function of the sub-integrated board in producing a sub-integrated board provided in a gaming machine, comprising an interface device, and the interface The apparatus includes inspection signal output means, serial data output means, parallel data reading means, inspection result determination means, and inspection result output means, and the inspection signal output means is externally connected to the sub-integrated board. When a request signal for starting the inspection of the serial function is input, the inspection start signal is output to the sub-integrated board, and the serial data output means serial data serially output by the sub-integrated board in response to the inspection start signal The inspection data is taken in, and the taken inspection data is output to a gaming machine as an inspection jig, The larel data reading means reads inspection data as parallel data obtained by converting the serial data into parallel data by the driving board provided in the gaming machine, and the inspection result determining means determines that the read inspection data is predetermined. It is determined whether or not the value matches, and the inspection result output means outputs the determination result to the outside.

  In this inspection system, when the sub-integrated board provided in the gaming machine is produced, when the serial function of the sub-integrated board is inspected, the gaming machine provided with the drive board is used as an inspection jig. The inspection system includes an interface device. The interface device includes inspection signal output means, serial data output means, parallel data reading means, inspection result determination means, and inspection result output means. The inspection signal output means outputs an inspection start signal to the sub-integrated board when a request signal for starting the inspection of the serial function of the sub-integrated board is input from the outside. The sub integrated substrate to which the inspection start signal is input outputs inspection data to the interface device in accordance with the inspection start signal. In the interface device that captures the inspection data that is serial data, the serial data output means outputs the captured inspection data to a gaming machine as an inspection jig. In a gaming machine as an inspection jig for taking in the inspection data, a driving board provided in the gaming machine converts inspection data, which is serial data, into parallel data. In the interface device, the parallel data reading means reads the inspection data converted into the parallel data, and the inspection result determination means determines whether or not the read inspection data matches a predetermined determination value. The inspection result output means outputs the determination result to the outside. In this way, even in gaming machines of different models, the gaming machine itself to which the sub-integrated board to be inspected is attached is used as an inspection jig, that is, by using the driving board provided in the gaming machine, an inspection jig is provided for each model. There is no need to create each one. Therefore, the inspection of the serial function of the sub-integrated board can be made common in gaming machines of different models.

  In the present embodiment, the pachinko machine 1 in FIG. 1 corresponds to a gaming machine, the lamp driving board 112 in FIG. 6 corresponds to a driving board, the inspection system 200 in FIG. 7 corresponds to an inspection system, and the interface device in FIG. 230 corresponds to the interface device, the start signal of the serial I / O check program in step S125 of FIG. 8 corresponds to the inspection signal output means, and the interface device 230 transfers the serial I / O check inspection data DAT to the transfer clock. In synchronization with CLK, each bit is output to the lamp driving substrate 112, which corresponds to serial data output means, serial I / O check inspection data corresponds to inspection data, and the interface device 230 converts the parallel data into the parallel data. Reading the converted serial I / O check test data is parallel data. 7 corresponds to the reading means, reads the serial I / O check verification data from the ROM 230b of FIG. 7, and determines whether or not it matches the serial I / O check inspection data, and corresponds to the inspection result determination means. The verification data for serial I / O check corresponds to the determination value, and the result of the serial I / O check in step S135 in FIG. 9 corresponds to the inspection result output means.

(Solution 11)
The inspection system according to the solution 10 includes an inspection integrated personal computer, and the inspection integrated personal computer receives the request signal when a request signal for starting an inspection of the serial function of the sub-integrated board is input from an operator. An inspection system that outputs a signal to the interface device and displays the determination result output from the interface device on a display screen of a monitor. In this way, the inspection integrated personal computer is provided with input devices such as a keyboard and a mouse, and the operator can start inspection of the serial function of the sub-integrated board by operating these input devices. it can. In addition, since the inspection result is displayed on the monitor, it is possible to confirm at a glance whether the sub-integrated substrate is non-defective or defective. If a failure occurs in the inspection integrated personal computer, another personal computer can be used as a substitute for the inspection integrated personal computer, and even if the personal computer is changed, the operation method of the input device does not change. , Less confusing to workers. Therefore, even if a defect occurs in the inspection integrated personal computer, it can be promptly dealt with.

  In the present embodiment, the inspection integrated PC 210 in FIG. 9 corresponds to an inspection integrated personal computer, and the monitor 220 in FIG. 9 corresponds to a monitor.

(Solution 12)
12. The inspection system according to claim 10 or 11, wherein the drive board provided in the gaming machine as an inspection jig is the drive board according to solution means 6. This drive substrate is suitable for use as a component of the inspection system of the present invention.

(Solution means 13)
An inspection method using a gaming machine with a driving board as an inspection jig when a computer inspects a serial function of the sub-integrated board in producing a sub-integrated board provided in a gaming machine, and (a) from the outside When a request signal for starting the inspection of the serial function of the sub-integrated board is input, a step of outputting an inspection start signal to the sub-integrated board fixed to a probe base; and (b) in response to the inspection start signal, Capturing inspection data as serial data serially output by the sub-integrated board and outputting the acquired inspection data to a gaming machine as an inspection jig; and (c) the driving board provided in the gaming machine has serial data Reading test data as parallel data obtained by converting the data into parallel data; and (d) the read test data is predetermined. Determining whether the determination value to match the inspection method characterized by comprising the steps of: outputting to the outside (e) the determination result.

  In this inspection method, when a request signal for starting the inspection of the serial function of the sub-integrated board is input from the outside, the inspection start signal is output to the sub-integrated board fixed to the probe base. In response to the inspection start signal, inspection data as serial data serially output by the sub-integrated board is captured, and the captured inspection data is output to a gaming machine as an inspection jig. Then, the driving board provided in the gaming machine reads inspection data as parallel data obtained by converting serial data into parallel data. It is determined whether or not the read inspection data matches a predetermined determination value, and the determination result is output to the outside. In this way, even in gaming machines of different models, the gaming machine itself to which the sub-integrated board to be inspected is attached is used as an inspection jig, that is, by using the driving board provided in the gaming machine, an inspection jig is provided for each model. There is no need to create each one. Therefore, the inspection of the serial function of the sub-integrated board can be made common in gaming machines of different models.

(Solution 14)
An inspection program for causing a computer to execute each step in the inspection method according to Solution 13. This program may be recorded on a computer-readable storage medium (for example, a magneto-optical disk, hard disk, CD, FD, ROM, RAM, etc.) or read from another computer via a computer network. May be issued. If this program is executed by a computer, each step of the above-described inspection method is executed, so that the same effect as the above-described inspection method can be obtained.

  In the gaming machine of the present invention, a plurality of LEDs can be controlled even when the gradation of LEDs is controlled by serially output drive data using a fixed-time timer interrupt process, and the brightness of each LED is controlled. Gradation control can be performed to smoothly change.

Next, preferred embodiments of the present invention will be described with reference to the drawings. First, a pachinko machine will be described, and then an inspection system that is an embodiment of the present invention will be described. FIG. 1 is a front view showing the pachinko machine 1, FIG. 2 is a perspective view showing the pachinko machine 1 in a state where the main body frame and the front frame are opened, and FIG. 3 is a rear view showing the back side configuration of the pachinko machine 1. is there.
[1. Configuration of pachinko machine]

  As shown in FIGS. 1 and 2, the pachinko machine 1 includes an outer frame 2, a main body frame 3, a game board 4, a front frame 5, and the like. The outer frame 2 is formed in a vertically rectangular frame shape by upper, lower, left and right frame members, and has a lower plate 6 that receives the lower surface of the main body frame 3 at the lower front side of the outer frame 2. A main body frame 3 is attached to the front side of the outer frame 2 by a hinge mechanism 7 so as to be opened and closed forward. The main body frame 3 is formed by integrally molding the front frame body 8, the game board mounting frame 9, and the mechanism mounting frame 10 with a synthetic resin material. The front frame 8 formed on the front side of the main body frame 3 is formed in a rectangular frame shape having a size corresponding to the outer shape excluding the support plate 6 on the front side of the outer frame 2.

  A game board 4 is attached to the game board mounting frame 9 integrally formed at the rear part of the front frame body 8 so as to be detachable and replaceable from the front. A guide rail 11 having an outer rail and an inner rail is provided on the board surface (front surface) of the game board 4, and a game area 12 is defined inside the guide rail 11. A low-frequency speaker 14 is mounted via a speaker mounting plate 13 near one side of the front lower portion of the front frame 8 positioned below the game board mounting frame 9. A launch rail 15 that guides a game ball toward the launch path of the game board 4 is attached to the upper portion in the lower region of the front surface of the front frame 8 in an inclined manner. On the other hand, a lower front member 16 is attached to a lower portion in the lower area of the front surface of the front frame body 8. A lower pan 17 is provided substantially at the center of the front surface of the lower front member 16, and an operation handle 18 is provided closer to one side.

  A function of locking the main body frame 3 with respect to the outer frame 2 is provided on the rear surface of the main body frame 3 (front frame body 8) opposite to the side where the hinge mechanism 7 is provided. A locking device 19 having a function of locking the front frame 5 is attached. The locking device 19 includes a plurality of upper and lower body frame locking hooks 21 that are detachably engaged with a closing tool 20 provided on the outer frame 2 to lock the main body frame 3 in a closed state, and an open side of the front frame 5. It includes a plurality of upper and lower door locking hooks 23 that detachably engage with a closing tool 22 provided on the rear surface to lock the front frame 5 in a closed state. Then, the key is inserted into the key hole of the cylinder lock 24 and rotated in one direction, so that the engagement between the main body frame locking hook 21 and the closing tool 20 of the outer frame 2 is released, and the main body frame 3 is released. When the key is locked and the key is rotated in the opposite direction, the engagement between the door locking hook 23 and the closing tool 22 of the front frame 5 is released, and the front frame 5 is unlocked. ing. The front end of the cylinder lock 24 is exposed to the front surface of the lower front member 16 through the front frame body 8 and the lower front member 16 so that the unlocking operation can be performed by inserting a key from the front of the pachinko machine 1. Are arranged.

  A front frame 5 is attached to one side of the front surface of the main body frame 3 by a hinge mechanism 25 so as to be opened and closed forward. The front frame 5 includes a door main body frame 26, a side decoration device 27, an upper plate 28, and an acoustic illumination device 29. The door main body frame 26 is formed of a pressed metal frame member, and is formed to have a size that covers a portion extending from the upper end of the front frame body 8 to the upper edge of the lower front member 16. A substantially circular opening window 30 through which the game area 12 of the game board 4 can be seen through from the front is formed at substantially the center of the door body frame 26. Further, a window frame 31 having a rectangular frame shape larger than the opening window 30 is provided on the rear side of the door body frame 26, and a transparent plate 32 is attached to the window frame 31.

  On the front side of the door main body frame 26, around the opening window 30, side decoration devices 27 are mounted on the left and right sides, an upper plate 28 is mounted on the lower portion, and an acoustic decoration device 29 is mounted on the upper portion. The side decoration device 27 is mainly configured by a side decoration body 33 in which a lamp substrate is disposed and formed of a synthetic resin material. A plurality of slit-like opening holes that are long in the horizontal direction are arranged in the side decoration body 33 in the vertical direction, and a lens 34 corresponding to a light source disposed on the lamp substrate is incorporated in the opening hole. The acoustic illumination device 29 includes a transparent cover body 35, a speaker 36, a speaker cover 37, a reflector body (not shown), and the like, and these constituent members are assembled together to form a unit.

  Next, the rear surface configuration of the main body frame 3 will be described. As shown in FIG. 3, a ball tank for storing game balls supplied from a ball lifting device installed on the game island is provided on the upper rear surface side of the main body frame 3. 140, a tank rail 141 that connects the ball tank 140 and the payout device 109 and allows the game balls stored in the ball tank to flow down are arranged. The payout device 109 connected to the ball tank 140 by the tank rail 141 is formed in a unit shape, and a predetermined number of game balls are received based on a signal for accepting a game ball from the tank rail 141 and instructing the payout of the game ball. Pay out.

  Below the tank rail 141, there is provided a substrate protective cover 142 in which various substrates such as the lamp control substrate 112 and the liquid crystal control substrate 113 are incorporated. The substrate protection cover 142 plays a role of preventing these substrates from being damaged by a sphere dropped from the tank rail 141 and preventing illegal acts on each substrate. Further, the board protection cover 142 projects to the back side of the pachinko machine 1, and the main control board 101 is disposed below the board protection cover 142. Further, a sub-integrated board 111 and a waveform control board 114 are disposed on the back side of the game board 4 of the main control board 101. As described above, the upper side of the main control board 101 is covered with the board protection cover 142 protruding to the back side of the pachinko machine 1, so that the main control board 101 is prevented from being damaged by the sphere dropped from the tank rail 141. ing. Thereby, the sub-integrated board 111 and the waveform control board 114 arranged on the back side of the game board 4 of the main control board 101 are also not damaged by the spheres dropped from the tank rail 141.

A launching device 135 is attached to the lower side of the back surface of the main body frame 3. This launching device 135 is configured by integrating a launching hammer that launches a sphere sent to the launching rail 15 and a launching motor that imparts a reciprocating rotation to the launching hammer, and is associated with the operation handle 18. ing. In addition, a payout control board 102 is provided on the right side of the launching device 135. The payout control board 102 drives and controls the payout device 109 based on the reception of a signal instructing payout of game balls from the main control board 101.
[2. Components of the game board]

  Next, various components provided in the game area 12 partitioned on the game board 4 will be described. FIG. 4 is a front view showing the game board 4.

  An effect device 40 is disposed in the central portion of the game area 12. The stage device 40 includes a special symbol display 41 that variably displays a special symbol by lighting of a plurality of light emitters (for example, four LEDs), and a plurality of types of three symbols including left, middle, and right symbols. Predetermined conditions are met by the lighting of a liquid crystal display 116 (denoted only by reference numerals in FIG. 5) and a plurality of light emitters (for example, four LEDs) that display decorative designs in a variable manner and display various effects in the display area 42. A special symbol memory lamp 54 for displaying the number of memories (starting memory number) that has been established (the game ball has won a prize at the start winning opening 45 and the electric start winning opening 46), but the variation of the special symbol has not yet started, and a special symbol And a front decorative plate 43 for attaching the display 41, the liquid crystal display 116 and the special figure memory lamp 54 to the surface of the game board 4 (game area 12). Further, effect lamps 44 a to 44 d are respectively attached to the left part, the upper part, and the right part of the effect device 40. These effect lamps 44 a to 44 d perform lighting display in accordance with the effect display by the display area 42. Further, gradation lamps 49a and 49b whose luminance is adjusted (gradation control is performed) are attached to the lower part of the effect device 40 (lower part of the display area 42).

  Below the stage device 40, there are provided a start winning opening 45 and an electric start winning opening 46 having a pair of opening and closing blades 47 below the starting winning opening 45. When the display result of the normal symbol display 50 is “winning”, the opening / closing blade 47 has a predetermined time (for example, 0.5 seconds in normal state (hereinafter referred to as “s”), In the probability fluctuation state, control is performed so that it is released for 3 s). It should be noted that a game ball from above can be won in the start winning opening 45, and the upper side is blocked by the start winning opening 45 in the electric start winning opening 46, and a game ball cannot be won if the open / close wing 47 is closed. It is in a state. For this reason, when the open / close wing 47 is in the open state, the game ball can be won.

  In addition, the game balls won in the start winning opening 45 and the electric start winning opening 46 are detected by a start opening sensor 55 (only the reference numeral is shown in FIG. 5), and based on this detection (predetermined condition is established), a special symbol display In 41, a special symbol variation display (decorative symbol variation display in the display area 42) is permitted. When the game ball is won at the start winning port 45 and the electric start winning port 46 and the game ball is detected by the start port sensor 55, the display result of the special symbol on the special symbol display 41 is hit (specific display mode). The jackpot determination random number for determining whether or not Further, the jackpot determination random number extracted based on the fact that the game ball has won the start winning opening 45 or the electric start winning opening 46 and has been detected by the start opening sensor 55 during the change of the special symbol is a predetermined number (for example, 4), and the stored number (starting stored number) is displayed by lighting a special-purpose memory lamp 54 composed of a plurality of light emitters (for example, four LEDs). The special symbol memory lamp 54 is disposed at substantially the same position as the special symbol display 41.

  On the left side of the game area 12, a normal symbol display 50 is provided for variably displaying normal symbols by lighting and blinking of light emitters (for example, LEDs). Also, a probability variation state lamp 51 that is turned on or off (in this embodiment, lighted in the probability variation state) is attached below the normal symbol display 50 depending on whether or not the gaming state is a probability variation state. Yes. Also, below the normal symbol display 50, a left gate having a gate sensor 53a and a right gate having a gate sensor 53b are provided. When the game ball is detected by the gate sensor 53a or the gate sensor 53b based on the passing of the game ball through the left gate or the right gate, the normal symbol display on the normal symbol display 50 is started. That is, the normal symbol display on the normal symbol display 50 is permitted in accordance with the detection of the game ball by the gate sensor 53a and the gate sensor 53b. When a game ball is detected by the gate sensor 53a and the gate sensor 53b, a normal random number for determining whether or not to win the normal symbol display result on the normal symbol display 50 is extracted. Further, the normal random number per normal symbol extracted based on the fact that the game ball passes through the left gate or the right gate and is detected by the gate sensors 53a and 53b during the variation of the normal symbol is a predetermined number (for example, four). ), And the stored number is displayed by turning on a general memory lamp 56 composed of a plurality of light emitters (for example, four LEDs). The general memory lamp 56 is arranged on the left side of the game area 12.

Below the electric start winning opening 46, a large winning opening device 60 having an open / close plate 62 for opening and closing a horizontally long rectangular winning opening 61 is disposed. The special prize opening device 60 includes a solenoid 63 that serves as a drive source for opening and closing the special prize opening 61 (opening / closing plate 62), and a count sensor 64 (both only the reference numerals are shown in FIG. 5). At the bottom of the game area 12 below the big prize opening device 60, there is provided an out port 48 through which the game balls that have flown down the game area 12 and have not won any prize winning devices or winning devices are taken in. Yes. Four winning ports 66 a to 66 d are provided on the left and right sides of the starting winning port 45, the electric starting winning port 46 and the large winning port device 60.
[3. Main board and peripheral board]

Next, the main substrate 100 and the peripheral substrate 110 provided on the back side of the pachinko machine 1 will be described. FIG. 5 is a block diagram showing the main board 100 and the peripheral board 110, and FIG. 6 is a block diagram of the lamp driving board 112.
[3-1. Main board]

The main board 100 includes a main control board 101 and a payout control board 102 as shown in FIG.
[3-1-1. Main control board]

As shown in FIG. 5, the main control board 101 is configured around a CPU 101 a and includes a ROM 101 b that stores various processing programs and various commands, and a RAM 101 c that temporarily stores data. Detection signals from the gate sensors 53a and 53b, the start port sensor 55, and the count sensor 64 are input to the main control board 101, respectively. On the other hand, the main control board 101 outputs drive signals to the solenoid 63, the special symbol display 41, the normal symbol display 50, the special symbol storage lamp 54, and the general symbol storage lamp 56 based on these detection signals. ing. In addition, various commands are serially output between the main control board 101 and the payout control board 102, and from the main control board 101 to the sub integrated board 111 between the main control board 101 and the sub integrated board 111. Various commands are output in parallel.
[3-1-2. Dispensing control board]

As shown in FIG. 5, the payout control board 102 includes a CPU 102a, a ROM 102b, and a RAM 102c. The payout control board 102 controls the payout apparatus 103 based on various commands serially output from the main control board 101. For example, when the payout control board 102 receives a command for driving the payout apparatus 103 (payout motor) output serially from the main control board 101, the payout control board 102 outputs a drive signal to the payout apparatus 103 (discharge motor) based on the command. . As a result, the payout device 103 pays out a winning ball or a rental ball.
[3-2. Peripheral board]

As shown in FIG. 5, the peripheral board 110 includes a sub-integrated board 111, a lamp driving board 112, a liquid crystal control board 113, and a waveform control board 114.
[3-2-1. Sub-integrated board]

  When the sub integrated board 111 receives a command from the main control board 101 described above, the sub integrated board 111 further adds information to the received command to create a command related to the effect. Then, the created command is output to the liquid crystal control board 113 and the waveform control board 114 described above. For this reason, the command output from the main control board 101 requires minimal information (for example, big hit, miss, short time, etc.). Further, when the sub integrated board 111 receives a command from the main control board 101, the sub integrated board 111 further creates a command for performing a rich variation based on the received command. That is, it is not necessary for the main control board 101 to directly create a command for performing a variety of effects, and the processing load is reduced. On the other hand, the sub integrated substrate 111 performs integrated control of the peripheral substrates 110 such as the liquid crystal control substrate 113 and the waveform control substrate 114 by outputting the created commands to the liquid crystal control substrate 113 and the waveform control substrate 114, respectively. In this way, the sub-integrated board 111 is separated from the main control board 101 in order to reduce the processing of the main control board 101 and to integrally control the peripheral board 110 such as the liquid crystal control board 113 and the waveform control board 114. Is provided.

  As shown in FIG. 5, the sub integrated substrate 111 includes a CPU 111a, a ROM 111b, and a RAM 111c. The CPU 111a is a 16-bit microprocessor, and is driven at 16 megahertz (MHz) as its control clock. As shown in FIG. 6, this microprocessor includes an arithmetic processing unit 111ac that performs various arithmetic processing, an output port 111aop that outputs various signals to the outside, a serial transmission unit 111at that serially outputs data to the outside, and the like. It is connected. In addition, an input port (not shown) to which various commands from the main control board 101 and various signals from the liquid crystal control board 113 are input is circuit-connected.

Note that the input / output terminal of the microprocessor functions as a parallel output port or parallel input port (parallel I / O), and also functions as a serial input / output (serial I / O). The function of this input / output terminal can be switched to parallel I / O or serial I / O by setting values in various registers built in the microprocessor. For example, an output terminal that functions as a parallel output port can function as a serial output terminal that outputs serial data or a transfer clock output terminal that outputs a transfer clock by setting a value in the built-in transmission / reception mode register. The function of the output terminal can be switched.
[3-2-1 (a). Arithmetic processing unit]

As shown in FIG. 6, the arithmetic processing unit 111ac creates and sets data (a latch signal LAT and a switching signal MODE, which will be described later) to be output to the output port 111aop in addition to various arithmetic processes, and sets the serial transmission unit 111at. The data to be serially output (drive data DAT described later) is created and set. The arithmetic processing unit 111ac sets or reads signals representing various states of the output port 111aop and the serial transmission unit 111at.
[3-2-1 (b). Serial transmission part]

As shown in FIG. 6, the serial transmission unit 111at serially outputs the data received from the arithmetic processing unit 111ac as drive data DAT to the lamp drive substrate 112 in synchronization with the transfer clock CLK. The drive data DAT includes effect lamp ON / OFF data for turning on (turning on) the effect lamps 44a to 44d, gradation data for gradation of gradation lamps 49a and 49b, and gradation lamps 49a and 49b. ON / OFF data for gradation lamps that are ON (lighted). In the present embodiment, the drive data DAT is updated every fixed time timer interruption processing time of 2 milliseconds (ms). The drive data is serially output from the serial transmission unit 111at to the lamp drive substrate 112 in synchronization with the transfer clock CLK within the fixed time timer interrupt processing time. The speed of the transfer clock CLK is set to 250 kilohertz (kHz), one period is 4 microseconds (μs), the pulse width is 2 μs, and the data width of the drive data DAT is 2 μs, which is the same as the pulse width.
[3-2-1 (c). Output port]

  As shown in FIG. 6, the output port 111aop outputs a latch signal LAT to shift registers 112h and 112i and a gradation control IC 112g mounted on the lamp driving substrate 112 described later. Specifically, the output port 111aop outputs the latch signal LAT when the shift registers 112h and 112i take in the effect lamp ON / OFF data, and the gradation control IC 112g outputs the gradation data or gradation lamp ON / OFF. The latch signal LAT is output when any of the OFF data is taken.

When the latch signal LAT is input, the shift registers 112h and 112i output drive signals to the effect lamps 44a to 44d, while the gradation control IC 112g receives drive signals to the gradation lamps 49a and 49b. Is output. The output port 111aop outputs a switching signal MODE for the gradation control IC 112g to take in either gradation data or gradation lamp ON / OFF data.
[3-2-2. Lamp drive board]

As shown in FIG. 6, the lamp driving board 112 includes shift registers 112 h and 112 i that capture ON / OFF data for effect lamps among the driving data DAT serially output from the sub-integrated board 111, gradation data, and gradation. And a gradation control IC 112g for taking in the lamp ON / OFF data. The shift registers 112h and 112i and the gradation control IC 112g are connected in a daisy chain, that is, in a daisy chain. Gradation data and gradation lamp ON / OFF data serially output from the sub-integrated board 111 are transferred to the shift register 112h. , 112i to the gradation control IC 112g.
[3-2-2 (a). Shift register]

As shown in FIG. 6, the shift registers 112 h and 112 i take in the effect lamp ON / OFF data from the drive data DAT serially output from the sub-integrated board 111. Then, when the latch signal LAT output from the sub-integrated board 111 is input, the latch signal LAT is used as a trigger to convert the serial data that is the ON / OFF data for the effect lamps taken into parallel data, and the parallel signal is converted into parallel data. It outputs to each of the effect lamps 44a to 44d as drive signals. The effect lamps 44a to 44d are turned on in response to this drive signal.
[3-2-2 (b). Gradation control IC]

  As described above, the CPU 111a of the sub-integrated board 111 performs various processes within each interrupt time for each reference period of 16 ms display and every 2 ms constant time timer interrupt processing time. In order to perform gradation control of LEDs whose brightness changes smoothly within the 2ms fixed time timer interrupt processing time, the number of LED, the stage (gradation degree) and the transfer clock are restricted (restricted). It was.

  Therefore, the gradation control IC 112g that performs gradation control of the gradation lamps (LEDs) 49a and 49b is used. Examples of the gradation control IC 112g include TLC5922 manufactured by Texas Instruments (TI). This TLC5922 has 16 channels of output. In addition to individual ON / OFF control, each output channel can flow a constant current with 1% accuracy that can be programmed in the range of 0 to 80 milliamperes (mA) for each channel. The output current can be set. By inputting 7-bit correction data (gradation data) from the external processor to the dot correction register for each channel, the channel current value can be set in 128 steps with respect to the maximum value. Thereby, the gradation control of the LED can be performed by correcting the luminance of the LED connected to the output channel.

  When LED gradation control is performed with the TLC5922, in addition to 16 channels x 7 bits of gradation data (112 bits), ON / OFF data for each channel (16 bits), a total of 128 bits of serial data (drive data) ) Must be output. The time required to finish serially outputting the 128-bit drive data is 512 μs (= 128 bits × 4 μs) when the transfer clock is set to 250 kHz. That is, the serial output of drive data can be completed in about one-fourth of the fixed-time timer interrupt processing time (2 ms (= 2000 μs)) of the sub-integrated substrate 111. In this way, when performing gradation control of the LED brightness in 128 steps using the gradation control IC (TLC 5922), all the drive data having a large information amount of 128 bits is serialized within the fixed-time timer interrupt processing time. Although it is necessary to output, since serial output is completed in about one quarter of this fixed time timer interrupt processing time, within the remaining time, that is, about three quarters of the fixed time timer interrupt processing time, Various other processes such as the process of controlling the stepping motor that operates the movable body described above can be sufficiently performed.

  In addition, since one cycle is 4 microseconds (μs) at the transfer clock of 250 kHz, the pulse width is 2 μs, and the data width of the drive data synchronized with the transfer clock is also 2 μs. Here, it has been experimentally obtained that the noise width falls within about 1 μs. That is, by setting the transfer clock to 250 kHz, the data width (2 μs) of the drive data does not approach the noise width (about 1 μs). Therefore, the drive data can be serially output to the gradation control IC (TLC 5922) with a transfer clock that is not easily affected by noise.

  As shown in FIG. 6, the gradation control IC (TLC 5922) 112g includes drive data DAT serially output from the sub-integrated board 111 based on the switching signal MODE and the latch signal LAT output from the sub-integrated board 111. Gradation data and gradation lamp ON / OFF data are respectively fetched. Specifically, when the switching signal MODE is input, the gradation control IC 112g captures gradation data into a built-in dot correction register (not shown). Then, when the latch signal LAT is input, the current is set so that the output current according to the fetched gradation data is obtained with the latch signal LAT as a trigger (this maximum output current is the gradation control IC). (It is set by a resistor (not shown) externally attached). Subsequently, when the switching signal MODE is no longer input, the gradation lamp ON / OFF data is taken into a built-in ON / OFF shift register (not shown). When the latch signal LAT is input again, the latch signal LAT is used as a trigger to convert the serial data, which is the gradation lamp ON / OFF data, into parallel data, and the parallel signal is set as the drive signal. The current is output to the gradation lamps 49a and 49b, respectively. The gradation lamps 49a and 49b are respectively lit with a luminance corresponding to the drive signal and output current.

  The gradation lamps 49a and 49b are each composed of four LEDs. As shown in FIG. 6, the gradation control IC 112g provides four gradation lamps 49a, four gradation lamps 49b, A total of eight drive signals are output at the set currents. Since these eight LEDs are respectively lit at a luminance corresponding to the drive signal and output current, the luminance of the gradation lamps 49a and 49b can be varied exponentially, and a fine effect can be performed.

  As described above, the gradation control IC 112g takes in gradation data in response to the input latch signal LAT. Similarly, the shift registers 112h and 112i output drive signals to the effect lamps 44a to 44d in response to the latch signal LAT. Therefore, when the gradation control IC 112g captures gradation data, the effect lamp ON / OFF data is serially output from the sub-integrated board 111 to the shift registers 112h and 112i following the gradation data. Thereby, even if the latch signal LAT is input, the effect lamps 44a to 44d are turned on based on the ON / OFF data for effect lamps, and the gradation control IC 112g can take in gradation data.

  On the other hand, when the gradation control IC 112g captures the gradation lamp ON / OFF data, the gradation registers ON / OFF data is captured by the shift registers 112h and 112i when the gradation control IC 112g captures the gradation data. The same effect lamp ON / OFF data as the effect lamp ON / OFF data is serially output from the sub-integrated board 111 again. As a result, with the latch signal LAT as a trigger, the gradation control IC 112g converts the serial data that is the acquired gradation lamp ON / OFF data into parallel data, and outputs a drive signal to the gradation lamps 49a and 49b. On the other hand, the shift registers 112h and 112i convert the serial data that is the ON / OFF data for the effect lamps taken into parallel data, and output drive signals to the effect lamps 44a to 44d.

As described above, the effect lamp ON / OFF data is serially output following the gradation data or following the gradation lamp ON / OFF data. That is, each time the effect lamp ON / OFF data is serially output. Therefore, the ON information is updated (overwritten) every time in the shift registers 112h and 112i. Such a serial output method for effect lamp ON / OFF data is performed in order to prevent the shift registers 112h and 112i from malfunctioning due to the influence of noise or the like.
[3-2-2 (c). Arrangement relationship between shift register and gradation control IC]

  When the shift register and gradation control IC (TLC 5922) is mounted on the lamp driving substrate 112, particularly when daisy chain connection is made, (1) the shift register is arranged at the first stage, and the gradation control IC is arranged at the last stage, (2) For example, a gradation control IC is arranged in the first stage, and a shift register is arranged in the last stage. In an inspection system 200 (inspection process) to be described later, a lamp driving substrate 112 provided in the pachinko machine 1 as an inspection jig is used. Then, the inspection data is serially output to the lamp driving substrate 112 in order to inspect the function of the serial transmission unit 111at built in the CPU 111a of the sub-integrated substrate 111 described above.

  However, as described above, the gradation control IC (TLC 5922) has a total of 128 bits of ON / OFF data (16 bits) for each channel in addition to gradation data (112 bits) for 16 channels × 7 bits. Need to capture serial data. At this time, the sub-integrated substrate 111 needs to perform switching control as to whether the gradation control IC captures gradation data or ON / OFF data, and the drive data is serially output to the gradation control IC. Not easy. Further, since the data length is as large as 128 bits, the inspection time becomes long in the inspection process.

  Therefore, the lamp driving substrate 112 has the above-described configuration (1), that is, a configuration in which the shift register is arranged in the first stage and the gradation control IC is arranged in the last stage (in this embodiment, as shown in FIG. 6). The shift register 112h is arranged in the first stage, and the gradation control IC 112g is arranged in the last stage, and they are daisy chained from the first stage to the last stage). Since the drive data fetched by the shift register is composed only of ON / OFF data, the shift register can output the drive data itself serially output from the sub-integrated board as a drive signal. On the other hand, since the drive data captured by the gradation control IC is composed of gradation data and ON / OFF data, the gradation control IC outputs the drive data itself serially output from the sub-integrated board as a drive signal. (In the gradation control IC, as described above, 16-channel output is provided for a total of 128-bit drive data).

If the shift register is arranged in the first stage and the gradation control IC is arranged in the last stage, for example, in the inspection process, the inspection data (serial port built in the microprocessor) is only in the first stage shift register. By serially outputting (ON / OFF data), the serial function of the microprocessor can be inspected based on the drive signal output from the first-stage shift register. Here, 74HC595 is mentioned as a shift register. Since this 74HC595 is an 8-bit (1 byte) shift register, the inspection data is only 1 byte, and the inspection time in the inspection process is about 1/16 of that of the gradation control IC (TLC 5922), which is shortened. .
[3-2-3. LCD control board]

As shown in FIG. 5, the liquid crystal control board 113 includes a CPU 113a, a ROM 113b, a RAM 113c, and a VDP (abbreviation for video display processor) (not shown). The liquid crystal control board 113 performs display control of the liquid crystal display 116 based on various commands output from the sub integrated board 111.
[3-2-4. Waveform control board]

As shown in FIG. 5, the waveform control board 114 includes a ROM 114b and a RAM 114c for storing voice and performance data, and a sound source IC (not shown). The waveform control board 114 controls the sound wave device 115 based on various commands output from the sub-integrated board 111. For example, control is performed to output sound effects from the sound wave device 115 in accordance with various effects displayed in the display area 42.
[4. Inspection system]

  As described above, the sub-integrated board 111 serially transmits drive data DAT from the sub-integrated board 111 to the lamp driving board 112 when lighting the production lamps 44a to 44d and when controlling the gradation lamps 49a and 49b. Output. The drive data DAT is taken into the shift registers 112h and 112i and the gradation control IC (TLC 5922) 112g mounted on the lamp drive substrate 112, and the shift registers 112h and 112i drive the drive signals (lights on) to the effect lamps 44a to 44d. On the other hand, the gradation control IC 112g outputs a driving signal (gradation driving signal) to the gradation lamps 49a and 49b.

  Thus, when performing lighting control and gradation control of a plurality of LEDs (effect lamps 44a to 44d and gradation lamps 49a and 49b), a serial function (serial) in the CPU 111a as a microprocessor mounted on the sub-integrated board 111 is used. Port) is required to operate normally.

  However, if a malfunction occurs in this serial function, as described above, the drive data cannot be serially output to the shift registers 112h and 112i and the gradation control IC (TLC 5922) 112g mounted on the lamp drive substrate 112. A drive signal cannot be output to the LED. The production line of the sub integrated substrate 111 has an inspection process for inspecting the sub integrated substrate 111. In this inspection process, the serial function of the microprocessor is also inspected.

  When inspecting the sub-integrated substrate 111, it is necessary to manufacture inspection jigs for inspecting various signals. For this reason, as the product life cycle is shortened, inspection jigs will be manufactured one after another along with product development. In addition, since many prototypes are made before the pachinko machine 1 (game machine) of the present embodiment is commercialized, the inspection jig for the prototype inspection is also changed in accordance with the design change of the sub-integrated board 111. (This inspection jig for prototype inspection will be used later in the inspection process).

  Therefore, when the serial function of the microprocessor mounted on the sub-integrated board 111 is inspected, the pachinko machine 1 (game machine) is used as an inspection jig, and the lamp driving board 112 attached to the pachinko machine 1 (game machine). Use the function of. Here, “the function of the lamp driving substrate 112” means that the serial data captured by the shift registers 112h and 112i and the gradation control IC (TLC5922) 112g is converted into parallel data using the input latch signal as a trigger. A parallel signal (drive signal) is output.

  Since both the sub-integrated board 111 and the lamp driving board 112 are boards that are attached to the pachinko machine 1 (game machine), the sub-integrated board 111 and the lamp driving board are used by using the lamp driving board 112 as an inspection jig. A harness for connecting a control signal or the like between the substrate 112 and the substrate can also be used for the inspection process.

  In addition, with the shortening of the product life cycle, the products flowing on the production line may change during the day. For example, this is a case where A product flows into the production line in the morning and B product flows into the production line from the afternoon of that day. At this time, when changing the jig or the like used for each product, if the setup is poor, the production line is stopped, the operation rate of the production line is lowered, and the production target of the day may not be achieved.

  Next, in the production line of the sub-integrated substrate 111, the inspection process of the sub-integrated substrate 111, particularly the inspection of the serial function of the CPU 111a as a microprocessor mounted on the sub-integrated substrate 111 will be described based on the drawings. FIG. 7 is an explanatory diagram illustrating a schematic configuration of an inspection system 200 that performs serial function inspection in an inspection process.

The inspection system 200 of this embodiment includes an inspection integrated personal computer 210 (hereinafter referred to as inspection integrated PC 210) that transmits various inspection request signals and displays various inspection results on the monitor 220, and various inspection requests from the inspection integrated PC 210. The interface device 230 that performs an inspection in accordance with a signal, a probe base 250 on which a substrate to be inspected is mounted, and a pachinko machine 1 as an inspection jig provided with a lamp driving substrate 112. The interface device 230 is connected to the interface device 230 by the interface device side cable 212, and the interface device 230 is connected to the probe table 250 by the probe table side cable 236. Further, a jig input side cable 238 for transmitting a signal to the lamp driving board 112 and a jig output side cable 240 for transmitting a signal from the lamp driving board 112 are connected to the interface device 230. The jig input side cable 238 uses a harness that connects between the sub integrated substrate 111 and the lamp driving substrate 112 attached to the pachinko machine 1 of the present embodiment. The pachinko machine 1 is connected to an AC power source (not shown) (24 volts (V)), and generates a common voltage (for example, 12 V) by the power supply board of the pachinko machine 1 to interface with the jig input side cable 238. This is supplied to the device 230 and the probe base 250.
[4-1. Inspection integrated PC]

The inspection integrated PC 210 includes an input device (not shown) such as a keyboard and a mouse. When an input request for starting various inspection tests is input to the input device, a request signal for the selected inspection test is output to the interface device 230. To do. Then, the inspection integration PC 210 displays the inspection result from the interface device 230 on the display screen of the monitor 220. On the display screen of the monitor 220, an OK image 222 is displayed on the upper side of the screen if the inspection result is good, and an NG image 224 is displayed on the lower side of the screen if the inspection result is not good.
[4-2. Interface device]

The interface device 230 includes a CPU 230a serving as a central processing unit, a ROM 230b that stores various control programs and various data, and a RAM 230c that temporarily stores calculation results and the like. A corresponding inspection start signal is output to the probe base 250. Further, an inspection is performed based on various inspection data read from the probe base 250 or the lamp driving substrate 112, and the inspection result is output to the inspection integrated PC 210. As described above, the interface device 230 is supplied with the common voltage from the pachinko machine 1, generates a control voltage (for example, 5V) by reducing the supply voltage, and supplies the control voltage to the CPU 230a and the like.
[4-3. Probe stand]

The probe base 250 includes a handle 252 for fixing the sub-integrated substrate 111 to be inspected, and a probe for transmitting various signals and various inspection data between the sub-integrated substrate 111 and the interface device 230. Although not shown, a plurality of probes are provided according to the specifications of the sub-integrated substrate 111 so as to contact a predetermined part of the sub-integrated substrate 111. Here, when the start signal of various inspection programs output from the interface device 230 is transmitted via the probe, the sub integrated substrate 111 transmits an inspection program corresponding to the start signal from the ROM 111b mounted on the sub integrated substrate 111. Read and start. Then, according to this inspection program, various inspection data and various signals are output to the interface device 230 via the probe. As described above, the probe base 250 is supplied with a common voltage from the pachinko machine 1 and supplies it to the sub-integrated substrate 111 via the probe. The sub-integrated board 111 generates a control voltage (for example, 5V) by stepping down the common voltage and supplies it to the CPU 111a as a microprocessor.
[4-4. Jig lamp drive board]

  The lamp driving substrate 112 is attached to the pachinko machine 1, and a part of its function is used in this embodiment. As described above, the lamp drive substrate 112 sets the shift registers 112h and 112i that output the input serial data as parallel signals, and the maximum output current of the parallel signal to be output based on the input serial data. Gradation control IC (TLC 5922) 112g. In the shift register 112h, serial I / O check inspection data DAT synchronized with the transfer clock signal CLK from the sub-integrated board 111 attached to the probe base 250 and the latch signal LAT are connected via the interface device 230. Each is entered. Then, the acquired serial I / O check inspection data is converted into parallel data in response to the input latch signal LAT and output to the interface device 230.

  In this way, in the inspection system 200 (inspection process), the pachinko machine 1 (game machine) is used as an inspection jig, and therefore, even with a different type of game machine, the sub-integrated board 111 and the lamp driving board 112 that are attached to the model. By using, there is no need to manufacture each inspection jig for each model.

Further, as described above, in the inspection system 200 (inspection process), the pachinko machine 1 (game machine) serving as the inspection reference machine is used as an inspection jig, and the sub-integrated substrate 111 flowing in the production line is attached to the inspection reference machine. The function of the lamp driving substrate 112 is used. For this reason, even if the product (game machine) to be produced changes, it is only necessary to replace the inspection reference machine, that is, no special setting is required, and the serial function of the microprocessor mounted on the sub-integrated board 111 can be achieved. Can be inspected. As a result, setup is facilitated and it is possible to respond quickly even if the product flowing on the production line changes. Further, if there is a process in which a problem occurs in the setup, people and time can be concentrated in the process, and the production line can be operated quickly. Therefore, it leads to the achievement of the production target.
[5. Parallel I / O and serial I / O check]

Next, the operation of the inspection system 200 according to the present embodiment will be described in the case where an operator checks the parallel I / O and serial I / O of the sub-integrated board 111. FIG. 8 is an explanatory diagram showing inspection of the sub-integrated substrate 111.
[5-1. Parallel I / O check]

  As shown in FIG. 8, the inspection integrated PC 210 transmits a parallel I / O check request signal in response to an operator's keyboard or mouse operation in a state where the sub integrated substrate 111 to be inspected is attached to the probe base 250. 230 (step S100). This parallel I / O check is performed to check whether or not the circuit of the sub-integrated substrate 111 is disconnected or short-circuited. The CPU 230a of the interface device 230, to which this request signal has been input, outputs a parallel I / O check program start signal to the probe base 250 (step S105). Then, the probe base 250 transmits a start signal for the parallel I / O check program to the CPU 111a of the sub-integrated board 111 via the probe described above. The CPU 111a to which the start signal is input reads the parallel I / O check program from the ROM 111b of the sub integrated board 111.

When the parallel I / O check program is started, the CPU 111a as the microprocessor sets a value in a built-in direction register so that the input / output terminal functions as a parallel I / O port. Here, a value is set in the direction register so that the parallel I / O port becomes a parallel output port. Then, parallel I / O check inspection data is set in the built-in port register, and parallel I / O check inspection data (parallel data) is output from the parallel output port to the interface device 230 via the probe (step). S110). The CPU 230a of the interface device 230 reads the parallel I / O check inspection data. Then, the collation data for parallel I / O check is read from the ROM 230b, it is determined whether or not it matches the inspection data for parallel I / O check, and the determination result of the parallel I / O check is output to the inspection integrated PC 210. (Step S115). Then, the inspection integrated PC 210 displays the determination result on the monitor 220. When the parallel I / O check verification data does not match the parallel I / O check inspection data, that is, when the circuit of the sub-integrated substrate 111 is disconnected or short-circuited, NG is displayed on the display screen of the monitor 220. An image 224 is displayed and the examination is terminated.
[5-2. Serial I / O check]

  On the other hand, when the parallel I / O check verification data matches the parallel I / O check inspection data, that is, when the circuit of the sub-integrated board 111 is not disconnected or short-circuited, the display screen of the monitor 220 is displayed. An OK image 222 is displayed. Then, a request signal for serial I / O check is output to the interface device 230 (step S120). This serial I / O check is to check whether or not there is a malfunction in the serial function of the sub-integrated board 111. The CPU 230a of the interface device 230, to which this request signal has been input, outputs a serial I / O check program start signal to the probe base 250 (step S125). Then, the probe base 250 transmits a start signal for the serial I / O check program to the CPU 111a of the sub-integrated board 111 via the probe. The CPU 111a to which this start signal is input reads the serial I / O check program from the ROM 111b. As described above, in some CPUs 111a, the input / output terminal functions as a parallel I / O and also functions as a serial I / O.

  When the serial I / O check program is started, the CPU 111a sets a value in a built-in transmission / reception mode register in order to switch the function of the input / output terminal from the parallel I / O port to the serial I / O port. Here, a value is set in the transmission / reception mode register so that the serial I / O port becomes a serial output port. Then, inspection data for serial I / O check is set in the built-in transmission buffer register, and this serial I / O check inspection data is transferred from the transmission buffer register to the built-in transmission register. The transferred serial I / O check inspection data (serial data) DAT is output to the interface device 230 bit by bit from the serial output port via the probe in synchronization with the transfer clock CLK. When this output is completed, the latch signal LAT is output from the parallel output port to the interface device 230 via the probe (step S130).

  The CPU 230a of the interface device 230, to which the serial I / O check inspection data DAT, the transfer clock CLK, and the latch signal LAT are input, synchronizes the serial I / O check inspection data DAT with the transfer clock CLK bit by bit. When this output is finished, the latch signal LAT is continuously output to the lamp drive substrate 112. Then, the lamp driving substrate 112 captures the serial I / O check inspection data DAT bit by bit in synchronization with the transfer clock CLK, and uses the input latch signal LAT as a trigger to convert the captured serial data into parallel data. The data is converted and output to the interface device 230. The CPU 230a of the interface device 230 reads the serial I / O check inspection data converted into the parallel data. Then, the serial I / O check verification data is read from the ROM 230b, it is determined whether or not it matches the serial I / O check inspection data, and the determination result of the serial I / O check is output to the inspection integrated PC 210. (Step S135). Then, the inspection integrated PC 210 displays the determination result on the monitor 220. When the serial I / O check verification data and the serial I / O check inspection data converted into parallel data do not match, that is, when a malfunction occurs in the serial function of the sub-integrated board 111, the monitor 220 The NG image 224 is displayed on the display screen, and this inspection is finished. On the other hand, when the verification data for serial I / O check matches the inspection data for serial I / O check as parallel data, that is, the serial function of the sub-integrated board 111 is not defective (normal). In some cases, an OK image 222 is displayed on the display screen of the monitor 220, and this inspection is terminated.

  Thus, when the shift registers 112h and 112i and the gradation control IC 112g are mounted on the lamp driving substrate 112, the lamp driving substrate 112 attached to the pachinko machine 1 as an inspection jig is used in the inspection system 200 (inspection process). In view of this, it is preferable to arrange the shift register 112h in the first stage and the gradation control IC 112g in the last stage as in this embodiment. In this case, the inspection of the serial function of the CPU 111a as the microprocessor mounted on the sub-integrated board 111 is simply controlled (the shift registers 112h and 112i are 74HC595 as described above, and are stored in 8 bits (1 byte). Because of the capacity, the inspection data is only one byte, and there is no need to perform switching control between the gradation data and gradation lamp ON / OFF data unlike the gradation control IC (TLC5922). Can be done in a short time.

  In addition, by adopting a configuration in which the shift register 112h is arranged in the first stage and the gradation control IC 112g is arranged in the last stage, for example, even in a lamp driving board of a different model composed of only a plurality of shift registers connected in a daisy chain, that is, in the first stage. If the shift register is configured, when testing the serial function of the microprocessor mounted on the sub-integrated board, the test of the serial function can be easily performed by outputting the test data serially only to the first-stage shift register. Control can be performed. Therefore, an inspection program for inspecting the serial function of the microprocessor mounted on the sub-integrated board can be diverted as long as the shift register is arranged in the first stage even with different types of lamp driving boards.

  Here, in the case where the gradation control IC is arranged in the first stage, as described above, it is necessary for the gradation control IC to output the switching signal MODE for taking in either gradation data or inspection data. Compared with the case where the shift register is arranged in the first stage, it takes time and effort.

  According to this inspection system 200, when the sub integrated board 111 provided in the pachinko machine 1 is produced, when the serial function of the sub integrated board 111 is inspected, the pachinko machine 1 provided with the lamp driving board 112 is used as an inspection jig. Use. The inspection system 200 includes an interface device 230, and the CPU 230a of the interface device 230 starts inspection on the sub-integrated substrate 111 when a request signal for starting inspection of the serial function of the sub-integrated substrate 111 is input from the outside. Output a signal. Then, the sub integrated substrate 111 to which the inspection start signal is input outputs inspection data to the interface device 230 according to the inspection start signal. The CPU 230a of the interface device 230 that captures the inspection data, which is serial data, outputs the acquired inspection data to the pachinko machine 1 as an inspection jig. In the pachinko machine 1 as an inspection jig for taking in the inspection data, the lamp driving board 112 provided in the pachinko machine 1 converts the inspection data as serial data into parallel data. Then, the CPU 230a of the interface device 230 reads the inspection data converted into the parallel data, determines whether or not the read inspection data matches the serial I / O check verification data, and uses the determination result as the external data. Output to. In this way, even with different types of pachinko machines, the pachinko machine itself to which the sub-integrated board 111 to be inspected is attached is used as an inspection jig, that is, the lamp driving board 112 provided in the pachinko machine is used to inspect each model. There is no need to create jigs for each. Therefore, the inspection of the serial function of the sub-integrated board 111 can be made common even in pachinko machines of different models.

  In addition, an inspection integrated personal computer (inspection integrated PC) 210 is provided. The inspection integration PC 210 receives the request signal for starting the inspection of the serial function of the sub-integrated board 111 from an operator, and outputs the request signal to the interface device. On the other hand, the determination result output from the interface device 230 is displayed on the display screen of the monitor 220. Since the inspection integrated PC 210 includes input devices such as a keyboard and a mouse, the operator can start inspection of the serial function of the sub integrated substrate 111 by operating these input devices. Further, since the inspection result is displayed on the monitor 220, it is possible to confirm at a glance whether the sub-integrated substrate is non-defective / defective. If a failure occurs in the inspection integrated PC 210, another personal computer can be used as a substitute for the inspection integrated PC 210, and even if the personal computer is changed, the operation method of the input device does not change. Less confused. Therefore, even when a defect occurs in the inspection integrated PC 210, it can be promptly dealt with.

  Further, since the lamp driving board 112 is provided separately from the sub-integrated board 111, a shift register can be added when the production lamps are increased, and a gradation control IC can be added when the gradation lamps are increased. There is no need to recreate the integrated substrate 111. Even if a shift register or a gradation control IC is presented to the lamp driving substrate 112, it can be dealt with only by changing the driving data DAT. Therefore, the lamp driving substrate 112 provided separately is suitable for use in the pachinko machine 1.

  In the present embodiment, an example of the inspection system is clarified by describing the inspection system 200, and at the same time, an example of the method of the inspection system and an example of the program of the inspection system are also clarified.

  The pachinko machine 1 according to the present embodiment described above includes the main control board 101, the sub-integrated board 111, the lamp driving board 112, the effect lamps 44a to 44d, and the gradation lamps 49a and 49b. The main control board 101 outputs a command to the sub-integrated board 111 based on the progress of the pachinko machine 1. The sub-integrated board 111 to which this command is input outputs drive data DAT for driving the gradation lamps 49a and 49b within a fixed time timer interruption processing time of 2 milliseconds (ms) based on the command. . The lamp driving substrate 112 to which the driving data DAT is input drives the gradation lamps 49a and 49b by gradation using the mounted gradation control IC 112g.

  The CPU 111a as a microprocessor of the sub-integrated board 111 has gradation data for setting the luminance of the gradation lamps 49a and 49b, and gradation lamp ON / OFF for setting the gradation lamps 49a and 49b to be turned on / off. The drive data DAT is created from the data and passed to the serial transmitter 111at. The serial transmitter 111at that receives the drive data DAT serially outputs the drive data DAT to the lamp drive board 112g. The CPU 111a controls the gradation control IC 112g to output a switching signal MODE for identifying either gradation data or gradation lamp ON / OFF data from the output port 111aop. The gradation control IC 112g When the data or the gradation lamp ON / OFF data is fetched, control is performed to output the latch signal LAT from the output port 111aop.

  When the gradation control IC 112g receives the latch signal LAT and the switching signal MODE output from the output port 111aop and receives the gradation data and gradation lamp ON / OFF data serially output from the serial transmission unit 111at, When the latch signal LAT is input from the output port 111aop, a drive signal (grayscale drive signal) based on the grayscale data, that is, an output current corresponding to the grayscale data is output based on the input of the latch signal LAT. Output to the lamps 49a and 49b. Therefore, even when the gradation lamps 49a and 49b are gradation controlled by the serially output drive data DAT by using the 2 ms constant time timer interruption process, the gradation lamps 49a and 49b can be controlled. Gradation control for smoothly changing the brightness of the LEDs of the adjustment lamps 49a and 49b can be performed.

  The lamp driving substrate 112 includes shift registers 112h and 112i. The shift registers 112h and 112i are daisy chain connected to the gradation control IC 112g. The CPU 111a as the microprocessor of the sub-integrated board 111 creates drive data DAT including effect lamp ON / OFF data for setting the lighting / extinguishing of the effect lamps 44a to 44d, which are controlled by the shift registers 112h and 112i, respectively. To the serial transmitter 111at. The shift registers 112h and 112i take in the effect lamp ON / OFF data output from the serial transmission unit 111at, and when the latch signal LAT is input from the output port 111aop, the input of the latch signal LAT is triggered. Based on the effect lamp ON / OFF data, a drive signal (lighting drive signal), that is, a lighting signal (ON signal) that is turned on according to the effect lamp ON / OFF data is output to the effect lamps 44a to 44d. For this reason, since the gradation control IC 112g and the shift registers 112h and 112i can be daisy chained, a combination of gradation control by the gradation control IC 112g and ON / OFF control by the shift registers 112h and 112i is possible. Become.

  Further, a shift register 112h is arranged at the first stage. When the shift registers 112h and 112i and the gradation control IC 112g are connected in a daisy chain, when the shift register 112h is arranged in the first stage, the gradation control IC 112g is connected to the first stage through the shift register 112h and the shift register 112i. Drive data DAT is serially output. The drive data DAT captured by the shift registers 112h and 112i is composed of effect lamp ON / OFF data, that is, data set to be turned on / off (ON / OFF data), and is therefore captured by the shift registers 112h and 112i. The drive data DAT and the drive data DAT serially output from the sub-integrated board 111 have a one-to-one correspondence. Therefore, by arranging the shift register 112h in the first stage, the drive data DAT itself can be immediately output as the lighting drive signal described above.

  Furthermore, since the serial transmission unit 111at is set to 250 kilohertz (kHz) as the transfer clock CLK, gradation control can be performed in 128 steps by setting the transfer clock CLK to 250 kHz. At the transfer clock of 250 kHz, one cycle is 4 microseconds (μs), so the pulse width is 2 μs, and the data width of the drive data DAT synchronized with this transfer clock is also 2 μs. Here, it has been experimentally obtained that the noise width falls within about 1 μs. That is, by setting the transfer clock CLK to 250 kHz, the data width (2 μs) of the drive data DAT does not approach the noise width (about 1 μs). Therefore, it is possible to serially output the drive data DAT to the gradation control IC 112g with the transfer clock CLK that is not easily affected by noise.

The lamp driving board 112 attached to the pachinko machine 1 is used for the inspection of the serial function of the sub-integrated board 111. The lamp driving board 112 is suitable for use in the inspection system 200 because the function of the lamp driving board 112, that is, the function of converting serial data into parallel data can be used as it is.
[6. Another example]

  It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the embodiment described above, the gradation control IC 112g mounted on the lamp driving substrate 112 is connected to the gradation lamps 49a and 49b, but drives the stepping motor in addition to the gradation lamps 49a and 49b. It may be connected to a drive board. FIG. 9 is a block diagram of a lamp driving substrate 112 ′ in which the gradation control IC 112 g is connected to the motor driving device in addition to the gradation lamps 49 a and 49 b.

  As shown in FIG. 9, the gradation control IC 112 g is connected to the gradation lamps 49 a and 49 b and is connected to the motor driving device 120. The motor drive device 120 includes a drive board 120d and stepping motors 120m and 120n. When the drive signal from the gradation control IC 112g is input to the drive board 120d, Stepping motors 120m and 120n are driven.

  The gradation control IC 112g can perform drive control of the stepping motors 120m and 120n in addition to gradation control for smoothly changing the brightness of the LEDs of the gradation lamps 49a and 49b. Here, the rated input current that can be driven by the stepping motors 120m and 120n is set as the output current output from the gradation control IC 112g. That is, the rated input current of the drive board 120d is set.

  Here, the serial transmission unit 111at serially outputs gradation data, and then serially outputs ON / OFF data for gradation lamps following the excitation data for setting switching of the excitation current flowing through each phase coil of the stepping motor. To do. The gradation control IC 112g outputs a drive signal to the drive substrate 120d according to the excitation data, and outputs an output current according to the gradation data to the gradation lamps 49a and 49b. The gradation control IC 112g captures gradation data or excitation data and gradation lamp ON / OFF data based on the switching signal MODE and the latch signal LAT output from the output port 111aop.

  In the embodiment described above, the pachinko machine 1 has been described as an example. However, a gaming machine to which the present invention can be applied is not limited to a pachinko machine, and a gaming machine other than a pachinko machine, for example, a slot machine or a pachinko machine. The present invention can also be applied to a fusion game machine that fuses with a slot machine (a game that uses a game ball to play a slot game).

It is a front view which shows 1 pachinko machine. It is a perspective view which shows 1 pachinko machine of the state which opened the main body frame and the front frame. It is a rear view which shows the back surface structure of the pachinko machine. 2 is a front view showing a game board 4. FIG. 2 is a block diagram showing a main substrate 100 and a peripheral substrate 110. FIG. 2 is a block diagram of a lamp driving substrate 112. FIG. It is explanatory drawing showing schematic structure of the test | inspection system 200 which test | inspects the serial function in a test process. It is explanatory drawing showing the test | inspection of the sub integration board | substrate 111. FIG. It is a block diagram of the lamp drive substrate 112 '.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine (game machine), 4 ... Game board, 12 ... Game area | region, 44a-44d ... Production lamp (multiple LED), 49a, 49b ... Tone lamp (multiple LED), 101 ... Main control board ( Main control board), 111 ... Sub-integrated board (sub-integrated board), 111a ... CPU as a microprocessor, 111at ... Serial transmission unit (serial transmission unit), 111aop ... Output port (output port), 112 ... Lamp drive board ( Driving board), 112h, 112i, shift register (shift register), 112g, gradation control IC (gradation control IC), 200, inspection system, 210, inspection integrated PC (inspection integrated personal computer), 220, monitor, 222 ... OK image, 224 ... NG image, 230 ... Interface device (interface device), 250 Probe table.

Claims (1)

A main control board, a sub-integrated board, a drive board, and a plurality of LEDs;
The main control board outputs a command to the sub-integrated board based on the progress of the game,
The sub-integrated board outputs drive data for gray-scale driving the plurality of LEDs in a fixed-time timer interrupt process based on the command,
The driving board is a gaming machine that performs gradation driving of the plurality of LEDs based on the driving data,
The sub-integrated board includes a serial transmission unit, an output port, drive data creation means, switching signal control means, and latch signal control means,
The drive substrate includes a gradation control IC,
The drive data creation means creates the drive data from gradation data for setting the luminance of the plurality of LEDs, respectively, and gradation ON / OFF data for setting the lighting / extinction of the plurality of LEDs. Pass to the serial transmitter,
The switching signal control means performs control to output from the output port a switching signal for identifying whether the gradation control IC is the gradation data or the gradation ON / OFF data,
The latch signal control means performs control to output a latch signal from the output port when the gradation control IC captures the gradation data or the gradation ON / OFF data,
The gradation control IC receives the gradation data output from the serial transmission unit and the gradation ON / OFF data when the latch signal and switching signal output from the output port are input, and the output When a latch signal is received from a port, a gradation driving signal is output to the plurality of LEDs based on the gradation data.

Images