JP2007042713A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which level difference in each region on an interlayer insulating film formed on an interconnect line by polishing can be reduced even if a dense region and a sparse region exist in the interconnect line formed on a semiconductor substrate. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a second interlayer insulating film 15 on a first interlayer insulating film 13 which is formed in a first region 16 on a semiconductor substrate 12 where aluminum interconnect lines 14 are formed densely and a second region 17 where aluminum interconnect line 14 is not formed, a step for implanting and diffusing impurities 23 into a protruding portion 15b above the first region 16 on the second interlayer insulating film 15 in order to increase polishing rate, and a step for planarizing the upper surface of the second interlayer insulating film 15 including the protruding portion 15b by CMP. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device for flattening unevenness on an interlayer insulating film, for example.

  As shown in FIG. 5, in the manufacturing method of the semiconductor device described above, first, in step 101, a first interlayer insulating film 102 is formed on a semiconductor substrate 101, and then, a known interlayer insulating film 102 is formed on the first interlayer insulating film 102. Aluminum wiring 103 is formed by a method. On the first interlayer insulating film 102, for example, a first region 104 in which aluminum wirings 103 are densely formed and a second region 105 in which the aluminum wiring 103 is not formed (including a sparse state) are included. .

  Next, in step 102, a second interlayer insulating film 106 made of, for example, a silicon oxide film is formed over the aluminum wiring 103 and the entire semiconductor substrate 101. In the second interlayer insulating film 106, the thickness of the aluminum wiring 103 formed on the first interlayer insulating film 102 is reflected, and the upper surface 106a of the second interlayer insulating film 106 is uneven. Thereafter, in step 103, in order to flatten the upper surface 106a of the uneven second interlayer insulating film 106, for example, as described in Patent Document 1, polishing is performed using a CMP (Chemical Mechanical Polishing) method. I do.

JP-A-11-154777

However, the portion 104a on the first region 104 on the upper surface 106a of the second interlayer insulating film 106 is uneven, reflecting the thickness of the aluminum wiring 103, but the aluminum wiring 103 is formed densely. Therefore, when polishing is performed by the CMP method, the pressure cannot be applied (concentrated) only to the convex portion, and the pressure applied to the portion 104a and the pressure applied to the portion 105a are substantially equal. As a result, the polishing amounts of the portion 104a and the portion 105a become substantially equal, and in step 103, a level difference A is generated between the portion 104a and the portion 105a, although it becomes flat within the range of the portion 104a and within the range of the portion 105a. There was a problem.
Due to the occurrence of the step A, when a new aluminum wiring is formed on the second interlayer insulating film 106 by photolithography, a place where the film which is the source of the aluminum wiring is in focus and a place where it does not match are generated ( As a result, for example, there is a problem that the width of the formed aluminum wiring varies.

  The present invention reduces the step on each region on the interlayer insulating film formed on the wiring by polishing even if the wiring formed on the semiconductor substrate has a dense area and a sparse area. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes an implantation step of implanting impurities for increasing a polishing rate into a convex portion on an interlayer insulating film formed on a semiconductor substrate. A diffusion step of diffusing the impurity implanted into the convex portion throughout the convex portion, and polishing for polishing the interlayer insulating film including the convex portion in order to flatten the interlayer insulating film. And a process.

  According to this method, since the impurities implanted into the convex portion on the interlayer insulating film in the implantation step are diffused throughout the convex portion in the diffusion step, it becomes possible to increase the polishing rate of the convex portion, Accordingly, when the interlayer insulating film is polished by the polishing process, the convex portion can be polished quickly, and the step between the convex portion and the other portion can be reduced. As a result, when etching is performed using photolithography to form a new wiring on the interlayer insulating film, it is possible to focus on the film that is the source of the wiring (within the depth of focus range). Thus, regular wiring can be formed. In addition, since the polishing rate of the convex portion can be increased, the polishing time can be shortened.

  A method of manufacturing a semiconductor device according to the present invention includes: a first region formed adjacent to a plurality of wirings on a semiconductor substrate in a dense state; and an interlayer insulating film formed on a second region that is another region. An implantation step of injecting impurities into the convex portion on the first region in the first region, and a diffusion step of diffusing the impurities implanted into the convex portion throughout the convex portion. And polishing the upper surface of the interlayer insulating film including the convex portion to flatten the upper surface of the interlayer insulating film.

  According to this method, since the impurity implanted into the convex portion on the first region on the interlayer insulating film in the implantation step is diffused throughout the convex portion in the diffusion step, the polishing rate of the convex portion is increased. Accordingly, it is possible to mitigate the reduction in the polishing amount of the convex portion due to the increase in the area of the upper surface of the convex portion due to the wirings being adjacent in a dense state. Therefore, when the interlayer insulating film is polished by the polishing process, the convex portion can be polished quickly, and the level difference between the convex portion on the first region and the non-convex portion on the second region can be reduced. Can do. As a result, since the level difference on the interlayer insulating film is reduced, it is necessary to focus on the film that is the source of the wiring when performing etching using a photolithography method in order to form a new wiring on the interlayer insulating film. (Within the range of the depth of focus) is possible, and regular wiring can be formed. In addition, since the polishing rate of the convex portion can be increased, the polishing time can be shortened.

  In the method for manufacturing a semiconductor device according to the present invention, it is desirable that the second region is a region where wiring is not formed or a region where wiring is formed in a sparse state.

  According to this method, the second region is a region where no wiring is formed or a region formed in a sparse state where the wirings are not adjacent to each other, so that the step difference from the convex first region is large. As described above, the impurity is implanted and diffused into the convex portion to increase the polishing rate of the convex portion, so that the level difference between the convex portion and the other region is Can be reduced.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the polishing step polishes the interlayer insulating film by a CMP method.

  According to this method, since the interlayer insulating film is mechanically polished by the CMP method, the polishing rate can be increased by the impurities implanted and diffused into the convex portion. As a result, the convex portion and the other portions can be accelerated. The level difference with the part can be reduced.

  In the method of manufacturing a semiconductor device according to the present invention, it is desirable that the wiring is formed at a constant interval.

  According to this method, since the wiring is formed with a constant interval, polishing is performed in a range on a dense region where the interval on the interlayer insulating film is small or in a range on a sparse region where the interval is large. Although there is a difference in amount, it can be flattened within that range. Therefore, even if there is a step between the dense region and the sparse region, the step can be formed substantially in parallel, so that the impurity can be easily implanted. Thereby, impurities can be implanted and diffused into the convex portion, and the level difference can be reduced by polishing.

  In the semiconductor device manufacturing method according to the present invention, the impurity is preferably fluorine.

  According to this method, since it is fluorine, it can be relatively easily implanted and diffused into the convex portion, and the polishing rate of the convex portion can be increased.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the diffusion step is thermal diffusion in which the impurities are diffused by applying heat to the semiconductor device.

  According to this method, since the impurity implanted by thermal diffusion is diffused, the impurity implanted into the convex portion can be diffused relatively easily, and the polishing rate of the convex portion can be increased. it can.

  Hereinafter, embodiments of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device. Hereinafter, the structure of the semiconductor device will be described with reference to FIG.

  As shown in FIG. 1, the semiconductor device 11 includes a semiconductor substrate 12, a first interlayer insulating film 13, an aluminum wiring 14 that is a wiring, and a second interlayer insulating film 15 that is an interlayer insulating film.

  The semiconductor substrate 12 is, for example, a silicon substrate. For example, transistor elements (not shown) are formed on the semiconductor substrate 12.

The first interlayer insulating film 13 is made of, for example, a silicon oxide film (SiO ₂ ) and is formed on the semiconductor substrate 12. The first interlayer insulating film 13 is formed so as to cover the entire surface of the semiconductor substrate 12 in order to insulate, for example, between transistor elements formed on the semiconductor substrate 12 or between wirings.

  The aluminum wiring 14 is made of, for example, aluminum (Al), and a plurality of aluminum wirings 14 are formed on the first interlayer insulating film 13. The plurality of aluminum wirings 14 are formed, for example, in a dense state (a dense state). The aluminum wiring 14 is electrically connected to a transistor element (not shown) formed on the semiconductor substrate 12 through a contact plug made of tungsten (W), for example.

The second interlayer insulating film 15 is made of, for example, a silicon oxide film (SiO ₂ ), and is formed on the entire first interlayer insulating film 13 so as to cover the aluminum wiring 14. The second interlayer insulating film 15 is used, for example, so as not to electrically connect the aluminum wirings 14 to each other. The second interlayer insulating film 15 includes a first region 16 and a second region 17.

  The first region 16 is a portion where a plurality of aluminum wirings 14 are formed in a dense state. The plurality of aluminum wirings 14 are formed, for example, at regular intervals. The second region 17 is a portion where the aluminum wiring 14 is not formed on the first interlayer insulating film 13.

  Further, the upper surface of the second interlayer insulating film 15 is planarized by, for example, polishing by a CMP (scientific mechanical polishing) method. The CMP method is mainly composed of, for example, an abrasive called a slurry and a polishing cloth called a polishing pad. While applying the slurry onto the semiconductor device 11, the semiconductor device 11 and the polishing pad are rotated, For example, the second interlayer insulating film 15 is polished.

  2 to 4 are schematic cross-sectional views showing a method of manufacturing a semiconductor device in the order of steps. Hereinafter, a method for manufacturing a semiconductor device will be described with reference to FIGS.

As shown in FIG. 2, in step 11, an aluminum wiring 14 is formed on the first interlayer insulating film 13. First, a transistor element (not shown) is formed on the semiconductor substrate 12 by a known method, for example. Next, a first interlayer insulating film 13 is formed on the entire semiconductor substrate 12 by a known method. Thereafter, a contact plug (not shown) is formed in the first interlayer insulating film 13 to connect the transistor element and the aluminum wiring 14.
After the contact plug is formed, an aluminum film (not shown) that is the source of the aluminum wiring 14 is formed on the first interlayer insulating film 13. The aluminum film 14 is formed on the first interlayer insulating film 13 by etching the aluminum film using a known method.

Note that the first interlayer insulating film 13 has a first region 16 formed in a dense state (a dense state) of aluminum wirings 14 and a second region 17 in which the aluminum wirings 14 are not formed.
As described above, the aluminum wiring 14 is formed on the first interlayer insulating film 13, and the aluminum wiring 14 in the first region 16 is connected to the transistor element via the contact plug (not shown).

In step 12, a second interlayer insulating film 15 is formed over the aluminum wiring 14 and the first interlayer insulating film 13. As described above, the second interlayer insulating film 15 is made of, for example, a silicon oxide film (SiO ₂ ) and is formed by a plasma CVD (Chemical Vapor Deposition) method.

  By depositing a silicon oxide film on the aluminum wiring 14 and the first interlayer insulating film 13 by plasma CVD, the thickness of the aluminum wiring 14 is reflected on the upper surface 15a of the second interlayer insulating film 15. A third region 21 (above the first region 16) which is a raised convex portion 15b (convex portion) and a fourth region 22 (second region) which is a concave portion 15c where the thickness of the aluminum wiring 14 is not reflected. 17 above) is formed.

  In step 13, a resist film 24 is formed on the second interlayer insulating film 15. The resist film 24 is used to inject the impurity 23 at a predetermined depth only into the convex portion 15b. The impurity 23 is, for example, fluorine (F).

  If the impurity is implanted with the unevenness on the second interlayer insulating film 15 exposed on the surface, the impurity 23 is implanted to a predetermined depth from the upper surface 15a of the uneven second interlayer insulating film 15. The impurity 23 cannot be injected only into the shaped portion 15b. Therefore, a resist film 24 for flattening the second interlayer insulating film 15 is formed.

  First, the resist film 24 is applied to the entire surface of the uneven second interlayer insulating film 15 by using, for example, a spin coating method. The resist film 24 is, for example, an organic solvent. As described above, the second interlayer insulating film 15 is flattened, and the impurity 23 can be implanted into the predetermined depth (horizontal) from the upper surface 24a of the resist film 24.

  As shown in FIG. 3, in step 14 (injection step), an impurity 23 is implanted into the convex portion 15 b of the second interlayer insulating film 15. First, fluorine, which is an impurity 23, is implanted at a predetermined depth from the upper surface 24a of the resist film 24 by a known method. The depth for injecting fluorine is, for example, the substantially central portion of the convex portion 15b. The depth of fluorine implantation from the upper surface 24a of the resist film 24 can be adjusted by, for example, the energy and angle of implantation.

Since the convex portion 15b made of a silicon oxide film and the resist film 24 made of an organic solvent are made of different materials, there may be a difference in fluorine implantation depth. However, since the purpose is to diffuse the impurity 23 into the convex portion 15b, it is desirable to perform the implantation under conditions that allow the impurity 23 to be implanted into the convex portion 15b.
From the above, the impurity 23 (fluorine) is implanted into the convex portion 15b (substantially central portion) in the second interlayer insulating film 15, and is implanted into the resist film 24 otherwise. .

  In step 15, the resist film 24 on the second interlayer insulating film 15 is removed. By removing (stripping) the resist film 24 by a known method, a second interlayer insulating film 15 having a convex portion 15 b into which an impurity 23 (fluorine) is implanted is formed on the first interlayer insulating film 13. Is done.

  In step 16 (diffusion step), the impurity 23 (fluorine) implanted into the convex portion 15b is diffused. First, heat treatment (thermal diffusion treatment) is performed on the entire semiconductor substrate 12 on which the second interlayer insulating film 15 having the convex portion 15b is formed. As a result, the fluorine in the convex portion 15b is diffused, whereby the convex portion 15b changes from a silicon oxide film to an FSG (fluorinated silicon oxide) film (also referred to as “SiOF film”).

  As described above, since the convex portion 15b is an FSG film, the polishing rate of the convex portion 15b can be increased as compared with the concave portion 15c made of a silicon oxide film. This makes it possible to make a difference in the polishing rate between the convex portion 15b and the concave portion 15c, and as a result, the convex portion 15b can be cut faster than the concave portion 15c.

  In addition, after performing CMP polishing in the process 17 described later, the FSG film remains in the second interlayer insulating film 15, whereby fluorine contained in the FSG film reacts with pure water used at the time of CMP polishing, The second interlayer insulating film 15 made of a silicon oxide film may be corroded. Therefore, it is desirable to form the FSG film only on the convex portion 15b to be removed by polishing.

  As shown in FIG. 4, in step 17 (polishing step), the upper surface 15a of the second interlayer insulating film 15 is planarized. First, a polishing pad (not shown) is brought into contact with the upper surface 15 a of the second interlayer insulating film 15. The polishing pad can be in contact with the entire surface (the third region 21 and the fourth region 22), although the upper surface 15a of the second interlayer insulating film 15 has irregularities. Thereby, the entire second interlayer insulating film 15 is polished.

However, since the convex portion 15b (see step 16) of the third region 21 is an FSG film in which fluorine is diffused, it can be cut faster than the concave portion 15c. The amount of polishing the convex portion 15b is, for example, about 1 μm from the upper surface of the convex portion 15b.
As described above, the step X between the third region 21 and the fourth region 22 (see FIG. 3, step 16) before polishing is reduced to the step Y. Since the level difference is reduced, the depth of focus when a new aluminum wiring is formed on the second interlayer insulating film 15 by using the photolithography method can be within an allowable range.

As described above in detail, according to the semiconductor device manufacturing method of the present embodiment, the following effects can be obtained.
(1) According to the manufacturing method of the semiconductor device of this embodiment, the impurity 23 implanted into the convex portion 15b on the second interlayer insulating film 15 in the implantation step (step 14) is diffused (step 16). Therefore, it is possible to increase the polishing rate of the convex portion 15b, and as a result, the aluminum wiring 14 is adjacent to the upper surface of the convex portion 15b. A reduction in the polishing amount of the convex portion 15b due to the increase in the area can be mitigated. Therefore, when the upper surface 15a of the second interlayer insulating film 15 is polished by the polishing step (step 17), the convex portion 15b can be polished faster than the concave portion 15c, whereby the first The level difference between the convex portion 15b (third region 21) on the region 16 and the concave portion 15c (fourth region 22) on the second region 17 can be reduced. As a result, in order to form a new wiring on the second interlayer insulating film 15, the etching is performed using a photolithography method so that the aluminum film as a base of the aluminum wiring is focused (within the allowable depth of focus range). For example, a wiring having a normal width can be formed.

  (2) According to the manufacturing method of the semiconductor device of the present embodiment, the impurity 23 (fluorine) is implanted and diffused into the convex portion 15b, so that the polishing rate of the convex portion 15b can be increased. Therefore, the polishing time for flattening the second interlayer insulating film 15 by CMP polishing can be shortened.

  (3) According to the semiconductor device manufacturing method of the present embodiment, it is possible to reduce the burden on the relatively expensive polishing pad and slurry by increasing the polishing rate of the convex portion 15b. The consumption of the polishing pad and slurry can be reduced. Thereby, this cost can be suppressed.

  In addition, this embodiment is not limited above, It can also implement with the following forms.

  (Modification 1) As described above, the impurity 23 to be implanted into the convex portion 15b is not limited to the use of fluorine, and any impurities can be used as long as the polishing rate of the convex portion 15b can be increased. For example, boron (B) or phosphorus (P) may be used.

  (Modification 2) As described above, as the portion where the step in the second interlayer insulating film 15 is likely to be generated, the aluminum wiring 14 is on the first region 16 in a dense state (dense state) and the aluminum wiring 14 is not present. Instead of comparing with the second region 17, the first region 16 in which the aluminum wiring 14 is dense may be compared with the region in which the aluminum wiring 14 is sparse.

Specifically, although the area of the sparse aluminum wiring 14 on the second interlayer insulating film 15 is convex, the area of the convex upper surface is small, so the pressure is applied to the convex part by the polishing pad. It is possible to concentrate and it is relatively easy to polish. As a result, a step is likely to occur between the first region 16 and the sparse region above the second interlayer insulating film 15, as described above. Therefore, even when the first region 16 and the sparse region are provided, the steps on the second interlayer insulating film 15 can be reduced by using the manufacturing method described above.
In the second modification, the portion into which the impurity 23 is implanted is the convex portion 15b and may be both the convex portion on the sparse region in the second interlayer insulating film 15. Alternatively, only the convex portion 15b may be used.

  (Modification 3) As described above, after performing CMP polishing instead of forming the FSG film by diffusing the impurity 23 only in the convex portion 15b on the second interlayer insulating film 15, As long as the FSG film does not remain in the second interlayer insulating film 15, for example, the FSG film may be formed by diffusing the impurity 23 to the upper layer of the second interlayer insulating film 15. According to this, it is possible to avoid that the pure water used at the time of CMP polishing reacts with fluorine contained in the FSG film, and the second interlayer insulating film 15 is corroded, and the step on the second interlayer insulating film 15 is prevented. Can be reduced.

  (Modification 4) The semiconductor device manufacturing method of the present invention as described above is not limited to being applied to the semiconductor device 11 in which nothing is formed in the second region 17 (such as the aluminum wiring 14). You may make it apply to the semiconductor device by which the dummy dummy pattern is arrange | positioned in the 2nd area | region 17. FIG.

  (Modification 5) As described above, the present invention is not limited to flattening the unevenness formed on the second interlayer insulating film 15, for example, when flattening the unevenness on the other interlayer insulating film, You may make it apply the manufacturing method of above-described this invention.

1 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to an embodiment. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in order of steps. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in order of steps. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in order of steps. FIG. 10 is a schematic cross-sectional view illustrating a conventional method for manufacturing a semiconductor device in the order of steps.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor device, 12 ... Semiconductor substrate, 13 ... 1st interlayer insulation film, 14 ... Aluminum wiring which is wiring, 15 ... 2nd interlayer insulation film which is interlayer insulation film, 15a ... Upper surface, 15b ... Projection part Convex portion, 15c ... concave portion, 16 ... first region, 17 ... second region, 21 ... third region, 22 ... fourth region, 23 ... impurity, 24 ... resist film, 24a ... top surface, 101 ... Semiconductor substrate 102 ... first interlayer insulating film 103 ... aluminum wiring 104 ... first region 104a ... part 105 ... second region 105a ... part 106 ... second interlayer insulating film 106a ... upper surface.

Claims (7)

An implantation step of injecting impurities for increasing the polishing rate into a convex portion on the interlayer insulating film formed on the semiconductor substrate;
A diffusion step of diffusing the impurity implanted into the convex portion throughout the convex portion;
A polishing step for polishing the interlayer insulating film including the convex portion in order to planarize the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: A plurality of wirings on a semiconductor substrate are formed adjacent to each other in a dense state on a convex portion on the first region on an interlayer insulating film formed on a second region which is a second region which is another region. An implantation step of injecting impurities for increasing the polishing rate;
A diffusion step of diffusing the impurity implanted into the convex portion throughout the convex portion;
A polishing step for polishing the interlayer insulating film including the convex portion in order to planarize the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the second region is a region where a wiring is not formed or a region where a wiring is formed in a sparse state. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 3,
In the polishing step, the interlayer insulating film is polished by a CMP method. A method of manufacturing a semiconductor device according to claim 2 or 3,
The method of manufacturing a semiconductor device, wherein the wirings are formed at regular intervals. A method for manufacturing a semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the impurity is fluorine. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 6,
The method of manufacturing a semiconductor device, wherein the diffusion step is thermal diffusion in which the impurities are diffused by applying heat to the semiconductor device.

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