JP2007042701A - Information display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information display system which evaluates the formed state of device structures which are formed process by process in a plurality of layers so as to be superposed on top of each other in each of a plurality of different zone areas on an object, which can improve a yield of device manufacturing processes. <P>SOLUTION: In the main window 650 of an evaluation application; averages of superposition errors, averages of line widths, etc. corresponding to a plurality of processes A-J are displayed on a graph 652, averages of superposition errors, averages of line widths, etc. corresponding to a plurality of wafers 1-10 in a lot are displayed on a graph 653, averages of superposition errors, and averages of line widths, etc. corresponding to a plurality of shot regions 1-10 are displayed on a graph 654. By specifying a process, wafer, shot region, and its coordinates by using these graphs and pulldown menus 657, 659, and 661; the specified device structure can be shown as a graphical image. The actually measured superposition error and line width of that portion are reflected in this graphical image. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information display system, and more specifically, an information display system for evaluating a formation state of a multi-layer device structure formed so as to overlap each of a plurality of different partitioned areas on an object in a process unit. About.

  In a device manufacturing process for manufacturing a device such as a semiconductor, a process (about 20 to 30 times) including film formation, resist coating, circuit pattern exposure, development, etching, ion implantation, and the like is repeatedly performed. In general, a circuit or the like (hereinafter also referred to as a device structure as appropriate) is formed in a plurality of layers on each of a plurality of different partitioned areas (shot areas) on an object (wafer or the like). .

  When forming a device structure, the size of each component in the device structure (for example, the line width of at least a part of a circuit) is as designed, and the device structure between layers that are strongly connected structurally It is important to maintain high overlay accuracy. In order to improve device quality and yield, overlay accuracy and line width accuracy are managed on a process basis, and overlay accuracy and line width accuracy of the device structure actually formed, that is, the formation state of the device structure is determined. Evaluation has been made conventionally. For example, after the device structure is formed, the overlay error or line width is actually measured by an overlay error measuring instrument or SEM, and the measurement data is collected by a personal computer or the like. Supports a function that allows the operator to check the display result and evaluate the formation state of the device structure by executing the operating evaluation application software and displaying the collected measurement data on the screen. ing.

  However, the display of the formation state of a device structure supported by such a function is generally performed for each device structure, and should be evaluated between processes, wafers, and shot areas. There is an inconvenience that it is not necessarily suitable for evaluation of overall overlay accuracy and line width accuracy.

  In general, the display of the formation state of the device structure supported by such a function is simply to display numerical values such as overlay error and line width. Such display of only the numerical value imposes an excessive burden on the operator who wants to evaluate the overlay accuracy and the line width accuracy based on the numerical value. In addition, measurement of the formation state of the device structure by SEM or the like is a complicated operation for the operator.

  In addition, such a function is intended for evaluation of only the exposure process, and other device forming apparatuses such as an etching apparatus, a resist coater / developer, an oxidation / ion implantation apparatus, a CMP apparatus, a film forming apparatus, etc. Currently, functions that can be managed and evaluated collectively have not yet been established.

  From a first viewpoint, the present invention displays information for evaluating the formation state of a multi-layered device structure formed so as to overlap each of a plurality of different partitioned regions on an object in a process unit. An information display system, wherein the calculation device calculates at least one type of information related to a formation state of the device structure based on information related to at least one of the formation process and the formation result of each device structure; And a display device that displays at least one type of information relating to the formation state of the device structure for at least one of a plurality of processes, a plurality of objects, and a plurality of partitioned regions.

  According to this, at least one type of information relating to the formation state of the device structure calculated based on information relating to at least one of the formation process and the formation result of the device structure is converted into a plurality of processes, a plurality of objects, a plurality of At least one of the divided areas is displayed. This makes it possible to comprehensively check the formation state of the device structure over a plurality of processes, a plurality of objects, and a plurality of partitioned regions.

  From a second viewpoint, the present invention displays information for evaluating the formation state of a multi-layered device structure formed so as to overlap each of a plurality of different partitioned regions on an object in a process unit. An information display system for designating a process, an object, a partition area, and a position coordinate of the partition area; and the partition area based on the specified process, object, partition area, and position coordinates of the partition area A calculation device that calculates at least one type of information related to a formation state of the device structure based on information related to at least one of a formation process and a formation result of the device structure in at least a part of the device structure; Design information of the device structure in at least a part of the partition area based on the position coordinates of the object, the partition area, and the partition area, and the partition An image display device that displays a graphic image of the device structure formed in at least a part of the partition area based on at least one type of information regarding a formation state of the device structure in at least a part of the area; An information display system provided.

  According to this, since the graphic image of the device structure is displayed in at least a part of the partition area based on the process, object, partition area, and position coordinates of the partition area specified by the specified device, the formation thereof A comprehensive assessment of the condition is facilitated.

  According to a third aspect of the present invention, there is provided an information display system for evaluating a device structure of a plurality of layers formed so as to be superimposed on each of a plurality of different partitioned regions on an object in a process unit. A calculation device that calculates information related to superimposition of a device structure of a device structure on the basis of information related to at least one of a formation process and a formation result of the device structure; Create information on matching between the device forming device that forms the device structure and the device forming device that forms the device structure of the layer that is the target of the device structure An information display system comprising: a creating device for displaying; and a display device for displaying information on the acquired matching. It is a non.

  By confirming the displayed information related to matching, it is possible to easily perform matching of an apparatus that performs overlay exposure and judge abnormality of overlay exposure.

  According to a fourth aspect of the present invention, there is provided an information display system for evaluating the formation state of a device composed of a plurality of layers of device structures formed so as to overlap each of a plurality of different partitioned regions on an object in a process unit. An acquisition device that acquires, for each process, information related to a device forming apparatus that forms a device structure for the object; and an apparatus information display that displays information related to the device forming apparatus used in a specified process. And an apparatus for displaying information.

  By confirming the displayed information related to the device forming apparatus, it is possible to identify the device forming apparatus that has affected the formation state of the device structure.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 schematically shows a configuration of a semiconductor manufacturing system 101 according to an embodiment of the present invention. The semiconductor manufacturing system 101 is a system for manufacturing a device such as a micro device by processing a substrate such as a semiconductor wafer or a glass plate (hereinafter collectively referred to as a wafer) and installed in a substrate processing factory. ing.

  As shown in FIG. 1, the semiconductor manufacturing system 101 includes an exposure apparatus 100, a coating and developing apparatus (hereinafter referred to as a track) 300 disposed adjacent to the exposure apparatus 100, an exposure process management controller 500, and the like. , An overlay / line width analysis system 600, an in-factory production management host system 700, an overlay / line width measuring instrument 800, and various device forming apparatus groups 900.

  The exposure apparatus 100 and the track 300 are in-line connected to each other. Here, in-line connection means that the apparatuses and the processing units in each apparatus are connected via a transfer device that automatically transfers a wafer such as a robot arm or a slider. For this reason, the combination of the exposure apparatus 100 and the track 300 can be regarded as one substrate processing apparatus. In the substrate processing apparatus, a coating process for coating a photosensitive agent such as a photoresist on the wafer, an exposure process for transferring the pattern on the reticle to the wafer coated with the photosensitive agent, and developing the wafer after the exposure process is completed. The development process is performed in cooperation with other apparatuses in the semiconductor manufacturing system 101 when necessary. Among these, the coating process and the development process are performed by the track 300, and the exposure process is performed by the exposure apparatus 100. Note that a plurality of wafers are processed as one unit (referred to as a lot).

  In FIG. 1, only one substrate processing apparatus (100, 300) is shown for the sake of space, but in reality, a plurality of substrate processing apparatuses are installed in the semiconductor manufacturing system 101. Yes. That is, in the semiconductor manufacturing system 101, a plurality of exposure apparatuses 100 and a plurality of tracks 300 connected inline to the exposure apparatus 100 are provided.

  Among the apparatuses constituting at least a part of the semiconductor manufacturing system 101, at least the substrate processing apparatuses (100, 300), the overlay / line width measuring instrument 800, and the various device forming apparatus groups 900 are temperature and humidity. Is installed in a controlled clean room. In addition, each device is connected via a network such as a LAN (Local Area Network) or a dedicated line (wired or wireless) installed in the substrate processing factory, and appropriately performs data communication between them. Can be done.

  An exposure apparatus 100 includes an illumination system that emits exposure illumination light, a reticle stage that holds a reticle on which a circuit pattern illuminated by illumination light from the illumination system, a projection optical system, and a wafer to be exposed. A wafer stage to be held and a control system thereof are provided. The exposure apparatus 100 performs relative synchronous scanning of the reticle held on the reticle stage and the wafer held on the wafer stage with respect to the exposure illumination light emitted from the illumination system, and thereby the circuit pattern on the reticle and Scanning exposure is performed in which an image of a pattern such as a wafer mark attached thereto is transferred to a plurality of different shot areas on the wafer W. When this scanning exposure is performed, the intensity of the illumination light, the synchronous control of both stages, and the autofocus / leveling (AF) for matching the wafer surface within the depth of focus of the projection optical system so that the exposure is performed with high accuracy. / L) Control is performed. That is, the exposure apparatus 100 is a step-and-scan projection exposure apparatus (scanning exposure apparatus).

  The exposure apparatus 100 is provided with two wafer stages, and wafers in one lot are alternately loaded on both wafer stages and sequentially exposed. In this way, the wafer can be loaded on the other wafer stage while the wafer held on one wafer stage is being exposed, so that the wafer can be replaced with one wafer stage. → The throughput of the exposure process can be significantly improved compared to repeated exposure. In such a case, even with the same exposure apparatus, one lot of wafers can be regarded as being alternately exposed by separate processing units. In FIG. 1, a portion of the exposure apparatus 100 that performs scanning exposure on a wafer held on one wafer stage is shown as a processing unit 1, and scanning exposure is performed on a wafer held on the other wafer stage. A portion to be performed is shown as a processing unit 2.

[Coating and developing equipment]
The track 300 is provided with a coater / developer (C / D) 310 that performs resist coating and development. Also in this C / D 310, two stages for holding the wafer are provided. By alternately applying the resist and developing the wafer held on the two stages, the required time can be shortened. It has been realized. In FIG. 1, a portion of the C / D 310 that performs resist coating and development on a wafer held on one stage is shown as a processing unit 1, and resist coating and development on a wafer held on the other wafer stage. A portion for performing the processing is shown as a processing unit 2.

[Overlay measuring machine]
The overlay / line width measuring machine 800 is a measuring device capable of measuring an overlay error and a line width such as a circuit pattern formed on a wafer developed by the C / D 310. Actually, the overlay / line width measuring machine 800 is a combination of an overlay measuring machine and a line width measuring machine. A plurality of overlay / line width measuring machines 800 are also provided.

[Exposure process control controller]
The exposure process management controller 500 controls and manages the exposure process performed by the plurality of exposure apparatuses 100 and manages the scheduling of the plurality of exposure apparatuses 100.

[Overlay / Line width analysis system]
The overlay / line width analysis system 600 is an apparatus that operates independently of the exposure apparatus 100, the track 300, and the like, collects various data from various apparatuses via a network, and performs necessary analysis processing. . As hardware for realizing such a system, for example, a personal computer (PC) can be employed. On this PC, an evaluation application that analyzes and evaluates data collected from various devices can be operated. In this evaluation application, it is possible to instruct commands to select and analyze collected data by operating the operator using a mouse or keyboard, and the analysis results can be displayed on the display. It has become.

[In-factory production management host system]
The factory production management host system 700 performs overall management of all semiconductor manufacturing processes in the substrate processing factory.

[Device forming equipment group]
The various device forming apparatus group 900 includes a film forming apparatus (CVD (Chemical Vapor Depositon) apparatus) 910 that generates a thin film on a wafer, an etching apparatus 920 that performs etching, and a chemical mechanical polishing to flatten the wafer. A CMP (Chemical Mechanical Polishing) apparatus 930 that performs a process for converting the wafer into an oxide, and an oxidation / ion implantation apparatus 940 that oxidizes the wafer and implants ions (impurities). The CVD apparatus 910, the etching apparatus 920, the CMP apparatus 930, and the oxidation / ion implantation apparatus 940 are also provided with two processing units (processing units 1 and 2) to improve throughput. Similarly to the exposure apparatus 100, a plurality of CVD apparatuses 910, etching apparatuses 920, CMP apparatuses 930, and oxidation / ion implantation apparatuses 940 are provided so that wafers to be processed can be transferred between them. Therefore, a transport path is provided.

<Device manufacturing process>
Here, a device manufacturing process performed in the semiconductor manufacturing system will be described. First, in the oxidation / ion implantation apparatus 940, an oxide film is formed on the wafer. Then, a resist is applied at C / D 310, and the circuit pattern is exposed at exposure apparatus 100. Thereafter, development is performed by the C / D 310, etching is performed by the etching apparatus 920, film formation is performed by the CVD apparatus 910, planarization is performed by the CMP apparatus 930, and ion is performed by the oxidation / ion implantation apparatus 940 as necessary. Perform injections. By repeating the above process many times, a device structure such as an electric circuit or the like is formed so as to overlap on several layers.

  Furthermore, an example of a manufacturing process of a semiconductor device having a CMOS structure will be described as an example of a device manufacturing process. First, a semiconductor device manufacturing process is roughly divided into a transistor process and a wiring process.

[Transistor process]
In the transistor process, a portion indicated by A in FIG. 2, that is, a transistor portion is formed. First, in the oxidation / ion implantation apparatus 940, the wafer is oxidized to form a silicon oxide film, and then a photoresist is applied in the C / D 310, a circuit pattern or the like is transferred in the exposure apparatus 100, and development is performed in the C / D 310. Do. An element isolation region is formed in a portion where the photoresist is peeled off by this development. Thereafter, etching is performed in the etching apparatus 920 to remove the silicon oxide film and the silicon portion below the portion where the photoresist is peeled off. After removing the resist, another silicon oxide film is further deposited using the CVD apparatus 910. As a result, another silicon oxide film is deposited on the portion where the silicon portion is etched and the portion of the oxide film deposited first. Next, when polishing is performed by the CMP apparatus 940, only the silicon oxide film deposited on the etched portion of the silicon portion remains. This becomes an element isolation region.

  Next, a so-called well region is formed in the silicon substrate by injecting ions (impurities) with the ion implantation apparatus 940 in the oxidation / ion implantation apparatus 940 to the portion from which the silicon oxide film has been removed.

  Next, in order to form the gate electrode 16 and the oxide film 14, a silicon oxide film and a polycrystalline silicon film are successively deposited by the CVD apparatus 910, a photoresist is applied in the C / D 310, and a circuit pattern is formed in the exposure apparatus 100. Transcript. Then, development by the C / D 310 and etching by the etching apparatus 920 are performed. Thereby, the gate electrode 16 and the oxide film 14 are formed. Next, ions are implanted in the oxidation / ion implantation apparatus 940 to form the source 12 / drain 13. In this way, a transistor is finally produced.

[About wiring process (multiple layers)]
After the transistor process is completed, a multilayer wiring layer shown in FIG. 2B is formed. In order to connect the transistors, a thick insulating film (interlayer insulating film) 15 is deposited on the transistors by the CVD apparatus 910. Next, a resist is applied by C / D 310, the contact hole pattern is transferred by exposure apparatus 100, and development by C / D 310 is performed. Next, the portion of the interlayer insulating film 15 to be wired is removed by etching with the etching apparatus 930 and the wiring material (tungsten) 11 is embedded. Then, when aluminum wiring is performed after the upper portion is planarized by the CMP apparatus 930, an aluminum film of material is deposited on the entire surface, resist coating by the C / D 310, transfer of the wiring pattern by the exposure apparatus 100, and by the C / D 310. Development and etching by an etching apparatus 920 are performed to form the aluminum wiring 10.

  In addition, in the same manner, formation of the interlayer insulating film 15 → resist application → contact hole pattern transfer → development → etching → wiring of wiring material (tungsten) → planarization → aluminum film deposition → resist application → wiring pattern formation Transfer, development, and etching are performed in this order. By repeating the above process, a multilayer wiring layer as shown in FIG. 2 is formed.

  In such a device formation process, the overlay and line width of circuits (device structures) formed on the wafer are measured by the overlay / line width measuring instrument 800 each time. The measurement result is sent to the overlay / line width analysis system 600 and managed. The exposure apparatus 100 stores exposure amount control, synchronization control between the wafer stage and the reticle stage, data relating to AF / L control, focus / synchronization accuracy / exposure amount trace data during scanning exposure. Trace data is also sent to the overlay / line width analysis system 600 and managed. Note that the various trace data acquisition methods and the like are disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-338870, and the detailed description thereof is omitted.

  Also, information on wafer alignment such as the EGA method performed for overlay exposure in the exposure apparatus 100 (for example, the correction amount of the position coordinates of each shot area, the difference between the measured position coordinates and the designed position coordinates, The difference (residual) between the position coordinates and the measured position coordinates is also sent to the overlay / line width analysis system 600 and managed. The EGA wafer alignment is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-44429, and detailed description thereof is omitted.

  In addition, history data (data including names of apparatuses used) of the exposure apparatus 100, C / D 300, device forming apparatus group 900, etc. used in the above process is also used, for example, in-plant production management host system 700, exposure process. The data is sent from the management controller 500 or the like to the overlay / line width analysis system 600 and managed.

  The overlay / line width analysis system 600 analyzes and forms the formation state of the device structure based on the actual measurement data sent from the overlay / line width measuring instrument 800 (that is, the overlay error and the actual measurement value of the line width). evaluate.

  FIG. 3 schematically shows a block diagram showing a software configuration of an evaluation application operating on the overlay / line width analysis system 600. This evaluation application is a multitasking application and includes a main task 610 and an overlay / line width simulation task 630. The main task 610 displays a main window 650 as shown in FIG. 4 on the overlay / line width analysis system 600 display when this application is activated. When an instruction is input from the operator by clicking a pull-down menu or various buttons in the main window 650 via a mouse, a keyboard, or the like, the overlay / line width simulation task 630 is performed according to the instruction. Or data related to the designated product is read from the storage device 640 as necessary. Further, based on the read measurement results, various trace data, data on wafer alignment, and the like, the overlay / line width data of the device structure formed on the wafer of the product is calculated. In addition to the above-described data, the storage device 640 stores design information of a device structure to be formed.

  This overlay / line width data is sent to the main task 610. The main task 610 displays the data in a graph format, a map format, or a graphic image format in the main window 650 or a pop-up window displayed by clicking various buttons on the main window 650.

<Main window>
As shown in FIG. 4, the main window 650 displays a process information display field 651, three graphs, several pull-down menus, and various buttons.

  The process information display column <Process Information> 651 includes a product name display column “Product Name” of the product to be evaluated, a process number display column “Number of LOT Process” of the lot, and the number of processes in the product. Display column “Number of Wafer”, a wafer number display column “Number of Wafer”, a shot area number display column “Number of Shot”, and a comment display column “Comment”. In FIG. 4, the product name DX-76543 is selected, and as its attribute information, it is displayed that the number of processes is 10, the number of wafers is 10, the number of shots is 10, and the comment is manufactured on January 21, 2005. This product is selected in advance by the operator's designation.

  Above the three graphs 652, 653, and 654, the graph names <LOT Process Control Graph>, <Wafer Process Control Graph>, and <Shot Process Control Graph> are displayed. A <LOT Process Control Graph> graph 652 is a graph representing a line width and an overlay error in a plurality of processes, and a <Wafer Process Control Graph> 653 is a graph representing a line width and an overlay error in a plurality of wafers. Yes, <Shot Process Control Graph> 654 is a graph showing the line width and overlay error in a plurality of shot regions. Display of line graphs and the like in these graph displays 652, 653, and 654 is realized by the calculation operation of the overlay / line width simulation task 630 and the display operation of the main task 610 as described above. Three graphs 652, 653, and 654 displayed on the main window 650 schematically show data waveforms regarding the formation state of each device structure over a plurality of processes, a plurality of wafers, and a plurality of shot regions. This graph should be called a thermal graph. By displaying these graphs 652, 653, 654, etc., for example, which process, which wafer, in which shot area, the line width and the overlay are not clearly understood can be seen at a glance.

  Below the process information display field 651, a display data setting check box group <Display Data> 655 and a display coordinate axis setting check box group <Display Axis> 656 are displayed. Each setting check box group 655 is set so that only one check box can be checked at a time. <Display Data> In 655, when CD & Overlay is checked, both line width and overlay error data are displayed in graphs 652, 653, and 654. When CD is checked, only line width data is displayed. When checking Overlay, only overlay error data is displayed. In <Display Axis> 656, when XY is checked, both X-axis and Y-axis data are displayed. When X is checked, only X-axis data is displayed, and Y is checked. Then, only the Y-axis data is displayed. In FIG. 4, since CD & Overlay is checked and X is checked, the three graphs 652, 653, and 654 both display the line width and overlay error regarding the X axis. The operator checks each setting check box using a mouse or the like to determine whether the data to be displayed is both the line width and the overlay error, or only one of them, and the coordinate axes to be displayed are Select either XY or both.

In <LOT Process Control Graph> 652, the line width corresponding to the ten processes A to J and the overlay error are displayed by a line graph and an arrow. FIG. 5 shows details of the graph 652. In this graph 652, the line width of the device structure corresponding to each process and the absolute value | X _MEAN | of the average value of the overlay error are shown by a line graph, and ± 3σ with reference to | X _MEAN | The range corresponding to is represented by up and down arrows.

  This graph display is realized as follows. First, when a product name is selected by the operator, the information is sent to the overlay / line width simulation task 630 via the main task 610. The overlay / line width simulation task 630 receives an electrical circuit (device structure) formed from the storage device 640, such as overlay error and measured line width in each process of the lot corresponding to the product name. ) And the device structure overlay error, the average value of the line width, and the 3σ value in each process are calculated and sent to the main task 610 based on the data. The main task 610 displays the device structure overlay error, the average value of the line width, and the 3σ value in each process sent as a line or an arrow.

  A pull-down menu “LOT Process Name” 657 for specifying a process is displayed in the upper right upper part of the main window 650 in FIG. In this pull-down menu, one of processes A to J can be selected by mouse operation or key input. In FIG. 4, process D is selected in this pull-down menu. Then, as illustrated in FIG. 5, a vertical line (designated line) α indicating that the process is designated is displayed in the process D of <LOT Process Control Graph>.

  In addition to the designation by the pull-down menu 657, it is also possible to designate a process by directly clicking the mouse in the graph 652 in the main window 650. The designation by the mouse operation and the pull-down menu 657 are linked, and the process designated in the graph 652 is displayed on the pull-down menu 657.

When a process is selected by designating the pull-down menu 657 or designating the process in the graph 652 by operating the mouse, <Wafer Process Control Graph> 653 includes 10 wafers 1 to 10 in the lot corresponding to the process D. The line width and overlay error corresponding to are displayed in a line graph or the like. In FIG. 6, an enlarged view of the graph 653 is displayed. In this graph 653, the exposure line width corresponding to each wafer and the absolute value | X _MEAN | of the moving average value of the overlay error are shown by a line graph, and the range of ± 3σ is based on the | X _MEAN |. Expressed by up and down arrows.

  This graph display is realized as follows. First, when a process is designated by the operator, the information is sent to the overlay / line width simulation task 630 via the main task 610. The overlay / line width simulation task 630 forms, from the storage device 640, an electrical circuit (device structure) formed on the wafer, such as an overlay error and an actual measurement value of the line width corresponding to the process. Data related to the result is read, and based on the data, the overlay error of the device structures on each wafer, the average value of the line width, and the 3σ value are calculated and sent to the main task 610. The main task 610 displays the device structure overlay error, the average value of the line width, and the 3σ value on each sent wafer as a line or arrow.

  In the middle part on the right side in the main window 650 in FIG. 4, a pull-down menu <Wafer No. > 659 is displayed. In this pull-down menu 659, one of wafer numbers 1 to 10 can be selected by a mouse operation or key input. In FIG. 4, wafer number 7 is selected in this pull-down menu. Then, as shown in FIG. 6, a vertical line (designated line) β indicating that the wafer is designated is displayed at wafer number 7 of <Wafer Process Control Graph> 653.

  In addition to the specification using the pull-down menu 659, it is also possible to specify the wafer number by clicking the mouse in the graph 653. A designated line β indicating that the wafer is designated is displayed at the wafer number designated by the mouse operation. The designation by the mouse operation and the pull-down menu 659 are linked to each other, and the pull-down menu 659 displays the wafer number designated in the graph 653.

When a wafer number is selected by specifying a pull-down menu 659 or by specifying a wafer number in the graph 653 by operating the mouse, <Shot Process Control Graph> 654 has 10 shot numbers 1 to 10 in the wafer. The line width and overlay error at are displayed in a line graph or the like. In FIG. 7, an enlarged view of the graph 654 is displayed. In this graph 654, the line width corresponding to each shot region and the absolute value | X _MEAN | of the moving average value of the overlay error are shown as a line graph, and the range of ± 3σ is based on the | X _MEAN | Expressed by up and down arrows.

  This graph display is realized as follows. First, when a wafer number is designated by the operator, the information is sent to the overlay / line width simulation task 630 via the main task 610. The overlay / line width simulation task 630 receives, from the storage device 640, the electrical circuit (device structure) in the shot area, such as the overlay error and the measured line width in each shot area corresponding to the wafer number. Data relating to the formation result is read, and based on the data, an overlay error of the device structure in each shot region, an average value of the line width, and a 3σ value are calculated and sent to the main task 610. The main task 610 displays the device structure overlay error, the average line width value, and the 3σ value of each sent shot area as a broken line or an arrow.

  In the lower right part of the main window 650 in FIG. 4, a pull-down menu <Shot No. > 661 is displayed. In this pull-down menu 661, one of shot numbers 1 to 10 can be selected by a mouse operation or key input. In FIG. 4, shot number 3 is selected in this pull-down menu 661. Then, as shown in FIG. 4, a vertical line (designated line) γ indicating that the shot number is designated is displayed in the shot number 3 portion of <Shot Process Control Graph> 654. . It is also possible to select the process, wafer number, shot number, etc. by sliding the designated lines α, β, γ described above with a mouse or the like.

  In addition to the designation using the pull-down menu 661, it is also possible to designate a shot number by clicking the part corresponding to each shot number in the graph. This mouse operation and the pull-down menu 661 are interlocked, and the shot number specified in the graph 654 is displayed on the pull-down menu 661.

<Display graphic image of device structure>
A <LOT / Wafer / Shot Select> button 663 is displayed on the lower left side in the main window 650. When this <LOT / Wafer / Shot Select> button 663 is clicked, a lot process name selection window 693 shown in FIG. 8 is popped up. In the lot process name selection window 693, at least one process can be selected from the processes A to J. FIG. 8 shows that processes A to F are selected from among processes A to H.

  When the OK button in the lot process name selection window 693 is clicked, a wafer number selection window 694 shown in FIG. 9 is popped up. In the wafer number selection window 694, at least one wafer number can be selected from a plurality of wafer numbers. FIG. 9 shows a state in which wafer numbers 1 to 7 are selected from wafer numbers 1 to 8.

  When the OK button of the wafer number selection window 694 is clicked, a shot position / in-shot position selection window 695 shown in FIG. 10 is popped up. In the shot position / in-shot position selection window 695, a matrix corresponding to the shot arrangement is displayed, and selectable shot areas are displayed in gray. In this window 695, at least one shot position can be selected from the shot positions displayed in gray by a mouse operation or the like. FIG. 10 shows a state where the shot position (3, 2) is selected.

  A crosshair cursor is displayed in this window. The cross cursor can be moved in the shot map by operating a mouse or inputting an arrow key on the keyboard. The position designated by the cross cursor is a reference position for displaying a graphic image of the device structure described later.

  When the OK button in the shot position / in-shot position selection window 695 is clicked, the window 695 is closed.

  When the <Device Structure> button 662 in FIG. 4 is clicked in this state, information regarding the designated process, wafer, shot region, and reference position thereof is sent to the overlay / line width simulation task 630. The overlay / line width simulation task 630 includes an overlay error and an actual measurement value of a device structure within a predetermined range with respect to a specified position, and their design information (designed circuit arrangement and line width). Width, etc.) is read from the storage device 640, basic information for displaying a graphic image of the device structure is calculated, and sent to the main task 610. Based on the basic information sent, the main task 610 pops up a graphic image of the device in the area based on the designated position.

  FIG. 11 shows a cross-sectional view of a device structure as an example of the graphic image display, and FIG. 12 shows a top view of the device structure.

  FIG. 11 shows a cross section of the device structure of the three layers (one element layer and two wiring layers) shown in FIG. In this cross-sectional view, the display width of the gate oxide film, gate electrode, source, drain, gate, silicon oxide film, and tungsten reflects the measured overlay error and line width in addition to their design values. ing. That is, by looking at this graphic image, it is possible to confirm the degree of displacement between layers, the size of each component, and the like. In FIG. 11 and FIG. 12, the size of a representative component among the components of the device structure is indicated by an arrow. The same numbers 1 to 5 are attached to the arrows for easy confirmation in association with FIGS.

  A check box “Display Axis” for designating coordinate axes to be displayed is displayed at the lower right of the cross-sectional view window of FIG. 11 and 12, a vector scale (slider) for changing the display scale of the graphic image is displayed. When the setting of the vector scale is changed by a mouse operation or the like, the display scale of the graphic image of the sectional view and the top view is changed according to the setting.

  In the cross-sectional view of FIG. 11, when this vector scale is changed, the display scale in the Z-axis direction also changes in synchronization with the display scale of the X-axis.

  Either one of the sectional view and the top view may be displayed, but both may be displayed. In this case, the sectional view and the top view display the same place. Further, in this case, the display scale of the top view of FIG. 12 may be changed in synchronization with the change of the display scale of the cross-sectional view of FIG. 11, or vice versa.

<Prediction of line width / overlapping error>
If this evaluation application is used, it is possible to predict the line width, overlay accuracy, etc. required in the next process by using the display results relating to the formation state of the device structure so far. For example, if the overlay error in process A is | X _MEAN | _A + 3σ _A [nm] and the overlay error in process B is | X _MEAN | _B + 3σ _B [nm] The total overlay error required in process B is expected to be | X _MEAN | _A + | X _MEAN | _B + √ [(3σ _A ) ² + (3σ _B ) ² ] [nm]. Therefore, when this process B is newly performed, this value can be made the required accuracy.

Further, in consideration of the data regarding the line width in process B, W _B : average line width, W _Design : line width design value, (3σ _L ) ² : line width variation, | X _MEAN | _A + | X _MEAN | _B + (W _B −W _Design ) + √ [(3σ _A ) ² + (3σ _B ) ² + (3σ _L ) ² ] [nm]. Therefore, in this case, when the process B is newly performed, this value can be made the required accuracy.

  The operator can select an apparatus (unit) suitable for the next process based on the predicted value calculated from the display result of the evaluation application. Note that such calculation is performed by the overlay / line width simulation task 630 of the evaluation application and displayed on the display, and a device that satisfies the predicted value (required accuracy) is selected, and the device name of the selected device. May be displayed. For this selection, a matching table described later can be used.

<CD map display>
Returning to FIG. 4, a map display button 660 is displayed in the middle of the right side of the main window 650. When the map display button 660 is clicked in a state where a wafer is designated by the pull-down menu 659 or the like, a shot map window 672 for the designated wafer shown in FIG. 13 is displayed. In this shot map window 672, an array map of shot areas of the wafer, that is, a shot map is displayed. In the shot area of the shot map, data related to the wafer alignment is displayed in vector in a so-called sample shot area that is a measurement target at the time of wafer alignment. This vector may be, for example, a correction amount obtained as a result of wafer alignment, or may be a difference between a design position coordinate of a wafer mark attached to the shot area and an actually measured position coordinate. Alternatively, it may be a difference (residual) between the actually measured position coordinates of the wafer mark and the position coordinates corrected by alignment correction. Hereinafter, the display of these vectors is referred to as a wafer vector map.

  Further, when any one shot area of the displayed shot map is clicked, a CD map window 673 in the shot area is displayed. This CD map is a distribution diagram of the line width error in the selected shot region. By referring to this, the line width uniformity in the shot region can be confirmed.

  As described above, in this evaluation application, the wafer vector map and the CD map can be displayed at the same time, whereby the operator can visually analyze and evaluate the overlay error and the line width. The wafer vector map and the CD map are the above-described graphic display and the data (overlay error and line width) that are the basis for calculating the display data such as the graphs 652, 653, and 654 are directly displayed in the graphic form. is there. Therefore, if the graphic images of FIG. 11 and FIG. 12, the wafer vector map, and the CD map are displayed side by side, the factor analysis that affects the formation state of the device structure can be performed more easily.

<Device matching>
Returning to FIG. 4, a <Matching Information> button 664 is displayed in the lower center portion of the main window 650. When this button 664 is clicked, the main task 610 sends a message to that effect to the overlay / line width simulation task 630. The overlay / line width simulation task 630 uses a combination of an exposure apparatus that performs overlay exposure and an exposure apparatus for a layer that is an object of overlay, by using the overlay error measurement value data stored in the storage device 640. Sort by each. Then, the overlay / line width simulation task 630 calculates an average value of overlay errors for each classified combination. Further, the overlay / line width simulation task 630 sends the calculated data to the main task 610 as data to be displayed on the matching table 682. The main task 610 creates the matching table 682 based on the sent data and displays it on the display. FIG. 14 shows an example of the matching table 682.

  The matching table 682 displays overlay errors between six exposure apparatuses (apparatus names are PA # 1 to PF # 6, respectively). For example, the overlay error in the overlay exposure in the exposure apparatus with the apparatus name PA # 1 and the exposure apparatus with the apparatus name PB # 2 is displayed as 10 nm. According to the matching table 682, it can be determined that the smaller the numerical value is, the devices that can perform better matching. In the matching table 682, locations where the numerical values are small and the matching is good are displayed in gray. The operator can confirm the degree of overlay error between apparatuses by referring to the matching table 682. For example, when a lot process of another lot is performed with the same product, an apparatus (unit) suitable for the next process can be selected with reference to the matching table 682. Further, when one of the devices with the best matching is stopped due to maintenance, it is possible to select a device with the next best matching.

  This matching table 682 can also be used for detecting an abnormality in overlay error. For example, when the overlay error in a certain process is large, the numerical value of the overlay error between the apparatus in the current process and the apparatus in the original process in the matching table 682 is read and is significantly larger than the numerical value (for example, In the case where it is larger than three times, it is possible to consider that the overlay is defective.

  The contents of the matching table 682 are updated each time a process is performed. That is, the overlay measurement result in overlay / line width measuring instrument 800 is sent to overlay / line width analysis system 600. The overlay / line width simulation task 630 of the evaluation application reflects this overlay error in the matching table 682. More specifically, the overlay / line width simulation task 630 calculates the average of the overlay errors between the original process apparatus so far and the current process apparatus, including the sent overlay error. Is registered as data of the matching table 682 in the storage device 640. In this way, the matching table 682 is updated and displayed as described above.

<Process information>
Returning to FIG. 4, a <Process Info> button 658 is displayed in the upper right part of the main window 650. When this button 658 is clicked in a state in which a process is designated by the pull-down menu 657 or the like, the main task 610 reads out data related to the device used in the designated process from the storage device 640 and is shown in FIG. Is displayed on a lot process processing information display window 683. The window 683 includes a product name, a process name, and various apparatuses that process the designated lot process, such as an exposure apparatus, an etching apparatus, a coater / developer, an oxidation / ion implantation apparatus, a CMP apparatus, a film forming apparatus, and a doping apparatus. A device type (System Type), a device name of each device (System Name), and a processing condition (Process Condition) in the device are displayed. In FIG. 15, two types of <part1> and <part2> are displayed as processing conditions. Such processing conditions include, for example, conditions such as which processing unit (processing units 1 and 2) processed in various apparatuses 910 to 940 in the exposure apparatus 100, C / D 310, and device forming apparatus group 900. included.

  By displaying this process information, the operator can confirm which processing conditions (multi-processing conditions, etc.) were used for which line width and overlay measurement results for each lot process. This makes it easier to manage the process.

  For example, referring to the matching table 682 and the like, if it is determined that the overlay is large in a certain process, the apparatus that caused the overlay error and its processing conditions based on the process information in which the overlay error occurred Can be specified. By this specification, for example, it is possible to determine a device that is commonly used in a process in which overlay abnormality occurs. As described above, in this evaluation application, the correlation between the line width and the overlay abnormality between the plurality of processes and the apparatus can be confirmed, so that the apparatus causing the abnormality can be specified. As a result, the apparatus can be readjusted and the device manufacturing yield can be improved.

  As described in detail above, according to the present embodiment, in the main window 650 of the evaluation application of the overlay / line width analysis system 600, a plurality of processes (A to J) in a specified lot and a plurality of in a lot are specified. Fluctuations such as the average value of the measured values of overlay error / line width and the 3σ value over a plurality of shot areas (wafer numbers 1 to 10) and a plurality of shot areas (shot numbers 1 to 10) are displayed in a graph. This graph display allows the operator to check the formation state of the device structure across multiple processes, multiple wafers, and multiple shot areas. However, the burden on the operator who comprehensively evaluates the formation state of the device structure across processes, between wafers, and between shot areas is reduced than when the formation state of the device structure cannot be displayed. The

  In addition, by confirming such a display result, for example, a process, a wafer, or a shot area having a large overlay error or line width error is identified, and the identified process, wafer, or shot area is identified. Various device forming apparatuses can be adjusted so as to improve the overlay and the line width, and as a result, an improvement in device manufacturing yield can be expected.

  More specifically, in the present embodiment, in the main task 610 of the evaluation application, the overlay error and the average of the line width and the 3σ value in each process are related to the formation state of the device structure over a plurality of processes. The graph is displayed as data on a graph 652, and the overlay error and the average of the line width and the 3σ value of each wafer in the lot are transferred to a plurality of wafers (wafer numbers 1 to 10) in the lot. A graph 653 is displayed as data relating to the formation state, and an overlay error, an average line width, and a 3σ value in the same shot region are formed over a plurality of shot regions (shot numbers 1 to 10). Display as status data.

  As described above, in this embodiment, the data displayed in a graph as the formation state of the device structure is the average of the overlay error, the line width, and 3σ, but the present invention is not limited to this. For example, it may be the overlay error and the maximum and minimum values of the line width, or may be the difference between the maximum value and the minimum value. Further, instead of 3σ, it may be 1σ, 5σ, or dispersion. In short, it may be a statistical index value based on information on the formation state of the device structure.

  In the present embodiment, the data to be displayed in the graph is both the overlay error and the line width, but any one of them may be used. Further, not only the line width of the wiring but also data such as the size of the electrode pattern may be displayed. Of course, from the viewpoint of comprehensively evaluating the device formation state, it is of course desirable to display both the overlay error and the line width.

  In this embodiment, the graph display data is the overlay error / line width actually measured by the overlay / line width measuring instrument 800, but is not limited thereto. For example, a value obtained by simulation may be used.

  Such a simulation is performed by the overlay / line width simulation task 630. As described above, the exposure apparatus 100 stores exposure amount control, synchronization control between the wafer stage and the reticle stage, data on AF / L control, focus / synchronization accuracy / exposure amount trace data during scanning exposure. These various types of trace data are also sent to the overlay / line width analysis system 600 and managed. Data relating to wafer alignment performed in the exposure apparatus 100 (data relating to correction amount, measured position, residual, etc.) is also sent to the overlay / line width analysis system 600 for management. The line width and overlay error of the pattern are affected by the process of forming such a device structure. For example, the line width is mainly affected by the focus state at the time of scanning exposure and the exposure amount, and the overlay error is mainly affected by the wafer alignment. Accordingly, it is possible to infer data relating to the formation state of the device structure based on the trace data relating to the formation process of these device structures and the result of wafer alignment. Therefore, the overlay / line width simulation task 630 calculates an overlay error, an estimated value of the line width data, and the like based on the various trace data and data on the wafer alignment, and the main task 610 calculates the calculated overlay. It is possible to display an alignment error and an estimated value of line width data. If the overlay error and the line width can be obtained by estimation, there is no need to actually measure the formation result of the device structure by SEM or the like, which is advantageous for the throughput.

  Further, in the present embodiment, the exposure apparatus 100 that forms each of the plurality of device structures based on the overlay error measured by the overlay / line width measuring machine 800, and the overlay target of the device structures The overlay / line width simulation task 630 obtains an average of overlay errors with the exposure apparatus 100 that forms the device structure. Then, based on the acquired average of overlay errors, the matching table 682 which is a table of information related to matching between the exposure apparatuses 100 is updated, and the updated matching table 682 is displayed. In this way, when performing overlay exposure between different exposure apparatuses 100, the overlay error between the apparatuses registered in the matching table 682 is sequentially updated. The matching can be maintained at a high level, and by using the matching table 682, it is possible to realize a highly accurate mix-and-match overlay exposure.

  Further, according to the present embodiment, the process, wafer, shot area, and position coordinates of the shot area are designated with reference to the main window 650 of the evaluation application. Then, the formation result of the device structure in at least a part of the shot area with reference to the designated process, wafer, shot area, and position coordinates of the shot area (actual value of overlay / line width measuring instrument 800) Based on the data, at least one type of data (such as an overlay error or an average value of line width) regarding the formation state of the device structure is calculated. Furthermore, based on the design information of the device structure in the specified process, wafer, shot area, at least part of the shot area with reference to the position coordinates of the shot area, and its overlay error and line width, Display the graphic image. In this way, if the graphic image of the designated device structure is displayed, the operator can grasp the device structure with a visual image and check the overall formation state, so that the evaluation can be performed. It becomes easy. That is, by adopting the graphic image display, the formation state of the device becomes clear at a glance. Therefore, the present invention can be said to be one of the optimum means for comprehensive evaluation of the formation state of the device.

  When calculating at least one type of data relating to the formation state of the device structure (such as overlay error or average value of line width), the data of the formation process (various trace data or data relating to wafer alignment) may be used. What is good is as described above.

  Further, according to the present embodiment, the graphic image is at least one of the cross-sectional view and the top view, but is not limited thereto, and may be a three-dimensional display such as a perspective view. Further, such a cross-sectional view, top view, and perspective view may be configured such that the viewpoint can be freely changed (that is, the display range can be changed) while being displayed. These graphic images can display the entire device structure or some of them.

  In the present embodiment, the display scale of another coordinate axis is set to be changed in accordance with the change of the display scale related to one of the coordinate axes in the graphic image. In this way, the display scale of the vertical axis and the horizontal axis can be constantly made the same, and an image can be displayed in a state close to the real thing, so that the operator's confirmation work is further facilitated. Here, the display scales of the other coordinate axes may be automatically adjusted so as to be easily understood visually. Of course, the scale may be changed for each axis. In this way, the scale of one axis can be greatly emphasized and displayed.

  In the present embodiment, when two types of graphic images of the device structure are displayed simultaneously (cross-sectional view and top view), the remaining graphic images are changed in accordance with the change of the display scale of any one of the graphic images. The display scale of was changed. In this way, since the top view and the cross-sectional view can always be compared and observed under the same display scale, it is easy to evaluate the formation state of the device structure. However, the present invention is not limited to this, and it is of course possible to cancel the synchronization of the display scales of both graphic images so that the scale of each image can be set individually.

  Further, the graphic image to be displayed may be divided and displayed in two or more parts to be displayed. In this way, it becomes possible to compare two portions that are separated in position.

  In the present embodiment, data relating to a device forming apparatus used for a plurality of processes is acquired every time a process is executed and stored in the storage device 640, and data relating to a specified process is obtained in the evaluation application. indicate. In this way, it becomes possible to specify all the device forming apparatuses that have formed the device structure constituting the device manufactured by the semiconductor manufacturing system 101 later. If the device forming apparatus involved in the device formation can be specified later, it can be used as a clue to prevent the device manufacturing yield when the device manufacturing yield decreases.

  In this embodiment, examples of the device forming apparatus include an exposure apparatus, an etching apparatus, a resist coating apparatus, a developing apparatus, an oxidation / ion implantation apparatus, a polishing apparatus, a film forming apparatus, an overlay measuring instrument, and a line width measuring instrument. However, it goes without saying that other devices may be stored as process information. Further, although a plurality of these device forming apparatuses are provided, it goes without saying that one device may be provided.

  Further, according to the present embodiment, based on the data related to the formation result of each device structure, the overlay error with the device structure of the layer that is the target of the overlay of the device structure is calculated. Then, based on the overlay error, a matching table between the exposure apparatus that forms the device structure and the exposure apparatus that forms the device structure of the layer that is the target of the device structure is obtained. Further, the acquired matching table is displayed. By referring to such a display, it becomes easy to select a combination of devices having a small overlay error, that is, a good matching. In the present embodiment, only the matching table of the exposure apparatus is displayed, but it goes without saying that the matching table may be created and displayed for other device forming apparatuses as well.

  Further, according to the present embodiment, data related to a device forming apparatus that forms a device structure is acquired for each process on the wafer, and data related to the device forming apparatus used in the specified process is displayed. . In this way, it is always possible to identify which device forming apparatus has been used in a process performed in the past.

  In the above embodiment, in the main window 650 of the evaluation application, a graph that spans multiple processes, a graph that spans multiple wafers, and a graph that spans multiple shot areas are displayed simultaneously, but the present invention is not limited to this. At least one type of graph may be displayed. Thus, the present invention is not limited to the specific display form of the evaluation application described above. For example, the line graph may be a bar graph or a variety of graphs such as a pie graph.

  Further, in the above-described embodiment, what is not displayed in the main window is displayed in the pop-up window. However, the present invention is not limited to this, and at least some of them may be displayed in the main window. . In addition, the types, positions, and shapes of various components on the window for specifying processes, wafers, shot areas, and position coordinates thereof can be changed as appropriate.

  The present invention is not limited to a semiconductor manufacturing process, but is also used in a manufacturing process of a display including a liquid crystal display element. The process of transferring a device pattern onto a glass plate, the manufacturing process of a thin film magnetic head, and imaging The present invention can be applied to all device manufacturing processes in addition to manufacturing processes of elements (such as CCDs), micromachines, organic ELs, and DNA chips.

  As described above, the information display system of the present invention is suitable for use in a device manufacturing inspection process or the like.

It is a block diagram which shows the structure of the semiconductor manufacturing system which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the device structure manufactured. It is a block diagram which shows the software structure of the evaluation application in an analysis system. It is a figure which shows an example of the main window of an evaluation application. It is a graph which shows the line | wire width in a several process process, and a superposition result. It is a graph which shows the line width in a some wafer, and the superposition result. It is a graph which shows the line | wire width in a some shot area | region, and the overlay result. It is a figure which shows an example of a lot process name selection window. It is a figure which shows an example of a wafer number selection window. It is a figure which shows an example of the window which selects a shot position and the position coordinate in a shot. It is an example of sectional drawing of the device structure displayed as a graphic image. It is an example of the top view of the device structure displayed as a graphic image. It is a figure which shows an example of the image display of a shot map and CD map. It is a figure which shows an example of the matching table | surface of exposure apparatus. It is a figure which shows an example of the display screen of process information.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Aluminum wiring, 11 ... Tungsten, 12 ... Source, 13 ... Drain, 14 ... Oxide film, 15 ... Interlayer insulation film, 16 ... Gate electrode, 100 ... Exposure apparatus, 101 ... Semiconductor manufacturing system, 300 ... Track, 310 ... Coater / developer, 500 ... Exposure process control controller, 600 ... Overlay / line width analysis system, 610 ... Main task, 630 ... Overlay / line width simulation task, 640 ... Storage device, 650 ... Main window, 651 ... Display field , 652, 653, 654 ... graph, 655, 656 ... check box group, 657 ... pull-down menu, 658 ... button, 659 ... pull-down menu, 660 ... match display button, 661 ... pull-down menu, 662 ... button, 663 ... button, 664 ... button, 67 ... sectional view, 671 ... top view, 672 ... shot map window, 673 ... CD map window, 682 ... matching table, 683 ... lot process processing information display window, 693 ... lot process name selection window, 694 ... wafer number selection window, 695 ... In-shot position selection window, 700 ... In-factory production management host system, 800 ... Overlapping / line width measuring machine, 900 ... Various device forming apparatus groups.

Claims (16)

An information display system for displaying information for evaluating a formation state of a multi-layered device structure formed to overlap each of a plurality of different partition regions on an object in a process unit,
A calculation device that calculates at least one type of information relating to the formation state of the device structure based on information relating to at least one of the formation process and the formation result of each device structure;
An information display system comprising: a display device that displays at least one type of information related to the calculated formation state of the device structure for at least one of a plurality of processes, a plurality of objects, and a plurality of partition regions. The display device
2. The information according to claim 1, wherein a statistical index value of the formation state of the device structure in the same process is displayed as information on the formation state of the device structure over a plurality of processes. Display system. The display device
The statistical index value of the formation state of the device structure with the same object is displayed as information on the formation state of the device structure over a plurality of objects. Information display system. The display device
The statistical index value of the formation state of the device structure in the same partition region is displayed as information on the formation state of the device structure over a plurality of partition regions. The information display system according to any one of the above. The statistical index value of the formation state of the device structure is:
5. The index value based on at least one of the maximum value, the minimum value, the difference between the maximum value and the minimum value, the average value, the deviation, the standard deviation, and the variance. The information display system according to one item. At least one type of information regarding the formation state of the device structure includes:
The information on the size of each component in the device structure and at least one of the information on the overlay with the device structure to be overlapped with the device structure are included. The information display system as described in any one of -5. Information on the size and information on the overlay are as follows:
The information display system according to claim 6, wherein the information display system is at least one of an actually measured value and a value obtained by simulation. Information on matching between a device forming apparatus that forms each of the plurality of device structures and a device forming apparatus that forms a device structure that is a target of overlapping of the device structures based on the information on the superposition. An acquisition device to acquire;
An update device that updates a matching table, which is a table of information related to matching between the device forming devices, based on the acquired information related to matching;
The information display system according to claim 6, further comprising: a matching display device that displays the updated matching table. An information display system for displaying information for evaluating a formation state of a multi-layered device structure formed to overlap each of a plurality of different partition regions on an object in a process unit,
A designation device for designating a process, an object, a partitioned area, and a position coordinate of the partitioned area;
The device based on information regarding at least one of a formation process and a formation result of the device structure in at least a part of the partition area based on the designated process, object, partition area, and position coordinates of the partition area A calculation device for calculating at least one type of information on the formation state of the structure;
Design information of a device structure in at least a part of the partition area based on the designated process, object, partition area, position coordinates of the partition area, and a device structure in at least a part of the partition area And an image display device that displays a graphic image of the device structure formed in at least a part of the partition area based on at least one type of information regarding the formation state of the information.   The information display system according to claim 9, wherein the graphic image of at least a part of the device structure in the partition region is at least one of a sectional view and a top view thereof.   The information display system according to claim 10, wherein a display scale of another coordinate axis is changed according to a change of a display scale related to one of the coordinate axes in the graphic image. The image display device includes:
Simultaneously displaying at least two types of graphic images of at least a portion of the device structure in the partitioned area;
12. The information display system according to claim 11, wherein the display scale of the remaining graphic image is changed in accordance with the change of the display scale of any one graphic image. An acquisition device for acquiring information relating to a device forming apparatus used in the plurality of processes;
The information display system according to claim 1, further comprising: a device information display device that displays information related to a device forming device used in a process designated by the designated device. In the device forming apparatus,
14. The information display system according to claim 13, further comprising at least one of an exposure apparatus, an etching apparatus, a resist coating apparatus, a developing apparatus, an oxidation / ion implantation apparatus, a polishing apparatus, and a film forming apparatus. An information display system for evaluating a multi-layered device structure formed to overlap each of a plurality of different partition areas on an object in a process unit,
A calculation device that calculates information on the overlaying of the device structure on the device structure on the basis of information on at least one of the formation process and the formation result of each device structure;
Based on the calculated information relating to superposition, the device forming apparatus that forms the device structure and the matching between the device forming apparatus that forms the device structure of the layer to be superposed on the device structure A creation device for creating information;
A display device that displays information about the acquired matching. An information display system for evaluating a formation state of a device composed of a plurality of layers of device structures formed so as to be superimposed on each of a plurality of different partition regions on an object in a process unit,
An acquisition device that acquires, for each process, information related to a device forming apparatus that forms a device structure for the object;
An information display system comprising: a device information display device that displays information about a device forming device used in a specified process.