JP2007041980A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of coping with increase in the number of interruption factors and maintaining the acceleration of interruption processing even though a CPU with a small number of interruption factor inputs is used. <P>SOLUTION: Interruption request signals IR<SB>0</SB>to IR<SB>m-1</SB>are given to the CPU 8 and interruption request signals IR<SB>m</SB>to IR<SB>m+n</SB>are given to an interruption expanding means 12. When receiving an interruption request, the interruption expanding means 12 generates a value (interruption vector number) of an operand part of an INT instruction needed for corresponding interruption processing by an instruction generating mean 16, rewrites the value of an operand part of an INT instruction held by a storing means 17 with the generated value and makes an interruption request to the CPU 8. When receiving an interruption request from the instruction generating means 16, the CPU 8 executes the INT instruction held by the storing means 17 to perform interruption processing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus having interrupt expansion means for coping with an increase in the number of interrupt factors.

  In recent years, with the progress of manufacturing technology of information processing devices, the number of peripheral devices that can be mounted on the information processing devices has increased, and more and more information processing devices have been requested due to the demand for a single information processing device to perform many controls. It is required to install peripheral devices. However, if a large number of peripheral devices are installed in the information processing device, the number of interrupt factors to be processed increases. When an existing CPU (central processing unit) is used, an interrupt request from an interrupt processing unit in the CPU is used. There is a problem that the number of inputs is insufficient.

  Here, if the design of the interrupt processing unit in the CPU is changed in accordance with the increase in the number of interrupt factors, it is possible to cope with an insufficient number of interrupt inputs. However, in order to realize this, it is necessary to prepare equivalent functions (interrupt level, mask function, priority order, etc.) for all interrupt factors. There is a problem that the circuit scale of the interrupt processing unit increases.

  In addition, if the interrupt processing unit in the CPU is designed each time as the number of interrupt factors increases, a certain amount of man-hours is required, and the interrupt processing unit is designed in anticipation of the maximum number of interrupt factors. However, if the number of interrupt factors is small, an interrupt processing mechanism that is not used will unnecessarily increase the circuit scale.

Thus, conventionally, for example, an information processing apparatus as shown in FIG. 7 has been proposed. In FIG. 7, IR ₀₁ , IR _0n , IR ₁ and IR _m are interrupt request signals from peripheral devices, and interrupt request signals IR _{02 to} IR _{0 (n-1)} and IR _{2 to} IR _m-1 are illustrated. Is omitted. Reference numeral 1 denotes an OR circuit which performs an OR operation on the interrupt request signals IR _{01 to} IR _0n and outputs an interrupt request signal IR ₀ .

Reference numeral 2 denotes a CPU that executes instructions, 3 ₀ , 3 ₁ , 3 _m are interrupt request signal input terminals of the CPU ₂ , and interrupt request signal input terminals 3 _{2 to} 3 _m-1 are not shown. 4 is an interrupt processing unit inside the CPU 2, 5 is a memory storing an interrupt vector, an interrupt processing program, and the like, 6 is an address bus, and 7 is a data bus.

The information processing apparatus for a plurality of related interrupt request signal IR ₀₁ ~IR _0n, and the logical sum to produce one interrupt request signal IR ₀ in OR circuit 1, an interrupt the interrupt request signal IR ₀ to give the required signal input terminal 3 _0, by sharing a single interrupt request signal input terminal 3 ₀ to a plurality of interrupt request signals IR ₀₁ ~IR _0m, deal with the interrupt request input insufficient interrupt processing section 4 It is what you do.

Figure 8 is a flow chart showing the interrupt processing operation when the interrupt request from the peripheral device sharing the interrupt request signal input terminal 3 ₀ is received in the information processing apparatus. That is, in this information processing apparatus, there is an interrupt request from a peripheral device sharing the interrupt request signal input terminal 3 ₀ and this is accepted (step S1), CPU 2 is a hardware interrupt at a break of the instruction being executed The process is started (step S2).

  That is, the CPU 2 reads the interrupt vector from the vector table of the memory 5, the value of the processor status (PS) indicating the current state of the CPU 2, and the program counter (PC) indicating the address at which execution should be resumed after completion of the interrupt processing. Processing such as saving the value to the stack is performed, and branching to the address indicated by the read interrupt vector is performed (step S2).

Then, the CPU 2 uses a program stored in the branch destination to read a flag indicating whether or not the peripheral device that is the output source of the interrupt request signal IR ₀₁ has made an interrupt request (step S3). It is determined whether or not the peripheral device that is the output source of the signal IR ₀₁ is the actual interrupt request source (step S4), and if the peripheral device that is the output source of the interrupt request signal IR ₀₁ is the actual interrupt request source Then, an interrupt processing program corresponding to the interrupt request from the peripheral device that is the output source of the interrupt request signal IR ₀₁ is executed (step S5), and then the main program is restored (step S10).

On the other hand, when the peripheral device from which the interrupt request signal IR ₀₁ is output is not the actual interrupt request source, the CPU 2 determines whether or not the peripheral device from which the interrupt request signal IR ₀₂ is output has made an interrupt request. leading flag indicating (step S6), and determines whether or not the output source peripheral device of the interrupt request signal IR ₀₂ is an actual interrupt requester (step S7), and the output source near the interrupt request signal IR ₀₂ If the device is an actual interrupt request source, an interrupt processing program corresponding to the interrupt request from the peripheral device that is the output source of the interrupt request signal IR ₀₂ is executed (step S8), and then the main program is restored (step S8). Step S10).

On the contrary, when the output source of the peripheral interrupt request signal IR ₀₂ is not the actual interrupt request source, In the same manner, sequentially the output source of the peripheral interrupt request signals IR ₀₃ ~IR _0n The actual interrupt request source is detected as a target, the corresponding interrupt processing program is executed (step S9), and then the process returns to the main program (step S10).
JP 2001-5676 A JP 55-092950 A JP-A-6-103224

In the conventional information processing apparatus shown in FIG. 7, there is an interrupt request from a peripheral device sharing the interrupt request signal input terminal 3 ₀ and this is accepted, using software, shared interrupt request signal input terminal 3 ₀ The actual interrupt request source is detected for the peripheral device to be detected, but the interrupt request source is detected in a preset order (for example, interrupt priority order).

For this reason, if the peripheral device to which the flag indicating whether or not an interrupt request has been issued is read in the subsequent order is the actual interrupt request source, the time to start interrupt processing will naturally be delayed, time to interrupts from peripheral devices sharing a request signal input terminal 3 ₀ requires process begins by generation, a problem that increasing as compared with the case of not sharing an interrupt request signal input terminal 3 ₀ there were.

  In view of this point, the present invention can cope with an increase in the number of interrupt factors even when using a CPU with a small number of interrupt request inputs, and can maintain high speed interrupt processing. An object is to provide a processing apparatus.

  The information processing apparatus according to the present invention includes a CPU and an interrupt expansion unit having one or more interrupt request inputs. The interrupt expansion unit issues an interrupt request to the CPU when the interrupt request is received, and the CPU interrupts the CPU. A predetermined instruction to be executed by the CPU when an interrupt request from the expansion means is received is held.

  According to the present invention, in addition to the CPU, there is provided interrupt extension means having one or more interrupt request inputs, and the interrupt extension means makes an interrupt request to the CPU when an interrupt request is received. Therefore, even if a CPU with a small number of interrupt request inputs is used, an increase in the number of interrupt factors can be dealt with.

  Further, when the interrupt extension means accepts an interrupt request, the CPU holds a predetermined instruction to be executed when the CPU accepts an interrupt request from the interrupt extension means. When an interrupt request is received, a predetermined instruction held by the interrupt extension means is executed to perform interrupt processing, and the peripheral device that actually made the interrupt request to the interrupt extension means is detected by software. The procedure becomes unnecessary. Therefore, it is possible to maintain high speed interrupt processing.

(First embodiment)
FIG. 1 is a block circuit diagram of the main part of the first embodiment of the present invention. The first embodiment of the present invention includes a CPU 8, a memory 9, an address bus 10, a data bus 11, and an interrupt extension unit 12. IR ₀ , IR _m−1 , IR _m , IR _{m + 1} , IR _{m + n} are interrupt request signals output from the peripheral devices, and are interrupt request signals IR _{1 to} IR _m−2 , IR _{m + 2 to} IR _{m + n-1} is not shown.

The CPU 8 executes instructions. In the CPU 8, 13 ₀ , 13 _m−1 and 13 _m are interrupt request signal input terminals, and the interrupt request signal input terminals 13 _{1 to} 13 _m-2 are not shown. In the first embodiment of the present invention, the interrupt request signal input terminals 13 _{0 to} 13 _m-1 are provided with interrupt request signals IR _{0 to} IR _m-1 output from a peripheral device that is supposed to give an interrupt request signal to the CPU 8. given, the interrupt request signal IR _E interrupt expanding means 12 outputs is applied to the interrupt request signal input terminal 13 _m.

Reference numeral 14 denotes an interrupt processing unit in the CPU 8. Or the interruption processing unit 14 receives the interrupt request signal _{IR 0 ~IR m-1, IR} E, based on the state such as priority and the interrupt level and interrupt mask interrupt factor set in advance, accepts an interrupt request When the CPU 8 determines whether or not to accept, the CPU 8 starts interrupt processing at the break of the instruction being executed, reads the interrupt vector, the processor status (PS) value indicating the current state of the CPU 8 and interrupt processing. Controls the saving of the value of the program counter (PC) indicating the address to be resumed after completion to the stack and the branching process to the address indicated by the read interrupt vector.

  The memory 9 has a vector table storing hardware interrupt vectors and software interrupt vectors, and an interrupt processing program storage area storing interrupt processing programs, and is connected to the CPU 8 by an address bus 10 and a data bus 11. Yes.

The interrupt extension means 12 is for dealing with an increase in the number of interrupt factors. In the interrupt extension means 12, 15 ₀ , 15 ₁ and 15 _n are interrupt request signal input terminals, and the interrupt request signal input terminals 15 ₂ to 15 _n-1 are not shown. In the first embodiment of the present invention, interrupt request signals IR _{m to} IR _{m + n} output from a peripheral device that is supposed to give an interrupt request signal to the interrupt extension means 12 are input to the interrupt request signal input terminals 15 ₀ to 15 _n. Given.

  In the first embodiment of the present invention, the CPU 8 has m + 1 interrupt request signal input terminals, and the interrupt extension means 12 has n + 1 interrupt request signal input terminals. Therefore, when the interrupt expansion unit 12 is not provided, the number of interrupt factors that can be handled is m + 1. However, when the interrupt extension unit 12 is provided, the number of interrupt factors that can be handled is m + n + 1. The number of interrupt factors that can be handled can be increased by n.

The interrupt extension unit 12 includes an instruction generation unit 16, a storage unit 17, and an address decoder 18. The instruction generation means 16 inputs the interrupt request signals IR _{m to} IR _{m + n,} and when receiving the interrupt request, the instruction generation means 16 stores the vector table of the memory 9 as the value of the operand part of the INT instruction (interrupt instruction: INT # u8). generates an interrupt vector number (u8), rewrites the value of the operand portion of the INT instruction storage means 17 is retained in the generated operand part of the value (interrupt vector number), asserts an interrupt request signal IR _E for CPU8 The CPU 8 issues an interrupt request.

  The storage means 17 holds an INT instruction as an instruction to be executed when the CPU 8 receives an interrupt request from the interrupt extension means 12, and also holds a RETI instruction (return instruction) for returning to the main program. The CPU 8 and the data bus 11 are connected. The INT instruction and the RETI instruction may be initialized by the CPU 8, or the instruction code part of the INT instruction and the RETI instruction may be held unnecessarily by the CPU 8.

  The address decoder 18 decodes the address value in the memory space (address space) of the CPU 8 output from the CPU 8 to the address bus 10, and enables the CPU 8 to access the storage means 17.

  In the first embodiment of the present invention, the address indicated by the interrupt vector that is read when the CPU 8 receives an interrupt request from the interrupt extension means 12 is the INT instruction of the storage means 17 when the address decoder 18 decodes it. The value of the address to be held is set. The address indicated by the interrupt vector (software interrupt vector) in the vector table of the memory 9 indicated by the operand value (u8) in the INT instruction is set as the start address of the target interrupt processing program.

  2A and 2B are diagrams showing the word configuration and operation contents of the INT instruction. FIG. 2A shows the word configuration and FIG. 2B shows the operation contents. The interrupt vector number (u8) is unsigned 8-bit data. SSP is a system stack register, PS is a processor status, PC is a program counter, I flag is an interrupt permission flag, S flag is a stack pointer, and TBR is a table base register (a register indicating the start address of an interrupt vector table).

Figure 3 is a diagram showing an example of an interrupt vector number (u8) generated by the instruction generator 16, FIG. 3 (A) interrupt request signal IR _m ~IR _{m + n} is at IR _m ~IR _{m + 2} FIG. 3B shows a case where the interrupt request signals IR _m to IR _{m + n} are IR _m to IR _{m + 5} , and x is “0” or “1”. In the example of FIG. 3B, among the interrupt request signals IR _{m to} IR _{m + 5,} an interrupt request signal with a small subscript value is given priority.

  In the first embodiment of the present invention configured as described above, when the interrupt processing unit 14 receives an interrupt request, the interrupt processing unit 14 generates an interrupt based on a preset priority order of interrupt factors, an interrupt level, an interrupt mask, or the like. Determine whether to accept the request.

Here, for example, when receiving an interrupt request from the peripheral device from which the interrupt request signals IR _{0 to} IR _m-1 are output, the CPU 8 starts hardware interrupt processing at the break of the instruction being executed, A program counter (PC) indicating reading of an interrupt vector (hardware interrupt vector) from the vector table of the memory 9, a value of a processor status (PS) indicating the current state of the CPU 8, and an address at which execution should be resumed after completion of interrupt processing Is saved to the stack, etc., the branch to the address indicated by the read interrupt vector is performed, the interrupt processing program is executed, and when the interrupt processing is completed, the main program is restored.

In contrast, there is an interrupt request to the interrupt expansion means 12, when the interrupt expansion means 12 has performed an interrupt request to the CPU 8 by the interrupt request signal IR _E, CPU 8 is an interrupt request from the interrupt expansion means 12 Is received, interrupt processing is performed as shown in FIG.

That is, when there is an interrupt request to the interrupt extension means 12 from the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output, and the interrupt extension means 12 accepts the interrupt request (step P1), the instruction generation means 16 The value of the operand part (interrupt vector number) of the INT instruction is generated, the value of the operand part of the INT instruction held in the storage means 17 is rewritten with the value of the generated operand part (interrupt vector number), and an interrupt request to the CPU 8 It asserts the signal IR _E, an interrupt request to the CPU 8 (step P2).

  When the CPU 8 receives an interrupt request from the interrupt extension means 12, the CPU 8 starts hardware interrupt processing at the break of the instruction being executed, and stores an interrupt vector (hardware interrupt vector) from the vector table of the memory 9. Reading, saving the value of the processor status (PS) indicating the current state of the CPU 8 and the value of the program counter (PC) indicating the address at which execution is to be resumed after completion of interrupt processing to the stack, etc. A branch to the indicated address is performed (step P3).

  Here, in the first embodiment of the present invention, the address indicated by the interrupt vector that is read when the CPU 8 receives an interrupt request from the interrupt extension means 12 is the address that holds the INT instruction in the storage means 17. Therefore, branching to the address indicated by the interrupt vector in step P3 is performed for the address holding the INT instruction in the storage means 17 of the interrupt extension means 12.

  Then, the CPU 8 reads the INT instruction from the storage means 17 and starts executing the INT instruction (step P4), and software indicated by the value of the operand part (interrupt vector number) of the INT instruction from the vector table of the memory 9 Reads the interrupt vector, saves the value of the processor status (PS) indicating the current state of the CPU 8 and the value of the program counter (PC) indicating the address at which execution is to be resumed after completion of the interrupt processing, and reads the interrupt vector. Branch to the address indicated by the software interrupt vector (step P5).

  Here, in the first embodiment of the present invention, the address indicated by the interrupt vector (software interrupt vector) of the vector table of the memory 9 indicated by the value (interrupt vector number) of the operand part in the INT instruction held by the storage means 17. Indicates the start address of the target interrupt processing program. Therefore, the branch to the address indicated by the software interrupt vector in step P5 holds the target interrupt processing program in the memory 9. This is performed for the head address.

  Then, the CPU 8 executes the target interrupt processing program, starts the return processing to the main program by the RETI instruction described at the end of the target interrupt processing program (step P6), and the storage means 17 The held RETI instruction is executed (step P7), and the process returns to the main program (step S8).

As described above, in the first embodiment of the present invention, the peripheral device that outputs the interrupt request signals IR _{0 to} IR _{m + n is} the same as the peripheral device that outputs the interrupt request signals IR _{0 to} IR _m−1 . The CPU 8 receives the interrupt request signals IR _{0 to} IR _m−1 , and the interrupt extension means 12 receives the interrupt request signal IR _m , divided into groups and groups of peripheral devices from which the interrupt request signals IR _{m to} IR _{m + n} are output. ~ IR _{m + n is} to be received.

Then, the instruction generation means 16 makes an interrupt request to the CPU 8 when receiving an interrupt request from the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output. Therefore, even if the CPU 8 having a small number of interrupt request inputs is used, it is possible to cope with an increase in the number of interrupt factors.

When the instruction generation means 16 receives an interrupt request from the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output, it generates an interrupt vector number (u8) in the vector table of the memory 9; It is assumed that the value (u8) of the operand part of the INT instruction held in the storage means 17 is rewritten with the generated interrupt vector number.

Then, CPU 8, when it has received the interrupt request from the instruction generating means 16, since running INT instruction storage means 17 holds will perform interrupt processing, the interrupt request signal IR _m ~IR _m Of the peripheral devices from which _{+ n} is output, the procedure of detecting the peripheral device that actually made the interrupt request with software is not necessary. Therefore, it is possible to maintain high speed interrupt processing.

  In the first embodiment of the present invention, the case where the storage unit 17 holds the INT instruction has been described. However, other instructions such as an unconditional branch instruction are held, and a branch is made in response to an interrupt request. A value indicating the destination may be generated by the instruction generation means 16, and the value of the operand part of the unconditional branch instruction may be changed with the generated value.

(Second Embodiment)
FIG. 5 is a block circuit diagram of the main part of the second embodiment of the present invention. Similar to the first embodiment of the present invention, the second embodiment of the present invention includes a CPU 8, a memory 9, an address bus 10, a data bus 11, and an interrupt extension means 12. The CPU 8 receives an interrupt request signal. In response to IR _{0 to} IR _m−1 , the interrupt extension means 12 receives the interrupt request signals IR _{m to} IR _{m + n} , but the storage means 17 stores the output source of the interrupt request signals IR _{m to} IR _{m + n} . An instruction sequence of an interrupt processing program corresponding to an interrupt request from a peripheral device is held so that the operand part of some instructions can be changed.

Here, for example, when a plurality of peripheral devices having the same function as the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output, an interrupt request from a plurality of peripheral devices having the same function In the corresponding interrupt processing, for example, only the value of the register address to be accessed is changed, and a common program may be usable for other processing. The second embodiment of the present invention is an information processing apparatus suitable for such a case.

In the second embodiment of the present invention, the storage means 17 holds an interrupt processing program corresponding to an interrupt request from a peripheral device that is the source of output of the interrupt request signals IR _{m to} IR _{m + n.} Is a common instruction sequence 19 common to interrupt processing corresponding to an interrupt request from the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output, and a change target that can be changed according to the received interrupt request And an instruction 20.

  FIG. 6 is a diagram illustrating a word configuration example of the change target instruction 20. For example, the code of the store instruction is held in the instruction code part of the instruction 20 to be changed, and the address (dir) of the register to be directly accessed is held in the operand part. Is generated for each interrupt request received by the instruction generation means 16, and the value of the operand part of the instruction 20 to be changed held by the storage means 17 is rewritten with the value of the generated operand part.

  In the second embodiment of the present invention, the address indicated by the interrupt vector that is read when the CPU 8 receives an interrupt request from the interrupt extension means 12 is the interrupt held by the storage means 17 when the address decoder 18 decodes it. The value is set to be the start address of the processing program.

In the second embodiment of the present invention configured as described above, there is an interrupt request from the peripheral device that is the source of the interrupt request signals IR _{m to} IR _{m + n} to the interrupt extension means 12, and the instruction generation means 16 Upon receipt, the instruction generation means 16 generates the value of the operand part of the change target instruction 20, rewrites the value of the operand part of the change target instruction 20 held by the storage means 17 with the generated value, and interrupts the CPU 8 asserting a request signal IR _E, an interrupt request to the CPU 8.

  When the CPU 8 accepts an interrupt request from the instruction generation means 16, the CPU 8 starts hardware interrupt processing at the break of the instruction being executed, and stores an interrupt vector (hardware interrupt vector) from the vector table of the memory 9. Reading, saving the value of the processor status (PS) indicating the current state of the CPU 8 and the value of the program counter (PC) indicating the address at which execution is to be resumed after completion of interrupt processing to the stack, etc. Branch to the indicated address.

  Here, the address indicated by the interrupt vector (hardware interrupt vector) read when the CPU 8 receives an interrupt request from the interrupt extension means 12 is the interrupt processing program held by the storage means 17 when the address decoder 18 decodes it. Therefore, the branch to the address indicated by the read interrupt vector (hardware interrupt vector) is performed for the start address of the interrupt processing program in the storage means 17. Therefore, the CPU 8 executes the interrupt processing program from the storage means 17 to perform the interrupt processing, and when this is completed, the CPU 8 returns to the main program.

As described above, in the second embodiment of the present invention, the peripheral devices that output the interrupt request signals IR _{0 to} IR _{m + n} are connected to the peripheral devices that output the interrupt request signals IR _{0 to} IR _m−1 . The CPU 8 receives the interrupt request signals IR _{0 to} IR _m−1 , and the interrupt extension means 12 receives the interrupt request signal IR _m , divided into groups and groups of peripheral devices from which the interrupt request signals IR _{m to} IR _{m + n} are output. ~ IR _{m + n is} to be received.

Then, the instruction generation means 16 makes an interrupt request to the CPU 8 when receiving an interrupt request from the peripheral device from which the interrupt request signals IR _{m to} IR _{m + n} are output. Therefore, even if the CPU 8 having a small number of interrupt request inputs is used, it is possible to cope with an increase in the number of interrupt factors.

When the instruction generation unit 16 receives an interrupt request from the peripheral device that is the source of the interrupt request signals IR _{m to} IR _{m + n} , the instruction to be changed 20 necessary for the interrupt processing corresponding to the received interrupt request. The value of the operand part (the value of the register address to be accessed) is generated, and the value of the operand part of the change target instruction 20 held in the storage unit 17 is rewritten with the value of the generated operand part.

When the CPU 8 receives an interrupt request from the instruction generation unit 16, the CPU 8 starts an interrupt process corresponding to the interrupt request. In this case, the CPU 8 executes the interrupt processing program held by the storage unit 17. Thus, the interrupt processing is performed, and the procedure of detecting the peripheral device that actually made the interrupt request among the peripheral devices from which the interrupt request signals IR _{m to} IR _{m + n} are output becomes unnecessary. .

Further, in the interrupt processing corresponding to the interrupt request from the peripheral device that is the source of the interrupt request signals IR _{m to} IR _{m + n} , the value of the register address that is accessed corresponding to the peripheral device that requested the interrupt is changed. For other processing, if a common program can be used, conventionally, the common program is converted into a subroutine, the register address is parameterized, and each interrupt processing routine is called. According to the second embodiment, a fixed interrupt processing program can be executed, and branch processing to a subroutine becomes unnecessary. Therefore, further high speed processing of interrupt processing is possible.

  Further, the storage means 17 is composed of a writable register or RAM so that the CPU 8 can freely set the values of the common instruction sequence 19 and the instruction code portion of the change target instruction 20 set in the storage means 17. Can cope with various interrupt factors without changing hardware.

It is a block circuit diagram of the principal part of 1st Embodiment of this invention. It is a figure which shows the word structure of the INT instruction | command used in 1st Embodiment of this invention, and the content of operation. It is a figure which shows the example of the interrupt vector number which the instruction generation means with which 1st Embodiment of this invention is provided produces | generates. 6 is a flowchart showing an operation example when an interrupt extension unit receives an interrupt request in the first embodiment of the present invention. It is a block circuit diagram of the principal part of 2nd Embodiment of this invention. It is a figure which shows the example of a word structure of the instruction | indication to be changed kept in the memory | storage means of the interrupt expansion means with which 2nd Embodiment of this invention is provided. It is a block circuit diagram of the principal part of an example of the conventional information processor. 8 is a flowchart showing an interrupt processing operation when an interrupt request is received from a peripheral device sharing an interrupt request signal input terminal in the conventional information processing apparatus shown in FIG.

Explanation of symbols

1 ... OR circuit 2 ... CPU
3 ₀ , 3 ₁ , 3 _m ... interrupt request signal input terminal 4 ... interrupt processing unit 5 ... memory 6 ... address bus 7 ... data bus 8 ... CPU
9 ... Memory 10 ... address bus 11 ... data bus 12 ... interrupt expansion means _{13 0, 13 m-1,} 13 m ... interrupt request signal input terminal 14 ... interrupt processing unit _{15 0, 15 1, 15 n} ... interrupt request signal input Terminal 16 ... Instruction generation means 17 ... Storage means 18 ... Address decoder 19 ... Common instruction sequence 20 ... Change target instruction

Claims (4)

CPU,
Having an interrupt extension means having one or more interrupt request inputs;
The interrupt extension means makes an interrupt request to the CPU when an interrupt request is accepted, and holds a predetermined instruction to be executed by the CPU when the CPU accepts an interrupt request from the interrupt extension means. An information processing apparatus characterized by the above. The predetermined instruction is an interrupt instruction,
The interrupt extension means includes
An instruction generation means for receiving an interrupt request;
Storage means for holding the interrupt instruction;
An address decoder that decodes an address in the memory space of the CPU output by the CPU and enables the CPU to access the storage means;
When the instruction generation unit receives an interrupt request, the instruction generation unit generates a value of an operand part of the interrupt instruction according to the received interrupt request, and the interrupt unit held by the storage unit with the generated operand part value The information processing apparatus according to claim 1, wherein the value of the operand part of the instruction is rewritten. The predetermined instruction is an interrupt processing program including a change target instruction,
The interrupt extension means includes
An instruction generation means for receiving an interrupt request;
Storage means for holding the interrupt processing program;
An address decoder that decodes an address in the memory space of the CPU output by the CPU and enables the CPU to access the storage means;
When the instruction generation unit receives an interrupt request, the instruction generation unit generates the value of the operand part of the instruction to be changed according to the received interrupt request, and the storage unit holds the value of the generated operand part The information processing apparatus according to claim 1, wherein the value of the operand part of the instruction to be changed is rewritten. The information processing apparatus according to claim 3, wherein the storage unit is configured to be able to write the interrupt processing program from the CPU.

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