JP2007036320A - Horizontal synchronizing signal output circuit and video reproducer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal synchronizing signal output circuit in which disturbance of a reproduction image due to a copy guard signal is prevented through a simple arrangement even when a PLL circuit not having a mask function is used, and to provide a video reproducer comprising it. <P>SOLUTION: The horizontal synchronizing signal output circuit comprises a synchronization separation circuit receiving a video signal, a PLL circuit receiving a composite synchronizing signal output from the synchronization separation circuit, a first timing circuit receiving a PLL output signal outputted from the PLL circuit, a second timing circuit receiving the composite synchronizing signal and a vertical synchronizing signal output from the synchronization separation circuit, and a gate circuit receiving the output signals from the first and second timing circuits and outputting the horizontal synchronizing signal of the video signal. The PLL circuit comprises an oscillation element circuit, a circuit for varying the PLL frequency of the PLL circuit, and a frequency divider wherein the output signal from the frequency divider becomes a PLL output signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a horizontal synchronizing signal output circuit that outputs a horizontal synchronizing signal included in a video signal, and a video reproducing device such as a display, a projector, or a disk reproducing device including the same.

  For the purpose of protecting the copyright of content such as a movie, the video signal may include a copy guard signal. A video signal to which a copy guard signal is added can be normally displayed on a display device such as a display, while a recording device such as a video tape recorder can maintain a good image quality and cannot record a video signal. . Typically, there is a macrovision signal of an analog video signal, and there is one in which a pseudo synchronization pulse is superimposed on a vertical blanking period (blank period) of the video signal. In this case, the automatic gain control circuit of the video tape recorder erroneously discriminates the pseudo sync pulse from the normal sync pulse, thereby preventing the video signal from being normally recorded.

  However, even in a video signal sync separation IC (integrated circuit) used in a display device such as a display, the horizontal sync signal may not be output accurately during the vertical blanking period after the vertical sync signal containing the copy guard signal. is there. As a result, there is a problem in that a PLL (Phase Locked Loop) circuit connected to the subsequent stage of the synchronization separation IC cannot correctly generate a clock to be supplied, the horizontal synchronization signal is disturbed, and the reproduced video is disturbed.

  Conventionally, during the vertical blanking period, by applying a so-called mask that causes the clock generation PLL circuit for image processing to hold the output of the phase comparator, the PLL processing is interrupted during this period, and the horizontal synchronization corresponding to this problem There is a signal output circuit (Patent Document 1).

JP 2001-94825 A (FIG. 1)

  However, when a PLL circuit that does not have many mask functions is used for the horizontal synchronizing signal output circuit, it is difficult to implement the conventional method. In other words, when selecting a PLL circuit, there is a problem that options for components constituting the horizontal synchronizing signal output circuit are limited in order to cope with the problem of the disturbance of the reproduced video caused by the copy guard signal.

  The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention relates to a horizontal synchronizing signal output circuit and a video reproducing apparatus including the same, and uses a PLL circuit having no mask function. Therefore, it is an object of the present invention to provide a horizontal synchronizing signal output circuit that does not cause disturbance of a reproduced video due to a copy guard signal, and a video reproducing apparatus including the same, with a simple configuration.

  The horizontal sync signal output circuit of the present invention includes a sync separator circuit to which a video signal is input, a PLL circuit to which a composite sync signal output from the sync separator circuit is input, and an output signal from the PLL circuit. 1 timing circuit, a second timing circuit to which a composite synchronization signal and a vertical synchronization signal output from the synchronization separation circuit are input, an output signal from the first timing circuit and an output signal from the second timing circuit are input to a video signal And a gate circuit that outputs a horizontal synchronization signal of the PLL circuit, the PLL circuit includes an oscillation element circuit, a frequency variable circuit that varies a PLL frequency of the PLL circuit, and a frequency divider, and the output signal of the frequency divider is PLL Output signal.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the PLL circuit includes a VCXO (voltage controlled crystal oscillator) having an oscillation element circuit including a crystal oscillator and a frequency variable circuit including a variable capacitor.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the variable range of the PLL frequency of the PLL circuit is set to a range of ± 1% of the oscillation frequency of the crystal oscillator.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the PLL circuit includes a phase detector and an LPF.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the first timing circuit has a pulse width of the horizontal synchronizing signal included in the composite synchronizing signal output from the synchronizing separation circuit based on the input PLL output signal. A pulse signal with a wide pulse width is output.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the first timing circuit receives a plurality of timing pulse signals from the frequency divider as a PLL output signal and is approximately equal to a time corresponding to two pulse widths of the horizontal synchronizing signal. A logic circuit that outputs a pulse signal having a pulse width is included.

  In the horizontal synchronization signal output circuit of the present invention, the second timing circuit has a pulse component equal to the frequency of the horizontal synchronization signal included in the composite synchronization signal based on the composite synchronization signal output from the synchronization separation circuit. In addition, a pulse signal having the same polarity in the vertical blanking period of the video signal is output.

  Preferably, in the horizontal synchronizing signal output circuit of the present invention, the second timing circuit outputs a pulse signal obtained by inverting the vertical synchronizing signal portion included in the composite synchronizing signal, and a pulse from the first logic circuit. A monostable multivibrator that time-shifts the signal, and a second logic circuit that outputs a pulse signal excluding the horizontal synchronizing signal portion of the composite synchronizing signal.

  Preferably, in the horizontal synchronization signal output circuit of the present invention, the second timing circuit receives the output signal from the monostable multivibrator and the output signal from the second logic circuit, and the frequency of the horizontal synchronization signal included in the composite synchronization signal And a logic circuit that outputs a pulse signal having the same pulse component and having the same polarity in the vertical blanking period of the video signal.

  The video reproduction apparatus according to the present invention includes any one of the horizontal synchronizing signal output circuits described above.

  The operation of the present invention will be described below.

  The horizontal synchronization signal output circuit of the present invention receives a synchronization separation circuit, a PLL circuit, a first timing circuit, a second timing circuit, an output signal of the first timing circuit, and an output signal of the second timing circuit. A gate circuit. When the video signal is input to the sync separation circuit, a horizontal sync signal of the video signal is output from the gate circuit. The video reproduction apparatus of the present invention includes the horizontal synchronization signal output circuit, and displays a video signal based on the output horizontal synchronization signal.

  A composite sync signal and a vertical sync signal are output from the sync separation circuit to which the video signal is input. The composite synchronization signal is input to the PLL circuit and the second timing circuit. The vertical synchronization signal is input to the second timing circuit. Further, a plurality of timing pulse signals from the frequency divider are input to the first timing circuit as PLL output signals.

  The PLL circuit to which the composite synchronization signal is input preferably includes a phase detector, an LPF, a VCXO (voltage controlled crystal oscillator), and a frequency divider, and the output signal of the frequency divider is a PLL output signal. . The PLL circuit includes a VCXO (voltage controlled crystal oscillator) having an oscillation element circuit including a crystal oscillator and a frequency variable circuit including a variable capacitor. Preferably, the variable range of the PLL frequency of the PLL circuit is a crystal oscillation. It is set within a range of ± 1% of the oscillation frequency of the child. Therefore, since the PLL circuit locks only to a narrow frequency range including the horizontal synchronizing signal, as a result, the PLL output signal from which the vertical synchronizing pulse, equivalent pulse, and copy guard signal included in the composite synchronizing signal are removed, that is, substantially horizontal. A pulse signal having only a synchronization signal component can be output.

  The PLL output signal from the PLL circuit is a pulse signal that includes substantially only the horizontal synchronizing signal component, but includes jitter caused by the PLL circuit. Therefore, the PLL output signal is used as a gate signal for extracting a horizontal synchronizing signal from a pulse signal output from a second timing circuit described later. The first timing circuit to which the PLL output signal is input receives a plurality of timing pulse signals from the frequency divider as the PLL output signal, and a pulse having a pulse width wider than the pulse width of the horizontal synchronizing signal included in the composite synchronizing signal. The signal is output and input to the gate circuit. Preferably, the first timing circuit receives a plurality of timing pulse signals from the frequency divider as a PLL output signal and outputs a pulse signal having a pulse width substantially equal to a time corresponding to two pulse widths of the horizontal synchronization signal. A logic circuit may be included.

  Further, the second timing circuit outputs a first logic circuit that outputs a pulse signal obtained by inverting the vertical synchronization signal portion included in the composite synchronization signal, a monostable multivibrator that time-shifts the pulse signal from the first logic circuit, A second logic circuit for outputting a pulse signal excluding the horizontal synchronizing signal portion of the composite synchronizing signal, and a logic for receiving the output signal from the monostable multivibrator and the output signal from the second logic circuit and outputting the composite horizontal synchronizing signal; A signal obtained by inverting the vertical synchronization signal portion included in the composite synchronization signal output from the synchronization separation circuit and input to the gate circuit. In other words, the second timing circuit inverts the polarity of the vertical synchronizing pulse period, has a pulse component equal to the frequency of the horizontal synchronizing signal included in the composite synchronizing signal, and has a polarity in the vertical blanking period of the video signal. The matched pulse signal is output as a composite horizontal synchronizing signal. As a result, the horizontal synchronization signal included in the output composite horizontal synchronization signal becomes a pulse signal having the same polarity as the whole. Therefore, the composite horizontal synchronization signal output from the second timing circuit includes an accurate horizontal synchronization signal without jitter although it includes a copy guard signal and the like, and this is input to the gate circuit.

  As a result, the horizontal synchronization signal of the video signal from which the copy guard signal and the like are removed is output from the gate circuit to which the output signal of the first timing circuit and the output signal of the second timing circuit are input. Even when the video signal includes a copy guard signal, a stable and accurate horizontal synchronization signal is output, and the playback video is not disturbed. In addition, since it is not necessary to apply a mask during the vertical synchronization period, it is possible to widen the options of components constituting the horizontal synchronization signal output circuit.

  The horizontal synchronizing signal output circuit and the video reproduction apparatus including the same according to the present invention can display a stable video signal without being affected by the copy guard signal.

  The horizontal synchronization signal output circuit and the video reproduction apparatus including the horizontal synchronization signal output circuit according to the present invention have a simple configuration and the reproduction video is disturbed due to the copy guard signal even when a PLL circuit without a mask function is used. For the purpose of providing a horizontal sync signal output circuit that does not occur, a sync separator circuit to which a video signal is input, a PLL circuit to which a composite sync signal output from the sync separator circuit is input, and an output signal from the PLL circuit are The first timing circuit that is input, the second timing circuit that receives the composite synchronization signal and the vertical synchronization signal that are output from the synchronization separation circuit, the output signal of the first timing circuit, and the output signal of the second timing circuit that are input And a gate circuit that outputs a horizontal synchronizing signal of the video signal, and the PLL circuit varies the PLL frequency of the oscillation element circuit and the PLL circuit. And the wave number variable circuit, and a frequency divider, by the output signal of the frequency divider and PLL output signal, was realized.

  Hereinafter, a horizontal synchronizing signal output circuit and a video reproduction apparatus including the same according to preferred embodiments of the present invention will be described, but the present invention is not limited to these embodiments.

  FIG. 1 is a diagram for explaining a horizontal synchronizing signal output circuit 1 according to a preferred embodiment of the present invention. The horizontal synchronization signal output circuit 1 is included in a projector (not shown) that reproduces video. The horizontal synchronizing signal output circuit 1 is connected to a synchronizing separation circuit 3, a PLL circuit 4, a first timing circuit 5, a second timing circuit 6, and an output terminal 8 connected to an input terminal 2 to which a video signal is input. And a gate circuit 7. When the video signal S0 is input to the input terminal 2, the horizontal synchronization signal output circuit 1 outputs a horizontal synchronization signal Hsync from the output terminal 8. The projector performs horizontal synchronization based on the horizontal synchronization signal Hsync to project and reproduce the video signal S0.

  FIG. 2A is a schematic diagram illustrating the video signal S0. When the video signal S0 is input from the input terminal 2, the sync separation circuit 3 outputs a composite sync signal (Composite Sync) CS and a vertical sync signal Vsync from the video signal S0. The composite synchronization signal CS includes a horizontal synchronization signal Hsync, a front equivalent pulse signal (not shown in FIG. 2A), a vertical synchronization signal Vsync, a rear equivalent pulse signal GT, and a copy guard signal CG. This is a signal obtained by synchronizing and separating the video signal S0. The copy guard signal CG is a pseudo synchronization pulse superimposed on a period after the post-equivalent equivalent pulse signal GT following the vertical synchronization signal Vsync, that is, a vertical blanking period (blank period) Vblank shown in the figure, and has a pulse width of about 2 μsec. These four pulses constitute one block at an interval of about 7 μsec, and are superposed following the eight horizontal synchronization signals Hsync. The copy guard signal CG is a pulse signal having a frequency higher than that of the horizontal synchronization signal Hsync, and is about 111 KHz in the illustrated case. The vertical synchronization signal Vsync is a pulse signal of about 31.5 KHz, and the post-equivalent pulse signal GT is a pulse signal of about 31.5 KHz.

  FIG. 2B is a schematic diagram illustrating the horizontal synchronization signal Hsync extracted from the composite synchronization signal CS. Preferably, the horizontal synchronization signal Hsync is a pulse signal of 15.75 KHz, and the pulse interval is about 63 μsec and the pulse width is about 5 μsec. In order to project and reproduce the video signal S0, the horizontal synchronization signal output circuit 1 outputs a horizontal synchronization signal Hsync obtained by removing the copy guard signal CG from the composite synchronization signal CS. In other words, the composite synchronization signal CS has a pre-equivalent pulse, a vertical synchronization signal Vsync, a post-equivalent pulse signal GT, and a copy guard signal CG superimposed on the horizontal synchronization signal Hsync in order for each period. Therefore, the horizontal synchronization signal output circuit 1 extracts and outputs only the horizontal synchronization signal Hsync. When the horizontal synchronizing signal Hsync is included in the video signal S0, the polarity of the horizontal synchronizing signal Hsync is inverted during the period in which the vertical synchronizing signal Vsync is superimposed.

  The composite synchronization signal CS is input from the synchronization separation circuit 3 to the PLL circuit 4 of the horizontal synchronization signal output circuit 1. The PLL circuit 4 includes a phase detector 41, an LPF (low-pass filter) 42, a frequency variable circuit 43 of a VCXO (voltage controlled crystal oscillator) that varies the PLL frequency fp of the PLL circuit 4, and an oscillation element circuit 44 of the VCXO. And a frequency divider 45. The VCXO includes a frequency variable circuit 43 and an oscillation element circuit 44. The phase detector 41 receives the composite synchronization signal CS and the PLL output signal SP which is the output signal of the frequency divider 45 and the output signal of the PLL circuit 4, thereby forming a PLL loop. As a result, the PLL circuit 4 outputs a pulse signal whose phase is locked to the PLL frequency fp from the composite synchronization signal CS.

  FIG. 3 is a diagram for explaining the details of the horizontal synchronizing signal output circuit 1. 3 shows a part of the PLL circuit 4 (the VCXO frequency variable circuit 43, the VCXO oscillation element circuit 44, and the frequency divider 45), the first timing circuit 5, the second timing circuit 6, and the gate circuit 7. The output terminal 8 is shown. FIG. 4 is a waveform diagram showing a pulse signal waveform in the horizontal synchronization signal output circuit 1. The composite synchronization signal CS output from the synchronization separation circuit 3, the vertical synchronization signal Vsync, and the output signal S 2 of the second timing circuit 6. 3 shows a pulse signal waveform at points a to e in FIG. 3, an output signal S1 of the first timing circuit 5, and a horizontal synchronization signal Hsync. Further, FIG. 5 is a waveform diagram showing a pulse signal waveform in the horizontal synchronizing signal output circuit 1, and shows a pulse signal waveform at points A to C of the frequency divider 45. The pulse signals at points B and C of the frequency divider 45 become input signals to the first timing circuit 5, and the output signal S 1 is output from the first timing circuit 5.

  First, the configuration and operation of the second timing circuit 6 of the horizontal synchronizing signal output circuit 1 will be described. The composite sync signal CS is a pulse signal that approximates the sync pulse signal waveform obtained by inverting the phase of the video signal S0, and is omitted from the second block of the copy guard signal CG in FIG. The second timing circuit 6 includes a first logic circuit that outputs a pulse signal obtained by inverting the vertical synchronization signal Vsync included in the composite synchronization signal CS, and a monostable multivibrator that time-shifts the pulse signal from the first logic circuit. And a second logic circuit for extracting and outputting a pulse signal excluding the horizontal sync signal portion of the composite sync signal, and an output signal from the monostable multivibrator and an output signal from the second logic circuit to receive the composite horizontal sync And a logic circuit that outputs the signal S2. Specifically, the first logic circuit includes a plurality of logic circuits, and receives an AND circuit 61 to which the composite synchronization signal CS and the vertical synchronization signal Vsync are input, and an output (point a) of the AND circuit 61. It includes a NOT circuit 62 and an AND circuit 63 to which the output (point b) of the NOT circuit 62 and the vertical synchronization signal Vsync are input. The second logic circuit includes a NOT circuit 64 to which the vertical synchronization signal Vsync is input, and an AND circuit 65 to which the output of the NOT circuit 64 and the composite synchronization signal CS are input. The logic circuit that outputs the composite horizontal synchronizing signal S2 is composed of an OR circuit 67.

  The monostable multivibrator 66 receives the output (point c) of the AND circuit 63 of the first logic circuit, and adds a time shift substantially equal to the pulse width of the horizontal synchronization signal Hsync starting from the falling edge of the pulse. Then, during the period of the vertical synchronization signal Vsync, a pulse signal that complements the horizontal synchronization signal that is missing from the output (point e) of the AND circuit 65 is output (point d). The output of the monostable multivibrator 66 (point d) and the output of the AND circuit 65 (point e) are input to the OR circuit 67, and the output signal S2 of the second timing circuit 6 is output. As a result, the output signal (composite horizontal synchronization signal) S2 of the second timing circuit 6 is a pulse signal including a front equivalent pulse, a vertical synchronization signal Vsync, a rear equivalent pulse signal GT, and a copy guard signal CG. However, it is output as a pulse signal in which the polarities of the horizontal synchronizing signal Hsync included in the composite synchronizing signal CS are made to coincide with each other. That is, the output signal (composite horizontal sync signal) S2 of the second timing circuit has a pulse component equal to the frequency of the horizontal sync signal included in the composite sync signal, and has the same polarity in the vertical blanking period of the video signal. Pulse signal.

  On the other hand, the composite synchronizing signal CS is input to the frequency variable circuit 43 of the VCXO including the variable capacitor 43a through the LPF 42 in the PLL circuit 4. The frequency variable circuit 43 is connected to a VCXO oscillation element circuit 44 including a crystal oscillator 44a, a coil 44b, and a trimmer 44c, and variably adjusts the oscillation frequency fv of the oscillation element circuit 44 including the crystal oscillator 44a. it can. The pulse signal having the oscillation frequency fv is divided by the frequency divider 45, and a PLL output signal SP having the PLL frequency fp is output. The PLL output signal SP is output from the frequency divider 45 to the phase detector 41 of the PLL circuit 4. Therefore, by changing the oscillation frequency fv by the frequency variable circuit 43 and setting the PLL frequency fp to 15.75 KHz which is the frequency of the horizontal synchronization signal Hsync, the output signal of the PLL circuit 4 is included in the composite synchronization signal CS. A pulse signal whose phase is locked to the horizontal synchronization signal Hsync can be used.

  Preferably, the variable range of the PLL frequency fp of the PLL circuit 4 is set to a range of ± 1% of the oscillation frequency fv of the oscillation element circuit 44 of the VCXO. Since the range of the oscillation frequency fv of the oscillation element circuit 44 including the crystal oscillator 44a is limited, the PLL circuit 4 is phase-locked only with the set PLL frequency fp, that is, a narrow frequency range including the horizontal synchronization signal Hsync. To do. Therefore, the PLL circuit 4 outputs the vertical synchronization pulse Vsync included in the composite synchronization signal CS, the post-equivalent pulse signal GT, and the output signal from which these are removed without being phase locked to the copy guard signal CG, that is, approximately A PLL output signal whose phase is locked only to the horizontal synchronization signal Hsync is obtained.

  For example, if the oscillation element circuit 44 of the VCXO is oscillating at the oscillation frequency fv = 18.4275 MHz by the crystal oscillator 44a, the frequency divider 45 divides the pulse signal by the inputted crystal oscillator by 1/1170. Then, a pulse signal of 15.75 KHz which is the frequency of the horizontal synchronization signal Hsync is output. Specifically, the frequency divider 45 includes a frequency divider 45a that divides 1/9, a frequency divider 45b that divides 1/10, and a frequency divider 45c that divides 1/13. Configured to achieve 1/1170 frequency division. To explain it conceptually, the oscillation frequency fv is in the range of ± 1% of 18.4275 MHz by the variable capacitor 43a, the coil 44b and the trimmer 44c connected in series to the oscillation element circuit 44 of the VCXO. It should just be adjusted to the range of 275 kHz (18.243225 MHz-18.611775 MHz). Even if the oscillation frequency of the oscillation element circuit 44 of the VCXO is slightly shifted to 18.4300 MHz, the oscillation frequency fv by the frequency variable circuit 43 of the VCXO can be adjusted, so that the PLL frequency fp is accurate. 15.75 KHz can be set. More preferably, in order to avoid the influence of the copy guard signal CG included in the composite synchronization signal CS, the variable capacitor 43a and the trimmer 44c are set so as to limit the variable range of the oscillation frequency fv to a narrower range. For example, the variable range may be ± 10 kHz. That is, when the oscillation frequency fv is 18.4275 MHz, the oscillation frequency fv may be limited to a range of 18.4175 MHz to 18.4375 MHz that is ± 0.54% or less.

  A plurality of timing pulses QB and QC are input to the first timing circuit 5 from the frequency divider 45 of the PLL circuit 4. Here, the first timing circuit 5 is a NOR circuit as a logic circuit to which the timing pulses QB and QC are input, and outputs an output signal S1 that is a pulse signal having a pulse width wider than the pulse width of the horizontal synchronization signal Hsync. To do. The PLL output signal phase-locked by the PLL circuit 4 is a pulse signal having only the component of the horizontal synchronization signal Hsync as described above, but includes jitter caused by the PLL circuit 4. Therefore, in the horizontal synchronization signal output circuit 1, the output signal S1 of the first timing circuit 5 is used as a gate signal for extracting the horizontal synchronization signal Hsync from the output signal S2 from the second timing circuit 6 described above. Here, in order to cope with jitter caused by the PLL circuit 4, the first timing circuit 5 generates a pulse signal S1 having a pulse width wider than the pulse width of the horizontal synchronization signal as a gate signal. Preferably, the pulse signal S1 has a pulse width substantially equal to the time corresponding to two pulse widths of the horizontal synchronization signal.

  Specifically, a pulse signal of 204.75 kHz (pulse interval of about 4.9 μsec) output from the frequency divider 45b (point A) is input to the frequency divider 45c. The 204.75 kHz pulse signal at (Point A) is a pulse signal obtained by dividing 18.475 MHz of the oscillation element circuit 44 of the VCXO by 1/90. The frequency divider 45c further divides the pulse signal of 204.75 kHz by 1/13 and outputs a pulse signal S1 of 15.75 KHz whose frequency is equal to the horizontal synchronization signal Hsync. Here, the frequency divider 45c outputs timing pulses QB (point B) and QC (point C) over a plurality of pulse intervals based on the pulse signal of 204.75 kHz. As shown in the waveform diagram of FIG. 5, the timing pulses QB and QC have the same polarity at intervals of two pulse signals of 204.75 kHz, that is, between about 9.8 μsec. The NOR circuit of the first timing circuit 5 to which the pulses QB and QC are input outputs a pulse signal S1 having a frequency of 15.75 KHz and a pulse width of about 9.8 μsec. In this embodiment, since the pulse width of the horizontal synchronization signal Hsync is about 5 μsec, the pulse width of the pulse signal S1 is wider than the pulse width of the horizontal synchronization signal Hsync included in the composite synchronization signal CS. Therefore, it is almost equal to the time corresponding to two pulse widths of the horizontal synchronizing signal Hsync.

  On the other hand, the pulse signal (composite horizontal synchronization signal) S2 output from the second timing circuit 6 is obtained by inverting the polarity of the portion of the vertical synchronization signal Vsync with respect to the composite synchronization signal CS, thereby causing the horizontal synchronization included in the composite synchronization signal CS. The polarity of the signal Hsync is matched as a whole. The horizontal synchronization signal Hsync component included in the pulse signal S2 is an accurate pulse signal without jitter and has the same polarity, and is input to the gate circuit 7. For example, when the horizontal synchronization signal Hsync is 15.75 KHz, the pulse signal S2 output from the second timing circuit includes an accurate 15.75 KHz horizontal synchronization signal without jitter, a copy guard signal CG, and the like. This is input to the gate circuit 7.

  The gate circuit 7 inputs the pulse signal S1 from the first timing circuit 5 as a gate signal, the pulse signal S2 from the second timing circuit 6 as a signal to be gated, and the horizontal synchronization signal Hsync to the output terminal 8 Output. The pulse signal S2 is phase-locked only in a narrow frequency range including the horizontal synchronization signal Hsync in addition to the polarity of the horizontal synchronization signal Hsync included in the composite synchronization signal CS being matched as a whole. The pulse signal S1 having a wide pulse width set by the first timing circuit 5 functions as a gate signal that allows only the horizontal synchronization signal Hsync included in the pulse signal S2 to pass therethrough. As a result, the horizontal synchronizing signal Hsync of the video signal S0 from which the copy guard signal CG and the like have been removed is output from the gate circuit 7.

  Therefore, in the horizontal synchronization signal output circuit 1, even when the input video signal S0 includes the copy guard signal CG, a stable and accurate horizontal synchronization signal Hsync is output, and the reproduced video is not disturbed. Even if the copy guard signal CG is a copy guard signal having a frequency different from that described above, if the pseudo guard pulse is superimposed on the vertical blanking period (blank period) Vblank, the PLL circuit 4 is horizontal. Since the phase is locked only in a narrow frequency range including the synchronization signal Hsync, a stable horizontal synchronization signal Hsync can be output.

  In addition, since it is not necessary to apply a mask during the vertical synchronization period, the options of the parts constituting the horizontal synchronization signal output circuit 1 can be expanded, and the cost can be reduced. As a result, the projector including the horizontal synchronization signal output circuit 1 can configure the horizontal synchronization signal output circuit 1 at low cost, and performs horizontal synchronization based on the stable horizontal synchronization signal Hsync to project the video signal S0. Can be played.

  Further, the frequency divider 45 and the first timing circuit 5 of the PLL circuit 4 are not limited to the above embodiment. The PLL circuit 4 may include a frequency divider 45 and a first timing circuit 5. From the pulse width of the horizontal synchronization signal Hsync included in the composite synchronization signal CS output from the synchronization separation circuit 3 so that the pulse signal S1 functions as a gate signal that passes only the horizontal synchronization signal Hsync included in the pulse signal S2. Alternatively, any configuration may be used as long as the pulse signal S1 having a wide pulse width is output.

  Note that if the pulse width of the pulse signal S1 is too wide than the pulse width of the horizontal synchronization signal Hsync, the copy guard signal CG adjacent to the pulse of the horizontal synchronization signal Hsync may pass without being removed. Therefore, it is preferable to set the pulse width appropriately. For example, when the interval between the pulse of the horizontal synchronization signal Hsync having a pulse width of about 5 μsec and the pulse of the adjacent copy guard signal CG is about 4 μsec as in the above embodiment, a pulse signal of 204.75 kHz , That is, a pulse width of about 13.7 μsec, which is wider than two pulse widths of the horizontal synchronization signal Hsync (about 9.8 μsec), is set from the gate circuit 7 to the copy guard. There is a possibility that part of the signal CG passes. Therefore, it is preferable to set the pulse width to be approximately equal to the time corresponding to two pulse widths of the horizontal synchronizing signal. By removing the copy guard signal CG, a stable horizontal synchronizing signal Hsync can be obtained.

  The horizontal synchronizing signal output circuit and the video reproduction apparatus including the same according to the present invention are not limited to the above configuration. The synchronization separation circuit 3 may be any circuit that outputs the composite synchronization signal CS and the vertical synchronization signal Vsync. The PLL circuit 4 has a variable range of the PLL frequency fp including the frequency of the horizontal synchronization signal Hsync. What is necessary is just to be restricted to a narrow range. The first timing circuit 5 may be any logic circuit that converts the PLL output signal SP from the PLL circuit 4 into a signal S1 that functions as a gate signal in the gate circuit 7, and the second timing circuit 6 is a composite circuit. Any logic circuit that has a pulse component equal to the frequency of the horizontal synchronizing signal included in the synchronizing signal and outputs a pulse signal having the same polarity in the vertical blanking period of the video signal may be used.

  The horizontal synchronizing signal output circuit according to the present invention is not only a projector for projecting images and a display installed in a home equipped with a display such as a liquid crystal monitor for displaying images, but also a disk playback device without a display. The present invention can also be applied to a video playback device.

It is a figure explaining the horizontal synchronizing signal output circuit by preferable embodiment of this invention. Example 1 It is the schematic explaining the composite synchronizing signal and horizontal synchronizing signal which the synchronous separation circuit of the horizontal synchronizing signal output circuit by preferable embodiment of this invention outputs. Example 1 It is a figure explaining the detail of the horizontal synchronizing signal output circuit by preferable embodiment of this invention. Example 1 It is a wave form diagram showing the pulse signal waveform in the 2nd timing circuit of the horizontal synchronizing signal output circuit by a desirable embodiment of the present invention. Example 1 It is a wave form diagram showing the pulse signal waveform in the 2nd timing circuit of the horizontal synchronizing signal output circuit by a desirable embodiment of the present invention. Example 1

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Horizontal synchronizing signal output circuit 2 Input terminal 3 Synchronization separation circuit 4 PLL circuit 5 1st timing circuit 6 2nd timing circuit 7 Gate circuit

Claims (10)

A sync separation circuit to which a video signal is input;
A PLL circuit to which a composite synchronization signal output from the synchronization separation circuit is input;
A first timing circuit to which an output signal from the PLL circuit is input;
A second timing circuit to which a composite synchronization signal and a vertical synchronization signal output from the synchronization separation circuit are input;
A gate circuit that receives the output signal of the first timing circuit and the output signal of the second timing circuit and outputs a horizontal synchronization signal of the video signal;
The PLL circuit includes an oscillation element circuit, a frequency variable circuit that varies a PLL frequency of the PLL circuit, and a frequency divider that divides a pulse signal of the PLL frequency, and outputs the output signal of the frequency divider to the PLL. As an output signal,
Horizontal sync signal output circuit. The PLL circuit includes a VCXO having the oscillation element circuit including a crystal oscillator and the frequency variable circuit including a variable capacitor.
The horizontal synchronizing signal output circuit according to claim 1. The variable range of the PLL frequency of the PLL circuit is set to a range of ± 1% of the oscillation frequency of the crystal oscillator.
The horizontal synchronizing signal output circuit according to claim 2. The PLL circuit includes a phase detector and an LPF.
The horizontal synchronizing signal output circuit according to claim 1. The first timing circuit outputs a pulse signal having a pulse width wider than a pulse width of a horizontal synchronization signal included in a composite synchronization signal output from the synchronization separation circuit based on the input PLL output signal.
The horizontal synchronizing signal output circuit according to claim 1. The first timing circuit receives a plurality of timing pulse signals from the frequency divider as the PLL output signal and outputs a pulse signal having a pulse width substantially equal to two pulse widths of the horizontal synchronization signal. Including logic circuits,
The horizontal synchronizing signal output circuit according to claim 5. The second timing circuit has a pulse component equal to the frequency of the horizontal sync signal included in the composite sync signal based on the composite sync signal output from the sync separation circuit, and the vertical feedback of the video signal. Output a pulse signal with the same polarity in the line period,
The horizontal synchronizing signal output circuit according to claim 1. A first logic circuit that outputs a pulse signal obtained by inverting a vertical synchronizing signal portion included in a composite synchronizing signal; and a monostable multivibrator that time-shifts the pulse signal from the first logic circuit; A second logic circuit for outputting a pulse signal excluding a horizontal synchronizing signal portion of the composite synchronizing signal,
The horizontal synchronizing signal output circuit according to claim 7. The second timing circuit receives an output signal from the monostable multivibrator and an output signal from the second logic circuit and has a pulse component equal to a frequency of a horizontal synchronizing signal included in the composite synchronizing signal; and Including a logic circuit that outputs a pulse signal having the same polarity in a vertical blanking period of the video signal,
The horizontal synchronizing signal output circuit according to claim 8. A video reproduction apparatus including the horizontal synchronizing signal output circuit according to claim 1.

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