JP2007035755A - Positional information calculating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly calculate the positional information of a specific chip on a wafer. <P>SOLUTION: In the method of calculating the positional information of each of a plurality of chips 1a formed on the wafer 1, an address in the X direction and an address in the Y direction which crosses the X direction at right angles are given to each chip 1a on the wafer 1. Using the addresses in the X and Y directions of the chips 1a, the center 1b of the wafer 1 is calculated. Then, the number of chips in the X direction and the number of chips in the Y direction from the center 1b to a specific chip 1a are calculated. The specific positional information showing the positional information of the specific chip 1a is calculated by multiplying the calculated number of chips in the X direction by the chip size in the X direction and the calculated number of chips in the Y direction by the chip size in the Y direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a position information calculation method for calculating position information of a chip, and more particularly to a position information calculation method for calculating position information of each chip of a wafer on which a plurality of chips are formed.

  Currently, in each manufacturing process of a chip (LSI, large scale integration), dust on the wafer and scratches on the wafer are generated due to various factors. These defects such as dust and scratches affect the yield of completed wafers. That is, these defects and yield have a correlation.

  It is necessary to accurately grasp these correlations and implement appropriate measures. For example, if an electrical failure occurs in the presence of dust on the wafer, it can be determined that the cause of the electrical failure is a facility such as a clean room, and that it is not a device trouble. .

  In order to grasp the correlation, for each product type, a defect map indicating the distribution of electrical defects on a wafer on which a plurality of chips are formed and a defect map indicating the distribution of dust on the wafer are overlaid, and these defect maps and Compare with defect map. When superimposing in this way, specific chip position information of these defect maps and defect maps is required.

  In order to detect the position information of a specific chip on the wafer, the defect map and the defect map are manually overlapped so that both are concentric circles, and then the position information of the specific chip in the defect map and the defect map is obtained. It is detected and registered in association with the defect map and the defect map for the product type. Once registered, this position information can be diverted and used continuously for the product type.

  Also, when developing a new product type, a system that automatically places each chip on a wafer is used, and the position information of a specific chip in that product type is obtained from that system, and a defect map and defect map for that product type are obtained. Registered in association.

A technique has been proposed in which an image of the outer peripheral edge of a wafer is taken and the position of the edge is detected (see, for example, Patent Document 1).
JP 2004-186306 A

  However, in the method of manually superimposing the defect map and the defect map, since it is manually superimposed, the defect map and the defect map may be misaligned when the chip size is small or the like, which is not accurate.

In addition, since the system that automatically arranges each chip on the wafer is not compatible with old varieties, it cannot be applied to all varieties.
The present invention has been made in view of these points, and an object of the present invention is to provide a position information calculation method capable of accurately calculating position information of a specific chip on a wafer.

  In the present invention, in order to solve the above problems, as illustrated in FIG. 1, in a position information calculation method for calculating position information of each chip 1 a of a wafer 1 on which a plurality of chips 1 a are formed, A step of giving an address in the X direction and an address in the Y direction orthogonal to the X direction to the chip 1a, a step of calculating the center 1b of the wafer 1 using the address in the X direction and the address in the Y direction, The step of calculating the number of chips in the X direction and the number of chips in the Y direction from 1b to a specific chip 1a, the number of chips in the X direction and the number of chips in the Y direction, respectively, the chip size in the X direction and the chip in the Y direction, respectively. And a step of calculating the specific position information indicating the position information of the specific chip 1a by multiplying by the size.

  According to this position information calculation method, an address in the X direction and an address in the Y direction orthogonal to the X direction are given to each chip 1a on the wafer 1. The center 1b of the wafer 1 is calculated using the address in the X direction and the address in the Y direction. The number of chips in the X direction and the number of chips in the Y direction from the center 1b to the specific chip 1a are calculated. The calculated number of chips in the X direction and the number of chips in the Y direction are multiplied by the chip size in the X direction and the chip size in the Y direction, respectively, and specific position information indicating the position information of the specific chip 1a is calculated. .

  In the present invention, an X-direction address and a Y-direction address are assigned to each chip on the wafer, the center of the wafer is calculated using the X-direction address and the Y-direction address, and the accurately calculated center is obtained. Since the distance from the specific chip to the specific chip is calculated, the position information of the specific chip on the wafer can be accurately calculated. As a result, the defect map and the defect map can be accurately superimposed using the position information, and the correlation between them can be grasped.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment of the present invention is applied to a defect map showing a distribution of electrical defects of a wafer on which a plurality of chips are formed.

First, a wafer on which a plurality of chips are formed will be described. FIG. 1 shows a wafer.
A plurality of chips 1 a having various functions are formed on the wafer 1. Each chip 1 a is arranged so that as many chips 1 a as possible can be formed on one wafer 1.

  Here, it is assumed that a cut is made in the wafer 1 in order to provide a facet for one side of the wafer 1. The cut-in part is the lower side with respect to the center of the wafer 1, the part facing the lower side is the upper side, the part moved 90 degrees rightward from the upper side is the right side, and 90 degrees leftward from the upper side The moved part is the left side. Due to this facet, the alignment of the chips 1 a is not symmetrical between the upper edge and the lower edge of the wafer 1. Further, it is assumed that a recognition character (not shown) for distinguishing and recognizing each wafer 1 is provided on the other side of the wafer 1. Due to this recognition character, the alignment of the chips 1 a is not symmetrical between the right edge and the left edge of the wafer 1.

  Next, the symmetry of the upper edge and the lower edge of the wafer 1 is lost, or the symmetry of the right edge and the left edge of the wafer 1 is lost. A method for calculating 1b will be described. Thereafter, a method for calculating the calculated distance from the center 1b of the wafer 1 to the specific chip 1a, that is, the specific position information indicating the position information of the specific chip 1a will be described.

  First, it is assumed that a cut is made on one side of the circular wafer 1. Further, the cutting direction is defined as the X direction, and the direction orthogonal to the X direction is defined as the Y direction. In addition, a text file that is a source of a defect map indicating the distribution of electrical defects on the wafer 1 includes a chip size, an address in the X direction of each chip 1a (hereinafter referred to as an X address), and an address in the Y direction of each chip 1a (hereinafter referred to as an address). , Y address) and the failure mode of each chip 1a. For example, as illustrated in FIG. 1, X addresses 15 to 36 and Y addresses 21 to 41 are described.

  Next, the center 1b of the wafer 1 is calculated using the X address and the Y address. Specifically, first, a group of chips 1a aligned in the X direction is scanned in the Y direction from the upper edge and the lower edge of the wafer 1, respectively. By scanning, the minimum X address and the maximum X address in each Y address are detected. Similarly, the group of chips 1a aligned in the Y direction is scanned in the X direction from the right edge and the left edge of the wafer 1, respectively. By scanning, the minimum Y address and the maximum Y address in each X address are detected. As a scan target, for example, one third of the number of all Y addresses is scanned from the upper edge of the wafer 1, and one third of the number of all Y addresses is scanned from the lower edge. Similarly, one-third of all X address numbers are scanned from the right edge of the wafer 1, and one-third of all X address numbers are scanned from the left edge.

  After scanning, the minimum X address and the maximum X address in the Y address of the upper edge of the wafer 1 are equal to the minimum X address and the maximum X address in the Y address of the lower edge. Detects the Y address of the upper edge and the lower edge of the wafer 1 in which the number of chips in the upper X direction chip group is equal to the number of chips in the lower X direction chip group. . For example, the minimum X address “18”, the maximum X address “33”, and the number of chips “16” are detected at the Y address “23”, and the minimum X address “18” is the maximum at the Y address “38”. X address “33” and chip number “16” are detected. Similarly, the minimum Y address and the maximum Y address in the X address of the right edge of the wafer 1 are equal to the minimum Y address and the maximum Y address in the X address of the left edge, and the right side of the wafer 1 The X address of the right edge of the wafer 1 and the X address of the left edge of the wafer 1 in which the number of chips in the Y direction chip group is equal to the number of chips in the left Y direction chip group are detected. For example, at the X address “35”, the minimum Y address “25”, the maximum Y address “36”, and the number of chips “12” are detected. At the X address “17”, the minimum Y address “25” Y address “36” and the number of chips “12” are detected.

  Next, the distance from the detected Y address of the upper edge of the wafer 1 to the maximum Y address located at the end of the wafer 1 and the detected Y address of the lower edge of the wafer 1 The maximum Y address located virtually at the end of the wafer 1 is corrected so that the distances to the minimum Y address located at the same position are equal. For example, the Y address “41” is deleted. Similarly, the distance from the detected X address of the right edge of the wafer 1 to the maximum X address located at the end of the wafer 1 and the detected X address of the left edge of the wafer 1 to the end of the wafer 1 most. The maximum X address that is virtually located at the end of the wafer 1 is corrected so that the distance to the minimum X address is equal. For example, an X address “37” is added. The center of the lowest Y address located at the end of the wafer 1 and the corrected maximum Y address located at the end of the wafer 1 or the detected Y address at the upper edge of the wafer 1 and the lower side The center of the edge and the Y address is calculated as the center 1 b of the wafer 1. Similarly, the center of the minimum X address located at the end of the wafer 1 and the corrected maximum X address located at the end of the wafer 1 or the X address of the right edge of the detected wafer 1 The center of the left edge with the X address is calculated as the center 1 b of the wafer 1. For example, the center of the lower side of the chip 1 a having the X address “26” and the Y address “30” is calculated as the center 1 b of the wafer 1.

Here, when correcting the maximum Y address and the maximum X address virtually located at the end of the wafer 1 virtually, the minimum Y address located at the end of the wafer 1 is defined as MINCY, and the maximum located at the end of the wafer 1 is maximum. Is set to MAXCY, the detected Y address of the upper edge of the wafer 1 is set to Y _min , the detected Y address of the lower edge of the wafer 1 is set to Y _max , the correction value is set to HOSEIY, and the most wafer 1 The minimum X address located at the end is MINX, the maximum X address located most at the end of the wafer 1 is MAXCX, the X address of the right edge of the detected wafer 1 is X _max , and the detected left Expressing the X address of the edge as X _min and the correction value as HOSEIX,
_{(Y min -MINCY) - (MAXCY} -Y max) = HOSEIY
(X _min -MINX)-(MAXCX-X _max ) = HOSEIX
It becomes. Since Y _min is 23, MINCY is 21, MAXCY is 41, and Y _max is 38, HOSEIY is (23-21)-(41-38) and becomes -1. Therefore, the maximum Y address located at the end of the wafer 1 is 41-1 = 40. Further, since X _min is 17, MINX is 15, MAXCX is 36, and X _max is 35, HOSEIX becomes (17-15)-(36-35) and becomes 1. Therefore, the maximum X address located at the end of the wafer 1 is 36 + 1 = 37.

  After scanning, the minimum X address and the maximum X address in the Y address of the upper edge of the wafer 1 are not equal to the minimum X address and the maximum X address in the Y address of the lower edge. In this case, without paying attention to the X address, the number of chips in the X direction chip group at the Y address on the upper edge of the wafer 1 and the number of chips in the X direction chip group at the Y address on the lower edge are the most. The Y address of the upper edge and the lower edge of the wafer 1 that are close may be detected. Similarly, if the minimum Y address and the maximum Y address in the X address of the right edge of the wafer 1 are not equal to the minimum Y address and the maximum Y address in the X address of the left edge, the Y address Wafer 1 in which the number of chips in the Y-direction chip group at the X address of the right edge of the wafer 1 is closest to the number of chips in the Y-direction chip group at the X address of the left edge. The X address of the right edge and the X address of the left edge may be detected.

  Next, the number of chips in the X direction and the number of chips in the Y direction from the calculated center 1b of the wafer 1 to the specific chip 1a are calculated. The X direction chip size and the Y direction chip size are multiplied by the calculated X direction chip number and Y direction chip number, respectively. By doing so, specific position information indicating the position information of the specific chip 1a is automatically calculated. For example, when a chip 1a having a chip size “2 mm × 3 mm”, an X address “28” and a Y address “28” is a specific chip 1a, the number of chips in the X direction “2” and the Y direction The number of chips “2” is multiplied by the chip size “2 mm” in the X direction and the chip size “3 mm” in the Y direction, respectively. The specific position information “(4 mm, 6 mm)” of the specific chip 1a is automatically calculated. The calculation result is registered in association with the defect map for each type, for each production lot, and for each probing area.

  Next, a defect map indicating the distribution of electrical defects on the wafer 1 on which a plurality of chips 1a are formed and a defect map indicating the distribution of dust on the wafer 1 will be described. FIG. 2 is a diagram showing a defect map. FIG. 3 is a screen display example of a defect map. FIG. 4 is a diagram showing a defect map.

  The defect map 10 is created by an electrical characteristic test that tests the presence of electrical defects on the wafer 1 on which a plurality of completed chips 1a are formed after all manufacturing processes are completed. Here, the chip 1a indicated by “*” is a non-defective product. Further, the chip 1a indicated by “29”, “30” and “7” is a defective product, and these numbers indicate the failure modes of the respective chips 1a. Further, when the defect map 10 illustrated in FIG. 2 is actually displayed on the display of the computer, the screen display illustrated in FIG. 3 is obtained. In this screen, the wafer 1 is elliptical, but the actual wafer 1 is circular.

  The defect map 20 is created by a defect test for testing the presence of dust on the wafer 1 on which a plurality of chips 1a are formed after completion of each notable manufacturing process. For example, it is created by a defect test in which a predetermined sensor scans the surface of the wafer 1. Here, the part indicated by a circle is garbage. Note that the chip 1a painted black has not been subjected to a defect test.

  Here, the specific position information of the specific chip 1a in the defect map 10 is calculated by the above-described method, and the specific position information of the specific chip 1a in the defect map 20 is automatically output as a file by a predetermined test apparatus. The Based on these two pieces of specific position information, the defect map 10 and the defect map 20 can be accurately superimposed, and the defect map 10 and the defect map 20 can be compared to execute defect analysis.

Next, the resistance for the electrical characteristic test used in the electrical characteristic test for creating the defect map 10 will be described. FIG. 5 is a diagram showing a resistance for an electrical characteristic test.
Each chip 1a of the wafer 1 includes, for example, resistors R1 and R2 for testing electrical characteristics at the edge of the chip 1a. By testing the operation of these resistors R1 and R2, it is determined whether the chip 1a is a good product or a defective product.

  Here, the description is made using only the resistors R1 and R2, but actually, the resistors R1 and R2, capacitors (not shown), transistors (not shown), diodes (not shown), and the like are used. ing.

Next, the test results of the resistors R1 and R2 for the electrical characteristic test will be described. FIG. 6 is a diagram showing test results of the electrical characteristic test.
The test result of the electrical characteristic test is that the current value of the current flowing through each of the resistors R1 and R2, the voltage value of the voltage according to the current value, and the SPEC that is the lowest voltage value that can determine each of the resistors R1 and R2 as a non-defective product. (Low) and SPEC (high), which is the maximum voltage value at which each of the resistors R1 and R2 can be determined as non-defective products.

  Here, the resistance values of the resistors R1 and R2 are 5 kΩ and 100Ω, respectively, and when a current of 1 mA is passed through the resistor R1, a voltage of 5.1 V is output. Since this 5.1V is between 5.5V of SPEC (high) and 4.5V of SPEC (low), this resistor R1 is a non-defective product. When a current of 10 mA is passed through the resistor R2, a voltage of 1V is output. Since 1V is between 1.1V of SPEC (high) and 0.9V of SPEC (low), the resistor R2 is a non-defective product.

Next, the failure mode corresponding to the test result of the electrical characteristic test will be described. FIG. 7 shows the determination result of the failure mode.
The determination result of the failure mode has, for example, a failure content corresponding to the test result of the electrical characteristic test illustrated in FIG. 6 and a failure mode which is a type indicating the failure content.

  Here, for example, when the failure content is “current failure”, the failure mode is “29”. When the failure content is “voltage failure”, the failure mode is “30”. When the failure content is “functional failure”, the failure mode is “7”.

By executing these electrical characteristic tests on each chip 1a, a defect map 10 of the wafer 1 is created.
Next, a flowchart for calculating the center 1b of the wafer 1 and calculating the specific distance information indicating the calculated distance from the center 1b of the wafer 1 to the specific chip 1a, that is, the position information of the specific chip 1a will be described. . FIG. 8 is a flowchart for calculating the specific position information. The following processing is executed by the computer.

  {Step S11} Chip size, MINWX which is the X address of the chip 1a located at the smallest X address in the smallest Y address located at the most end of the wafer 1, MAXCX which is the largest X address located at the most end of the wafer 1. MINX which is the minimum X address located at the end of the wafer 1, MAXCY which is the maximum Y address located at the end of the wafer 1, and MINCY which is the minimum Y address located at the end of the wafer 1 are acquired.

{Step S12} The first correction process for correcting the maximum X address and the maximum Y address exemplified in FIG. 9 is executed.
{Step S13} It is determined whether or not the maximum X address and the maximum Y address can be corrected in the first correction process. If it can be corrected, the process proceeds to step S15, and if it cannot be corrected, the process proceeds to step S14.

{Step S14} The second correction process for correcting the maximum X address and the maximum Y address illustrated in FIG. 10 is executed.
{Step S15} The specific position information is calculated.

Here, when calculating the coordinates of the chip 1a located at the smallest X address in the smallest Y address located closest to the edge of the wafer 1, the chip size in the X direction is CHIP_X, the chip size in the Y direction is CHIP_Y, MINWX, which is the X address of the chip 1a located at the smallest X address at the smallest Y address located at the edge of the wafer 1, and MINCY as the smallest Y address located at the edge of the wafer 1, and the maximum located at the edge of the wafer 1. When the Y address is expressed as MAXCY, the smallest X address located at the end of the wafer 1 is MINX, and the largest X address located at the end of the wafer 1 is expressed as MAXCX.
X = CHIP_X × (MINWX−MINX− (MAXCX−MINC + 1 + 1) / 2)
Y = CHIP_Y × ((MAXCY−MINCY + 1) / 2-1)
It becomes.

Next, the first correction process by the computer will be described. FIG. 9 is a flowchart showing the first correction process. The following processing is executed by the computer.
{Step S21} From the upper edge and the lower edge of the wafer 1, the group of chips 1a arranged in the X direction is scanned in the Y direction. As a scan target, for example, one third of the number of all Y addresses is scanned from the upper edge of the wafer 1, and one third of the number of all Y addresses is scanned from the lower edge.

{Step S22} The minimum X address and the maximum X address in each Y address are detected.
{Step S23} The minimum X address and the maximum X address in the Y address of the upper edge of the wafer 1 are compared with the minimum X address and the maximum X address in the Y address of the lower edge.

  {Step S24} The minimum X address and the maximum X address in the Y address of the upper edge of the wafer 1 are equal to the minimum X address and the maximum X address in the Y address of the lower edge. The Y address of the upper edge and the Y address of the lower edge are detected.

  {Step S25} From the detected Y address of the upper edge of the wafer 1 to the maximum Y address MAXCY located at the end of the wafer 1 and the detected lower Y edge Y address MAXCY is virtually corrected so that the distance to MINCY, which is the smallest Y address located at the end of the wafer 1, is equal.

This first correction process is executed not only for MAXCY but also for MAXCX.
Next, the second correction process by the computer will be described. FIG. 10 is a flowchart showing the second correction process. The following processing is executed by the computer.

  {Step S61} In order to scan one-third of all the Y addresses, MINCY, which is the smallest Y address located at the end of the wafer 1, is extracted from MAXCY, which is the largest Y address located at the end of the wafer 1. Subtract, and then reduce to one third to calculate XXMAX, which is the number of addresses scanned from the edge of wafer 1.

{Step S62} XF which is the number of chips in the X-direction chip group in MAXCY is calculated.
{Step S63} XT which is the number of chips in the X direction in MINCY is calculated.

{Step S64} It is determined whether XF and XT match. If they match, the process proceeds to step S82, and if they do not match, the process proceeds to step S65.
{Step S65} After the process of step S64, NN as the count number is set to 1.

{Step S66} XT is subtracted from XF to calculate XCNT (NN).
{Step S67} It is determined whether XCNT (NN) is greater than zero. If larger, the process proceeds to step S68, and if smaller, the process proceeds to step S75.

{Step S68} After the processing in step S67, NN is added to MINCY to calculate a new CY.
{Step S69} XT which is the number of chips in the X direction in CY is calculated.

{Step S70} Add 1 to NN to calculate a new NN.
{Step S71} XT is subtracted from XF to calculate a new XCNT (NN). Here, although only one XF is compared, it is compared with a plurality of XFs.

{Step S72} It is determined whether NN and XXMAX match. If they match, the process proceeds to step S73, and if they do not match, the process proceeds to step S68.
{Step S73} After the processing in step S72, 1 is subtracted from NN where XCNT (NN) is closest to 0, and the correction value HOSEIY is calculated.

{Step S74} HOSEIY is added to MAXCY to calculate a newly corrected MAXCY.
{Step S75} After the processing in step S67, NN is subtracted from MAXCY to calculate a new CY.

{Step S76} XF, which is the number of chips in the X direction in CY, is calculated.
{Step S77} Add 1 to NN to calculate a new NN.
{Step S78} XT is subtracted from XF to calculate a new XCNT (NN). Here, although only one XT is compared, it is compared with a plurality of XTs.

{Step S79} It is determined whether NN and XXMAX match. If they match, the process proceeds to step S80, and if they do not match, the process proceeds to step S75.
{Step S80} After the processing of step S79, 1 is subtracted from NN where XCNT (NN) is closest to 0, and the correction value HOSEIY is calculated.

{Step S81} Subtract HOSEIY from MAXCY to calculate a newly corrected MAXCY.
{Step S82} After the process of step S64, MAXCY is not corrected.

This second correction process is executed not only for MAXCY but also for MAXCX.
Next, the calculation result of specific position information is demonstrated. FIG. 11 shows the calculation result of the specific position information.

  The calculation result of the specific position information includes LOTNO, FACET, WSIZE, MINWX, MINXX, MAXCX, MINCY, MAXCY, CHIP_X, CHIP_Y, REF_X, REF_Y, FJREF_X, FJREF_Y, DELTA_X, and DELTA_Y.

  LOTNO is a number representing a production lot. FACET indicates the position of the facet on the wafer 1. Specifically, it is indicated by “TOP”, “BOTTOM”, “RIGHT” and “LEFT”. WSIZE is the wafer size. MINWX is the X address of the chip 1a positioned at the minimum X address in the minimum Y address positioned closest to the wafer 1 end. MINX is the smallest X address located at the end of the wafer 1 most. MAXCX is the maximum X address located at the end of the wafer 1 most. MINCY is the minimum Y address located at the end of the wafer 1 most. MAXCY is the maximum Y address located at the end of the wafer 1 most. CHIP_X is the chip size in the X direction. CHIP_Y is the chip size in the Y direction. REF_X is a coordinate in the X direction of the specific chip 1a. REF_Y is a coordinate in the Y direction of the specific chip 1a. FJREF_X is a theoretical value of coordinates in the X direction of the specific chip 1a. FJREF_Y is a theoretical value of coordinates in the Y direction of the specific chip 1a. DELTA_X is an error of REF_X from FJREF_X. DELTA_Y is an error of REF_Y from FJREF_Y. In the determination, it is determined whether or not the error is within an allowable range. For example, when “1” is within the allowable range, REF_X and REF_Y can be used, and when “0”, REF_X and REF_Y cannot be used. The correction is a correction value for the maximum X address and the maximum Y address located at the end of the wafer 1. For example, three Y addresses are added in the Y direction.

  In this way, since the center 1b of the wafer 1 is calculated and the distance from the accurately calculated center 1b to the specific chip 1a is calculated, the position information of the specific chip 1a on the wafer 1 can be calculated. Thereby, even when the chip size is small, the defect map 10 and the defect map 20 can be accurately superimposed, so that the correlation between them can be grasped.

Further, since the position information of the specific chip 1a on the wafer 1 can be calculated for all types, it may be an old type or a new type.
Further, since the position information of the specific chip 1a on the wafer 1 can be automatically calculated, even when the production lot is changed, it can be easily handled in real time. Moreover, even when the probing area is changed, it can be easily handled in real time. Further, even when each chip 1a is rearranged on the wafer 1, it can be easily handled in real time. Therefore, even when a large number of varieties are developed, the position information registration work can be reduced, and the registration schedule can be shortened.

  The above calculation function can be realized by a computer. The computer is provided with a program describing the processing content of the function that the calculation function should have, and the above calculation function is realized on the computer by executing the program on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the recording medium include a magnetic recording device, an optical disc, a magneto-optical disc, and a semiconductor memory.

  When distributing the program, for example, a portable recording medium such as an optical disk on which the program is recorded is used. Further, the program is stored in a storage device of a server computer, and the program is transferred from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. The program is read from its own storage device, and processing according to the program is executed. The computer can also read the program directly from the portable recording medium and process it according to the program. In addition, each time a program is transferred from the server computer, the computer can also process according to the transferred program at any time.

(Supplementary Note 1) In a position information calculation method for calculating position information of each chip of a wafer on which a plurality of chips are formed,
Providing each chip on the wafer with an address in the X direction and an address in the Y direction orthogonal to the X direction;
Calculating the center of the wafer using the address in the X direction and the address in the Y direction;
Calculating the number of chips in the X direction and the number of chips in the Y direction from the center to a specific chip;
Multiplying the number of chips in the X direction and the number of chips in the Y direction by the chip size in the X direction and the chip size in the Y direction, respectively, calculates specific position information indicating the position information of the specific chip. Steps,
A position information calculation method characterized by comprising:

(Appendix 2) The center of the wafer is
The minimum X-direction address and the maximum X-direction address match, the center of the minimum Y-direction address and the maximum Y-direction address,
The position information calculation method according to appendix 1, wherein the minimum Y-direction address and the maximum Y-direction address are the center of the minimum X-direction address and the maximum X-direction address.

(Appendix 3) When calculating the center of the wafer,
The distance from the maximum Y-direction address to the maximum Y-direction address located at the end of the wafer, and the distance from the minimum Y-direction address to the minimum Y-direction address located at the end of the wafer. Correct the maximum Y-direction address to be equal,
The distance from the largest X-direction address to the largest X-direction address located at the end of the wafer and the distance from the smallest X-direction address to the smallest address in the X-direction located at the end of the wafer. The positional information calculation method according to appendix 2, wherein the maximum X-direction address is corrected so as to be equal.

(Appendix 4) The center of the wafer is
The center of the smallest Y-direction address and the largest Y-direction address, with the closest number of chips in the X-direction chip group;
The position information calculation method according to appendix 1, wherein the number of chips in the Y-direction chip group is the center between the smallest X-direction address and the largest X-direction address.

(Supplementary Note 5) When calculating the center of the wafer,
The distance from the maximum Y-direction address to the maximum Y-direction address located at the end of the wafer, and the distance from the minimum Y-direction address to the minimum Y-direction address located at the end of the wafer. Correct the maximum Y-direction address to be equal,
The distance from the largest X-direction address to the largest X-direction address located at the end of the wafer and the distance from the smallest X-direction address to the smallest address in the X-direction located at the end of the wafer. The position information calculation method according to appendix 4, wherein the maximum address in the X direction is corrected so as to be equal.

(Supplementary Note 6) In a position information calculation program for calculating position information of each chip of a wafer on which a plurality of chips are formed,
On the computer,
For each chip on the wafer, an address in the X direction and an address in the Y direction perpendicular to the X direction are given,
Using the address in the X direction and the address in the Y direction, calculate the center of the wafer,
Calculate the number of chips in the X direction and the number of chips in the Y direction from the center to a specific chip,
Multiplying the number of chips in the X direction and the number of chips in the Y direction by the chip size in the X direction and the chip size in the Y direction, respectively, calculates specific position information indicating the position information of the specific chip. A position information calculation program characterized by causing a process to be executed.

(Supplementary note 7) In a computer-readable recording medium recording a position information calculation program for calculating position information of each chip of a wafer on which a plurality of chips are formed,
On the computer,
For each chip on the wafer, an address in the X direction and an address in the Y direction perpendicular to the X direction are given,
Using the address in the X direction and the address in the Y direction, calculate the center of the wafer,
Calculate the number of chips in the X direction and the number of chips in the Y direction from the center to a specific chip,
Multiplying the number of chips in the X direction and the number of chips in the Y direction by the chip size in the X direction and the chip size in the Y direction, respectively, calculates specific position information indicating the position information of the specific chip. A computer-readable recording medium having a position information calculation program recorded thereon, wherein the position information calculation program is recorded.

It is a figure which shows a wafer. It is a figure which shows a defect map. It is a screen display example of a defect map. It is a figure which shows a defect map. It is a figure which shows the resistance for an electrical property test. It is a figure which shows the test result of an electrical property test. It is a determination result of a failure mode. It is a flowchart which calculates specific position information. It is a flowchart which shows a 1st correction process. It is a flowchart which shows a 2nd correction process. It is a calculation result of specific position information.

Explanation of symbols

1 Wafer 1a Chip 1b Center

Claims (5)

In a position information calculation method for calculating position information of each chip of a wafer on which a plurality of chips are formed,
Providing each chip on the wafer with an address in the X direction and an address in the Y direction orthogonal to the X direction;
Calculating the center of the wafer using the address in the X direction and the address in the Y direction;
Calculating the number of chips in the X direction and the number of chips in the Y direction from the center to a specific chip;
Multiplying the number of chips in the X direction and the number of chips in the Y direction by the chip size in the X direction and the chip size in the Y direction, respectively, calculates specific position information indicating the position information of the specific chip. Steps,
A position information calculation method characterized by comprising: The center of the wafer is
The minimum X-direction address and the maximum X-direction address match, the center of the minimum Y-direction address and the maximum Y-direction address,
2. The position information calculation method according to claim 1, wherein the minimum Y-direction address and the maximum Y-direction address coincide with each other, and are the center of the minimum X-direction address and the maximum X-direction address. . When calculating the center of the wafer,
The distance from the maximum Y-direction address to the maximum Y-direction address located at the end of the wafer, and the distance from the minimum Y-direction address to the minimum Y-direction address located at the end of the wafer. Correct the maximum Y-direction address to be equal,
The distance from the largest X-direction address to the largest X-direction address located at the end of the wafer and the distance from the smallest X-direction address to the smallest address in the X-direction located at the end of the wafer. The position information calculation method according to claim 2, wherein the maximum address in the X direction is corrected so as to be equal. The center of the wafer is
The center of the smallest Y-direction address and the largest Y-direction address, with the closest number of chips in the X-direction chip group;
The position information calculation method according to claim 1, wherein the number of chips in the Y-direction chip group is the closest center between the minimum X-direction address and the maximum X-direction address. When calculating the center of the wafer,
The distance from the maximum Y-direction address to the maximum Y-direction address located at the end of the wafer, and the distance from the minimum Y-direction address to the minimum Y-direction address located at the end of the wafer. Correct the maximum Y-direction address to be equal,
The distance from the largest X-direction address to the largest X-direction address located at the end of the wafer and the distance from the smallest X-direction address to the smallest address in the X-direction located at the end of the wafer. The position information calculation method according to claim 4, wherein the maximum address in the X direction is corrected so as to be equal.

Images