JP2007033113A - Overcurrent detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an overcurrent detection circuit capable of heightening detection accuracy. <P>SOLUTION: In this overcurrent detection circuit 10, when ON-control is performed, a sense current corresponding to a current Ids flows respectively, to thereby generate each voltage drop in NMOS transistors DM2, DM3. A voltage (divided voltage) corresponding to the NMOS transistor DM3 between each voltage drop is input into a positive side input terminal of a comparator COMP1 as a sense voltage Vdo, and used as a comparison object. Though a constant voltage drop (RonDM4*i3) by a current value i3 is generated in an NMOS transistor DM4, the voltage drop is input into a negative side input terminal of the comparator COMP1 as a reference voltage Vrefo, and used as a comparison reference. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an overcurrent detection circuit, and more particularly to a technique for increasing detection accuracy.

  A conventional overcurrent detection circuit for a power driver causes a sense current corresponding to the current flowing through the driver NMOS transistor to flow through the sense NMOS transistor and the first resistance element connected in series with each other, and the voltage drop due to the first resistance element Is used as a sense voltage to detect overcurrent. That is, the sense voltage is compared with a reference voltage for comparison obtained by passing a constant current (reference current) through a second resistance element connected in parallel with the first resistance element, and the sense voltage is compared. When the voltage is higher than the reference voltage, it is determined that an overcurrent has occurred in the power driver. Examples of conventional overcurrent detection circuits are disclosed in Patent Documents 1 and 2, for example.

Japanese Patent Laid-Open No. 10-163486 JP 2002-26707 A

  In a conventional overcurrent detection circuit, an overcurrent is detected using a sense NMOS transistor, a first resistance element, and a second resistance element. However, since the structures of the NMOS transistor and the resistance element are greatly different, when they are mixed, variations in the manufacturing process greatly affect the threshold current value for detecting the overcurrent. Therefore, there is a problem that detection accuracy is lowered.

  In order to solve such a problem, a method is conceivable in which the resistance values of the first resistance element and the second resistance element are made so small that they can be ignored compared to the on-resistance value of the sense NMOS transistor. However, if the resistance values of the first resistance element and the second resistance element are reduced, the sense voltage and the reference voltage are reduced, so that the switching noise of the driver NMOS transistor greatly affects the threshold current value for detecting the overcurrent. To do. Therefore, there is a problem that detection accuracy is lowered.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an overcurrent detection circuit capable of improving detection accuracy.

  The overcurrent detection circuit according to the present invention includes a second transistor through which a sense current corresponding to a current flowing through the first transistor for a driver flows, and a second transistor connected in series with the second transistor to generate a sense voltage when the sense current flows. Three transistors, a fourth transistor that generates a reference voltage when a reference current flows, and a first comparator that detects an overcurrent by comparing a sense voltage with the reference voltage.

  The overcurrent detection circuit according to the present invention includes a second transistor through which a sense current corresponding to a current flowing through the first transistor for a driver flows, and a second transistor connected in series with the second transistor to generate a sense voltage when the sense current flows. Three transistors, a fourth transistor that generates a reference voltage when a reference current flows, and a first comparator that detects an overcurrent by comparing a sense voltage with the reference voltage. Therefore, since a resistance element can be dispensed with, it is possible to prevent a decrease in detection accuracy due to manufacturing variations caused by a mixture of transistors and resistance elements.

<Embodiment 1>
FIG. 1 is a circuit diagram showing a configuration of a power driver according to the first embodiment.

  As shown in FIG. 1, the power driver according to the present embodiment detects whether or not the current Ids flowing between the source and drain of the driver NMOS transistor DM1 (first transistor) is an overcurrent. The overcurrent detection circuit 10 and a clamp circuit ZD1 for preventing the voltage between the gate and the source of the NMOS transistor DM1 from becoming an overvoltage are incorporated. The clamp circuit ZD1 is configured by connecting a plurality of Zener diodes and has a clamp voltage Vzd1 of several tens of volts.

  The overcurrent detection circuit 10 includes NMOS transistors DM2 to DM4 (second transistor to fourth transistor), a PMOS transistor M3, constant current sources I3 and I4, a comparator COMP1 (first comparator), and a terminal Tover. Yes. The NMOS transistors DM2 to DM4 are obtained by reducing the NMOS transistor DM1 with the same structure.

  In the NMOS transistor DM1, the source is grounded, the drain is connected to the power source VS having the potential Vs via the terminal T and the coil L at the contact N4, and the gate is given the gate potential at the contact VG4. This terminal T is arranged at the boundary between a power driver circuit built in the LSI and a coil L which is an external element. Hereinafter, the potential of the contact N4 (N3), that is, the drain potential (drain voltage) of the NMOS transistor DM1 is referred to as a potential Vq. In general, the overcurrent of the current Ids is caused by a short circuit of the coil L or the like.

  The drain of the NMOS transistor DM1 is connected to the input of the clamp circuit ZD1 at the contacts N3 to N4, and the gate of the NMOS transistor DM1 is connected to the output of the clamp circuit ZD1 at the contact VG4.

  A control signal for controlling the NMOS transistor DM1 is input from the input terminal Tin, and is input to the gates of the NMOS transistor M1 and the PMOS transistor M2. The drain of the NMOS transistor M1 and the drain of the PMOS transistor M2 are connected to each other at the contact point VG1. The source of the NMOS transistor M1 is grounded at the contact N7 via the constant current source I1. The source of the PMOS transistor M2 is connected to the power supply VDD having the potential Vdd at the contact N1 via the constant current source I2.

  The potentials of the contacts VG1 to VG4 are equal to each other, and the control signal input from the terminal Tin is inverted by the CMOS inverter including the NMOS transistor M1 and the PMOS transistor M2, and input to the gate of the NMOS transistor DM1 at the contact VG4. That is, when an L level control signal is input from the terminal Tin, the gate of the NMOS transistor DM1 is charged by the constant current source I2 through the conductive PMOS transistor M2, and an H level control signal is input from the terminal Tin. In this case, the gate of the NMOS transistor DM1 is discharged by the constant current source I1 through the NMOS transistor M1 that has been made conductive.

  When an L level control signal is input from the terminal Tin, the potentials of the contacts VG1 to VG4 become H level, so that the NMOS transistor DM1 becomes conductive (off control). When an H level control signal is input from the terminal Tin, the potentials of the contacts VG1 to VG4 become L level, so that the NMOS transistor DM1 is cut off (ON control).

  The drain of the NMOS transistor DM1 is connected to the drain of the NMOS transistor DM2 at the contacts N3 to N4. The source of the NMOS transistor DM2 is connected to the drain of the NMOS transistor DM3 at the contact N6. The source of the NMOS transistor DM3 is grounded at the contacts N7 to N9. A sense current corresponding to the current Ids flows through the NMOS transistors DM2 to DM3 connected in series with each other. The source of the NMOS transistor DM2 and the drain of the NMOS transistor DM3 are connected to the positive side input terminal of the comparator COMP1 at the contact N6. The gate of the NMOS transistor DM2 is given a gate potential at the contact point VG2.

  The gate of the NMOS transistor DM3 is connected to the drain of the PMOS transistor M3, and the source of the PMOS transistor M3 is connected to the power supply VDD at the contacts N1 and N2 via the constant current source I4. The PMOS transistor M3 is always conductive because the gate is grounded at the contacts N7 to N8. In the present embodiment, the current value and PMOS transistor supplied by the constant current source I3 are set so that the NMOS transistor DM3 is always turned on and the voltage drop in the PMOS transistor M3 is equal to the voltage drop (when turned on) in the PMOS transistor M2. The on-resistance value of M3 is set in advance. As a result, when the L level control signal is input from the terminal Tin (ON control), the gate potentials applied to the NMOS transistors DM2 and DM3 can be equalized when the PMOS transistors M2 to M3 and the NMOS transistors DM1 to DM3 are turned on. It is said. As a result, in all the NMOS transistors DM1 to DM4, it is possible to equalize the gate potentials applied when conducting.

  The drain of the NMOS transistor DM4 is connected to the negative input terminal of the comparator COMP1 at the contact N5, and is also connected to the power supply VDD via the constant current source I3. The source of the NMOS transistor DM4 is grounded at the contacts N7 to N9, and the gate of the NMOS transistor DM4 is given a gate potential at the contact VG3.

  Next, the overcurrent detection operation in FIG. 1 will be described. In the following description, the on-resistance values respectively generated based on the gate-source voltages in the NMOS transistors DM1 to DM4 are RonDM1 to RonDM4, and the current value of the constant current (reference current) passed by the constant current source I3 is i3.

  In the overcurrent detection circuit 10 shown in FIG. 1, when ON control is performed, a voltage drop occurs due to a sense current flowing in the NMOS transistors DM2 and DM3 according to the current Ids. Among these voltage drops, the voltage (divided voltage) corresponding to the NMOS transistor DM3 is input to the positive input terminal of the comparator COMP1 as the sense voltage Vdo and is a comparison target. Further, in the NMOS transistor DM4, a constant voltage drop (RonDM4 * i3) due to the current value i3 occurs. This voltage drop is input to the negative input terminal of the comparator COMP1 as the reference voltage Vrefo, and is compared with the comparison reference. Become. That is, the comparator COMP1 subtracts the reference voltage Vrefo input to the negative input terminal from the sense voltage Vdo input to the positive input terminal, and an overcurrent is generated when the subtraction result is positive. And an H level overcurrent detection signal is output from the terminal Tover. In the overcurrent detection circuit 10 shown in FIG. 1, the overcurrent detection threshold current I (over) th in the on-control is expressed by the following equation (1).

  I (over) th ≒ ((RonDM4 / RonDM1) * (RonDM2 + RonDM3) / RonDM3) * i3 (1)

  As shown in FIG. 1, the overcurrent detection circuit 10 according to the present embodiment generates a sense voltage Vdo and a reference voltage Vrefo using NMOS transistors DM3 and DM4 instead of resistance elements. As a result, as shown in Expression (1), the threshold current I (over) th is determined based only on the current value i3 and the on-resistance values RonDM1 to RonDM4 of the NMOS transistors DM1 to DM4. Therefore, as compared with an overcurrent detection circuit that generates a voltage drop using a resistance element, it is possible to prevent a decrease in detection accuracy due to manufacturing variations caused by mixing of NMOS transistors and resistance elements. FIG. 2 shows an overcurrent detection circuit using resistance elements R1 and R2 in place of the NMOS transistors DM3 and DM4 in the overcurrent detection circuit 10 shown in FIG. 1 for comparison (NMOS transistor DM3). The PMOS transistor M3 and the constant current source I4 for supplying a gate potential to the transistor are unnecessary and are omitted). The threshold current I (over) th in such an overcurrent detection circuit includes resistance values r1 and r2 based on the resistance elements R1 and R2, respectively, as represented by the following formula (2), and manufacturing variations. It becomes easy to be affected. As described above, the resistance values r1 and r2 are smaller than the on-resistance values of the NMOS transistors DM2 and DM3, respectively.

  I (over) th ≒ (RonDM2 + r1) / RonDM1) * (r2 / r1) * i3 (2)

  Further, in the overcurrent detection circuit 10 shown in FIG. 1, when the off control is performed, the NMOS transistor DM2 is cut off, so that the sense current does not flow through the conductive NMOS transistor DM3 and the sense voltage Vdo = 0V. . At this time, since the NMOS transistor DM4 is also cut off, the reference voltage Vrefo = Vdd.

  As an example of each potential in FIG. 1, the potential Vdd is about 5V, the potential Vs is about 12V, and the potential Vq is 1V (when the NMOS transistor DM1 is conducting) to 40V (when the NMOS transistor DM1 is shut off).

  Next, the operation of the power driver of FIG. 1 will be described using the timing chart of FIG.

  First, when a control signal of H level is input from the terminal Tin as shown in FIG. 3A (off control), the potential Vg of the contacts VG1 to VG4 is L level as shown in FIG. 3B. It becomes. Therefore, as shown in FIG. 3C, no current Ids flows between the source and drain of the NMOS transistor DM1, so that no voltage is generated in the coil L. Therefore, the potential Vq of the contact N4, that is, the drain potential of the NMOS transistor DM1 is equal to the potential Vs. Further, since the NMOS transistors DM2 and DM4 are cut off, the sense voltage Vdo = 0V and the reference voltage Vrefo = Vdd as described above.

  Next, when the control signal input from the terminal Tin is lowered to the L level as shown in FIG. 3A (on control), the potential Vg of the contacts VG1 to VG4 is changed as shown in FIG. Becomes H level. Therefore, as shown in FIG. 3C, a current Ids flows between the source and drain of the NMOS transistor DM1, and a voltage is generated in the coil L. Therefore, the potential Vq of the contact N4, that is, the drain potential of the NMOS transistor DM1 is lower than the potential Vs. Since the NMOS transistors DM2 and DM4 are turned on, the sense voltage Vdo rises from 0V and the reference voltage Vrefo falls from Vdd.

  Next, when the control signal input from the terminal Tin is again raised to the H level as shown in FIG. 3A (off control), the potential Vg of the contacts VG1 to VG4 as shown in FIG. 3B. Becomes L level. At this time, the potential Vq of the contact N4 rapidly rises due to the current energy accumulated in the coil L. When the potential Vq of the contact N4 becomes larger than the clamp voltage Vclamp = Vzd1 + Vgsdm1 (gate-source voltage of the NMOS transistor DM1), the clamp circuit ZD1 becomes conductive, so that the potential of the contact VG4, that is, the gate potential of the NMOS transistor DM1 also rises. That is, as shown in FIGS. 3C and 3D, immediately after switching from the on control to the off control, the NMOS transistor DM1 becomes conductive until the current energy accumulated in the coil L is released, and the current flows. After Ids (Iclamp) flows, the NMOS transistor DM1 is cut off.

  FIG. 4 is a timing chart showing the operation of the power driver shown in FIG. In FIG. 2, unlike FIG. 1, a constant current always flows through the resistor R2 regardless of the level of the control signal. Therefore, unlike FIG. 3, in FIG. 4, the reference voltage Vrefo takes a constant value higher than the potential Vdd. In FIG. 2, the resistance values r1 and r2 are smaller than the on-resistance values of the NMOS transistors DM2 and DM3, respectively. Therefore, the sense voltage Vdo and the reference voltage Vrefo in FIG. 4 are smaller than those in FIG. .

  Thus, in the overcurrent detection circuit 10 according to the present embodiment, the sense voltage Vdo and the reference voltage Vrefo are generated by using the NMOS transistors DM3 and DM4 to generate a voltage drop with the on-resistance. Therefore, since a resistance element can be made unnecessary, it is possible to prevent a decrease in detection accuracy due to manufacturing variations caused by mixing of NMOS transistors and resistance elements.

  Also, in the overcurrent detection circuit 10 according to the present embodiment, when the NMOS transistor DM1 is controlled to be off, the NMOS transistor DM4 is cut off and no current (i3) flows, so that the overcurrent detection circuit of FIG. , Power consumption can be reduced.

<Embodiment 2>
In the first embodiment, the sense voltage Vdo is generated using the NMOS transistor DM3 instead of the resistance element, thereby preventing the detection accuracy from being lowered due to manufacturing variations caused by the mixture of the NMOS transistor and the resistance element. . However, even when a resistance element is used in place of the NMOS transistor DM3, if the resistance value of this resistance element is large enough to ignore the on-resistance RonDM2 of the NMOS transistor, the detection accuracy is reduced due to manufacturing variations. Can be prevented.

  FIG. 5 is a circuit diagram showing a configuration of the power driver according to the second embodiment. FIG. 5 includes an overcurrent detection circuit 10a instead of the overcurrent detection circuit 10 in FIG. The overcurrent detection circuit 10a shown in FIG. 5 is similar to the overcurrent detection circuit 10 shown in FIG. 1 except that the resistance element R1 ′ is connected to one end of the NMOS transistor DM2 in series with the NMOS transistor DM2 instead of the NMOS transistor DM3. The resistor element R2 ′ is further connected in series with the NMOS transistor DM2 to the other end of the NMOS transistor DM2 (the PMOS transistor M3 and the constant current source I4 for applying the gate potential to the NMOS transistor DM3 are also unnecessary). Omitted).

  It is assumed that the resistance elements R1 'to R2' have resistance values r1 'and r2' that are not less than 20 times the on-resistance value RonDM2 of the NMOS transistor DM2 and are large enough to ignore the on-resistance value RonDM2. At this time, the threshold current I (over) th in the overcurrent detection circuit 10a is expressed by the following equation (3).

  I (over) th ≒ ((RonDM4 / RonDM1) * (r2 '+ r1') / r1 ') * i3 (3)

  This equation (3) uses r1 ′ instead of RonDM3 and r2 ′ instead of RonDM2 in equation (1). That is, in the first embodiment, the potential Vq is divided by the on-resistances of the NMOS transistors DM2 and DM3 to generate the sense voltage Vdo, whereas in the present embodiment, the potential Vq is a resistance. The sense voltage Vdo is generated by dividing the resistance values r1 ′ and r2 ′ of the elements R1 ′ and R2 ′.

  As described above, in the overcurrent detection circuit 10a according to the second embodiment, the resistance elements R1 ′ and R2 ′ having resistance values r1 ′ and r2 ′ that are sufficiently larger than the on-resistance RonDM2 of the NMOS transistor DM2, respectively. By connecting in series to the NMOS transistor DM2, the potential Vq is divided using only the resistance values r1 ′ and r2 ′ (without using the on-resistance value RonDM2). Therefore, as in the first embodiment, manufacturing variations due to the mixture of NMOS transistors and resistance elements do not occur, and a decrease in detection accuracy can be prevented.

<Embodiment 3>
In the first embodiment, a sense voltage Vdo is generated by flowing a sense current corresponding to the current Ids flowing between the source and drain of the NMOS transistor DM1 to the NMOS transistors DM2 and DM3, and this sense voltage Vdo is set as the reference voltage Vrefo. An overcurrent is detected by comparison. However, the comparison may be performed by directly using the potential Vq of the contact N4, that is, the drain potential of the NMOS transistor DM1, as the sense voltage Vdo without using the sense current. In this case, as the comparator COMP1, it is necessary to use a comparator having a higher withstand voltage than when a sense current is used.

  FIG. 6 is a circuit diagram showing a configuration of a power driver according to the third embodiment. 6 includes an overcurrent detection circuit 10b instead of the overcurrent detection circuit 10 in FIG. The overcurrent detection circuit 10b shown in FIG. 6 connects the drain of the NMOS transistor DM1 directly to the negative input terminal of the comparator COMP1 at the contacts N3 to N4 in the overcurrent detection circuit 10 shown in FIG. The NMOS transistors DM2 and DM3 (and the PMOS transistor M3 and the constant current source I4 for applying a gate potential to the NMOS transistor DM3) are omitted.

  In FIG. 6, the drain of the NMOS transistor DM4 is connected to the positive input terminal of the comparator COMP1 at the contact N5. That is, FIG. 6 differs from FIG. 1 in that the reference voltage Vrefo is input to the positive input terminal of the comparator COMP1, and the sense voltage Vdo is input to the negative input terminal of the comparator COMP1. The output part of the comparator COMP1 is connected to the other input part of the NOR circuit whose one input part is connected to the terminal Tin at the contact N10. The output part of the NOR circuit is connected to the terminal Tover.

  In the overcurrent detection circuit 10b shown in FIG. 6, the comparator COMP1 subtracts the sense voltage Vdo (potential Vq) input to the negative input terminal from the reference voltage Vrefo input to the positive input terminal, and the subtraction result Is negative, it is determined that an overcurrent may have occurred, and an L level signal is input to the other input portion of the NOR circuit. The NOR circuit to which the L level signal is input outputs an H level overcurrent detection signal from the terminal Tover only when the control signal input from the terminal Tin is at the L level (ON control). When the control signal input from the terminal Tin is at the H level (off control), as described above with reference to FIG. 3D in the first embodiment, the potential Vq rapidly increases immediately after switching, and the reference voltage Since it becomes higher than Vrefo, an L level signal may be output from the comparator COMP1, but an L level overcurrent detection signal is always output from the NOR circuit. That is, the NOR circuit keeps the overcurrent detection signal output from the terminal Tover at the L level at the time of off control, thereby selectively extracting the output signal from the comparator COMP1 only at the time of the on control, and immediately after switching. This is to prevent malfunction. In the overcurrent detection circuit 10b shown in FIG. 6, the threshold current I (over) th is expressed by the following equation (4).

  I (over) th ≒ (RonDM4 / RonDM1) * i3 (4)

  Thus, in the overcurrent detection circuit 10b according to the present embodiment, the drain potential (current voltage) of the NMOS transistor DM1 (driver transistor) is directly used as the sense voltage Vdo without using the sense current, and the NMOS transistor DM4. Comparison is made with a reference voltage Vrefo generated in (reference voltage generation transistor). Therefore, a comparator having a high withstand voltage is required as compared with the first embodiment, but since the sense voltage Vdo is large, the detection accuracy can be further improved.

<Embodiment 4>
In the first embodiment, by comparing the reference voltage Vrefo generated at the drain of the NMOS transistor DM4 with the sense voltage Vdo based on the sense current corresponding to the current Ids, the overcurrent of the current Ids caused by the short circuit of the coil L or the like is obtained. Detected. However, in addition to the overcurrent, a current decrease (abrupt decrease in current) caused by an open failure due to deterioration of the coil L may be detected. In the case of reduced current, the potential Vq is greatly reduced, so that it is necessary to directly compare the reference voltage Vrefo generated at the drain of the NMOS transistor DM4 with the potential Vq without using a sense current, as in the third embodiment. There is.

  FIG. 7 is a circuit diagram showing a configuration of a power driver according to the fourth embodiment. FIG. 7 includes an overcurrent detection circuit 10c instead of the overcurrent detection circuit 10 in FIG. The overcurrent detection circuit 10c shown in FIG. 7 is the same as the overcurrent detection circuit 10 shown in FIG. 1 except for the comparator COMP2 (second comparator) for detecting the reduced current and the reduced current detection signal from the comparator COMP2. Is provided with a terminal Tunder. This comparator COMP2 has a higher breakdown voltage than the comparator COMP1 using the sense current. The positive input terminal of the comparator COMP2 is connected to the drain of the NMOS transistor DM1 at the contacts N3 and N11, and the negative input terminal of the comparator COMP2 is connected to the drain of the NMOS transistor DM4 at the contacts N5 and N12. Has been. That is, the comparator COMP2 subtracts the reference voltage Vrefo input to the negative side input terminal from the potential Vq input to the positive side input terminal, and if the subtraction result is negative, a current reduction occurs. Judgment is made and an L level reduced current detection signal is output from the terminal Tover. Thereby, in the current Ids, it is possible to detect a reduced current in addition to the overcurrent. In the overcurrent detection circuit 10c shown in FIG. 7, the threshold current I (under) th for detecting the reduced current is expressed by the following equation (5).

  I (under) th ≒ (RonDM4 / RonDM1) * i3 (5)

  As described above, in the overcurrent detection circuit 10c according to the present embodiment, the reference voltage Vrefo is compared with the voltage Vq in addition to the sense voltage Vdo, thereby detecting a reduction current in addition to the overcurrent. Therefore, as compared with the first embodiment, it is possible to detect the reduced current only by adding the comparator COMP2.

  In the above description, the potential of the contact N5, that is, the drain voltage of the NMOS transistor DM4 is used as the reference voltage Vrefo. However, the present invention is not limited to this. It may be Vrefo.

FIG. 3 is a circuit diagram showing a configuration of an overcurrent detection circuit according to the first embodiment. It is a circuit diagram which shows the structure of an overcurrent detection circuit. 3 is a timing chart illustrating an operation of the power driver according to the first embodiment. It is a timing chart which shows operation | movement of a power driver. FIG. 6 is a circuit diagram showing a configuration of an overcurrent detection circuit according to a second embodiment. FIG. 6 is a circuit diagram showing a configuration of an overcurrent detection circuit according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of an overcurrent detection circuit according to a fourth embodiment.

Explanation of symbols

10 Overcurrent detection circuit, COMP1 to COMP2 comparator, DM1 to DM4, M1 NMOS transistor, I1 to I4 constant current source, L coil, M2 to M3 PMOS transistor, N1 to N11 contact, R1 to R2 resistance element, T terminal, ZD1 Clamp circuit.

Claims (7)

A second transistor in which a sense current corresponding to a current flowing through the first transistor for a driver flows;
A third transistor connected in series with the second transistor and generating a sense voltage by flowing the sense current;
A fourth transistor that generates a reference voltage by flowing a reference current;
An overcurrent detection circuit comprising: a first comparator that detects an overcurrent by comparing the sense voltage with the reference voltage. The overcurrent detection circuit according to claim 1,
The first and second and fourth transistors are controlled by the same potential,
An overcurrent detection circuit in which the third transistor is always conducting. The overcurrent detection circuit according to claim 1 or 2,
The first to fourth transistors are overcurrent detection circuits which are NMOS transistors. An overcurrent detection circuit according to any one of claims 1 to 3,
A first resistance element having a resistance value of 20 times or more of the on-resistance of the second transistor is connected to one end of the second transistor in series with the second transistor instead of the third transistor;
An overcurrent detection circuit in which a second resistance element having a resistance value of 20 times or more of the on-resistance of the second transistor is further connected to the other end of the second transistor in series with the second transistor. The overcurrent detection circuit according to claim 3,
An overcurrent detection circuit further comprising a second comparator for detecting a current reduction by comparing a drain voltage of the first transistor with the reference voltage. A first comparator that detects overcurrent by comparing the current voltage of the driver transistor with a reference voltage;
A reference voltage generating transistor that generates the reference voltage when a reference current flows;
An overcurrent detection circuit comprising: a circuit for selectively extracting an output signal from the first comparator when the driver transistor is conductive. The overcurrent detection circuit according to claim 6,
The overcurrent detection circuit, wherein the driver transistor and the reference voltage generation transistor are NMOS transistors.

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