JP2007027472A - Device incorporating component and manufacturing method therefor - Google Patents

Device incorporating component and manufacturing method therefor Download PDF

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Publication number
JP2007027472A
JP2007027472A JP2005208501A JP2005208501A JP2007027472A JP 2007027472 A JP2007027472 A JP 2007027472A JP 2005208501 A JP2005208501 A JP 2005208501A JP 2005208501 A JP2005208501 A JP 2005208501A JP 2007027472 A JP2007027472 A JP 2007027472A
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component
hole
substrate
chip
conductor
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JP2007027472A5 (en
JP5134194B2 (en
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Tadatomo Suga
唯知 須賀
Katsuhide Tsukamoto
勝秀 塚本
Akito Yoshii
明人 吉井
Masahiro Kitamura
昌広 北村
Hiroshi Yamaguchi
博 山口
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Namics Corp
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Namics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a device incorporating components capable of arranging a via to easily penetrate both sides of a semiconductor IC chip in a dry process and incorporating even an electronic component other than a semiconductor, and to provide its manufacturing method. <P>SOLUTION: The method is the one for manufacturing an electronic device where component chips 101 are embedded inside a substrate 103 made of an insulation resin and which is the device incorporating the components. A first through-hole 102 penetrating the both sides of the component chip 101 is arranged at least in one component chip 101; a second through-hole 104 penetrating the both sides of the substrate 103 passes through the first through-hole 102, and is arranged at a position not to contact the inner surface of the first through-hole 102 in the substrate 103; and electric circuit conductive bodies 106, 107 arranged on the both sides of the substrate 103 are conductively connected by a conductive body 108 which is disposed in the second through-hole 104. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導電体をはじめとする電子部品を内蔵したデバイスに関し、特に、貫通穴をあけた部品チップの表裏面側を電気的に接続した部品内蔵デバイス及びその製造方法に関する。   The present invention relates to a device incorporating an electronic component such as a semiconductor, and more particularly to a component-embedded device in which front and back sides of a component chip having a through hole are electrically connected and a method for manufacturing the device.

近年、電子機器の小型高密度化に伴い、電子部品の小型化を目指して、部品を回路基板内に内蔵するような部品内蔵デバイスの開発が行なわれている。例えば、抵抗、コイル、コンデンサなどを基板内に内蔵するものや、その他、半導電体ICを内蔵するものも出現している。また、半導電体ICチップのパッケージにおいても、チップ搭載面積を小さくするために、2つあるいは3つの半導電体ICチップを積層するような3次元実装が取り入れられ、携帯電話などにも多く用いられている。また、一方で、半導電体ICチップ内の集積化にも限界がきており、大規模な半導電体ICチップ(超LSIチップ)の開発時間の長期化や、マスクコスト、装置コストなどの増加により、大規模な回路を一つのチップ内に納めることが困難になってきている。   2. Description of the Related Art In recent years, with the increase in the size and density of electronic equipment, development of a component-embedded device that incorporates a component in a circuit board has been carried out with the aim of reducing the size of the electronic component. For example, there are those that incorporate resistors, coils, capacitors, etc. in the substrate, and others that incorporate semi-conductor ICs. Also in the semi-conductor IC chip package, in order to reduce the chip mounting area, three-dimensional mounting in which two or three semi-conductor IC chips are stacked is adopted, and it is also frequently used for mobile phones and the like. It has been. On the other hand, there is a limit to the integration within the semi-conductor IC chip, and the development time of a large-scale semi-conductor IC chip (VLSI chip) is prolonged, and the mask cost and the equipment cost increase. For this reason, it has become difficult to fit a large-scale circuit into one chip.

このような背景から、複数個の半導電体ICチップを積層して床面積を小さくするいわゆる3次元実装の必要性が高まり、広く開発が進められている。半導電体ICチップを回
路基板内に3次元的に内蔵する際、半導電体ICチップの表裏面を貫通するヴィア接合が可能であると効率的な配線が実現できる。このヴィア接合を行なうために、例えば、半導電体ICチップの表面から穴を掘り、その穴の内壁表面には絶縁膜処理を施してからその中にメッキ銅を埋め、裏側からメッキ銅が現れるまで研磨して、チップの裏側からも電気信号を取り出せるようにした技術が開発されている。(例えば、非特許文献1参照。)
Kenji.Takahashi,et al "Process Integration of 3D Chip Stack with Vertical Interconnection" Proceedings of 2004 Electronic Components and Technology Conference, P601-609 (2004)
Against this background, the need for so-called three-dimensional mounting in which a plurality of semi-conductor IC chips are stacked to reduce the floor area has increased, and development has been promoted widely. When the semiconductive IC chip is three-dimensionally incorporated in the circuit board, efficient wiring can be realized if via bonding that penetrates the front and back surfaces of the semiconductive IC chip is possible. In order to perform this via bonding, for example, a hole is dug from the surface of the semi-conductor IC chip, the inner wall surface of the hole is treated with an insulating film, and then plated copper is filled therein, and the plated copper appears from the back side. A technology has been developed in which the electrical signal can be taken out from the back side of the chip. (For example, refer nonpatent literature 1.)
Kenji.Takahashi, et al "Process Integration of 3D Chip Stack with Vertical Interconnection" Proceedings of 2004 Electronic Components and Technology Conference, P601-609 (2004)

しかし、この非特許文献1に記載されるような半導電体ICチップの表裏面を電気的に貫通するヴィアは、フォトリソグラフィ、メッキプロセス、酸化絶縁膜生成といった工程を経て形成されるので、製造工程が長く製造コストも高くなる問題が生じる。また、この工程には水を使うため、廃液の処理などの問題も生じる。   However, the via that electrically penetrates the front and back surfaces of the semiconductive IC chip as described in Non-Patent Document 1 is formed through processes such as photolithography, plating process, and generation of an oxide insulating film. There is a problem that the process is long and the manufacturing cost is high. In addition, since water is used in this process, problems such as waste liquid treatment also occur.

従って、本発明の目的は上記の問題を解決し、ドライな工程で簡単に半導電体ICチップの表裏面を貫通するヴィアを設けることが可能であり、更に、半導電体以外の電子部品も内蔵することが可能な部品内蔵デバイス、及びその製造方法を提供することにある。   Therefore, the object of the present invention is to solve the above problems, and to provide vias penetrating the front and back surfaces of the semiconductive IC chip in a dry process, and also to provide electronic components other than the semiconductor. An object of the present invention is to provide a component built-in device that can be built in, and a method for manufacturing the device.

上記の目的を達成するため、本発明に係る部品内蔵デバイスとして、絶縁性樹脂からなる基板の内部に部品チップが埋め込まれた電子デバイスであって、部品チップの少なくとも1つには、該部品チップの表裏面を貫通する第1の貫通穴が設けられ、基板には、基板の表裏面を貫通する第2の貫通穴が、第1の貫通穴の中を通り、かつ第1の貫通穴の内面に接しない位置に設けられ、基板の表裏面に備えられた電気回路導電体が、第2の貫通穴の中に備えられた導電体によって導通可能に接続されている部品内臓デバイスが考えられる。   In order to achieve the above object, an electronic device in which a component chip is embedded in a substrate made of an insulating resin as a component-embedded device according to the present invention, wherein at least one of the component chips includes the component chip. A first through hole penetrating the front and back surfaces of the substrate is provided, and a second through hole penetrating the front and back surfaces of the substrate passes through the first through hole and the first through hole is formed on the substrate. A component built-in device that is provided at a position not in contact with the inner surface and in which electrical circuit conductors provided on the front and back surfaces of the substrate are connected to be conductive by the conductor provided in the second through hole is conceivable. .

本実施態様では、任意の数の部品チップを基板の内部に埋め込むことが可能であり、また、他の電子部品をこの基板の中に埋め込むことも可能である。また、基板の中に内蔵された部品チップのうち、全ての部品チップに第1の貫通穴を設けることも考えられるし、一部の部品チップにだけ第1の貫通穴を設けることも考えられる。   In this embodiment, any number of component chips can be embedded in the substrate, and other electronic components can be embedded in the substrate. In addition, it is conceivable to provide the first through holes in all the component chips among the component chips built in the substrate, and it is also conceivable to provide the first through holes only in some of the component chips. .

ここで、基板や部品チップの「表裏面」とは、基板や部品チップを構成する面のうちの任意の相対する2面であって、例えば、基板や部品チップが平板状の形状であれば、その広面が考えられる。この表裏面には、電気回路を形成したり他の部材と電気的に接続するための接続点を設けることもできる。ただし、この表裏面は広面には限られず、基板や部品チップの形状や用途によって、任意の相対する2面を表裏面として用いることができる。   Here, the “front and back surfaces” of the substrate or component chip are any two opposing surfaces of the surfaces constituting the substrate or component chip. For example, if the substrate or component chip is a flat plate shape, , That wide side is considered. Connection points for forming an electric circuit or electrically connecting with other members can be provided on the front and back surfaces. However, the front and back surfaces are not limited to a wide surface, and any two opposing surfaces can be used as the front and back surfaces depending on the shape and application of the substrate or component chip.

第1の貫通穴は、1つの部品チップにおいて任意の数の貫通穴を設けることが可能であ
り、第2の貫通穴も、第1の貫通穴の数に応じて任意の数の貫通穴を設けることができる
。また、これらの第1の貫通穴や第2の貫通穴の断面形状については、円形、楕円形、矩形をはじめとするあらゆる形状の断面を有することができる。また、「第2の貫通穴が第1の貫通穴の中を通り、かつ第1の貫通穴の内面に接しない位置に設けられ」とは、第2の貫通穴の外形と第1の貫通穴の内壁の間に絶縁性樹脂が存在することを意味し、第2の貫通穴の中に備えられた導電体と部品チップとの間では、電気的な絶縁性が確保されていることになる。
The first through hole can be provided with an arbitrary number of through holes in one component chip, and the second through hole has an arbitrary number of through holes according to the number of the first through holes. Can be provided. Moreover, about the cross-sectional shape of these 1st through-holes and 2nd through-holes, it can have a cross section of all shapes including circular, an ellipse, and a rectangle. Further, “the second through hole is provided at a position passing through the first through hole and not in contact with the inner surface of the first through hole” means that the outer shape of the second through hole and the first through hole It means that there is an insulating resin between the inner walls of the hole, and electrical insulation is ensured between the conductor provided in the second through hole and the component chip. Become.

本実施態様によれば、導電体を、部品チップとの間の絶縁を保ちながら部品チップの中を貫通させて通すことができるので、三次元モジュールやパッケージを形成するのに非常に有効である。   According to this embodiment, the conductor can be passed through the component chip while maintaining the insulation with the component chip, which is very effective for forming a three-dimensional module or package. .

本発明に係る部品内蔵デバイスとして、更に、電気回路導電体と部品チップの電極とが電気的に接続されている部品内臓デバイスが考えられる。本発明のデバイスにおいては、導電体と部品チップの第1の貫通穴の内壁の間は電気的に絶縁されているが、本実施態様では、電気回路導電体と部品チップに設けられた電極との間を電気的に接続することによって、部品チップの端子点を部品内臓バイスの基板の表裏面に、容易に設けることができる。   As the component built-in device according to the present invention, a component built-in device in which the electric circuit conductor and the electrode of the component chip are electrically connected can be considered. In the device of the present invention, the conductor and the inner wall of the first through hole of the component chip are electrically insulated, but in this embodiment, the electric circuit conductor and the electrode provided on the component chip By electrically connecting the two, the terminal points of the component chip can be easily provided on the front and back surfaces of the substrate of the component built-in device.

本発明に係る部品内蔵デバイスとして、更に、第1の貫通穴が略円形の断面形状を有し、第2の貫通穴が略円形の断面形状を有し第1の貫通穴と略同心円状に配置されている部品内臓デバイスが考えられる。本実施態様によれば、第1の貫通穴や第2の貫通穴の加工を、容易に低コストで形成することができる。   As the component built-in device according to the present invention, the first through hole has a substantially circular cross-sectional shape, and the second through hole has a substantially circular cross-sectional shape and is substantially concentric with the first through hole. A device with a built-in component is conceivable. According to this embodiment, the processing of the first through hole and the second through hole can be easily formed at low cost.

本発明に係る部品内蔵デバイスとして、更に、部品チップが半導電体ICチップである部品内蔵デバイスが考えられる。   Further, as the component built-in device according to the present invention, a component built-in device in which the component chip is a semiconductive IC chip is conceivable.

また、本発明に係る部品内蔵デバイスとして、更に、縁性樹脂がレーザ加工可能な材料である部品内蔵デバイスや、絶縁性樹脂が感光性樹脂である部品内蔵デバイスが考えられる。   Further, as the component built-in device according to the present invention, a component built-in device in which the edge resin is a material capable of laser processing and a component built-in device in which the insulating resin is a photosensitive resin can be considered.

また、本発明に係る部品内蔵デバイスとして、更に、導電体が導電性ペーストである部品内蔵デバイスや、導電体がメッキ銅である部品内蔵デバイスが考えられる。   Further, as the component built-in device according to the present invention, a component built-in device in which the conductor is a conductive paste, and a component built-in device in which the conductor is plated copper are conceivable.

また、本発明に係る部品内蔵デバイスとして、更に、電気回路導電体が、基板の表面及び/または裏面に設けられた溝に埋め込まれた導電性ペーストからなる部品内蔵デバイスが考えられる。   Further, as the component-embedded device according to the present invention, a component-embedded device in which an electric circuit conductor is made of a conductive paste embedded in a groove provided on the front surface and / or the back surface of the substrate can be considered.

更に、本発明に係る多層の部品内蔵デバイスとして、上述の部品内臓デバイスを少なくとも1つ含み、該部品内蔵デバイスの上下に多層の配線層を重ねた多層の部品内蔵デバイスが考えられる。本実施態様によれば、製造工程が少なく低い製造コストで容易に多層の部品内蔵デバイスを製造することができる。   Furthermore, as a multilayer component-embedded device according to the present invention, a multilayer component-embedded device including at least one of the above-described component-embedded devices and having multilayer wiring layers stacked on top and bottom of the component-embedded device can be considered. According to this embodiment, it is possible to easily manufacture a multilayer component-embedded device with a small number of manufacturing steps and a low manufacturing cost.

更に、本発明に係る多両面I/Oパッケージとして、上述の部品内臓デバイスに備えられた電気回路導電体に、電極パッドを設けることによって形成される両面I/Oパッケージが考えられる。また、本発明に係る多両面I/Oパッケージとして、更に、基板の表裏面に設けられた電極パッドが、表裏面で同配列に整列している両面I/Oパッケージが考えられる。これらのI/Oパッケージは、3次元実装に非常に有効である。   Further, as the multi-sided I / O package according to the present invention, a double-sided I / O package formed by providing an electrode pad on an electric circuit conductor provided in the above-described component-embedded device is conceivable. Further, as the multi-sided I / O package according to the present invention, a double-sided I / O package in which electrode pads provided on the front and back surfaces of the substrate are arranged in the same arrangement on the front and back surfaces can be considered. These I / O packages are very effective for three-dimensional mounting.

更に、本発明に係る部品内臓デバイスの製造方法として、部品チップに、該部品チップの表裏面を貫通する第1の貫通穴をあける工程と、第1の貫通穴を有する部品チップを少なくとも含む部材を、絶縁性樹脂で埋め込んで基板を形成する工程と、基板に、該基板の表裏面を貫通する第2の貫通穴を、第1の貫通穴の中を通り、かつ第1の貫通穴の内面に接しない位置にあける工程と、第2の貫通穴の中に導電体を設け、基板の表裏面に導電体と電気的に接続するように電気回路導電体を設ける工程と、を含む部品内臓デバイスの製造方法が考えられる。   Furthermore, as a method for producing a component-embedded device according to the present invention, a member including at least a component chip having a first through hole penetrating the front and back surfaces of the component chip in the component chip, and the component chip having the first through hole Are embedded with an insulating resin to form a substrate, and a second through hole penetrating the front and back surfaces of the substrate is passed through the first through hole and the first through hole is formed in the substrate. A component including a step of not being in contact with the inner surface, and a step of providing a conductor in the second through hole and providing an electric circuit conductor on the front and back surfaces of the substrate so as to be electrically connected to the conductor. A method of manufacturing a built-in device is conceivable.

本実施態様によれば、従来に比べて、少ない製造工程で、短時間に低コストで、部品内臓デバイスを製造できる。更に、フォトリソ工程などのような廃液が出る工程を含まないため、環境保全に有利である。   According to this embodiment, it is possible to manufacture a device with a built-in component in a short time and at a low cost with fewer manufacturing steps than in the past. Furthermore, it does not include a process for producing waste liquid such as a photolithography process, which is advantageous for environmental conservation.

本発明に係る部品内蔵デバイスでは、半導電体ICチップを始めとする部品チップを貫通する導電体を、絶縁性を確保して容易に低コストで備えることができるので、三次元モジュールやパッケージには非常に有効であり、デバイスの小型化、更にはシステム装置の小型化や低コスト化が容易に図れる。   In the component built-in device according to the present invention, a conductor penetrating a component chip such as a semi-conductor IC chip can be easily provided at low cost while ensuring insulation, so that it can be provided in a three-dimensional module or package. Is very effective, and it is possible to easily reduce the size of the device and further reduce the size and cost of the system apparatus.

また、本発明に係る部品内蔵デバイスの製造においては、フォトリソ工程などのような廃液が出る工程を含まないため、環境保全に適したクリーンな製造プロセスを実現できる。   In addition, since the manufacturing of the component built-in device according to the present invention does not include a step of producing a waste liquid such as a photolithography step, a clean manufacturing process suitable for environmental protection can be realized.

本発明に係る実施形態を、図面を参照しながら詳細に説明する。   Embodiments according to the present invention will be described in detail with reference to the drawings.

(実施形態1)
本発明に係る部品内臓デバイスの1つの実施形態を図1に示す。本図は半導電体ICチップ(部品チップ)に貫通ヴィアを設けた部品内蔵デバイスを示す断面図である。
(Embodiment 1)
One embodiment of a component built-in device according to the present invention is shown in FIG. This figure is a sectional view showing a component built-in device in which a through-via is provided in a semiconductive IC chip (component chip).

半導電体ICチップ101には、その表裏面を貫通する第1の貫通穴102があけられている。ここでは、紙面で下側の面を表面、上側の面を裏面と称する。この第1の貫通穴102があけられた半導電体ICチップ101が、絶縁性樹脂からなる基板103内に埋め込まれている。また、基板103には、その表裏面を貫通する第2の貫通穴104が、第1の貫通穴102と略同心円状となる位置に、第1の貫通穴102の内壁に触れないように、つまり半導電体ICチップ101に触れないようにあけられている。従って、第2の貫通穴104の外形と第1の貫通穴102の内壁との間には絶縁性樹脂が存在する。ここで、基板103の場合も半導電体ICチップ101の場合と同様に、紙面で下側の面を表面、上側の面を裏面と称する。本図では、半導電体ICチップ101には3個の第1の
貫通穴102が設けられ、各々の第1の貫通穴102の中には第2の貫通穴104が設け
られている。
The semiconductive IC chip 101 is provided with a first through hole 102 penetrating the front and back surfaces thereof. Here, the lower surface in the drawing is referred to as the front surface, and the upper surface is referred to as the back surface. The semiconductive IC chip 101 with the first through hole 102 is embedded in a substrate 103 made of an insulating resin. In addition, the second through hole 104 penetrating the front and back surfaces of the substrate 103 is positioned so as to be substantially concentric with the first through hole 102 so that the inner wall of the first through hole 102 is not touched. That is, it is opened so as not to touch the semiconductive IC chip 101. Therefore, an insulating resin exists between the outer shape of the second through hole 104 and the inner wall of the first through hole 102. Here, also in the case of the substrate 103, as in the case of the semiconductive IC chip 101, the lower surface in the drawing is referred to as the front surface, and the upper surface is referred to as the back surface. In this figure, the semiconductive IC chip 101 is provided with three first through holes 102, and a second through hole 104 is provided in each of the first through holes 102.

基板103の左右に位置する第2の貫通穴104の中には、導電体107が備えられ、この導電体107の両端は基板103の表裏面まで達している。また、基板103の表面には電気回路導電体106が備えられ、基板103の裏面には電気回路導電体108が備えられており、これらの電気回路導電体106、108は、導電体107によって電気的に接続されている。   A conductor 107 is provided in the second through hole 104 located on the left and right of the substrate 103, and both ends of the conductor 107 reach the front and back surfaces of the substrate 103. Further, an electric circuit conductor 106 is provided on the front surface of the substrate 103, and an electric circuit conductor 108 is provided on the back surface of the substrate 103, and these electric circuit conductors 106, 108 are electrically connected by the conductor 107. Connected.

また、基板103の表面には、半導電体ICチップ101のI/O電極パッド105(電極)の位置に、コンタクト窓113があけられている。このコンタクト窓113を通して、I/O電極パッド105と電気回路導電体106とが電気的に接続されている。なお、半導電体ICチップ101の内部の構造はこの図には示されていない。   Further, a contact window 113 is opened on the surface of the substrate 103 at the position of the I / O electrode pad 105 (electrode) of the semiconductive IC chip 101. Through this contact window 113, the I / O electrode pad 105 and the electric circuit conductor 106 are electrically connected. The internal structure of the semiconductive IC chip 101 is not shown in this drawing.

一方、基板103の中央に位置する第2の貫通穴104の中には、導電体112が備えられ、この導電体112の両端は基板103の表裏面まで達している。また、基板103の表面には電気回路導電体110が備えられ、基板103の裏面には電気回路導電体111が備えられており、これらの電気回路導電体110、111は、導電体112によって電気的に接続されている。ただし、導電体112により接続された電気回路導電体110、111は、上述の電気回路導電体106、108とは異なり、半導体ICチップ101とは独立している。   On the other hand, a conductor 112 is provided in the second through hole 104 located at the center of the substrate 103, and both ends of the conductor 112 reach the front and back surfaces of the substrate 103. In addition, an electric circuit conductor 110 is provided on the front surface of the substrate 103, and an electric circuit conductor 111 is provided on the back surface of the substrate 103. These electric circuit conductors 110 and 111 are electrically connected by the conductor 112. Connected. However, the electric circuit conductors 110 and 111 connected by the conductor 112 are independent of the semiconductor IC chip 101, unlike the electric circuit conductors 106 and 108 described above.

以上のように、電気回路導電体106、108と導電体107で構成される貫通ヴィアを用いれば、半導電体ICチップ101の表面だけでなく、裏面側にもI/O電極パッドを設けることができる。従って、裏面に半導電体ICチップや他の部品を積層する場合、従来であれば、I/O電極パッドと裏面の配線とを接続するために、半導電体ICチップの外側を回って配線を繋げる必要があったが、本実施形態ではそのような煩雑な配線を行なう必要がない。また、その分配線長も短くなるという利点も有する。   As described above, if through vias constituted by the electric circuit conductors 106 and 108 and the conductor 107 are used, an I / O electrode pad is provided not only on the front surface of the semiconductive IC chip 101 but also on the back surface side. Can do. Therefore, when a semiconductive IC chip and other components are stacked on the back surface, conventionally, in order to connect the I / O electrode pad and the back surface wiring, the wiring is made around the outside of the semiconductive IC chip. However, in this embodiment, there is no need to perform such complicated wiring. In addition, the wiring length is shortened accordingly.

また、電気回路導電体110、111と導電体112で構成される独立貫通ヴィアを用いれば、基板や半導体ICチップを貫いて配線できるので、3次元実装において大きな利点を有する。   In addition, if an independent through via constituted by the electric circuit conductors 110 and 111 and the conductor 112 is used, wiring can be made through a substrate or a semiconductor IC chip, which has a great advantage in three-dimensional mounting.

(部品内蔵デバイスの製造プロセス)
次に、図1に示す部品内蔵デバイスの製造プロセスの一例を説明する。まず、半導体ICチップ101に第1の貫通穴102をあける場合には、イオンエッチングあるいはプラズマエッチングなどの半導電体加工技術により正確に穴あけを行なうことができる。また、最近はレーザなどで穴あけを行なうとも可能になっている。
(Manufacturing process of component built-in device)
Next, an example of a manufacturing process of the component built-in device shown in FIG. 1 will be described. First, when the first through hole 102 is formed in the semiconductor IC chip 101, the hole can be accurately formed by a semiconductor processing technique such as ion etching or plasma etching. Recently, drilling with a laser or the like is also possible.

イオンエッチングによれば、アスペクト比の高い、つまり、径に比べて深い貫通穴の加工が可能である。例えば、直径10μφで深さ70μの穴もあけられるようになっている。ただし、近年では、半導体ICチップの厚さが薄く加工されるようになってきており、例えば、50μぐらいの厚さの半導体ICチップも使われ始めていて、穴あけ加工自体は容易になってきている。   According to ion etching, it is possible to process a through hole having a high aspect ratio, that is, deeper than the diameter. For example, a hole having a diameter of 10 μφ and a depth of 70 μ can be formed. However, in recent years, the thickness of semiconductor IC chips has been processed to be thin. For example, semiconductor IC chips having a thickness of about 50 μm have started to be used, and the drilling process itself has become easier. .

また、150μ以上の大きな穴径でもよい場合には、被加工物に砂をぶつけて削るサンドブラストを用いることもできる。近年は、この技術でも微細加工が可能なようになってきており、若干テーパ形状となることについて問題が生じない場合には、安価な穴あけ方法として利用することができる。   In addition, when a large hole diameter of 150 μm or more may be used, sand blasting can be used in which sand is hit against the workpiece. In recent years, fine processing has become possible even with this technique, and when there is no problem with the slight taper shape, it can be used as an inexpensive drilling method.

次に、上述のようにして形成した第1の貫通穴102を有する半導電体ICチップ10
1を、絶縁性樹脂からなる基板103に埋め込む。この絶縁性樹脂からなる基板103の中に埋め込む方法には、いくつかの方法があるが、平滑な仕上がり表面を要する場合には、2枚の半硬化(B−ステージ)樹脂シートで第1の貫通穴102を有する半導電体IC
チップ101を挟み込んで、加圧加熱する方法が適している。この場合、貫通穴内部に空隙ができないようにするためには、真空中でこの処理を行なうことが好ましい。また、その他の方法としては、絶縁体シートの上に第1の貫通穴102を有する半導電体ICチッ
プ101を置き、液状樹脂を流して硬化させて埋め込む方法もある。
Next, the semiconductive IC chip 10 having the first through hole 102 formed as described above.
1 is embedded in a substrate 103 made of an insulating resin. There are several methods for embedding in the insulating resin substrate 103. If a smooth finished surface is required, two semi-cured (B-stage) resin sheets are used for the first. Semiconductor IC having through hole 102
A method in which the chip 101 is sandwiched and heated under pressure is suitable. In this case, it is preferable to perform this treatment in a vacuum in order to prevent a void from being formed inside the through hole. As another method, there is a method in which a semiconductive IC chip 101 having a first through hole 102 is placed on an insulator sheet, and a liquid resin is poured and cured to be embedded.

次に、以上のようにして形成した第1の貫通穴102を有する半導電体ICチップ10
1を埋め込んだ基板103に、第1の貫通穴102と略同心円状であって半導電体ICチップ101に触れないように第2の貫通穴104をあけ、更に、半導電体ICチップ101のI/O電極パッド105の位置にコンタクト窓113をあける工程を行なう。
Next, the semiconductive IC chip 10 having the first through hole 102 formed as described above.
A second through hole 104 is formed in the substrate 103 embedded with 1 so as to be substantially concentric with the first through hole 102 so as not to touch the semiconductive IC chip 101. A step of opening the contact window 113 at the position of the I / O electrode pad 105 is performed.

貫通穴は機械的ドリルであけてもよいが、コンタクト窓113の加工も考慮すると、レーザ加工が好ましい。微細な貫通穴の場合は、エキシマレーザあるいはヘムトレーザが適している。どのようなレーザを選択すべきかについては、許容される加工の微細さや仕上がり穴の形状に応じて、製造コストの最も低い方法を選択するのが望ましい。   The through hole may be opened by a mechanical drill, but laser processing is preferable in consideration of processing of the contact window 113. In the case of a fine through hole, an excimer laser or a hemto laser is suitable. As for what kind of laser should be selected, it is desirable to select a method with the lowest manufacturing cost in accordance with the allowable fineness of processing and the shape of the finished hole.

レーザによる樹脂の加工は、樹脂材料により大きく異なる。有機物の樹脂単体からなる場合は、炭酸ガスレーザ、YAGレーザ、エキシマレーザなど大半のレーザで穴あけ加工が可能である。また、樹脂中にシリカなどの無機のフィラーを混入する場合には加工性が悪くなるが、耐湿特性など向上するためにフィラーを混入したコンポジット材料を使用することも可能である。絶縁性樹脂として感光性の樹脂を選べば、露光現像して貫通穴をあけることも可能である。   Processing of the resin by the laser varies greatly depending on the resin material. When an organic resin is used alone, drilling can be performed with most lasers such as a carbon dioxide laser, YAG laser, and excimer laser. In addition, when an inorganic filler such as silica is mixed in the resin, the processability is deteriorated, but it is also possible to use a composite material mixed with a filler in order to improve moisture resistance and the like. If a photosensitive resin is selected as the insulating resin, a through hole can be formed by exposure and development.

従来のように、酸化膜処理により絶縁性を確保する場合には、その絶縁性は穴表面や穴形状に大きく左右されるため、製品の歩留まりが悪くなる問題が生じるが、本発明においては、穴表面や穴形状には関係なく良好な絶縁性が得られるという大きな利点を有する。   As in the prior art, when insulating properties are ensured by the oxide film treatment, the insulating properties are greatly affected by the hole surface and the hole shape, and thus there is a problem that the yield of the product is deteriorated. There is a great advantage that a good insulating property can be obtained regardless of the hole surface and hole shape.

次に、上述のようにしてあけられた第2の貫通穴104の中に、導電体107を設ける。導電体107を設けるには、導電体を埋め込むことも可能であるし、第2の貫通穴104の内壁面に導電体を付着させてもよい。導電体を埋め込む場合には、導電性ペーストをスキージ等で押し込んでもよいし、穴が大きい場合にはスクリーン印刷も可能である。スクリーン印刷により導電体107として導電性ペーストを埋め込む場合には、電気回路導電体106、108も同時に印刷してしまうと効率がよい。勿論、一旦導電性ペーストを穴に充填した後に印刷してもよい。   Next, the conductor 107 is provided in the second through hole 104 opened as described above. In order to provide the conductor 107, it is possible to embed a conductor, or the conductor may be attached to the inner wall surface of the second through hole 104. When embedding a conductor, the conductive paste may be pushed in with a squeegee or the like, and screen printing is possible when the hole is large. When embedding a conductive paste as the conductor 107 by screen printing, it is efficient to print the electric circuit conductors 106 and 108 at the same time. Of course, printing may be performed after the hole is once filled with the conductive paste.

また、電気回路導電体106、108は、導電性ペーストを充填した後、硬化させてその後メッキ銅で配線してもよい。このような技術については、プリント配線板の技術を適用することができる。また、導電体107を埋め込むのではなく、第2の貫通穴104の内壁面にメッキ銅を施して、表裏の回路導電体106、108の導通を取ることもできる。これもプリント配線板の技術では古く知られた技術であり、詳細な説明は省略する。   Further, the electric circuit conductors 106 and 108 may be hardened after filling with a conductive paste and then wired with plated copper. For such a technique, a technique of a printed wiring board can be applied. Instead of embedding the conductor 107, the inner wall surface of the second through-hole 104 can be plated with copper so that the circuit conductors 106 and 108 on the front and back sides can be electrically connected. This is also a technique that has long been known in the art of printed wiring boards, and a detailed description thereof will be omitted.

(実施形態2)
図2には、メッキ銅で回路導電体及び導電体を形成した実施形態を示す。導電体201は、第2の貫通穴104の内壁面に施しためっき銅で形成され、その内部は空洞202となっている。また、電気回路導電体106、108もメッキ銅で形成され、半導電体ICチップ101のI/O電極パッド105との接続もメッキ銅のでなされている。I/O電極パッド105は、通常アルミで作られるが、今回のような場合には、クロムやチタンあ
るいはタングステンなどの金属で表面を変換し、最終的に銅や金の表面にすることが知られている。オーミックな電気的コンタクトを得るためである。
(Embodiment 2)
FIG. 2 shows an embodiment in which circuit conductors and conductors are formed of plated copper. The conductor 201 is made of plated copper applied to the inner wall surface of the second through hole 104, and the inside thereof is a cavity 202. The electric circuit conductors 106 and 108 are also formed of plated copper, and the connection with the I / O electrode pad 105 of the semiconductive IC chip 101 is also made of plated copper. The I / O electrode pad 105 is usually made of aluminum, but in this case, it is known that the surface is converted with a metal such as chromium, titanium or tungsten, and finally the surface is made of copper or gold. It has been. This is to obtain an ohmic electrical contact.

回路導電体106、108がメッキ銅の場合には、そのままプリント基板などへ半田接続することができる。また、導電性ペーストを用いる場合には半田接続が困難であるが、メッキを施すかあるいは半田付けが可能な導電性ペーストを上塗りすることにより、電気的接続が可能である。プリント基板への電気的接続を、半田を用いずに導電性ペーストを用いて行なう場合には、導電性ペーストのまま何ら処理をする必要がない。また、導電性ペースト同士のコンタクトをよくするために、プラズマ処理を行なうことが好ましい。   When the circuit conductors 106 and 108 are plated copper, they can be directly soldered to a printed circuit board or the like. In addition, when a conductive paste is used, solder connection is difficult, but electrical connection is possible by plating or overcoating a conductive paste that can be soldered. When electrical connection to the printed circuit board is performed using a conductive paste without using solder, there is no need to perform any treatment with the conductive paste. In order to improve the contact between the conductive pastes, it is preferable to perform plasma treatment.

(実施形態3)
電気回路導電体を形成するには、印刷ではなく溝に導電性ペーストを埋め込んで形成することもできる。この場合には、第2の貫通穴104に導電性ペーストを埋め込むと同時に、電気回路導電体106、108も形成できるため、工程が著しく簡単になる。
(Embodiment 3)
In order to form the electric circuit conductor, the conductive paste can be embedded in the groove instead of printing. In this case, since the electric circuit conductors 106 and 108 can be formed simultaneously with embedding the conductive paste in the second through hole 104, the process is remarkably simplified.

本発明に係る部品内臓デバイスの他の実施形態を図3に示す。本図は、導電性ペーストを溝に埋め込んで電気回路導電体を形成した部品内蔵デバイスの断面図を示す。 ここでは、第1の貫通穴302を有する半導電体ICチップ301を、絶縁性樹脂からなる基板304に埋め込んだ後、第1の貫通穴302と略同心円状であって半導電体ICチップ301に触れない位置に第2の貫通穴305をあけ、I/O電極パッド303の位置にコンタクト窓306をあける。更に、基板304の表裏面に、回路パターンに従って溝307と308を彫る。そして、彫られた溝307、308、コンタクト窓306、及び第2の貫通穴305に、導電性ペースト309を埋め込み、充填した後に加熱硬化させる。以上の工程により、電気回路導電体(配線)も導通ヴィアも同時に形成することができる。   Another embodiment of a component built-in device according to the present invention is shown in FIG. This figure shows a cross-sectional view of a component built-in device in which an electric circuit conductor is formed by embedding a conductive paste in a groove. Here, after the semiconductive IC chip 301 having the first through hole 302 is embedded in the substrate 304 made of an insulating resin, the semiconductive IC chip 301 is substantially concentric with the first through hole 302. A second through hole 305 is formed at a position where the contact hole 306 is not touched, and a contact window 306 is formed at a position of the I / O electrode pad 303. Further, grooves 307 and 308 are carved on the front and back surfaces of the substrate 304 according to the circuit pattern. Then, the conductive paste 309 is embedded in the engraved grooves 307 and 308, the contact window 306, and the second through-hole 305, and then cured by heating. Through the above steps, the electric circuit conductor (wiring) and the conductive via can be formed simultaneously.

(実施形態4)
これまで説明したように、本発明によれば、同一の基板内に埋め込んだ複数個の半導電体ICチップ、あるいは半導電体ICチップ以外の電子部品を互いに接続した部品内蔵デバイスを形成することができる。また、そのような部品内蔵デバイスを多層に重ねた多層部品内蔵デバイスも形成することもできる。
(Embodiment 4)
As described above, according to the present invention, a plurality of semiconductive IC chips embedded in the same substrate, or a component built-in device in which electronic components other than the semiconductive IC chip are connected to each other are formed. Can do. In addition, a multilayer component built-in device in which such component built-in devices are stacked in multiple layers can also be formed.

ここで、図4には、本発明の他の実施形態である多層の部品内蔵デバイスの断面図を示す。本実施形態では、第1の貫通穴を有する半導電体ICチップ402を内蔵する部品内
蔵デバイス401の上(裏面側)に、部品チップ405を内蔵する部品チップ内蔵層404を重ね、下側(表面側)には部品チップを含まない電気回路導電体層403を重ねている。部品内蔵デバイス401については、既に説明したものと同様である。
Here, FIG. 4 shows a cross-sectional view of a multilayer component built-in device according to another embodiment of the present invention. In the present embodiment, a component chip built-in layer 404 containing a component chip 405 is superimposed on the component built-in device 401 containing the semiconductive IC chip 402 having the first through hole (on the back side), and the lower side ( An electric circuit conductor layer 403 not including a component chip is overlaid on the front surface side. The component built-in device 401 is the same as that already described.

部品チップ内蔵層404は、貫通穴のない部品チップ405を絶縁性樹脂中に埋め込んで、貫通穴と表面の溝に充填した導電性ペースト407で配線した構造を有している。ここで、部品番号406で示した部材は、部品チップの電極である。部品内蔵デバイス401の電気回路導電体415と部品チップ内蔵層404の電気回路導電体414とは、接続点408で電気的に接続されている。また、部品番号409で示した部材は、貫通穴と表面に彫った溝に埋め込んだ導電性ペーストからなる電気回路導電体である。また、下層の電気回路導電体層403は、貫通穴と表面に彫った溝に充填した導電性ペーストからなる電気回路導電体410のみを有する構造となっている。   The component chip built-in layer 404 has a structure in which a component chip 405 having no through hole is embedded in an insulating resin and wired with a conductive paste 407 filled in the through hole and the groove on the surface. Here, the member indicated by the part number 406 is an electrode of a part chip. The electrical circuit conductor 415 of the component built-in device 401 and the electrical circuit conductor 414 of the component chip built-in layer 404 are electrically connected at a connection point 408. A member indicated by a part number 409 is an electric circuit conductor made of a conductive paste embedded in a through hole and a groove carved on the surface. The lower electric circuit conductor layer 403 has a structure having only the electric circuit conductor 410 made of a conductive paste filled in the through hole and the groove carved on the surface.

このような3層構造の多層の部品内蔵デバイスは、小型の機能モジュールを得るのに有効である。また、多層の部品内蔵デバイスの表面には、従来の部品の表面実装が可能である。図4には、フリップ実装した様子を破線で示してある(部品番号411)。このような多層の部品内蔵デバイスの両面に、更に部品内蔵デバイスや電気回路導電体からなる配
線層を重ねることも可能である。
Such a multilayered component built-in device having a three-layer structure is effective for obtaining a small functional module. In addition, a conventional component can be surface-mounted on the surface of the multilayer component-embedded device. In FIG. 4, the state of flip mounting is indicated by broken lines (part number 411). It is also possible to overlap a wiring layer made of a component built-in device or an electric circuit conductor on both surfaces of such a multilayer component built-in device.

(多層の部品内蔵デバイスの製造プロセス)
次に、このような多層の部品内蔵デバイスの製造プロセスの一例を説明する。単層の部品内蔵デバイス401の製造プロセスについては既に説明を行なった。部品チップ内蔵層404を積層するには、部品チップ405をB-ステージの絶縁性樹脂で挟み込んで、部
品内蔵デバイス401の上に重ね、加圧加熱して絶縁性樹脂を硬化させて基板416を形成することができる。絶縁性樹脂に施す貫通穴加工や溝加工は、機械加工、プラズマ加工、レーザ加工などを用いることができ、必要とされる寸法精度により、最適の加工手段を選択することができる。
(Manufacturing process of multi-component embedded device)
Next, an example of a manufacturing process of such a multilayer component built-in device will be described. The manufacturing process of the single-layer component built-in device 401 has already been described. In order to laminate the component chip built-in layer 404, the component chip 405 is sandwiched between B-stage insulating resins, stacked on the component built-in device 401, and heated by pressure to cure the insulating resin, and the substrate 416 is formed. Can be formed. Machining, plasma processing, laser processing, or the like can be used for through-hole processing or groove processing to be applied to the insulating resin, and an optimal processing means can be selected depending on required dimensional accuracy.

本実施例では、レーザ加工を用いる場合を例にとって説明する。レーザ加工としては、加工後の残渣などの少ないエキシマレーザを用いることが特に好ましい。絶縁性樹脂からなる基板416に、レーザを用いて、溝413、貫通穴414、及びコンタクト窓412をあける。貫通穴414は、基板416を貫通して部品内蔵デバイス401の電気回路導電体415の位置で止められている。ただし、電気的な接合を良好にするためには、電気回路導電体415に少し入り込むまで掘りこまれるのが好ましい。また、導電性ペーストに気泡が入り込まないように充填するには、真空中で充填するのが好ましい。具体的には、真空中においてスキージで押し込むか、または導電性ペースト溜まりの中にディップした後大気中に取り上げて、表面の導電性ペーストを取り除く方法が考えられる。   In this embodiment, a case where laser processing is used will be described as an example. As the laser processing, it is particularly preferable to use an excimer laser with little residue after processing. A groove 413, a through hole 414, and a contact window 412 are formed in a substrate 416 made of an insulating resin using a laser. The through hole 414 passes through the substrate 416 and is stopped at the position of the electric circuit conductor 415 of the component built-in device 401. However, in order to improve electrical connection, it is preferable to dig into the electric circuit conductor 415 until it slightly enters. In order to fill the conductive paste so that bubbles do not enter, it is preferable to fill in a vacuum. Specifically, a method of removing the conductive paste on the surface by pushing with a squeegee in a vacuum or dipping into a conductive paste reservoir and taking it up in the atmosphere can be considered.

次に、下層の電気回路導電体層403を形成するには、B-ステージの絶縁性樹脂を重
ねて加熱加圧硬化させて基板417を形成し、貫通穴(基板417のみを貫通し、部品内蔵デバイス401上の電気回路導電体の位置で止まる穴)と溝をレーザで形成し、更に導電性ペーストを充填して加熱硬化すればよい。また、貫通穴や溝を掘る前に、上層の部品チップ内蔵層404と下層の電気回路導電体層403とを積層して、同時に加圧過熱して一時に形成することもできる。
Next, in order to form the lower electric circuit conductor layer 403, a B-stage insulating resin is stacked and heated and pressurized and cured to form a substrate 417, and a through hole (through only the substrate 417, A hole that stops at the position of the electric circuit conductor on the built-in device 401) and a groove may be formed with a laser, and a conductive paste may be further filled and heat cured. Further, before digging a through hole or groove, the upper component chip built-in layer 404 and the lower electric circuit conductor layer 403 can be laminated and simultaneously formed by heating and heating at the same time.

本実施例では、B−ステージの未硬化樹脂を用いて説明したが、部品チップを埋め込んで硬化させた絶縁性樹脂層を用いる方法や、硬化した樹脂層を接着剤で重ねる方法を採用することもできる。以降の工程については上述と同様であるので、説明は省略する。   In this embodiment, the B-stage uncured resin has been described. However, a method of using an insulating resin layer in which a component chip is embedded and cured, or a method of stacking a cured resin layer with an adhesive is adopted. You can also. Since the subsequent steps are the same as described above, description thereof will be omitted.

上記においては、各層の積層を順次積層する説明を行なったが、一括積層を行なうことも考えられる。この場合には、各層の電気的接続を異方導電性接着剤あるいは導電性接剤を用いて行なうことができる。ただし、積層物の品質を考慮すると順次積層型が好ましい。本発明のようなデバイスは、一般的に一層が非常に薄く(100μ以下)、積層時の位置合わせなどがデバイスの伸びのために困難である。順次積層型の場合には、貫通穴あけや溝彫りなどにおいて、下のパターンを見ながら加工できるので、位置合わせといった作業を要しない。従って、層間の位置ずれをカバーするヴィアランドなどの必要性が無いため、より微細なヴィアや配線を実現できる。また、上述の説明では、導電体は導電性ペーストを用いたが、既に説明したように、メッキ銅を用いることもできる。   In the above description, the layers are sequentially stacked. However, batch stacking is also conceivable. In this case, each layer can be electrically connected using an anisotropic conductive adhesive or a conductive adhesive. However, in view of the quality of the laminate, the sequential laminate type is preferable. Devices such as the present invention are generally very thin (100 μm or less), and alignment during lamination is difficult due to the elongation of the device. In the case of the sequential laminated type, it is possible to perform processing while looking at the lower pattern in through-hole drilling or grooving, so that alignment work is not required. Accordingly, since there is no need for via land or the like that covers the misalignment between layers, finer vias and wiring can be realized. In the above description, a conductive paste is used as the conductor. However, as already described, plated copper can also be used.

(実施形態5)
既に説明した多層の部品内蔵デバイスの特殊な場合として、図5に示すような構造を有する両面I/Oパッケージが考えられる。この両面I/Oパッケージは、3次元実装には有効なパッケージであり、特に、積層型大容量メモリモジュールなどには有効である。
(Embodiment 5)
As a special case of the multilayer component-embedded device already described, a double-sided I / O package having a structure as shown in FIG. 5 can be considered. This double-sided I / O package is an effective package for three-dimensional mounting, and is particularly effective for stacked large-capacity memory modules.

ここで、部品内蔵デバイス501及び電気配線導電体層502、503については、実施形態4に示したものと同様である。本実施形態の特徴部分は、多層のモジュールの表裏面に整列したI/Oパッド504、505を有することである。図5ではI/Oパッドの
配列を裏表面で同じ配列にしてあるが、異なる配列にすることもできる。また、複雑なデバイスにおいては、更に電気回路導電体層を重ねる必要性を有する場合もある。逆に、簡単なデバイスにおいては、図5の部品内蔵デバイスに示すように、それ自体で電気回路導電体層502、503を重ねなくとも両面I/Oパッケージを実現できる場合もある。また、両面あるいは片面のパッドに接続用ボール(半田ボールなど)を付けることもできる。このとき、I/Oパッド504、505の表面がメッキ銅の場合には全て半田付けが可能であるが、導電性ペーストの場合にはメッキを施したり、銅箔を貼り付けたりする必要がある。
Here, the component built-in device 501 and the electric wiring conductor layers 502 and 503 are the same as those described in the fourth embodiment. The feature of this embodiment is that it has I / O pads 504 and 505 aligned on the front and back surfaces of the multilayer module. In FIG. 5, the arrangement of the I / O pads is the same on the back surface, but may be different. Also, in complex devices, there may be a need for additional electrical circuit conductor layers. On the contrary, in a simple device, as shown in the component built-in device in FIG. 5, there is a case where a double-sided I / O package can be realized without overlapping the electric circuit conductor layers 502 and 503 by itself. Further, a connection ball (such as a solder ball) can be attached to the double-sided or single-sided pad. At this time, when the surfaces of the I / O pads 504 and 505 are plated copper, all of them can be soldered. However, in the case of a conductive paste, it is necessary to perform plating or paste a copper foil. .

(その他の実施形態)
以上のように、本発明について様々な実施形態や実施例を挙げて説明したが、その他にも多くの変形や特殊な形状が本発明に含まれる。つまり、第1の貫通穴を有する部品チップを絶縁性樹脂中に埋め込み、この第1の貫通穴の中に部品チップに触れないように第2
の貫通穴をあけ、この第2の貫通穴に導電体を備えて表裏面の電気回路導電体の導通を取るようにしたデバイス及びその製造方法であれば、その他のあらゆる実施形態が本発明に含まれる。
(Other embodiments)
As described above, the present invention has been described with reference to various embodiments and examples, but many other modifications and special shapes are included in the present invention. That is, the component chip having the first through hole is embedded in the insulating resin, and the second chip is not touched in the first through hole.
Any other embodiment is applicable to the present invention as long as it is a device and a method of manufacturing the same in which the second through hole is provided with a conductor and the electrical circuit conductor on the front and back surfaces is made conductive. included.

本発明に係る部品内蔵デバイスの実施形態1を示す断面図である。It is sectional drawing which shows Embodiment 1 of the component built-in device which concerns on this invention. 本発明に係る部品内蔵デバイスの実施形態2を示す断面図である。It is sectional drawing which shows Embodiment 2 of the component built-in device which concerns on this invention. 本発明に係る部品内蔵デバイスの実施形態3を示す断面図である。It is sectional drawing which shows Embodiment 3 of the component built-in device which concerns on this invention. 本発明に係る多層の部品内蔵デバイスである実施形態4を示す断面図である。It is sectional drawing which shows Embodiment 4 which is a multilayer built-in device which concerns on this invention. 本発明に係る両面I/Oパッケージである実施形態5を示す断面図である。It is sectional drawing which shows Embodiment 5 which is a double-sided I / O package based on this invention.

符号の説明Explanation of symbols

101 第1の貫通穴を有する半導電体ICチップ
102 第1の貫通穴
103 絶縁性樹脂からなる基板
104 第2の貫通穴
105 I/O電極パッド
106 電気回路導電体
107 導電体
108 電気回路導電体
110 電気回路導電体
111 電気回路導電体
112 導電体
113 コンタクト窓
201 導電体
202 空洞
301 半導体ICチップ
302 第1の貫通穴
303 I/O電極パッド
304 基板
305 第2の貫通穴
306 コンタクト窓
307 溝
308 溝
309 導電性ペースト
401 部品内蔵デバイス
402 半導体ICチップ
403 電気回路導電体層
404 部品チップ内蔵層
405 部品チップ
406 電極
407 導電性ペースト
408 接続点
409 電気回路導電体
410 半導体ICチップ
411 フリップ実装
412 コンタクト窓
413 溝
414 貫通穴
415 電気回路導電体
416 基板
417 基板
501 部品内蔵デバイス
502 電気回路導電体層
503 電気回路導電体層
504 I/Oパッド
505 I/Oパッド
DESCRIPTION OF SYMBOLS 101 Semiconductor IC chip which has 1st through-hole 102 1st through-hole 103 Board | substrate which consists of insulating resin 104 2nd through-hole 105 I / O electrode pad 106 Electric circuit conductor 107 Electric conductor 108 Electric circuit electric conduction Body 110 Electrical circuit conductor 111 Electrical circuit conductor 112 Conductor 113 Contact window 201 Conductor 202 Cavity 301 Semiconductor IC chip 302 First through hole 303 I / O electrode pad 304 Substrate 305 Second through hole 306 Contact window 307 Groove 308 groove 309 conductive paste 401 component built-in device 402 semiconductor IC chip 403 electric circuit conductor layer 404 component chip built-in layer 405 component chip 406 electrode 407 conductive paste 408 connection point 409 electric circuit conductor 410 semiconductor IC chip 411 flip-flop 412 contact window 413 groove 414 through hole 415 Electrical conductor 416 substrate 417 substrate 501 component embedded device 502 electrical circuit conductor layer 503 Electrical conductor layer 504 I / O pads 505 I / O pads

Claims (13)

絶縁性樹脂からなる基板の内部に部品チップが埋め込まれた電子デバイスであって、
前記部品チップの少なくとも1つには、該部品チップの表裏面を貫通する第1の貫通穴が設けられ、
前記基板には、該基板の表裏面を貫通する第2の貫通穴が、前記第1の貫通穴の中を通り、かつ前記第1の貫通穴の内面に接しない位置に設けられ、
前記基板の表裏面に備えられた電気回路導電体が、前記第2の貫通穴の中に備えられた導電体によって導通可能に接続されていることを特徴とする部品内臓デバイス。
An electronic device in which a component chip is embedded inside a substrate made of an insulating resin,
At least one of the component chips is provided with a first through hole that penetrates the front and back surfaces of the component chip.
In the substrate, a second through hole penetrating the front and back surfaces of the substrate is provided at a position passing through the first through hole and not in contact with the inner surface of the first through hole,
The component-embedded device, wherein electrical circuit conductors provided on the front and back surfaces of the substrate are connected to be conductive by a conductor provided in the second through hole.
前記電気回路導電体と前記部品チップの電極とが電気的に接続されていることを特徴とする請求項1に記載の部品内臓デバイス。   The component built-in device according to claim 1, wherein the electric circuit conductor and the electrode of the component chip are electrically connected. 前記第1の貫通穴が略円形の断面形状を有し、前記第2の貫通穴が略円形の断面形状を有し前記第1の貫通穴と略同心円状に配置されていることを特徴とする請求項1または2に記載の部品内臓デバイス。   The first through-hole has a substantially circular cross-sectional shape, and the second through-hole has a substantially circular cross-sectional shape and is arranged concentrically with the first through-hole. The device with a built-in component according to claim 1 or 2. 前記部品チップが半導電体ICチップであることを特徴とする請求項1から3の何れか1項に記載の部品内蔵デバイス。   The component built-in device according to claim 1, wherein the component chip is a semiconductive IC chip. 前記絶縁性樹脂がレーザ加工可能な材料であることを特徴とする請求項1から4の何れか1項に記載の部品内蔵デバイス。   The component built-in device according to claim 1, wherein the insulating resin is a material that can be laser processed. 前記絶縁性樹脂が感光性樹脂であることを特徴とする請求項1から4の何れか1項に記
載の部品内蔵デバイス。
The component built-in device according to claim 1, wherein the insulating resin is a photosensitive resin.
前記導電体が導電性ペーストであることを特徴とする請求項1から6の何れか1項に記
載の部品内蔵デバイス。
The component built-in device according to claim 1, wherein the conductor is a conductive paste.
前記導電体がメッキ銅であることを特徴とする請求項1から6の何れか1項に記載の部品内蔵デバイス。   7. The component built-in device according to claim 1, wherein the conductor is plated copper. 前記電気回路導電体が、前記基板の表面及び/または裏面に設けられた溝に埋め込まれた導電性ペーストからなることを特徴とする特許請求項1から8の何れか1項に記載の部品内蔵デバイス。   9. The component built-in according to claim 1, wherein the electric circuit conductor is made of a conductive paste embedded in a groove provided on a front surface and / or a back surface of the substrate. device. 請求項1から9の何れか1項に記載の部品内臓デバイスを少なくとも1つ含み、該部品
内蔵デバイスの上下に多層の配線層を重ねたことを特徴とする多層の部品内蔵デバイス。
A multilayer component-embedded device comprising at least one component-embedded device according to any one of claims 1 to 9, wherein a multilayer wiring layer is stacked above and below the component-embedded device.
請求項1から9の何れか1項に記載の部品内臓デバイスに備えられた前記電気回路導電体に電極パッドを設けることによって形成されることを特徴とする両面I/Oパッケージ。   A double-sided I / O package formed by providing an electrode pad on the electric circuit conductor provided in the component-embedded device according to any one of claims 1 to 9. 前記基板の表裏面に設けられた前記電極パッドが、表裏面で同配列に整列していることを特徴とする請求項11に記載の両面I/Oパッケージ。   The double-sided I / O package according to claim 11, wherein the electrode pads provided on the front and back surfaces of the substrate are aligned in the same arrangement on the front and back surfaces. 部品チップに、該部品チップの表裏面を貫通する第1の貫通穴をあける工程と、
前記第1の貫通穴を有する前記部品チップを少なくとも含む部材を、絶縁性樹脂で埋め込
んで基板を形成する工程と、
前記基板に、該基板の表裏面を貫通する第2の貫通穴を、前記第1の貫通穴の中を通り、
かつ前記第1の貫通穴の内面に接しない位置にあける工程と、
前記第2の貫通穴の中に導電体を設け、前記基板の表裏面に前記導電体と電気的に接続するように電気回路導電体を設ける工程と、
を含むことを特徴とする部品内臓デバイスの製造方法。
A step of making a first through hole penetrating the front and back surfaces of the component chip in the component chip;
A step of forming a substrate by embedding a member including at least the component chip having the first through hole with an insulating resin;
A second through hole penetrating the substrate through the front and back surfaces of the substrate passes through the first through hole,
And a step of not being in contact with the inner surface of the first through hole;
Providing a conductor in the second through hole and providing an electric circuit conductor on the front and back surfaces of the substrate so as to be electrically connected to the conductor;
A method of manufacturing a device with a built-in component, comprising:
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