JP2007025882A - Means of fast recovery from power-saving mode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a system hangs up since while contents of a DRAM are expected to be held, a main program in the DRAM is executed to cause an unexpected operation if part of the contents of the DRAM is broken owing to noise or if a holding mode of the DRAM can not be entered normally because of limitation of hardware. <P>SOLUTION: The system which has a power-saving mode and comprises a CPU, a DRAM, an SRAM, and a hard disk calculates and holds a check sum of a main program part in the SRAM when the power-saving mode is selected and confirms that the main program part in the DRAM is not destroyed by using the check sum during recovery from the power-saving mode, and is not started up if the main program part is destroyed, thereby avoiding a stoppage of the system. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a general system that reduces standby power in a power saving mode and needs to be activated at a high speed for incoming remote data such as a network or a FAX.

  In recent years, means for shutting down the CPU power supply in the power saving mode has already been put into practical use in order to meet the increasingly strict energy saving standards. However, on the other hand, there is an increasing need to return from the power saving mode to the normal operation mode at high speed, such as a printer or a multifunction device compatible with the network. In recent multifunction devices, etc., the scale of the program has increased, and if all programs are stored in ROM, there is a concern about cost increase, so the hard disk is also used as an image storage means and the program is stored in a part of the area. Sometimes. However, in this case, the program is downloaded from the hard disk to the RAM after startup, and then the program is executed on the RAM. There is an element that conflicts with the necessity of the above-described rapid recovery.

  Therefore, the CPU main program is held on the DRAM when shifting to the power saving mode, and the main program held on the DRAM is started at high speed when returning from the power saving mode to the normal operation mode. The main program writes a flag intended for the power saving mode to the storage means configured by inexpensive logic, holds the flag even when the power saving mode is executed, and the main program refers to the state of the flag when the power saving mode returns. Thus, by providing a system characterized by having means for determining that the main program has returned from the power saving mode, it is possible to realize a high speed return from the power saving mode at a low price.

As a conventional example, for example, Patent Document 1 can be cited.
JP 2004-005029 A

  However, if noise occurs and the contents of the DRAM are partially destroyed, or if the transition to the DRAM retention mode cannot be performed normally due to hardware restrictions, the main program on the DRAM is expected to be retained. Will cause unexpected behavior and the system will hang.

  Therefore, in the present invention, there is a power saving mode, and in a system composed of a CPU, DRAM, SRAM, and hard disk, when the power saving mode is selected, a checksum of the main program part is calculated and stored in the SRAM, When returning, check that the main program part on the DRAM is not destroyed, and if it is destroyed, restart the system to stop the system. It can be avoided.

  As described above, in the present invention, a power saving mode exists, and in a system including a CPU, ROM, DRAM, SRAM, and hard disk, power supplied to the CPU that controls the system is cut off when the power saving mode is selected. When entering the power saving mode, a checksum of the main program of the previous term CPU is calculated and held in the previous term SRAM, and the main program of the CPU is held in the DRAM, and the power saving mode When returning from the normal operation mode to the normal operation mode, the main program held in the DRAM is confirmed by the checksum in the SRAM, and the main program held in the DRAM has a mechanism for starting at high speed. In the case of a low-cost, low-power-consumption system where memory destruction occurs due to power supply noise in the power-saving mode, etc. System that operates stably even when

  Examples of the present invention will be described below.

  FIG. 1 is a conceptual schematic diagram illustrating the system configuration of the first embodiment.

  In FIG. 1, reference numeral 101 denotes a network using a known technique for connecting devices. In this embodiment, it is assumed that the TCP / IP protocol is used.

  Reference numeral 102 denotes a network scanner that optically reads a document printed on paper or the like, and includes a network interface. Scanned image data is a RGB color scanner.

  Reference numerals 108, 107, and 106 are network printers that have a network interface, receive print data and image data sent via the network interface, and actually print on media such as paper using a known print technology such as electrophotographic technology. . Network printers 108, 107, and 106 are also connected to each device via the network 101. Here, reference numeral 108 denotes a black and white digital multifunction peripheral, 107 denotes a color laser printer, and 106 denotes a black and white laser beam printer.

  A fax 104 includes a network interface and transmits and receives image data via the public line 105. An interface that transmits image data read by the scanner 102 on the network 101, outputs the received image data from the printers 108, 107, and 106, and inputs and outputs image data to be filed on the PC 103 on the public line 105 is there.

  Details of the hardware and software of this embodiment will be described below.

[hardware]
Overall Configuration The overall configuration diagram is shown in FIG. Controller Unit 2000 is a controller for inputting / outputting image information and device information by connecting to Scanner 2070 as an image input device and Printer 2095 as an image output device, while connecting to LAN 2011 or public line (WAN) 2051. is there. The CPU 2001 is a controller that controls the entire system. A RAM 2002 is a system work memory for operating the CPU 2001, and is also an image memory for temporarily storing image data. ROM 2003 is a boot ROM, which stores a system boot program. The HDD 2004 includes a hard disk drive and an IDE controller, and stores system software, image data, and management information thereof. SRAM 2009 is a non-volatile memory that holds system configuration data. An operation unit I / F 2006 is an operation unit (UI) 2012 and an interface unit, and outputs image data to be displayed on the operation unit 2012 to the operation unit 2012. Also, it plays a role of transmitting information input from the operation unit 2012 by the system user to the CPU 2001. Network2010 connects to LAN2011 and inputs / outputs information. A Modem 2050 is connected to the public line 2051 and inputs / outputs information. The above devices are arranged on the system bus 2007. Image Bus I / F2005 is a bus bridge that connects a system bus 2007 and an image bus 2008 that transfers image data at high speed, and converts the data structure. The image bus 2008 is configured by a PCI bus or IEEE1394. The following devices are arranged on the image bus 2008. A raster image processor (RIP) 2060 expands the PDL code into a bitmap image. A device I / F unit 2020 connects an image input / output device such as a scanner 2070 and a printer 2095 to the controller 2000, and performs synchronous / asynchronous conversion of image data. A scanner image processing unit 2080 corrects, processes, and edits input image data. The printer image processing unit performs printer correction, resolution conversion, and the like on the print output image data. The image rotation unit 2030 rotates image data. The image compression unit 2040 performs compression / expansion processing of JPEG for multi-valued image data and JBIG, MMR, and MH for binary image data.

Image Input / Output Unit An image input / output device is shown in FIG. A scanner unit 2070 serving as an image input device illuminates an image on paper as an original and scans a CCD line sensor (not shown), thereby converting the image into raster signal data 2071 into an electrical signal. The manuscript paper is set on the tray 2073 of the manuscript feeder 2072, and when the apparatus user gives an instruction to start reading from the operation unit 2012, the controller CPU2001 gives an instruction to the scanner 2070 (2071). Feeds and reads the original image.

  The printer unit 2095, which is an image output device, is a part that converts raster image data 2096 into an image on paper. The method is an electrophotographic method using a photosensitive drum or a photosensitive belt, and ink is ejected from a micro nozzle array. In addition, there is an ink jet method for printing an image directly on a sheet, but any method may be used. The start of the printing operation is started by an instruction 2096 from the controller CPU2001. The printer unit 2095 has a plurality of paper feed stages so that different paper sizes or different paper orientations can be selected, and has paper cassettes 2101, 2102, 2103, 2104 corresponding to the paper feed stages. A paper discharge tray 2111 receives paper that has been printed.

Operation Unit The configuration of the operation unit 2012 is shown in FIG. The LCD display unit 2013 has a touch panel sheet pasted on the LCD, displays a system operation screen, and transmits the position information to the controller CPU 2001 when a displayed key is pressed. A start key 2014 is used when starting a document image reading operation. In the center of the start key 2014, there is a green and red two-color LED 2018, which indicates whether or not the start key 2014 can be used. The stop key 2015 works to stop the running operation. The ID key 2016 is used when inputting the user ID of the user. A reset key 2017 is used when initializing settings from the operation unit.

Scanner Image Processing Unit The configuration of the scanner image processing unit 2080 is shown in FIG. The image bus I / F controller 2081 is connected to the image bus 2008, and controls the bus access sequence and generates control and timing of each device in the scanner image processing unit 2080. The filter processing unit 2082 performs a convolution operation with a spatial filter. For example, the editing unit 2083 recognizes a closed region surrounded by a marker pen from the input image data, and performs image processing such as shading, shading, and negative / positive inversion on the image data in the closed region. A scaling processing unit 2084 performs enlargement and reduction by performing an interpolation operation in the main scanning direction of the raster image when changing the resolution of the read image. The scaling in the sub-scanning direction is performed by changing the scanning speed of an image reading line sensor (not shown). The table 2085 is table conversion performed to convert image data that is read luminance data into density data. A binarization 2086 binarizes multi-value grayscale image data by error diffusion processing or screen processing.

  The processed image data is transferred to the image bus via the image bus controller 2081 again.

Printer Image Processing Unit The configuration of the printer image processing unit 2090 is shown in FIG. The image bus I / F controller 2091 is connected to the image bus 2008, and controls the bus access sequence, and generates control and timing of each device in the scanner image processing unit 2090. The resolution conversion unit 2092 performs resolution conversion for converting image data from the Network 2011 or the public line 2051 into the resolution of the printer 2095. The smoothing processing unit 2093 performs processing to smooth out jaggies (roughness of an image appearing in a black and white boundary portion such as an oblique line) of image data after resolution conversion.

Image Compression Unit The configuration of the image compression unit 2040 is shown in FIG. The image bus I./F controller 2041 is connected to the image bus 2008 to control the bus access sequence, timing control for exchanging data with the input buffer 2042 and the output buffer 2045, and an image compression unit 2043 Control the mode setting for. The processing procedure of the image compression processing unit is shown below.

  Settings for image compression control are performed from the CPU 2001 to the image bus I / F controller 2041 via the image bus 2008. With this setting, the image bus I / F controller 2041 performs settings necessary for image compression (for example, MMR compression and JBIG expansion) for the image compression unit 2043. After making the necessary settings, the CPU 2001 again permits image data transfer to the image bus I / F controller 2041. In accordance with this permission, the image bus I / F controller 2041 starts transferring image data from each device on the RAM 2002 or the image bus 2008. The received image data is temporarily stored in the input buffer 2042, and the image is transferred at a constant speed in response to an image data request from the image compression unit 2043. At this time, the input buffer determines whether image data can be transferred between both the image bus I / F controller 2041 and the image compression unit 2043, reads the image data from the image bus 2008, and reads the image compression unit 2043. When it is impossible to write an image to the image, control is performed so as not to transfer data (hereinafter, such control is referred to as handshaking). The image compression unit 2043 temporarily stores the received image data in the RAM 2044. This is because several lines of data are required depending on the type of image compression processing to be performed, and several lines of image data are prepared in order to compress the first one line. This is because the image cannot be compressed unless it is empty. The image data subjected to the image compression is immediately sent to the output buffer 2045. The output buffer 2045 performs handshaking with the image bus I / F controller 2041 and the image compression unit 2043 and transfers image data to the image bus I / F controller 2041. The image bus I / F controller 2041 transfers the transferred compressed (or expanded) image data to each device on the RAM 2002 or the image bus 2008. This series of processing is repeated until there is no processing request from the CPU 2001 (when the required number of pages has been processed), or until a stop request is issued from this image compression unit (when an error occurs during compression or decompression). It is.

Image Rotation Unit The configuration of the image rotation unit 2030 is shown in FIG. The image bus I / F controller 2031 is connected to the image bus 2008 to control the bus sequence, control to set a mode or the like in the image rotation unit 2032, and timing to transfer image data to the image rotation unit 2032 Take control. The processing procedure of the image rotation unit is shown below.

  Settings for image rotation control are performed from the CPU 2001 to the image bus I / F controller 2031 via the image bus 2008. With this setting, the image bus I / F controller 2041 performs settings necessary for image rotation (for example, image size, rotation direction, angle, and the like) for the image rotation unit 2032. After making the necessary settings, the CPU 2001 again permits image data transfer to the image bus I / F controller 2041. In accordance with this permission, the image bus I / F controller 2031 starts transfer of image data from each device on the RAM 2002 or the image bus 2008. Here, the size of the image to be rotated is set to 32 × 32 (bit), and the image transfer is performed in units of 32 bits when transferring the image data on the image bus 2008. The image to be handled is assumed to be binary).

As described above, in order to obtain a 32 × 32 (bit) image, it is necessary to perform the above unit data transfer 32 times, and it is necessary to transfer image data from discontinuous addresses. (See Figure 10)
The image data transferred by the discontinuous addressing is written in the RAM 2033 so that it is rotated at a desired angle at the time of reading. For example, if the rotation is 90 degrees counterclockwise, the 32-bit image data transferred first is written in the Y direction as shown in FIG. By reading in the X direction at the time of reading, the image is rotated.

  After the 32 × 32 (bit) image rotation (writing to the RAM 2033) is completed, the image rotation unit 2032 reads the image data from the RAM 2033 by the above-described reading method, and transfers the image to the image bus I / F controller 2031.

  The image bus I / F controller 2031 that has received the rotated image data transfers the data to each device on the RAM 2002 or the image bus 2008 by continuous addressing.

  Such a series of processing is repeated until there is no processing request from the CPU 2001 (when processing of the required number of pages is completed).

Device I / F Unit The configuration of the device I / F unit 2020 is shown in FIG. The image bus I / F controller 2021 is connected to the image bus 2008, and controls the bus access sequence and generates control and timing of each device in the device I / F unit 2020. In addition, control signals to the external scanner 2070 and the printer 2095 are generated. The scan buffer 2022 temporarily stores the image data sent from the scanner 2070, and outputs the image data in synchronization with the image bus 2008. The serial-parallel / parallel-serial conversion 2023 arranges the image data stored in the scan buffer 2022 in order or decomposes and converts the image data into a data width that can be transferred to the image bus 2008. The parallel-serial / serial-parallel conversion 2024 decomposes the image data transferred from the image bus 2008 or arranges them in order, and converts the image data into a data width that can be stored in the print buffer 2025. The print buffer 2025 temporarily stores the image data sent from the image bus 2008 and outputs the image data in synchronization with the printer 2095.

  The processing procedure at the time of image scanning is shown below. The image data sent from the scanner 2070 is stored in the scan buffer 2022 in synchronization with the timing signal sent from the scanner 2070. If the image bus 2008 is a PCI bus, when image data is 32 bits or more in the buffer, the image data is sent in 32 bits on a first-in first-out basis from the buffer to the serial-parallel / parallel-serial conversion 2023. Is transferred to the image bus 2008 through the image bus I / F controller 2021. If the image bus 2008 is IEEE1394, the image data in the buffer is first-in-first-out, sent from the buffer to the serial-parallel / parallel-serial conversion 2023, converted to serial image data, and then converted to serial image data through the image bus I / F controller 2021. Transfer on 2008.

  The processing procedure at the time of image printing is shown below. When the image bus 2008 is a PCI bus, the 32-bit image data sent from the image bus is received by the image bus I / F controller, sent to the parallel-serial / serial-parallel conversion 2024, and the number of input data bits of the printer 2095 Are stored in the print buffer 2025. When the image bus 2008 is IEEE1394, the serial image data sent from the image bus is received by the image bus I / F controller, sent to the parallel serial / serial / parallel conversion 2024, and the number of input data bits of the printer 2095 is It is converted into image data and stored in the print buffer 2025. Then, in synchronization with the timing signal sent from the printer 2095, the image data in the buffer is sent to the printer 2095 in a first-in first-out manner.

[Quick recovery from power saving mode]
Next, the quick return means from the power saving mode which is the center of the present invention will be described. 12 to 13 show a main part of the controller unit 2000 shown in FIG. 2 and circuit parts necessary for achieving the power saving mode. A solid line portion and a broken line portion shown in the figure indicate divisions of the portions driven by the night-night power system and the emergency night power system, respectively. The night-time power supply system mentioned here indicates a power supply system that is supplied even when the power saving mode proposed by the present invention is shifted, and the emergency night power supply system is always indicated when the power saving mode proposed by the present invention is shifted. A power system that is disconnected from the night power system and is not supplied with power. 12 to 13, the FET 11001 plays a role of separating the night power system from the night power system. In this way, when the night power supply system and emergency night power supply system are disconnected and the system is switched to the power saving mode, the power is turned off except for the main part of the controller unit (the part that requires the minimum power supply). It becomes possible to suppress electric power. Although not shown in FIGS. 12 to 13, the ROM 2003 in FIG. 2 is supplied by the nightly power system, and the HDD 2004 is supplied by the emergency night power system.

  What is characteristic in the present invention is that the power supply of the CPU 2001, which is generally large in power consumption in the controller unit, is supplied in an emergency night power system, and in a power saving mode, the power is not supplied and the standby is performed. However, this system is equipped with a mechanism necessary for the system to return to its own power due to external factors. In addition, this system controls a large number of functions as described above, and the software has a very large capacity, so only the information necessary for booting is written in ROM2003 for the purpose of reducing the total cost of the system. The software that describes the actual main operation is stored in the HDD 2004 used mainly for the purpose of storing image information. For this reason, when the main power supply is activated, the main program is executed after downloading a large-capacity main program on the HDD 2004 to the RAM 2002 (in this embodiment, SDRAM is used). In this case, the main program is started. Because it takes time to complete, communication may be interrupted due to timeout depending on external activation factors such as network and fax. In recent years, the startup time itself is often the selling point of the specifications of multifunction devices and the like, and from this aspect, it is necessary to devise a way to shorten the startup time as much as possible. In order to solve this problem, the present invention performs the following control using a low-cost storage means such as that shown in FIGS.

When shifting to the power saving mode FIG. 12 is a circuit configuration diagram showing the control flow when the system shifts to the power saving mode. Hereinafter, the flow of control when shifting to the power saving mode will be described.

  (1) First, when the user designates the shift to the power saving mode on the operation unit 2012 or when the system is not used for a certain period of time, the software of this system satisfies the condition for shifting to the power saving mode. The main program checksum is calculated and stored in SRAM2009.

  (2) Next, as a means for storing the transition to the power saving mode, the CPU 2001 changes the general-purpose output port GPO <1> from L to H to FripFrop11005 to set a flag (output of FripFrop11005 = '1') I do. Since the FripFrop11005 is driven by the power supply system all night, this flag holds the value even when the mode is shifted to the power saving mode.

  (3) Next, a self-refresh command is issued to the SDRAM 2002 to hold the main program and data.

  (4) Next, for FripFrop11002, CPU2001 changes the general-purpose output port GPO <0>, presets the output of FripFrop11002 to H, turns off FET11001, shuts off the emergency night power supply system including CPU2001, and saves power Migrate to

  The above is the flow of control until shifting to the power saving mode. Buffer11006 to Buffer11008 in the figure are driven by an emergency night power supply system, and play a role of preventing current flow from the nighttime power supply system when shifting to the power saving mode. Further, the RESET IC 11003 monitors the power supply system all night and plays a role of clearing the flag of FripFrop11005 at the time of startup after the main power supply which will be described later. The logic OR gate 11004 summarizes the factors for returning from the power saving mode, and generates an interrupt to the CPU 2001 when an event that causes any one of the factors occurs.

When returning from the power saving mode FIG. 13 is a circuit configuration diagram showing the flow of control when the system returns from the power saving mode. Hereinafter, the flow of control when returning from the power saving mode will be described.

  (1) When this system is waiting in the power saving mode, a power on signal from means that can be a factor for returning from the power saving mode is input to the interrupt terminal of the CPU 2001 via the logic OR gate 11004. In this embodiment, an example in which UI (operation unit 2012), Network 2010, and FAX (modem 2050) can be factors is shown.

  (2) The power on signal is also connected to FripFrop11002. When a factor for returning from the power saving mode occurs, the clock edge is given to FripFrop11002, FET10001 is turned on, the emergency power supply system starts up and the power saving mode starts. Return begins.

  (3) When the emergency night power supply system is turned on, the CPU 2001 boots and executes the boot program on the ROM 2003. The boot program refers to the value of the flag stored in the FripFrop 11005 from the general-purpose output port GPI <0> of the CPU 2001.

  (4) Since the reading value of the flag is “1”, the boot program interprets that the state has returned from the power saving mode, obtains the checksum of the main program held on the SRAM 2009, and stores it on the SDRAM 2002. A checksum is again calculated from the stored main program and compared to confirm that they match.

  (5) If they match, the main program stored on the SDRAM 2002 starts to be executed. Also, the main program receives the signal input to the interrupt terminal of CPU2001, recognizes that some external activation factor has occurred, and the power on the UI (operation unit 2012), Network2010, FAX (modem2050) Search for the on factor, figure out what the activation factor is, and execute control after activation.

  (6) If they do not match, reboot itself and restart.

  This completes the description of the quick return means from the power saving mode according to the present invention.

1 is an overall configuration diagram of a network system in the present invention. 1 is an overall block diagram of this system. FIG. 3 is an external view of a scanner unit, a printer unit, and an operation unit. Operation part. The block diagram of a scanner image processing part. FIG. 3 is a block diagram of a printer image processing unit. The block diagram of an image compression process part. The block diagram of a device I / F part. The block diagram of an image rotation part. Explanatory drawing of an image rotation process. Explanatory drawing of an image rotation process. The control flow and circuit block diagram when shifting to a power saving mode. The control flow and circuit block diagram when returning from a power saving mode.

Claims (6)

  In a system that includes a power saving mode and includes a CPU, ROM, DRAM, SRAM, and hard disk, the power supplied to the CPU that controls the system is cut off when the power saving mode is selected. When entering the power mode, the CPU calculates the checksum of the main CPU of the previous term and holds it in the previous term SRAM. The main program of the CPU is held in the DRAM and returns from the power saving mode to the normal operation mode. In some cases, the main program held on the DRAM is confirmed by a checksum on the SRAM, and the system has a mechanism for starting at high speed by the main program held on the DRAM.   2. The mechanism for operating according to the main program held on the DRAM when returning from the power saving mode to the normal operation mode is an inexpensive logic in which power is supplied even when the power saving mode is executed. The main program writes a flag intended for the power saving mode to the storage means configured as follows, the flag is retained even when the power saving mode is executed, and the boot program stored in the ROM when the power saving mode is restored is the flag of the flag. A system characterized in that it is means for judging that the state has been returned from the power saving mode by referring to the state.   3. The boot program according to claim 1, wherein the storage means erases the flag when the power supply of the entire system is cut off, and the boot program determines that it is not the return from the power saving mode at the start-up but the start-up of the entire system. Thus, a system having means for avoiding a startup failure due to an erroneous determination of a boot program.   2. The main program for controlling the system according to claim 1, wherein the main program is stored in the hard disk, and the main program is downloaded from the hard disk to the DRAM of the system when the power is turned on after the entire system is powered off. A system characterized by executing a main program on DRAM.   2. The system according to claim 1, wherein the means for holding the main program on the DRAM is realized by issuing a self-refresh command to the DRAM.   When the main program held in the DRAM is confirmed by the checksum on the SRAM when returning from the power saving mode to the normal operation mode in claim 1, it is confirmed that the checksum is abnormal. A system characterized by reloading the main program from the hard disk in the same way as normal startup.

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