JP2007019528A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves improving an yield. <P>SOLUTION: The semiconductor device has: an interlayer insulating film 37 formed on a semiconductor substrate 36, a metal pattern formed on the interlayer insulating film; an inorganic insulating film 38 with first openings formed to expose the metal pattern, protruded electrodes 35a electrically connected to the metal pattern through the first openings, organic insulating film 32 formed on the inorganic insulating film having second openings to expose at least upper portions of the protruded electrodes; an underlying metal layers 41 and a solder layers 42 formed on the surfaces of at least the upper portions of the protruded electrodes; and a cover film 46 made of a resin or a metal formed on at least one of the backside and side surfaces of the semiconductor substrate. The organic insulating film can be formed of a material having an absorption rate of 0.5% or less for 24 hours at a room temperature. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an external connection terminal and a semiconductor device, and more particularly to an external connection terminal in a semiconductor device, an electronic component, a wiring board, a package, and the like, and a semiconductor device provided with a protruding connection terminal.

  Solder is used to electrically and mechanically connect the semiconductor device and the ceramic substrate, or to electrically and mechanically connect the electronic component and the wiring substrate.

  For example, the solder is placed in a ball shape on the metal wiring, and then applied onto the metal wiring by screen printing, and then joined to the metal wiring by heating and melting. The metal wiring is generally made of a metal containing a large amount of aluminum (Al) or copper (Cu).

  When solder is bonded to the surface of a metal wiring, a diffusion barrier metal (barrier metal) is formed between the solder and the metal wiring in order to prevent mutual diffusion between the constituent elements of the metal wiring and tin (Sn) in the solder. In general, a nickel (Ni) layer is formed as a layer. As a method of forming the nickel layer, it is advantageous to adopt an electroless plating method that does not use a power supply terminal in order to shorten the film forming process and to reduce the cost. Moreover, in order to improve the wettability of solder, a gold layer may be formed on a nickel layer.

  FIG. 1 shows, for example, a state before the solder is joined onto the metal wiring on which such a nickel layer and a gold layer are formed. In FIG. 1, a nickel (Ni) layer 103 and a gold (Au) layer 104 are formed on a part of a surface of a metal wiring 102 on an insulating film 101 by an electroless plating method, and a tin alloy solder 105 is placed thereon. It is burned.

  Further, before forming the tin alloy solder 105, another solder layer made of a material having a higher melting point and lower tin content than that of the tin alloy solder is formed on the gold layer 104 by an electroless plating method or the like. It is described in 2000-133739.

  As another structure between the solder layer and the metal wiring, Japanese Patent Laid-Open No. 2000-22027 describes that a nickel plating layer, a palladium plating layer, and a gold plating layer are formed on the wiring.

  Further, a gold film may be used instead of the tin alloy solder layer. As a barrier metal film between the gold film and the wiring, for example, in Japanese Patent Application Laid-Open No. 3-209725, a nickel film is formed by an electroless plating method. It is described to form.

  Various other structures are known as the layer structure between the wiring and the solder layer.

  For example, in Japanese Patent Laid-Open No. 9-8438, an electroless nickel plated film, a substituted palladium film, an electroless palladium plated film, a substituted gold plated film, and an electroless gold plated film are sequentially formed on the surface of a wire bonding terminal. Is described.

  In JP-A-5-299534, as a stem to be soldered, a first layer made of electrolytic nickel plating, a second layer made of electroless nickel boron plating or electroless nickel phosphorus plating, and palladium or a palladium alloy are used. The structure which formed the 3rd layer which becomes the order on the metal outer ring is described. Here, palladium or palladium alloy is formed in order to improve solder wettability.

Incidentally, the conductive pins used as the external connection terminals of the semiconductor device are described in, for example, Japanese Patent Publication No. 9-505439 (published in Japan), and the surface of the semiconductor device on the side where the conductive pins are formed is a resin package. Covered by. A protruding electrode used for an external connection terminal of a semiconductor device is described in, for example, Japanese Patent Application Laid-Open No. 5-55278. The semiconductor device in which these conductive pins and protruding electrodes are formed has a real chip size.
JP 2000-133739 A Japanese Patent Laid-Open No. 3-209725 Japanese Patent Laid-Open No. 9-8438 JP-A-5-299534 Japanese National Patent Publication No. 9-505439 JP-A-5-55278

  As described above, nickel or a nickel alloy is formed on the surface of the wiring, pin, or stem to which the solder is joined, and a single layer or a multilayer structure made of gold, palladium, or the like is further formed thereon.

  However, according to such a structure, after solder is heated and melted and joined to the wiring, pin, or stem, the solder is easily peeled off from the wiring, pin, or stem by an external impact or the like.

  As a cause of such peeling, Japanese Patent Laid-Open No. 2000-133739 states that phosphorus contained in a nickel layer formed by an electroless plating method has a high concentration when the solder is melted.

  By the way, there is a point to be improved as follows in the package of a semiconductor device and the external connection terminal formed in the semiconductor device.

  For example, as described in JP-A-5-55278 and JP-A-9-505439, a semiconductor device miniaturized to the same size as a chip has the ability to relieve thermal stress in a conventional package. In comparison, the stress tends to concentrate on the external connection terminal mounting portion.

  In the semiconductor device described in Japanese Patent Laid-Open No. 5-55278, the sealing resin is formed only on one surface of the silicon chip, and the side surface and the back surface are exposed. Since silicon has a property of being easily chipped, if the silicon chip is thinned, a circuit formed in the chip may be damaged due to chipping of silicon from the exposed surface side.

  In other words, in a package miniaturized to the same size as the chip, chipping and cracks on the back and side surfaces may cause circuit damage, which may reduce the manufacturing yield.

  The structure described in Japanese Patent Application Laid-Open No. 9-505439 aims at improving mounting reliability by forming electrodes on metal pads with deformable metal wires. Although this electrode can be formed by a normal wire bonder, the formation tact takes many times as long as normal bonding, and the manufacturing cost increases. In addition, the electrode made of metal wire is covered with a metal shell formed by electrolytic plating. However, if the electroplating is performed with the wiring pattern connected to the metal wire exposed, the film of the metal shell The thickness distribution greatly depends on the current density distribution during electrolytic plating, and it is difficult to obtain a sufficient and uniform thickness, so that it is difficult to make fine pitches of electrodes made of metal wires. Moreover, if the metal shell is formed by electrolytic plating and then the metal film is etched to form a wiring, there is a concern about migration of the wiring material.

  Japanese Patent Publication No. 9-505439 discloses that a pin-shaped metal wire is covered with a nickel layer and a gold layer, and then the metal wire is connected to the outside by soldering. When forming the film by electroless plating, cracks may occur between the solder and the metal wire as described above.

  An object of the present invention is to provide a semiconductor device capable of improving yield.

  The above-described problems include an interlayer insulating film formed on a semiconductor substrate, a metal pattern formed on the interlayer insulating film, an inorganic insulating film in which a first opening exposing the metal pattern is formed, A protruding electrode electrically connected to the metal pattern through the first opening; an organic insulating film having a second opening formed on the inorganic insulating film and exposing at least an upper portion of the protruding electrode; A base metal layer and a solder layer formed on at least the upper surface of the projecting electrode; and a coating film made of resin or metal formed on at least one of the lower surface and the side surface of the semiconductor substrate. This is solved by the featured semiconductor device.

  In the semiconductor device described above, the organic insulating film is formed of a material having an absorption rate of 0.5% or less for 24 hours at room temperature.

  Next, the operation of the present invention will be described.

  According to the present invention, in the chip-like semiconductor device having the protruding electrode, the coating film made of an organic insulating material or metal is formed on at least one of the lower surface and the side surface of the semiconductor substrate. Chipping and cracking are less likely to occur, and damage to the semiconductor circuit is prevented, improving the yield of the semiconductor device.

  Further, by covering the metal pattern to which the external connection terminal is connected with an organic insulating film having a low moisture absorption rate, it is possible to prevent the migration of the metal pattern, and the reliability of the package is improved. In addition, by using any one of copper, aluminum, and gold for electrodes and wiring, it becomes possible to form a semiconductor device at low cost with existing equipment with electrodes and wiring excellent in electrical conductivity and heat dissipation.

  By making the external connection terminal into a rod shape such as a columnar shape or a polygonal columnar shape, the length of the external connection terminal can be increased without increasing the width, and the fine pitch of the external terminal can be made.

  In addition, by forming the external connection terminal in a straight line shape, it is possible to form the external connection terminal with a short tact time with an existing apparatus when performing wire bonding.

  As described above, the concern about migration of the wiring material can be eliminated, and the fine pitch of the protruding electrodes can be achieved.

(First embodiment)
First, the analysis results after joining the nickel phosphorus layer and the tin alloy solder layer formed in sequence on the uppermost metal wiring or metal pad of the semiconductor device will be described below.

  FIG. 2A is a cross-sectional view showing a conventional structure immediately before solder is joined to wiring on a semiconductor device.

  In FIG. 2A, a wiring 111 made of copper or aluminum is formed on the insulating film 110, and a nickel phosphorus (NiP) layer 112 is formed on a part of the wiring 111 by an electroless plating method. Furthermore, a eutectic tin lead (SnPb) solder layer 113 is placed thereon. The nickel phosphorus layer 112 that is a barrier layer is formed by incorporating phosphorus contained in diphosphorous acid that is a reducing agent for electroless plating into the nickel layer, and the phosphorus concentration in the nickel phosphorus layer 112 is It is 8-15 wt.%.

  In such a state, after the solder layer 113 was heated and melted and then cooled, a cross section of the interface between the NiP layer 112 and the solder layer 113 was taken with an SEM photograph, and a layer structure as shown in FIG. 3 was confirmed. . That is, it has been clarified that the structure shown in FIG. 2A is changed to the structure shown in FIG. In addition, FIG. 3 is drawn based on the SEM photograph.

  In FIG. 2 (b), a high concentration (rich) phosphorus-containing NiP layer (hereinafter referred to as a “rich P—Ni layer”) 112a, a NiSnP layer 112b, and a NiSn layer 112c are formed on the NiP layer 112 by heating and melting. Tin alloy solder layers 113 were formed in order, and dot-like voids 114 were formed in the NiSnP layer 112b as shown in FIG. The heated and melted solder layer 113 is used as an external connection terminal together with the wiring 111.

  The change in the interface between the solder layer 113 and the NiP layer 112 due to heating is as follows.

  When the solder layer 113 melts, a high P-Ni layer 112a and a NiSn layer 112c grow between the solder layer 113 and the NiP layer 112 due to mutual diffusion of tin and nickel, and at the same time, the high P-Ni layer 112a and A NiSnP layer 112b is formed between the NiSn layers 112c. As the heating continues, nickel in the NiSnP layer 112b diffuses toward the solder layer 113 due to the Kirkendall effect, and the NiSn layer 112c further grows. This is called Kendall void.) 114 occurs. The inventors have confirmed that such a phenomenon also occurs when the solder layer 113 is heated and melted again after the solder layer 113 is joined to the wiring 111.

  The high P—Ni layer 112a is formed in a portion of the NiP layer 112 close to the solder layer 113, and the phosphorus concentration increases as nickel in the NiP layer 112 diffuses into the solder layer 113. Is formed. The phosphorus concentration in the high P—Ni layer 112a is 15 to 25 wt.%.

  Next, a connection terminal having the structure shown in FIG. 2 (b) is formed on the ceramic substrate, the solder layer 113 is heated and melted again and joined to the wiring on the semiconductor device (not shown), and then a drop test of the ceramic substrate is performed. As a result, the connection terminal was destroyed and the solder layer 113 was peeled off from the wiring 111. When a cross-section of the layer structure on the wiring 111 after the solder layer 113 was peeled off was photographed with an SEM photograph, the solder layer 113 and the NiSn layer 112c were peeled off from the wiring 111 and the NiSnP layer 112b was exposed as shown in FIG. It was.

  In order to suppress such peeling of the solder layer 113, it is conceivable to fill the underfill between the semiconductor device and the ceramic substrate and bond them, but this increases the manufacturing cost and in subsequent tests. There is a disadvantage that when a connection failure of the connection terminal is found, the semiconductor device on the ceramic substrate cannot be replaced.

  As shown in FIG. 5 (a), a Pd (palladium) layer 115 is formed on a wiring 111 made of copper or aluminum to a thickness of 2 μm by an electroless plating method, and a tin lead (SnPb) solder layer is further formed thereon. 113 was formed. Thereafter, when the solder layer 113 was heated and melted, a structure as shown in FIG. 5B was obtained. In FIG. 5B, a large amount of PdSn alloy layer 115a is grown at the interface between the Pd layer 115 and the SnPb solder layer 113, and Kirkendall voids are generated in the PdSn alloy layer 115a, and the solder layer 113 is peeled off. It has been confirmed by the inventors' experiments that it is easy to do this.

  As described above, the data regarding the strength of the external connection terminal obtained by joining the Pd layer 115 and the solder layer 113 is not described at least in the publicly known literature described in the background art section.

  Based on the analysis results as described above, the inventors of the present invention have the following connection terminals formed on a semiconductor device, a circuit board, an electronic component, etc. in order to improve the bonding strength between the NiP layer and the Sn alloy solder layer. I thought about adopting a simple structure.

  The first structure is to suppress the growth of the high P—Ni layer by adopting a structure that prevents Sn in the Sn alloy solder layer from excessively diffusing into the NiP layer.

  The second structure is to suppress the generation of Kirkendall void by adopting a structure in which the NiSnP layer is not formed at the interface between the NiP layer and the NiSn layer.

  In order to realize such a structure, the inventors formed external connection terminals having structures as shown in the following (i) to (iii) on the wiring.

(I) 1st external connection terminal The 1st external connection terminal on the metal pattern used as a wiring and a pad is formed as follows, for example.

  First, as shown in FIG. 6A, a ceramic (insulating) substrate 1 having a wiring 3 formed on the upper surface is used and covered with a resist 2 except for a solder joint region of the wiring 3.

  Subsequently, as shown in FIG. 6B, a NiP layer 5 is formed as a barrier metal layer on the wiring (electrode) 3 made of aluminum, copper, or an alloy containing either of them as a main component by an electroless plating method. It is formed to a thickness of 2 μm. As a plating solution for forming the NiP layer 5, for example, diphosphorous acid, linden SA (trade name, manufactured by World Metal) or the like is used. The phosphorus concentration in the NiP layer 5 is 1 to 15 wt.%.

  Further, as shown in FIG. 6C, a palladium (Pd) layer 6 having a thickness of 200 nm or less and a gold (Au) layer 7 having a thickness of 100 nm or less are formed on the NiP layer 5 by an electroless plating method. . As a plating solution for forming the Pd layer 6, for example, Linden PD (trade name of World Metal Co.) is used. Further, as a plating solution for forming the Au layer 7, for example, Oureclectres SMT-210 (trade name, manufactured by Nihon Leronal) is used.

  The Au layer 7 is formed in order to improve the wettability of the solder when the solder is melted, and the Pd layer 6 is formed in order to prevent the NiP layer 5 from being oxidized.

  Next, as shown in FIG. 6 (d), a tin alloy solder layer 8 containing at least 5 wt.% Of Sn, such as tin lead (SnPb) solder, tin silver copper (SnAgCu) solder, is formed on the Au layer 7. To do. The tin alloy solder 8 may be a SnBi layer containing 4% of bismuth (Bi). When the tin alloy solder 8 is formed, a method such as screen printing using a solder paste or ball mounting is employed.

  Thereafter, the solder layer 8 is heated and bonded to the wiring 3 through the NiP layer 5, the Pd layer 6, and the Au layer 7. In this case, it is preferable that the heating temperature is higher than the melting point of the solder layer 8 and the heating time is shorter than 20 minutes.

  When the Au layer 7 and the Pd layer 6 are not interposed between the solder layer 8 and the NiP layer 5, the solder layer 8 can be joined to the NiP layer 5 at a temperature below the solder melting point. However, if the Au layer 7 and the Pd layer 6 are interposed between the solder layer 8 and the NiP layer 5, the solder layer 8 is sufficiently wet on the NiP layer 5 unless the solder layer 8 is melted at a temperature equal to or higher than its melting point. Does not spread.

  When the solder layer 8 is controlled by a time / temperature profile as shown in FIG. 8, the structure above the wiring 3 is as shown in FIG. 7 (a).

  In the temperature profile of FIG. 8, the solder layer 8 is held at a temperature equal to or higher than the melting point for approximately 2 minutes, and the peak temperature at that time is set to 250 ° C. or lower. In this example, the solder layer 8 is made of eutectic tin lead, and the melting point of the solder layer 8 is 183 ° C.

  7A, on the wiring 3, a NiP layer 5 having a thickness of 1400 to 1600 nm, a high P—Ni layer 5a having a thickness of 50 to 300 nm, a NiSn layer 5b having a thickness of 2000 to 4000 nm, A Sn-rich SnPd layer (hereinafter also referred to as a high Sn—Pd layer) 8a having a thickness of 10 to 200 nm and a solder layer 8 were present in this order. The phosphorus concentration in the high P—Ni layer 5a is 15 to 25 wt.%, The tin concentration in the high Sn—Pd layer 8a is 50 to 70 wt.%, And the tin concentration in the NiSn layer 5b is 52 wt.% Or less. It is. The layer structure between the solder layer 8 and the wiring 3 is also referred to as a base metal layer below.

  The thin high Sn—Pd layer 8a prevents the alloying of Ni and Sn. Thus, the NiSnP layer was not formed between the high P—Ni layer 5a and the NiSn layer 5b, and the NiSnP layer was not formed even when the solder layer 8 was repeatedly heated and melted.

  By the way, when the Pd layer 6 on the NiP layer 5 shown in FIG. 6C is made thicker than 200 nm, a SnPd layer that easily generates Kirkendall voids is formed between the solder layer 8 and the NiP layer 5, which is preferable. Absent. On the other hand, when the thickness of the Pd layer is 200 nm or less, the high Sn—Pd layer 8a is formed extremely thin, and no Kirkendall void is generated in the high Sn—Pd layer 8a.

  When the Au layer 7 is thicker than 100 nm, an AuSn alloy having a low mechanical strength is formed between the solder layer 8 and the NiP layer 5. On the other hand, when the Au layer 7 is 100 nm or less, all elements of the Au layer 7 diffuse into the solder layer 8 when the solder layer 8 is heated and melted, and the Au layer 7 disappears. In addition, since Au and Pd are contained in the solder layer 8 at a low concentration as a solid solution, the solder strength is not adversely affected.

  If the heating time for heating the solder layer 8 above the melting point is too long, NiSn crystal grains 5c are generated in the NiSn layer 5b formed between the solder layer 8 and the NiP layer 5 as shown in FIG. The crystal grains spread like needles into the solder layer 8. The NiSn crystal grains extending in a needle shape cause the strength of the interface between the solder layer 8 and the wiring 3 to become brittle, and deteriorate the shear strength of the connection terminal 10.

  Therefore, it is appropriate to heat the solder layer 8 at a temperature equal to or higher than its melting point, for example, 2 to 10 minutes. Such heating conditions are not only in the process of joining the solder layer 8 on the wiring 3 but also in the case of joining the solder layer 8 to the wiring 10 on another substrate 9 as shown in FIG. Applied.

  The connection terminals described above may also be formed on the metal pattern 12 constituting the uppermost wiring or pad of the semiconductor device 11 as shown in FIG. In FIG. 10, a gate electrode 14b is formed on a semiconductor (silicon) substrate 13 via a gate insulating film 14a, and impurity diffusion layers 14c and 14d are formed in the semiconductor substrate 13 on both sides of the gate electrode 14b. . The MOS transistor 14 is constituted by the gate electrode 14b, the impurity diffusion layers 14c and 14d, and the like. An interlayer insulating film 15 having a single-layer or multilayer wiring structure covering the MOS transistor 14 is formed on the semiconductor substrate 13, and an inorganic material such as a silicon oxide film or a silicon nitride film is formed on the interlayer insulating film 15. A metal pattern 12 which is a wiring or pad covered with the insulating film 16 is formed. On the metal pattern 12 exposed from the opening of the inorganic insulating film 16, an underlying metal film having the same structure as that shown in FIG. 7A, that is, the NiP layer 5, the high P-Ni layer 5a, the NiSn layer 5b, and the Sn rich Sn. An alloy layer 8a is formed, and an Sn alloy solder layer 8 is formed on the underlying metal film.

  10 indicates a field insulating film surrounding the MOS transistor 13 on the surface of the semiconductor substrate 13, and reference numeral 17 b indicates an organic insulating film surrounding the solder connection region of the metal pattern 12.

(Ii) Second connection terminal In order to form the second connection terminal on the substrate, a nickel copper phosphorous (NiCuP) layer 18 having a thickness of 3000 nm is formed on the wiring 3 as shown in FIG. A gold (Au) layer 19 having a thickness of 100 nm or less is formed thereon by an electroless plating method, and then an Sn alloy solder layer 20 containing 5 wt.% Or more of Sn is placed on the gold layer 19. . The phosphorus concentration in the NiCuP layer 18 is 1 to 15 wt.%.

  The NiCuP layer 18 is formed using, for example, a plating solution having copper sulfate pentahydrate and nickel sulfate hexahydrate, or using a plating solution containing a copper source, a nickel source, a complexing agent and a reducing agent. Formed. Further, the gold layer 19 is formed using a plating solution such as Oureclectres SMT-210 (trade name, manufactured by Nihon Leronal).

  Thereafter, when the solder layer 20 was melted and joined to the wiring 3, a structure as shown in FIG. 11B was obtained. That is, a NiCuP layer 18a having a high phosphorus concentration (hereinafter referred to as a “rich P—NiCu layer”) 18a having a thickness of 10 to 50 nm is formed on the surface of the NiCuP layer 18, and a copper layer is further formed thereon. The NiCuSn layer 18b was formed to a thickness of 100 to 300 nm by the diffusion of nickel. The Sn content in the NiCuSn layer 18b is 52 wt.% Or less. In this case, the Kirkendall effect was not generated, and no void was generated between the solder layer 20 and the NiCuP layer 18. As a result, the solder layer 20, which is a connection terminal formed on the wiring 3, is difficult to peel from the wiring 3. Further, the gold layer 19 diffused into the solder layer 20 by heating and disappeared.

  A palladium layer (not shown) having a thickness of 200 nm or less may be formed between the gold layer 19 and the NiCuP layer 18.

  Even if such a connection terminal is connected to, for example, the wiring 10 on another substrate 9 by heating and melting again, the layer structure hardly changes and hardly breaks down.

  The connection terminal having the NiCuP layer 18, the high P-NiCu layer 18a, the NiCuSn layer 18b, and the solder layer 20 may be formed on the uppermost metal pattern 12 of the semiconductor device 11 as shown in FIG. .

(iii) Third connection terminal In order to form the third connection terminal on the substrate, a nickel phosphorus (NiP) layer 21 having a thickness of 3000 nm is not formed on the wiring 3 as shown in FIG. An electroplating method is used to form an Au layer 22 having a film thickness of 100 nm or less on the electroplating method. Further, the copper containing tin (Sn) as a main component and copper (Cu) 0.5% is contained. A tin alloy solder layer 23, for example, a SnCuAg solder layer 23 is formed on the gold layer 22. The tin content in the SnCuAg solder layer 23 may be 5 wt.% Or more.

  Subsequently, when the solder layer 23 was heated and melted and joined to the wiring 3, a connection terminal having a structure as shown in FIG. 14B was obtained. That is, a high P-Ni layer 21a having a high phosphorus concentration of 15 to 25 wt.% Is formed on the NiP layer 21, and a NiCuSn layer 21b is formed thereon by mutual diffusion of copper and nickel. It was done. Sn in the NiCuSn layer 21b has a content of 52 wt.% Or less.

  In this case, there was no Kirkendall void between the solder layer 23 and the NiP layer 21, which made it difficult for the solder layer 23 to peel off the wiring.

  The gold layer 22 diffused into the solder layer 23 by heating and disappeared.

  A palladium layer (not shown) having a thickness of 200 nm or less may be formed between the gold layer 22 and the NiP layer 21.

  Even if such a connection terminal is bonded to, for example, the wiring 10 on another substrate 9 as shown in FIG. 15, the layer structure hardly changed and no breakdown occurred.

  By the way, instead of the NiP layer 21 shown in FIG. 14A, a NiCuP layer 24 containing 1 to 15 wt.% Phosphorus may be formed by electroless plating. In this case, when the solder layer 23 is heated and melted, the NiCuP layer 24, the phosphorus-rich NiCuP (high P-NiCu) layer 24a, the NiCuSn layer 24b and the solder layer 23 are formed on the wiring 3 as shown in FIG. The connection terminal consisting of was formed. The Sn content in the NiCuSn layer 24b is 52 wt.% Or less.

  Also in this case, no Kirkendall void was formed between the solder layer 23 and the NiCuP layer 24.

  Note that the connection terminals described above may be formed on the uppermost metal pattern 12 of the semiconductor device 11 as shown in FIG.

  According to the third connection terminal configured as described above, since the solder layer 23 does not contain lead, no fume is generated at the time of soldering, and the ceramic substrate 1 and the semiconductor device having such a connection terminal. Even when 11 etc. are discarded, it can be said that it is harmless and environmentally friendly. Furthermore, the copper-containing tin alloy solder has a connection reliability equal to or higher than that of eutectic tin-lead solder when the connection terminals are mounted.

  A drop test is performed by joining the wirings of the two boards through the connection terminals (i) to (iii) described above, and the wirings of the two boards are joined through the connection terminals of the conventional structure. When a drop test was performed, the results shown in Table 1 were obtained.

  Thereby, it became clear that solder joint becomes favorable by the connection terminal of (i)-(iii). The drop test is a test in which a load of 300 g is applied to one substrate and the wires are dropped from a height of 1 m in a state where the wirings of the two substrates are joined by the connection terminals.

  Between the metal pattern and the solder layer, a NiP layer or a NiCuP layer was formed as an underlying metal layer by electroless plating. However, when forming a nickel layer as a barrier metal and using a solution containing dimethylamineboric acid as a plating solution, nickel boron (NIB) is formed on the metal pattern. Even in such a case, the structure and manufacturing method described above can be used. However, in the above structure, the NiP layer is a NiB layer, the high P-Ni layer is a high B-Ni layer, the high P-NiCu layer is a high B-NiCu layer, the NiSnP layer is a NiSnB layer, and the NiCuP layer is NiCuB layer. Such a layer structure may be applied to the following embodiments.

  In the present embodiment, the connection terminal in which solder is bonded onto the metal pattern and the method for forming the connection terminal have been described. However, in the following embodiment, the solder layer is bonded to the surface of the protruding electrode connected on the metal pattern. explain.

(Second Embodiment)
FIG. 17 is a plan view of a chip-like semiconductor device according to the second embodiment of the present invention.

  In FIG. 17, a cover film 32 is formed on the uppermost surface of a semiconductor device 31 on which semiconductor elements and semiconductor circuits are formed, and a plurality of openings 33 are formed in the cover film 32 along the vicinity of the periphery thereof. . Metal pads (metal patterns) are formed under these openings 33, and wire-like or protruding electrodes 35 that pass through the openings 33 are connected to the metal pads.

  Several examples of the cross-sectional structure viewed from the line II in FIG. 17 will be described below.

  (i) FIG. 18 is a first example of a cross-sectional structure taken along the line II of FIG.

  In FIG. 18, an interlayer insulating film 37 having a multilayer wiring structure (not shown) is formed on a silicon (semiconductor) substrate 36 on which semiconductor elements are formed. The interlayer insulating film 37 is made of an inorganic insulating material such as silicon oxide or silicon nitride, and a metal pad (metal pattern) 34 is formed thereon. The metal pad 34 is made of copper, aluminum, or an alloy containing either of them as a main component.

  An inorganic insulating film 38 such as silicon oxide or silicon nitride is formed on the metal pad 34 and the interlayer insulating film 37 to a thickness of 2000 to 2500 nm. Further, on the inorganic insulating film 38, polyimide or benzocyclobutene is formed. A base cover film 39 made of such a resin is formed to a thickness of 3000 to 4000 nm.

  The base cover film 39 and the inorganic insulating film 38 are formed with a plurality of openings 38a that expose the metal pads 34 individually. When the base cover film 39 is made of a photosensitive resin, the opening 38 a is formed through exposure and development of the base cover film 39.

  On the metal pad 34 exposed from the opening 38a, a metal wire 35a is formed as a protruding electrode 35 to a length of about 100 μm. The metal wire 35a is made of gold, copper, palladium, or the like, is formed in a straight line using a wire bonding method, and is connected to the metal pad 34. By making the metal wire 35a straight, wire bonding can be formed with a short tact time using an existing apparatus.

  The lower part of the metal wire 35 a and the base cover film 39 are covered with the cover film 32. Examples of the constituent material of the cover film 32 include benzocyclobutene, bismalimide, silicon resin, and epoxy resin, which are formed by methods such as spin coating, dispensing, printing, molding, and lamination. The constituent material of the cover film 32 preferably has a moisture absorption rate of 0.5% or less at room temperature for 24 hours.

Note that the cover film 32 formed by spin coating or the like may slightly adhere to the upper part of the metal wire 35a. However, if the cover film 32 is thinned by plasma ashing using O ₂ or CF ₄ gas, metal It is easily removed from the upper part of the wire 35a.

  On the upper surface of the metal wire 35a exposed through the opening 33 of the cover film 32, a base metal layer 41 for solder and a solder layer 42 are formed. The outer shape of the solder layer 42 shown in FIG. 18 is columnar or needle-shaped. By making the solder layer 42 into a needle shape, a fine pitch can be achieved.

  The base metal layer 41 has one of the structures shown in FIGS.

  19 (a) includes a NiP layer 41a, a high P—Ni layer 41b, a NiSn alloy layer 41c, and a high (rich) continuously formed on the surface of the metal wire 35a that is the protruding electrode 35. ) A Sn-containing layer 41d is provided, and the solder layer 42 on the high Sn-containing layer 41d is made of SnPb. 19B has a NiCuP layer 41e, a high P—NiCu layer 41f, and a NiCuSn layer 41g that are continuously formed on the surface of the metal wire 35a that is the protruding electrode 35. The solder layer 42 on the NiCuSn layer 41g is made of SnPb.

  The base metal layer 41 in FIG. 19C has a NiP layer 41h, a high P—Ni layer 41i, and a NiCuSn layer 41j that are continuously formed on the surface of the metal wire 35a that is the protruding electrode 35. The solder layer 42 on the layer 41j is made of SnAgCu. 19D has a NiCuP layer 41k, a high P—NiCu layer 41m, and a NiCuSn layer 41n that are continuously formed on the surface of the metal wire 35a that is the protruding electrode 35. The solder layer 42 on the NiCuSn layer 41n is made of SnAgCu.

  The formation method of the base metal layer 41 and the solder layer 42 is the same as that of the first reference example, and the base layer 41 before the solder layer 42 is joined is as shown in FIGS. 20 (a) to 20 (d). ing.

  FIG. 20A shows an initial state of the underlayer 41. On the surface of the metal wire 35a, there are a NiP layer 41p, a Pd layer (thickness of 200 nm or less) 41q, and an Au layer (thickness of 100 nm or less) 41r. After the SnPb solder layer 42 is formed in order by the electroless plating method and the solder layer 42 is heated at a temperature equal to or higher than its melting point for 2 to 10 minutes, a structure as shown in FIG. 19A is obtained. It is done.

  FIG. 20 (b) shows another initial state of the underlayer 41. On the surface of the metal wire 35a, a NiCuP layer 41s, Au or Pd layer 41t is sequentially formed by an electroless plating method, and a SnPb layer is formed thereon. After the solder layer 42 is formed, the structure shown in FIG. 19B is obtained by heating the solder layer 42 at a temperature equal to or higher than its melting point for 2 to 10 minutes.

  FIG. 20 (c) shows still another initial state of the underlayer 41. On the surface of the metal wire 35a, a NiP layer 41u, Au or Pd layer 41v is sequentially formed by an electroless plating method. When the SnCuAg solder layer 42 is formed and then heated at a temperature equal to or higher than the melting point of the solder layer 42 for 2 to 10 minutes, a structure as shown in FIG. 19C is obtained.

  FIG. 20 (d) shows another initial state of the underlayer 41. On the surface of the metal wire 35a, a NiCuP layer 41w, Au or Pd layer 41x is sequentially formed by an electroless plating method, and a SnCuAg is formed thereon. When the solder layer 42 is formed and then heated at a temperature equal to or higher than the melting point of the solder layer 42 for 2 to 10 minutes, a structure as shown in FIG. 19D is obtained.

  By forming the metal layer as described above by the electroless plating method, the film thickness becomes uniform and the connection terminals 35 can be fine pitched.

  The film thickness of the Au or Pd layer 41t, 41v, 41x is 100 nm or less.

  Next, steps from the step of forming the base cover film 39 to the plurality of semiconductor devices 31 formed on the semiconductor wafer to the step of dividing the semiconductor wafer into the semiconductor devices 31 will be described.

  First, as shown in FIG. 21A, a semiconductor wafer 50 on which a plurality of semiconductor devices 31 are formed is prepared. In this case, in each semiconductor device, the inorganic insulating film 38 covering the metal pad 34 is the uppermost surface.

  Subsequently, as shown in FIG. 21B, a base cover film 39 is formed on the inorganic insulating film 38 by a method such as spin coating, dispensing, or laminating, and then the base cover film 39 is patterned to form a metal pad. An opening 38a is formed on a part of 34, and then the inorganic insulating film 38 is etched using the base cover film 39 as a mask to expose the metal pad 34. When the base cover film 39 is omitted, the inorganic insulating film 38 is patterned by photolithography to form an opening 38a that exposes the metal pad 34.

  Furthermore, as shown in FIG. 21C, a metal wire 35a is connected as a protruding electrode 35 to each of the metal pads 34 through the opening 38a. The metal wire-like protruding electrodes 35a are connected by a wire bonding method. The constituent material of the protruding electrode 35 is selected from metal materials such as gold, copper, and palladium.

  Next, as shown in FIG. 22A, a cover film 32 having a thickness that exposes the upper portion of the protruding electrode 35 is formed on the base cover film 39. Thereafter, the cover film 32 is patterned and removed from regions other than the semiconductor devices 31.

  Subsequently, as shown in FIG. 22 (b), the base metal layer 41 shown in any of FIGS. 20 (a) to 20 (d) is formed on the surface of the plurality of protruding electrodes 35 exposed from the cover film 32. In addition, a solder layer 42 is formed on the base metal layer 41. Before forming the base cover film 39 and the cover film 32, a NiP layer or a NiCuP layer constituting the base metal layer 41 may be formed on the surface of the protruding electrode 35 in advance.

  Thereafter, as shown in FIG. 22C, each semiconductor device 31 is separated by laser cutting or dicing the semiconductor wafer 50.

  Thereby, the formation of the chip-like semiconductor device having the structure shown in FIG. 18 is completed.

  When the cover film 32 is patterned in the step shown in FIG. 22A, when the cover film 32 other than the base portion is removed from the surface of the metal wire 35a, the semiconductor device 31 shown in FIG. 23 is formed.

  (Ii) FIG. 24 is a second example of a cross-sectional structure taken along the line II of FIG. In FIG. 24, the same reference numerals as those in FIG. 18 denote the same elements.

  In FIG. 24, a plurality of metal pads 34 are formed on the interlayer insulating film 37 on the silicon substrate 36. In addition, an inorganic insulating film 38 is formed on the metal pad 34 and the interlayer insulating film 37, and a base cover film 39 made of a resin such as polyimide, benzocyclobutene, or epoxy is further formed on the inorganic insulating film 38. Is formed. The resin desirably has photosensitivity.

  The base cover film 39 and the inorganic insulating film 38 are formed with a plurality of openings 38a that expose the metal pads 34 individually. When the base cover film 39 is made of a photosensitive resin, the opening 38a is formed through exposure and development of the base cover film 39.

  On the metal pad 34 exposed from such an opening 38a, a metal column 35b made of gold, copper or palladium having a height of about 100 μm is formed as the protruding electrode 35 by electrolytic plating or electroless plating. The outer shape of the rod-shaped metal column 35b is a columnar shape or a polygonal column shape. Thereby, the length of the terminal can be increased without widening the gap between the protruding electrodes 35, and a fine pitch can be achieved.

  The lower part of the metal pillar 35 b and the base cover film 39 are covered with a cover film 32 made of resin, and the upper part of the metal pillar 35 b protrudes from the opening 38 a of the cover film 32. The cover film 32 is formed by a method such as spin coating, dispensing, printing, molding, or lamination.

  A base metal layer 41 and a solder layer 42 having the structure shown in FIGS. 19A to 19D are sequentially formed on the metal pillar 35 b protruding from the cover film 32, that is, on the upper surface of the protruding electrode 35. Has been.

  Note that the method of forming the semiconductor device 31 having the structure shown in FIG. 24 can be similarly applied except that the metal pillar 35b is formed instead of the metal wire 35a in the manufacturing steps shown in FIGS. The metal column 35b is formed on the metal pad 34 by an electroless plating method or an electrolytic plating method.

  By the way, in the first example and the second example of the semiconductor device 31 shown in FIGS. 18 and 24, the layer structure of the base metal layer 41 formed on the surface of the metal wire 35a and the metal column 35b to be the protruding electrode 35 is as follows. Are formed above the cover film 32, but the NiP layers 41p and 41u or the NiCuP layers 41s and 41w among the layers constituting the base metal layer 41 shown in FIGS. A structure in which a part of the cover film 32 is embedded in the cover film 32 may be employed. According to such a structure, the adhesion between the protruding electrode 35 and the cover film 32 is improved.

  For example, as shown in FIG. 25 (a), before forming the cover film 32 on the base cover film 39, the NiP layers 41p and 41u or the NiCuP layers 41s and 41w are formed on the surface of the metal wire 35a by electroless plating. After the formation, the cover film 32 is formed on the base cover film 39 so as to embed the lower portion of the metal wire 35a. When the base cover film 39 in FIG. 25A is omitted, the structure shown in FIG.

  Note that all the layers of the base metal film 41 shown in FIGS. 20A to 20D may be formed on the surface of the portion of the protruding electrode 35 embedded in the cover film 32.

  By the way, the outer shape of the solder layer 42 may be a columnar shape or a needle shape reflecting the outer shape of the protruding electrode 35 (35a, 35b) as shown in FIGS. As shown in (b), it may be substantially spherical. By making the solder layer 42 spherical, a self-alignment effect can be obtained, and high-speed mounting that does not require severe precision is possible.

  Examples of the method of covering the substantially spherical solder layer 42 include a plating method, a ball mounting method, and a printing method. The solder shape and formation method are similarly adopted in other embodiments described below.

  FIGS. 27A and 27B illustrate a state where the protruding electrodes 35 (35a and 35b) of the semiconductor device 31 as described above are connected to the wiring on the ceramic substrate. The ceramic substrate 1 shown in FIGS. 27A and 27B has the structure shown in FIG. 7A according to the first embodiment, and a NiP layer 5 or the like is formed on the surface of the wiring 3. ing. In this case, since the protruding electrode 35 is connected via the solder layer 42 and the resin for reinforcing the connecting portion is not filled between the semiconductor device 31 and the ceramic substrate 1, the existing equipment has a high speed. Implementation becomes possible. This connection is the same in the embodiments described below.

  When the solder layer 8 on the wiring 3 of the ceramic substrate 1 is used, the structure after soldering is almost the same even if the solder layer 42 on the protruding electrode 35 is omitted.

(Third embodiment)
In FIG. 18, the protruding electrode 35 is connected directly to the surface of the metal pad 34 through the opening 38 a of the base cover film 39 and the inorganic insulating film 38 on the semiconductor device 31. However, if the interval between the openings 38a becomes narrower, it becomes difficult to connect the protruding electrode 35 to the metal pad 34, so the connection position of the protruding electrode 35 is changed to a position closer to the center of the semiconductor device 31. It is preferable.

  In order to change the connection position of the protruding electrode 35, as shown in FIG. 28, a lead-out wiring (also referred to as a rearrangement wiring) 44 from the metal pad 34 existing in the vicinity of the periphery of the semiconductor device 31 toward the inner region. Is preferably formed. In FIG. 28, the cover film 32 is omitted.

  Here, the side away from the metal pad 34 out of the two ends of the lead-out wiring 44 is defined as a rearrangement region.

  28 shows a cross-sectional structure taken along the line II-II in the rearrangement region of the lead wiring 44 as shown in FIG. 29, FIG. 30, and FIG. FIG. 29 shows a structure in which the electrical connection position between the metal wire 35a and the metal pad 34, which becomes the protruding electrode 35 shown in FIG. 18, is changed. FIG. 30 shows a structure in which the electrical connection position between the metal wire 35a and the metal pad 34 shown in FIG. 23 is changed. FIG. 31 shows a structure in which the electrical connection position between the metal column 35b and the metal pad 34 to be the protruding electrode 35 shown in FIG. 24 is changed.

  The base metal layer 41 and the solder layer 42 described in the second embodiment are formed on the surface of the protruding electrode 35 (35a, 35b) shown in FIGS. Further, in the structure in which the protruding electrode 35 is connected to the rearrangement region of the lead wiring 44, all or a part of each layer of the base metal layer 41 is also formed on the portion of the surface of the protruding electrode 35 embedded in the cover film 32. One example is shown in FIG.

  28 to 32, the same reference numerals as those in FIGS. 17 to 25 denote the same elements as those in FIGS.

  An example of the connection state between the protruding electrode 35 whose connection position has been changed and the wiring on the ceramic substrate is as shown in FIG. The ceramic substrate 1 shown in FIG. 33 (a) has the structure shown in FIG. 7 (a) of the first embodiment, and a NiP layer 5 or the like is formed on the surface of the wiring 3 on the ceramic substrate 1. Has been. In this case, the protruding electrode 35 is connected to the wiring 3 through the solder layer 42. FIG. 33 (b) shows the connection between the protruding electrode 35 in which the base metal film 41 is also formed on the portion covered with the cover film 32 and the wiring 3.

  Next, processes from the formation of the rearrangement wiring 44 on the semiconductor wafer 50 to the division of the semiconductor wafer 50 will be described.

  The structure shown in FIG. 34A is formed through the following steps.

  First, a semiconductor wafer 50 on which a plurality of semiconductor devices 31 are formed is prepared. Each semiconductor device 31 is covered with an inorganic insulating film 38 and a base cover film 39. Then, the metal pad 34 is exposed by patterning the base cover film 39 and the inorganic insulating film 38 to form an opening 38 a as shown in FIG. 29 on the metal pad 34. Subsequently, after forming a metal film such as aluminum, gold, or copper in the opening 38a and on the base cover film 39, the metal film is patterned to form a plurality of rearrangement wirings (metals) as shown in FIG. Pattern) 44 is formed.

  Next, as shown in FIG. 34B, the protruding electrodes 35 are connected to the respective rearrangement regions of the rearrangement wiring 44. Those protruding electrodes 35 are formed by the same method as in the second embodiment.

  Next, as shown in FIG. 34C, the cover film 32 is formed on the rearrangement wiring 44 and the base cover film 39 so that the upper part of the protruding electrode 35 is exposed. Thereafter, if the cover film 32 is a photosensitive material, it is patterned and left on each semiconductor device 31.

  Subsequently, as shown in FIG. 34 (d), the base metal layer 41 and the solder layer as shown in FIGS. 19 (a) to 19 (d) are formed on the surfaces of the plurality of protruding electrodes 35 exposed from the cover film 32. 42 is formed. Before forming the base cover film 39 and the cover film 32, as shown in FIG. 32, all or part of the base metal layer 41 may be formed on the surface of the protruding electrode 35 in advance. Good.

  Thereafter, each semiconductor device 31 is separated by laser cutting or dicing the semiconductor wafer 50.

  Thus, the formation of the chip-like semiconductor device 31 having the structure shown in FIGS. 29, 30 and 31 is completed.

(Fourth embodiment)
In this embodiment, a structure having a protruding electrode as an external connection terminal and reducing the exposed area of a semiconductor substrate and a method for forming the structure will be described.

(I) Structure in which coating film is formed on upper surface and back surface of semiconductor substrate FIGS. 35, 36, and 37 show an under coating film 46 on the lower surface of the semiconductor substrate 36 shown in FIGS. 18, 23, and 24, respectively. It is sectional drawing which shows the structure which formed.

  The under coating film 46 is, for example, a resin such as polyimide, benzocyclobutene, bismalimide, silicon resin, or epoxy resin, or copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), or the like. Composed of metal.

  Next, a process for forming the semiconductor device 31 shown in FIG. 35 will be described.

  First, from the state of FIG. 22B shown in the second embodiment, an under coating film 46 made of resin or metal is formed on the lower surface of the semiconductor wafer 50 as shown in FIG. Such a resin is formed on the lower surface of the semiconductor wafer 50 by a method such as spin coating, dispensing, printing, molding, or lamination. Further, such a metal is formed on the lower surface of the semiconductor wafer 50 by a method such as sputtering, plating, or laminating.

  Thereafter, as shown in FIG. 38B, each semiconductor device 31 is separated by dicing the semiconductor wafer 50.

  Thereby, the formation of the chip-like semiconductor device having the structure shown in FIG. 18 is completed.

  Note that the solder layer formed on the surface of the protruding electrode 35 may be substantially spherical. For example, in FIGS. 36 and 37, a solder layer 42 having a columnar or needle shape is formed on the surface of the protruding electrode 35. However, as shown in FIGS. 39 (a) and 39 (b), it may be substantially spherical. . The solder layer 42 having a substantially spherical outer shape is formed by a plating method, a ball mounting method, a printing method, or the like.

(Ii) Structure in which a coating film is formed on the top surface and side surface of the substrate FIGS. 40, 41, and 42 show a side coating film 47 on the side surface of the semiconductor substrate 36 shown in FIGS. 18, 23, and 24, respectively. It is sectional drawing which shows the formed structure.

  The side coating film 47 is made of, for example, a resin such as polyimide, benzocyclobutene, bismalimide, silicon resin, or epoxy resin, or a metal such as Cu, Ti, Al, or Ni.

  Next, a process for forming the semiconductor device 31 shown in FIG. 40 will be described.

  FIG. 43A shows a state in which the metal wire 35a which is the protruding electrode 35 is connected to the metal pad 34 of the semiconductor device 31 formed in plural on the semiconductor wafer 50, as in FIG.

  Subsequently, as shown in FIG. 43 (b), a groove 51 having a depth of 200 to 400 μm is formed along a scribe line around the semiconductor device 31 of the semiconductor wafer 50. The formation of the groove 51 includes not only a method using a blade but also a method using etching.

  Further, as shown in FIG. 43 (c), a resin film 47 a covering the groove 51, the metal wire 35 a, and the semiconductor device 31 is formed on the semiconductor wafer 50. Such a resin film 47a is formed by a method such as spin coating, dispensing, printing, or molding.

  Thereafter, as shown in FIG. 44 (a), the lower surface of the semiconductor wafer 50 is polished until it reaches the bottom of the groove 51 by a CMP (chemical mechanical polishing) method or a back grind method. At this stage, the plurality of semiconductor devices 31 formed on the semiconductor wafer 50 are substantially divided, but are connected to each other through the resin film 47a. The metal wire 35a is protected by a resin film 47a.

  Subsequently, as shown in FIG. 44B, the resin film 47a is etched and thinned until the upper portion of the metal wire 35a is exposed.

  Thereafter, as shown in FIG. 44C, when the semiconductor device 31 is separated by cutting the resin film 47a in the groove 51, the resin film 47a is side-coated on the side surface of the semiconductor substrate 36 constituting the semiconductor device 31. The resin layer 46 a remaining as the layer 47 and remaining on the semiconductor device remains as the cover film 32.

  Thereby, the formation of the chip-like semiconductor device having the structure shown in FIG. 40 is completed.

  45, 46, and 47 show the semiconductor substrate 36 formed through the step of forming the groove 51 using a tapered blade, and a taper 36a is formed on the side surface thereof.

  Further, the solder layer formed on the surface of the protruding electrode 35 may be substantially spherical. For example, in FIGS. 40 and 42, a solder layer 42 having a columnar or needle shape is formed on the surface of the protruding electrode 35. However, as shown in FIGS. 48 (a) and 48 (b), it may be substantially spherical. . The solder layer 42 having a substantially spherical outer shape is formed by a plating method, a ball mounting method, a printing method, or the like.

(Iii) Structure in which a coating film is formed on the upper surface, back surface and side surface of the substrate FIGS. 49, 50 and 51 respectively show the under coating film on the lower surface of the semiconductor substrate 36 shown in FIGS. 46 is a cross-sectional view having a structure in which a side coating film 47 is formed on each side surface.

  The under coating film 46 and the side coating film 47 are made of, for example, a resin such as polyimide, benzocyclobutene, bismalimide, silicon resin, or epoxy resin, or a metal such as Cu, Ti, Al, or Ni.

  Next, a process for forming the semiconductor device 31 shown in FIG. 49 will be described.

  First, as shown in FIG. 44 (b), the groove 51 is formed in the semiconductor wafer 50, and then the resin 47a is formed. Further, the lower surface of the semiconductor wafer 50 is polished by the CMP method or the back grinding method.

  Subsequently, as shown in FIG. 52A, an under coating film 46 made of resin or metal is formed on the lower surface of the semiconductor wafer 50. Such a resin is formed on the lower surface of the semiconductor wafer 50 by a method such as spin coating, dispensing, printing, or molding. Further, such a metal is formed on the lower surface of the semiconductor wafer 50 by a method such as sputtering, plating, or laminating.

  Further, as shown in FIG. 52B, the resin film 47a is thinned until the upper portion of the metal wire 35a is exposed.

  Thereafter, as shown in FIG. 52 (c), when the resin film 47a and the under coating layer 47 in the groove 51 are cut to divide the semiconductor device 31 into chips, the under coating layer 47 remains as it is in the semiconductor device 31. The resin layer 47a covering the bottom and remaining on the side surface of the semiconductor device 31 becomes the side coating layer 47, and the resin layer 47a remaining on the semiconductor device becomes the cover film 32.

  Thereby, the formation of the chip-like semiconductor device having the structure shown in FIG. 49 is completed.

  53, 54, and 55 show the semiconductor device 31 obtained by forming the groove 51 using a tapered blade, and a taper 36a is formed on the side surface thereof.

  The solder layer 42 formed on the surface of the protruding electrode 35 may be substantially spherical. For example, in FIGS. 49, 50, and 51, a solder layer 42 having a columnar or needle shape is formed on the surface of the protruding electrode 35. However, as shown in FIGS. It is good. The solder layer 42 having a substantially spherical outer shape is formed by a plating method, a ball mounting method, a printing method, or the like.

  Note that the coating films 46 and 47 described above may be formed on the lower surface and side surfaces of the semiconductor device 31 having the rearrangement wiring 44 shown in FIGS.

(Appendix 1) An electrode formed on a substrate or an insulating film on the substrate;
A first element-containing nickel layer formed as a barrier metal on the electrode and containing a first element of either phosphorus or boron;
A high first element-containing nickel layer formed on the first element-containing nickel layer and containing more of the first element than the nickel first element alloy layer;
A nickel tin alloy layer formed on the high first element-containing nickel layer;
A tin alloy layer formed on the nickel tin alloy layer;
An external connection terminal comprising: a tin alloy solder layer formed on the tin alloy layer.

  (Supplementary note 2) The external connection terminal according to supplementary note 1, wherein each of the nickel-tin alloy layer and the tin-alloy solder layer contains copper.

  (Supplementary note 3) The external connection terminal according to supplementary note 1, wherein the tin alloy layer is a tin palladium layer.

  (Additional remark 4) The said 1st element containing nickel layer is 1-15 wt. The external connection terminal according to Supplementary Note 1, wherein the external connection terminal is contained in%.

  (Supplementary Note 5) The tin alloy layer contains 52 wt. The external connection terminal according to appendix 1, wherein the external connection terminal is contained at a concentration of not more than%.

(Appendix 6) An electrode formed on a substrate or an insulating film on the substrate;
A first element-containing nickel copper layer formed as a barrier metal on the electrode and containing a first element of either phosphorus or boron;
A high first element-containing nickel copper layer formed on the first element-containing nickel copper layer and containing more of the first element than the first element-containing nickel copper layer;
A nickel copper tin alloy layer formed on the high first element-containing nickel copper layer;
An external connection terminal comprising: a tin alloy solder layer formed on the nickel copper tin alloy layer.

  (Additional remark 7) The said tin alloy solder layer contains copper, The external connection terminal of Additional remark 6 characterized by the above-mentioned.

  (Additional remark 8) The said 1st element containing nickel copper layer contains 1-15 wt% of said 1st elements, The external connection terminal of Additional remark 6 characterized by the above-mentioned.

  (Supplementary Note 9) The nickel copper tin alloy layer contains 52 wt. The external connection terminal according to appendix 6, wherein the external connection terminal is contained in a percentage or less.

  (Supplementary note 10) The external connection terminal according to supplementary note 1 or 6, wherein the tin alloy solder layer contains 5 wt% or more of tin.

  (Appendix 11) The external connection terminal according to Appendix 1 or 6, wherein the substrate is a semiconductor substrate or an insulating substrate.

  (Supplementary note 12) The external connection terminal according to supplementary note 1 or supplementary note 6, wherein the electrode is made of a conductor mainly composed of copper or aluminum, or aluminum or copper.

  (Supplementary note 13) The external connection terminal according to Supplementary note 1 or 6, wherein the electrode is a protruding electrode that is electrically connected to a metal pattern on the substrate or the insulating film.

  (Supplementary note 14) The external connection terminal according to supplementary note 13, wherein the protruding electrode has a wire shape, a columnar shape, or a polygonal columnar shape.

  (Supplementary note 15) The external connection terminal according to supplementary note 13, wherein the protruding electrode is made of copper, gold, or palladium.

  (Additional remark 16) The said board | substrate is a semiconductor substrate in which the semiconductor element was formed, the said metal pattern is formed in the upper surface of the said insulating film, an extraction wiring is connected on the said metal pattern, and on this extraction wiring 14. The external connection terminal according to appendix 13, wherein the protruding electrode is connected.

  (Supplementary note 17) The supplementary note 16, wherein the metal pattern is covered with a cover film made of an organic insulating material, and the protruding electrode protrudes from the cover film through a first opening formed in the cover film. External connection terminal described in 1.

  (Supplementary Note 18) An inorganic insulating film having a second opening that exposes the metal pattern is formed on the insulating film, the extraction wiring is formed on the inorganic insulating film, and the extraction electrode is formed of the inorganic insulating film. The external connection terminal according to appendix 17, wherein the external connection terminal is connected to the metal pattern through the second opening of the insulating film.

  (Supplementary note 19) The external connection terminal according to supplementary note 11 or supplementary note 16, wherein a coating film made of an organic insulating material or metal is formed on at least one of a side surface and a bottom surface of the semiconductor substrate.

  (Supplementary note 20) The external connection terminal according to supplementary note 17 or 19, wherein the organic insulating material is formed of a material having a moisture absorption rate of 0.2% or less for 24 hours at room temperature.

  (Appendix 21) The external connection terminal according to appendix 17 or appendix 19, wherein the organic insulating material is any one of benzocyclobutene, bismalimide, silicone resin, and epoxy resin.

  (Supplementary note 22) The outer connection terminal according to supplementary note 17, characterized in that, from the surface of the protruding electrode, the barrier metal to the tin alloy solder layer are formed only in a portion protruding from the cover film. .

  (Supplementary Note 23) The first element-containing nickel layer is formed on the lower surface of the surface of the protruding electrode covered with the cover film, and the first element-containing nickel layer is projected on the upper surface protruding from the cover film. Item 18. The external connection terminal according to appendix 17, wherein up to the tin alloy solder layer is formed.

  (Supplementary Note 24) The first element-containing nickel copper layer is formed on the lower surface covered with the cover film among the surfaces of the protruding electrodes, and the upper surface protrudes from the cover film. The external connection terminal according to appendix 17, wherein a layer to a tin alloy solder layer are formed.

  (Additional remark 25) The thickness of the said tin alloy layer is 10-200 nm, The external connection terminal of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 26) The external connection terminal according to supplementary note 1, wherein the high first element-containing nickel layer has a thickness of 50 to 500 nm.

  (Supplementary note 27) The external connection terminal according to supplementary note 6, wherein the high first element-containing nickel copper layer has a thickness of 10 to 500 nm.

  (Appendix 28) The external connection terminal according to appendix 1 or appendix 6, wherein the tin alloy solder layer has a substantially spherical, substantially columnar, or substantially needle-shaped outer shape.

(Supplementary note 29) an interlayer insulating film formed on the semiconductor substrate;
A metal pattern formed on the interlayer insulating film;
An inorganic insulating film formed with a first opening exposing the metal pattern;
A protruding electrode electrically connected to the metal pattern through the first opening;
An organic insulating film having a second opening formed on the inorganic insulating film and exposing at least an upper portion of the protruding electrode;
A base metal layer and a solder layer formed on at least the upper surface of the protruding electrode;
A semiconductor device comprising: a coating film made of resin or metal formed on at least one of a lower surface and a side surface of the semiconductor substrate.

  (Supplementary note 30) The semiconductor device according to supplementary note 29, wherein the first opening and the second opening are formed so as to overlap each other, and the protruding electrode is directly connected to the metal pattern.

(Supplementary Note 31) The first opening and the second opening are formed apart from each other,
29. The supplementary note 29, comprising the lead-out wiring formed on the inorganic insulating film, connected to the metal pattern through the first opening, and connected to the protruding electrode under the second opening. Semiconductor device.

  (Supplementary note 32) The semiconductor device according to supplementary note 29, wherein a base cover film made of an organic insulating material is formed between the organic insulating film and the inorganic insulating film.

  (Supplementary note 33) The semiconductor device according to supplementary note 29, wherein the organic insulating film is made of a material having a moisture absorption rate of 0.5% or less at room temperature for 24 hours.

  (Supplementary note 34) The semiconductor device according to supplementary note 29, wherein the organic insulating film is any one of benzocyclobutene, bismalimide, silicon resin, and epoxy resin.

FIG. 1 is a cross-sectional view showing the structure of a conventional first connection terminal. 2 (a) and 2 (b) are cross-sectional views showing a conventional process for forming a first connection terminal. FIG. 3 is a cross-sectional view showing a layer structure after heating the conventional first connection terminal. FIG. 4 is a cross-sectional view showing a layer structure in which the solder is peeled off after heating the conventional first connection terminal. 5 (a) and 5 (b) are cross-sectional views showing a conventional process of forming a second connection terminal. FIGS. 6A to 6D are cross-sectional views (part 1) showing the process of forming the first external connection terminal according to the first embodiment of the present invention. FIGS. 7A and 7B are sectional views (No. 2) showing the first external connection terminal forming step according to the first embodiment of the present invention. FIG. 8 is a formation temperature profile of the solder interface alloy in the first external connection terminal according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing the layer structure on the wiring when the heating time is excessive in the first external connection terminal according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view showing a semiconductor device having a first connection terminal according to the first embodiment of the present invention. FIGS. 11A and 11B are cross-sectional views showing a process for forming a second external connection terminal according to the first embodiment of the present invention. FIG. 12 is a cross-sectional view showing a connection state between wires by the second external connection terminal according to the first embodiment of the present invention. FIG. 13 is a cross-sectional view showing a semiconductor device having a second external connection terminal according to the first embodiment of the present invention. 14 (a) and 14 (b) are cross-sectional views showing a process of forming a third external connection terminal according to the first embodiment of the present invention. FIG. 15 is a cross-sectional view showing a connection state between wires by the third external connection terminal according to the first embodiment of the present invention. FIG. 16 is a cross-sectional view showing a semiconductor device having a third external connection terminal according to the first embodiment of the present invention. FIG. 17 is a plan view of a semiconductor device according to the second embodiment of the present invention. FIG. 18 is a cross-sectional view of the first semiconductor device according to the second embodiment of the present invention. FIGS. 19A to 19D are cross-sectional views showing the structure of the external connection terminal of the semiconductor device according to the second embodiment of the present invention. 20A to 20D are sectional views showing an initial state of the structure of the external connection terminal of the semiconductor device according to the second embodiment of the present invention. FIGS. 21A to 21C are cross-sectional views (part 1) showing the process of forming the semiconductor device according to the second embodiment of the invention. 22A to 22C are cross-sectional views (part 2) illustrating the process for forming the semiconductor device according to the second embodiment of the invention. FIG. 23 is a cross-sectional view of a second semiconductor device according to the second embodiment of the present invention. FIG. 24 is a cross-sectional view of a third semiconductor device according to the second embodiment of the present invention. 25A and 25B are cross-sectional views showing other structures of the external connection terminals of the semiconductor device according to the second embodiment of the present invention. 26 (a) and 26 (b) are cross-sectional views showing fourth and fifth semiconductor devices according to the second embodiment of the present invention. FIGS. 27A and 27B are cross-sectional views showing a connection state between the external connection terminals of the semiconductor device according to the second embodiment of the present invention and the wiring on the ceramic circuit board. FIG. 28 is a plan view of a semiconductor device according to the third embodiment of the present invention. FIG. 29 is a cross-sectional view of the first semiconductor device according to the third embodiment of the present invention. FIG. 30 is a cross-sectional view of a second semiconductor device according to the third embodiment of the present invention. FIG. 31 is a cross-sectional view of a third semiconductor device according to the third embodiment of the present invention. FIG. 32 is a cross-sectional view showing a connection state of external terminals of a semiconductor device according to the third embodiment of the present invention. 33 (a) and 33 (b) are cross-sectional views showing the connection state between the external connection terminals of the semiconductor device according to the third embodiment of the present invention and the wiring on the ceramic circuit board. 34 (a) to 34 (d) are cross-sectional views illustrating the steps of forming a semiconductor device according to the third embodiment of the present invention. FIG. 35 is a cross-sectional view of the first semiconductor device according to the fourth embodiment of the present invention. FIG. 36 is a cross-sectional view of the second semiconductor device according to the fourth embodiment of the present invention. FIG. 37 is a cross-sectional view of a third semiconductor device according to the fourth embodiment of the present invention. FIGS. 38A and 38B are cross-sectional views showing the steps of forming the first, second, or third semiconductor device according to the fourth embodiment of the present invention. 39 (a) and 39 (b) are cross-sectional views of fourth and fifth semiconductor devices according to the fourth embodiment of the present invention. FIG. 40 is a cross-sectional view of a sixth semiconductor device according to the fourth embodiment of the present invention. FIG. 41 is a cross-sectional view of the seventh semiconductor device according to the fourth embodiment of the present invention. FIG. 42 is a sectional view of an eighth semiconductor device according to the fourth embodiment of the present invention. FIGS. 43A to 43C are cross-sectional views (part 1) showing the formation process of the sixth, seventh, or eighth semiconductor device according to the fourth embodiment of the present invention. 44 (a) to 44 (c) are cross-sectional views (part 2) showing the formation process of the sixth, seventh, or eighth semiconductor device according to the fourth embodiment of the present invention. FIG. 45 is a sectional view of a ninth semiconductor device according to the fourth embodiment of the present invention. FIG. 46 is a cross-sectional view of the tenth semiconductor device according to the fourth embodiment of the present invention. FIG. 47 is a sectional view of an eleventh semiconductor device according to the fourth embodiment of the present invention. 48 (a) and 48 (b) are cross-sectional views of the twelfth and thirteenth semiconductor devices according to the fourth embodiment of the present invention. FIG. 49 is a sectional view of a twelfth semiconductor device according to the fourth embodiment of the present invention. FIG. 50 is a sectional view of a thirteenth semiconductor device according to the fourth embodiment of the present invention. FIG. 51 is a sectional view of a fourteenth semiconductor device according to the fourth embodiment of the present invention. 52 (a) to 52 (c) are cross-sectional views showing the steps of forming a twelfth, thirteenth or fourteenth semiconductor device according to the fourth embodiment of the present invention. FIG. 53 is a sectional view of a fifteenth semiconductor device according to the fourth embodiment of the present invention. FIG. 54 is a sectional view of a sixteenth semiconductor device according to the fourth embodiment of the present invention. FIG. 55 is a sectional view of a seventeenth semiconductor device according to the fourth embodiment of the present invention. FIGS. 56A and 56B are cross-sectional views of the eighteenth and nineteenth semiconductor devices according to the fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ceramic (insulation) board | substrate, 2 ... Resist, 3 ... Wiring (metal pattern), 5 ... NiP layer, 5a ... High P-Ni layer, 5b ... Sn layer, 6 ... Pd layer, 7 ... Au layer, 8 ... Sn alloy solder layer, 8a ... high Sn-Pd layer, 9 ... substrate, 10 ... wiring, 11 ... semiconductor device, 13 ... semiconductor substrate, 14 ... MOS transistor, 15 ... interlayer insulating film, 16 ... protective insulating film, 17 ... Field insulating film, 18 ... NiCuP layer, 18a ... High P-NiCu layer, 18b ... NiCuSn layer, 19 ... Au layer, 20 ... Sn alloy solder layer, 21 ... NiP layer, 21a ... High P-Ni layer, 21b ... NiCuSn Layer, 22 ... Au layer, 23 ... SnCuAg solder layer, 24 ... NiCuP layer, 24a ... high P-NiCu layer, 24b ... NiCuSn layer, 31 ... semiconductor device, 32 ... cover film, 33 ... opening, 34 ... metal pad (Metal pattern) 35 ... Projection electrode 35a ... Metal wire 35b ... Metal pillar 36 ... Semiconductor substrate 37 ... Layer Interlayer insulating film 38 ... Inorganic insulating film 39 ... Base cover film 41 ... Base metal film 41a ... NiP layer 41b ... High P-Ni layer 41c ... NiSn alloy layer 41d ... High Sn content layer 41e ... NiCuP layer, 41f ... high P-NiCu layer, 41g ... NiCuSn layer, 41h ... NiP layer, 41i ... high P-Ni layer, 41j ... NiCuSn layer, 41k ... NiCuP layer, 41m ... high P-NiCu layer, 41n ... NiCuSn Layer, 41p ... NiP layer, 41q ... Pb layer, 41r ... Au layer, 41s ... NiCuP layer, 41t ... Au or Pd layer, 41u ... NiP layer, 41v ... Au or Pd layer, 41w ... NiCuP layer, 41x ... Au or Pd layer, 42 ... solder layer, 44 ... lead wiring (metal pattern), 46 ... under coating film, 47 ... side coating film, 47a ... resin film.

Claims (6)

An interlayer insulating film formed on the semiconductor substrate;
A metal pattern formed on the interlayer insulating film;
An inorganic insulating film formed with a first opening exposing the metal pattern;
A protruding electrode electrically connected to the metal pattern through the first opening;
An organic insulating film having a second opening formed on the inorganic insulating film and exposing at least an upper portion of the protruding electrode;
A base metal layer and a solder layer formed on at least the upper surface of the protruding electrode;
A semiconductor device comprising: a coating film made of resin or metal formed on at least one of a lower surface and a side surface of the semiconductor substrate. The first opening and the second opening are formed to overlap each other,
The semiconductor device according to claim 1, wherein the protruding electrode is directly connected to the metal pattern. The first opening and the second opening are formed apart from each other,
2. The lead wiring formed on the inorganic insulating film, connected to the metal pattern through the first opening, and connected to the protruding electrode under the second opening. Semiconductor device.   The semiconductor device according to claim 1, wherein a base cover film made of an organic insulating material is formed between the organic insulating film and the inorganic insulating film.   2. The semiconductor device according to claim 1, wherein the organic insulating film is made of a material having an absorptance of 0.5% or less at room temperature for 24 hours.   2. The semiconductor device according to claim 1, wherein the organic insulating film is one of benzocyclobutene, bismalimide, silicon resin, and epoxy resin.

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