JP2007014039A - Amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifying circuit capable of driving a load at high speed while suppressing increase in power consumption. <P>SOLUTION: A current inputted through a node N1 to an npn transistor Q1 is detected in a current detection circuit 1. In a bias control circuit 2, a base voltage of an npn transistor Q2 is controlled so as to decrease a current of the npn transistor Q2 in accordance with increase of the detected current and to increase the current of the npn transistor Q2 in accordance with decrease of the detected current. Thus, since a current that may transiently flow to a load can be enlarged, even if the capacitance of a load capacitor CL is great or a frequency is high, an output voltage can follow up a change in an input voltage at high speed, thereby suppressing the distortion of an output voltage waveform. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an amplifier circuit including an emitter follower circuit in an output stage.

  The emitter follower circuit has characteristics of high input impedance and low output impedance, and has a large current gain, and thus is widely used as a buffer circuit for driving a capacitive load.

Patent Documents 1 and 2 disclose buffers.
9 and 10 are diagrams showing a configuration example of a general emitter follower circuit.

The emitter follower circuit shown in FIG. 9 includes an npn transistor Q101 and a resistor R101.
Npn transistor Q101 has a collector connected to power supply voltage line Vcc, and an emitter connected to ground line G via resistor R101. The base receives the output voltage of the amplifier circuit AMP101 in the previous stage.

In the emitter follower circuit shown in FIG. 9, the input is the base of the npn transistor Q101, and the output is the emitter of the npn transistor Q101.
When the output potential becomes lower than the input potential and the potential difference becomes larger than the forward voltage of the pn junction, the emitter current of the npn transistor Q101 increases abruptly and the load from the emitter (capacitor CL in the example of FIG. 8). Current flows in a series circuit of a RL and a resistor RL. When the capacitor CL of the load is charged by this current and the potential difference between the output and the input becomes smaller than the forward voltage of the pn junction, the emitter current of the npn transistor Q101 decreases and the current output to the load stops.
When the output is higher than the input, the npn transistor Q101 is turned off and current is drawn from the load to the resistor R101. When the charge of the capacitor CL is discharged by this drawing current and the output becomes a potential lower than the input by the forward voltage of the pn junction, the emitter current of the npn transistor Q101 charges the capacitor CL as described above, and the output voltage is reduced. It can be suppressed.
In this manner, a voltage obtained by shifting the input voltage by the forward voltage of the pn junction is generated at the output of the emitter follower circuit in a steady state. Therefore, the amplification factor for the AC voltage signal is substantially “1”, and the output signal is in phase with the input signal.

The emitter follower circuit shown in FIG. 10 has the same configuration (npn transistor Q101, resistor R101) as the emitter follower circuit shown in FIG. 9, and has an npn transistor Q102.
The npn transistor Q102 is inserted between the emitter of the npn transistor Q101 and the resistor R101, and a constant bias voltage is supplied to the base by the bias supply circuit B101.

The npn transistor Q102 is a constant current circuit that allows a constant bias current Ibs to flow between the emitter of the npn transistor Q101 and the ground line G. Current can be drawn from the load within a range not exceeding this bias current Ibs.
Microfilm of Japanese Utility Model No. 56-048284 (Japanese Patent Application No. 57-160222) JP 09-260974 A

  Incidentally, the conventional emitter follower circuit shown in FIGS. 9 and 10 has a problem that the ability to draw current from the load to the ground line G is lower than the ability to discharge current from the power supply voltage line Vcc to the load. That is, when a current is discharged to the load, a large current can be supplied through the npn transistor Q101. However, when a current is drawn from the load, the magnitude of the current is limited by a constant current circuit or the like. If the pull-in current is limited, the discharge rate of the capacitor is limited. Therefore, when the capacitance of the capacitor is large or the signal frequency is high, the output voltage cannot follow the change in the input voltage, and the waveform is distorted. .

FIG. 11 is a diagram illustrating an example of an output voltage waveform in a conventional emitter follower circuit.
The signal frequency is about 500 kHz in FIG. 11 (A) and about 50 MHz in FIG. 10 (B). As can be seen from the portion surrounded by the dotted line in FIG. 11B, when the signal frequency is increased from 500 kHz to 50 MHz, the output voltage cannot follow the change in the input voltage during the period of drawing current from the load, and the waveform is distorted. It will end up.

  In order to improve such distortion of the output voltage waveform, it is necessary to increase the bias current Ibs that flows between the emitter of the npn transistor Q101 and the ground line G. However, when the bias current Ibs is increased, the bias current Ibs constantly flows regardless of the presence or absence of a load, which causes a problem that power consumption increases.

  The present invention has been made in view of such circumstances, and an object thereof is to provide an amplifier circuit capable of driving a load at high speed while suppressing an increase in power consumption.

  In order to achieve the above object, the first amplifier circuit of the present invention includes a first transistor having a control terminal electrically connected to a signal input terminal, and a control terminal electrically connected to the signal output terminal. A second transistor that forms a differential circuit together with the first transistor, and is electrically connected in common to the first and second transistors, for supplying current to the first and second transistors. A third transistor; a first resistance element electrically connected between the first transistor and the first power supply voltage supply line; the second transistor and the first power supply voltage supply line; A second resistance element electrically connected between the third transistor, a third resistance element electrically connected between the third transistor and the second power supply voltage supply line, and the third resistance element. Via that supplies a predetermined bias voltage to the control terminal of the transistor A first capacitor electrically connected between the control terminal of the third transistor and the second power supply voltage supply line; the first power supply voltage supply line; and the signal output. A fourth transistor electrically connected between the terminal, a fifth transistor electrically connected between the signal output terminal and the second power supply voltage supply line, and the first transistor A fourth resistance element provided in a current path between a power supply voltage supply line and the fourth transistor; and a current path provided between the fifth transistor and the second power supply voltage supply ship. A fifth capacitor, a second capacitor electrically connected between a connection line between the fourth resistor and the fourth transistor, and a control terminal of the fifth transistor; Between the control terminal of the fifth transistor and the second power supply voltage supply line. A third capacitor connected electrically, and a sixth resistor element electrically connected between the control terminal of the third transistor and the control terminal of the fifth transistor, The control terminal of the fourth transistor is electrically connected to a connection line between the second resistance element and the second transistor.

  In the second amplifier circuit of the present invention, the control terminal is electrically connected to the first signal input terminal, and the control terminal is electrically connected to the second signal input terminal. A second transistor; a first resistance element electrically connected between the first power supply voltage supply line and the first transistor; the first power supply voltage supply line and the second transistor; A second resistance element electrically connected between the second transistor, a third transistor electrically connected between the first transistor and the second power supply voltage supply line, and the second transistor A fourth transistor electrically connected between the transistor and the second power supply voltage supply line; and a current path between the third transistor and the second power supply voltage supply line. A current path between the third resistance element, the fourth transistor, and the second power supply voltage supply line; A fourth resistance element provided on the path, a connection line between the first transistor and the third transistor, and a connection line between the second transistor and the fourth transistor. A fifth resistance element electrically connected to the control circuit, a bias supply circuit for supplying a predetermined bias voltage to the control terminals of the third and fourth transistors, and a control terminal of the third and fourth transistors; A first capacitor electrically connected between the second power supply voltage supply line and a first capacitor electrically connected between the first power supply voltage supply line and the first signal output terminal; 5 transistors, a sixth transistor electrically connected between the first signal output terminal and the second power supply voltage supply line, the first power supply voltage supply line and the fifth power supply line A sixth resistance element provided in a current path between the transistor and the sixth transistor; A seventh resistance element provided in a current path between the transistor and the second power supply voltage supply line; a connection line between the sixth resistance element and the fifth transistor; and the sixth resistance element. A second capacitor electrically connected between the control terminal of the transistor and a third capacitor electrically connected between the control terminal of the sixth transistor and the second power supply voltage supply line; A capacitor, an eighth resistor element electrically connected between the control terminals of the third and fourth transistors and the control terminal of the sixth transistor, the first power supply voltage supply line, and the first A seventh transistor electrically connected between the second signal output terminal and an eighth transistor electrically connected between the second signal output terminal and the second power supply voltage supply line; Provided in a current path between the transistor and the first power supply voltage supply line and the seventh transistor. The ninth resistor element, the tenth resistor element provided in the current path between the eighth transistor and the second power supply voltage supply line, the ninth resistor element, and the seventh resistor A fourth capacitor electrically connected between the connection line between the first transistor and the control terminal of the eighth transistor, the control terminal of the eighth transistor and the second power supply voltage supply line And an eleventh resistor electrically connected between the control terminals of the third and fourth transistors and the control terminal of the eighth transistor. And the control terminal of the fifth transistor is electrically connected to a connection line between the second resistance element and the second transistor, and the control terminal of the seventh transistor. Is connected to the connection line between the first resistance element and the first transistor. Connected with care.

  According to the present invention, a load can be driven at high speed with low power consumption without constantly flowing a large current through a transistor.

  Hereinafter, three embodiments of the amplifier circuit of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating an example of a configuration of a buffer circuit according to a first embodiment of an amplifier circuit of the present invention.

The buffer circuit shown in FIG. 1 includes npn transistors Q1 and Q2, a current detection circuit 1, a bias control circuit 2, a resistor R2, and a bias supply circuit B1.
The npn transistor Q1 is an embodiment of the first transistor of the present invention.
The npn transistor Q2 is an embodiment of the second transistor of the present invention.
The current detection circuit 1 is an embodiment of the current detection circuit of the present invention.
The bias control circuit 2 is an embodiment of the bias control circuit of the present invention.

The npn transistor Q1 controls the current flowing from the node N1 to the node N2 according to a signal input based on the base.
That is, npn transistor Q1 has its collector connected to node N1, its emitter connected to node N2, and the output signal of amplifier circuit AMP1 at the previous stage being input to the base.

The npn transistor Q2 controls the current flowing from the node N2 to the ground line G according to the bias voltage supplied to the base.
That is, npn transistor Q2 has its collector connected to node N2, its emitter connected to ground line G via resistor R2, and inputs a bias voltage to its base.

  Current detection circuit 1 detects a current input from power supply line Vcc to npn transistor Q1 via node N1.

  The bias supply circuit B1 generates a DC bias voltage supplied to the base of the npn transistor Q2.

The bias control circuit 2 controls the bias voltage generated in the bias supply circuit B1 according to the current detection result in the current detection circuit 1, and inputs the bias voltage to the base of the npn transistor Q2.
That is, the bias control circuit 2 decreases the bias current Ibs of the npn transistor Q2 according to the increase in the detection current of the current detection circuit 1, and increases the bias current Ibs of the npn transistor Q2 according to the decrease in the detection current. The base voltage of the npn transistor Q2 is controlled.
More specifically, the base voltage of the npn transistor Q2 is decreased according to the increase in the detection current of the current detection circuit 1, and the base voltage of the npn transistor Q2 is increased according to the decrease in the detection current.

  In the example of FIG. 1, a series circuit of a capacitor CL and a resistor RL is connected as a load between the emitter of the npn transistor Q1 and the ground line G.

  Here, the operation of the buffer circuit shown in FIG. 1 having the above-described configuration will be described.

In the buffer circuit shown in FIG. 1, the input is the base of the npn transistor Q1, and the output is the emitter of the npn transistor Q1.
When the output potential becomes lower than the input potential and the potential difference becomes larger than the forward voltage of the pn junction, the emitter current of the npn transistor Q1 increases abruptly and the emitter to the load (capacitor CL and resistor RL). Current flows. When the capacitor CL of the load is charged by this current and the potential difference between the output and the input becomes smaller than the forward voltage of the pn junction, the emitter current of the npn transistor Q1 is reduced and the current output to the load is stopped.
When the output is higher than the input, the npn transistor Q1 is turned off, and current is drawn from the load to the resistor R1. When the charge of the capacitor CL is discharged by this drawing current and the output becomes a potential lower than the input by the forward voltage of the pn junction, the emitter current of the npn transistor Q1 charges the capacitor CL as described above, and the output voltage decreases. It can be suppressed.
In this way, a voltage obtained by shifting the input voltage by the forward voltage of the pn junction is generated at the output of the buffer circuit in the steady state. Therefore, similarly to the emitter follower circuit shown in FIGS. 9 and 10, the amplification factor for the AC voltage signal is substantially “1”, and the output signal is in phase with the input signal.

Furthermore, according to the above configuration, the current detection circuit 1 detects the current input to the npn transistor Q1 via the node N1. In the bias control circuit 2, the base voltage of the npn transistor Q2 is controlled so that the current of the npn transistor Q2 decreases as the detection current increases, and the current of the npn transistor Q2 increases as the detection current decreases. The
Therefore, when the base voltage of the npn transistor Q1 rises according to the output signal of the amplifier circuit AMP1 and the current of the npn transistor Q1 increases, the current flowing to the npn transistor Q2 decreases, so that the load from the npn transistor Q1 ( The current discharged to the capacitor CL and the resistor RL) increases. Further, when the current flowing through npn transistor Q1 decreases, the current flowing through npn transistor Q2 increases, so that the current drawn from the load to npn transistor Q2 increases. That is, in both cases where the discharge current flows from the npn transistor Q1 to the load and the pull-in current flows from the load to the npn transistor Q2, the bias control circuit 2 controls the bias voltage so that the current flows transiently. However, the current that can be increased can be increased. In particular, it is possible to improve the ability to flow a drawing current transiently. As a result, even when the capacity of the load capacitor CL is large or the frequency is high, the output voltage can follow the change of the input voltage (especially, the change at the time of current drawing) at high speed, and the output voltage waveform is distorted. Can be effectively suppressed.

  Further, in order to increase the load pull-in current, the method of constantly setting the bias current Ibs of the npn transistor Q2 large regardless of the current of the npn transistor Q1 steadily increases through the npn transistor Q1 and the npn transistor Q2. Since the current flows, power is wasted. However, according to the buffer circuit shown in FIG. 1, the bias current Ibs of the npn transistor Q2 is decreased / increased according to the increase / decrease of the npn transistor Q1, so that It is possible to increase the load drawing current without flowing a large current, and it is possible to suppress an increase in power consumption.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.
FIG. 2 is a diagram showing an example of the configuration of the buffer circuit according to the second embodiment of the amplifier circuit of the present invention.

The buffer circuit shown in FIG. 2 includes npn transistors Q1 and Q2, resistors R1 to R3, capacitors C1 and C2, and a bias supply circuit B1.
The resistor R1 is an embodiment of the impedance circuit of the present invention.
The circuit including resistor R3 and capacitors C1 and C2 is an embodiment of the bias control circuit of the present invention.
The series circuit of capacitors C1 and C2 is an embodiment of the series circuit of capacitors of the present invention.
Resistor R3 is an embodiment of the resistor of the present invention.

Resistor R1 is connected between power supply line Vcc and node N1.
Capacitor C1 is connected between the base of npn transistor Q2 and node N1.
Capacitor C2 is connected between the base of npn transistor Q2 and ground line G.
The resistor R3 is connected between the base of the npn transistor Q2 and the bias voltage output terminal of the bias supply circuit B1.
Resistor R2 and npn transistors Q1 and Q2 have the same connection relationship as the constituent elements having the same reference numerals in FIG.

  If the AC component of the voltage generated in the resistor R1 is ‘vr1’, the AC component Vb2 of the base voltage of the npn transistor Q2 can be approximated by the following equation.

    vb2 = vr1 × {c1 / (c1 + c2)} (1)

In Expression (1), “c1” indicates the capacitance value of the capacitor C1, and “c2” indicates the capacitance value of the capacitor C2.
As can be seen from this equation, a signal obtained by dividing the AC signal vr1 of the voltage signal generated in the resistor R1 by the series circuit of the capacitors C1 and C2 is input to the base of the npn transistor Q2.

As described above, according to the buffer circuit shown in FIG. 2, the AC voltage generated in the resistor R1 according to the current flowing through the npn transistor Q1 is divided by the series circuit of the capacitors C1 and C2, and the bias supply circuit B1 is generated. The signal is superimposed on the DC bias voltage and input to the base of the npn transistor Q2.
When the base voltage of the npn transistor Q1 rises according to the output signal of the amplifier circuit AMP1 and the current of the npn transistor Q1 increases, the current flowing through the resistor R1 increases and the potential of the node N1 decreases. The base voltage of the npn transistor Q2, which is a connection point with C2, also decreases, and the current of the npn transistor Q2 decreases. This increases the current discharged from npn transistor Q1 to the load. Further, when the current flowing through npn transistor Q1 decreases, the current flowing through resistor R1 decreases and the potential of node N1 rises. Therefore, contrary to the above, the base voltage of npn transistor Q2 rises and npn transistor Q2 Current increases. This increases the current drawn from the load to npn transistor Q2. In other words, the current that can be passed through the load transiently can be increased in both cases where a discharge current flows from npn transistor Q1 to the load and a sink current flows from load to npn transistor Q2.
Therefore, even when the capacitance of the load capacitor CL is large or the frequency is high, the output voltage can follow the change of the input voltage at a high speed, and distortion of the output voltage waveform that is likely to occur particularly during the current drawing period can be obtained. It can be effectively suppressed.

  Further, according to the buffer circuit shown in FIG. 2, the DC component of the bias current Ibs flowing through the npn transistor Q2 is kept constant according to the DC bias voltage of the bias supply circuit B1, and a transient load pull-in current is obtained. Since it is not necessary to set a large DC component in order to increase the power consumption, an increase in power consumption due to a steady bias current can be suppressed.

  In addition, the buffer circuit shown in FIG. 2 has a very simple configuration that can be realized by adding a current detection resistor R and two capacitors to the circuit shown in FIG. It is possible to greatly improve the response characteristics while minimizing.

  As described above, since the buffer circuit according to the present embodiment has excellent output response performance and can suppress power consumption and circuit area to be small, for example, a high speed and low performance like a TV tuner circuit in a mobile phone. The present invention can be suitably applied to a circuit that requires power consumption, a circuit that drives a capacitive load at high speed such as a driver circuit that drives a switch at high speed, and the like.

FIG. 3 is a diagram showing an example of an output voltage waveform of the buffer circuit shown in FIG. 2, and shows a comparative example with a conventional emitter follower circuit.
In FIG. 3, a curve C1 shows the output voltage waveform of the buffer circuit according to this embodiment, and a curve C2 shows the output voltage waveform of the conventional emitter follower circuit. As can be seen from a comparison between the two, in the buffer circuit according to the present embodiment, the current drawing capability from the load can be transiently increased, so that the waveform distortion found in the conventional circuit is improved.

  Next, an application example of the buffer circuit shown in FIG. 2 will be described.

FIG. 4 is a diagram showing an example of a unity gain amplifier circuit in which the buffer circuit shown in FIG. 2 is provided in the output stage.
The amplifier circuit shown in FIG. 4 has buffer circuits (Q1, Q2, R1 to R3, C1, C2, and B1) having the same configuration as the circuit shown in FIG. 2, and npn transistors Q3 to Q5 are used as differential amplifier circuits. , Pnp transistors Q6 and Q7, resistors R4 to R6, and a capacitor C3.

Npn transistors Q3 and Q4 have their emitters connected in common, and this connection point is connected to the collector of npn transistor Q5. The npn transistor Q5 has an emitter connected to the ground line G via a resistor R4, and a DC bias voltage of the bias supply circuit B1 is input to the base.
The bases of the pnp transistors Q6 and Q7 are connected in common, and this connection point is connected to the collector of the pnp transistor Q6. The collector of the pnp transistor Q6 is connected to the collector of the npn transistor Q3, and the emitter thereof is connected to the power supply line Vcc via the resistor R5. The collector of the pnp transistor Q7 is connected to the collector of the npn transistor Q4, and the emitter thereof is connected to the power supply line Vcc via the resistor R6.
The connection point between the collectors of the pnp transistor Q7 and the npn transistor Q4 is connected to the base of the npn transistor Q1. Node N2 is connected to the base of npn transistor Q4.
The capacitor C3 is connected in parallel with the bias supply circuit B1 and prevents fluctuations in the DC bias voltage.
The bias supply circuit B1 is shared by the output stage buffer circuit and the preceding differential amplifier circuit.

According to the amplifier circuit shown in FIG. 4, when an input signal is applied from the input terminal Tin to the base of the npn transistor Q3, a signal having substantially the same voltage waveform is output from the node N2 to the output terminal Tout.
That is, when the output terminal Tout has a potential difference with respect to the input terminal Tin, the potential difference is amplified by the differential amplifier circuit having the above-described configuration and fed back to the base of the npn transistor Q1, so that the potential difference is reduced. The voltage at the output terminal Tout changes. Assuming that the gain of the differential amplifier circuit is sufficiently large, the potential difference between the terminal Tin and the terminal Tout becomes almost zero by this negative feedback control, and the voltage waveform of the output signal becomes almost the same as the input signal.

FIG. 5 is a diagram showing an example of a differential amplifier circuit in which two buffer circuits shown in FIG. 2 are mounted in the output stage.
The differential amplifier circuit shown in FIG. 5 has a buffer circuit BUF1 (Q1-1, Q2-1, R1-1 to R3-1, C1-1, C2-1, B1) having the same configuration as the circuit shown in FIG. ) And a buffer circuit BUF2 (Q1-2, Q2-2, R1-2 to R3-2, C1-2, C2-2, B1), and npn transistors Q8 to Q11 and a resistor as a differential amplifier circuit R7 to R11 and a capacitor C3.

Npn transistors Q8 and Q9 have their emitters connected via a resistor R7. Npn transistor Q8 has its collector connected to power supply line Vcc via resistor R8, its base connected to input terminal Tin1, and its emitter connected to the collector of npn transistor Q10. Npn transistor Q9 has its collector connected to power supply line Vcc via resistor R9, its base connected to input terminal Tin2, and its emitter connected to the collector of npn transistor Q11.
The npn transistors Q10 and Q11 have their emitters connected to the ground line G via resistors R10 and R11, respectively, and the bases are commonly supplied with the DC bias voltage of the bias supply circuit B1.
The collector of npn transistor Q8 is connected to the base of npn transistor Q1-2, and the collector of npn transistor Q9 is connected to the base of npn transistor Q1-1.
The capacitor C3 is connected in parallel with the bias supply circuit B1 and prevents fluctuations in the DC bias voltage.
The bias supply circuit B1 is shared by the two buffer circuits (BUF1 and BUF2) at the output stage and the differential amplifier circuit at the preceding stage.

According to the amplifier circuit shown in FIG. 5, when a differential signal is input between the input terminals Tin1 and Tin2, the differential signal obtained by amplifying the differential signal is connected to the output terminal Tout1 and the node connected to the node N1-1. It occurs between the output terminal Tout2 connected to N1-2.
That is, when a differential signal is input between the input terminals Tin1 and Tin2, the differential signal is amplified by the differential amplifier circuit having the above-described configuration and output from the two collectors of the npn transistors Q8 and Q9. Is done. The amplified differential signal is output between the output terminals Tout1 and Tout2 via the two buffer circuits (BUF1 and BUF2) in the output stage, and is supplied to the load with low impedance.

  By the way, in the buffer circuit shown in FIG. 2, the AC voltage signal generated in the resistor R1 (that is, the signal detecting the change in the current of the npn transistor Q1) is divided and fed back to the base of the npn transistor Q2. A connection point of capacitors C1 and C2 connected in series with the line G is connected to the base of the npn transistor Q2. Considering that the voltage signal fed back to the base of the npn transistor Q2 is AC, the connection between the capacitors C1 and C2 may be changed as shown in FIGS. 6 and 7, for example.

The buffer circuit shown in FIG. 6 is obtained by disconnecting the connection between the capacitor C2 and the ground line G in the buffer circuit shown in FIG. 2, and connecting this connection to the output terminal of the DC bias voltage of the bias supply circuit B1. The buffer circuit shown in FIG. 7 is obtained by connecting this connection to the power supply line Vcc.
In any circuit, since a signal obtained by dividing the AC voltage signal generated in the resistor R1 is generated at the connection point between the capacitors C1 and C2, the same effect as that of the circuit shown in FIG. 2 can be obtained.

<Third Embodiment>
Next, a third embodiment of the amplifier circuit of the present invention will be described.

FIG. 8 is a diagram showing an example of the configuration of the buffer circuit according to the third embodiment of the present invention.
The buffer circuit shown in FIG. 8 includes npn transistors Q1 and Q2, a resistor R2, inductors L1 and L2, and a bias supply circuit B1.
The inductor L1 is an embodiment of the first inductor of the present invention.
The inductor L2 is an embodiment of the second inductor of the present invention.

  Inductor L1 is inserted on a wiring for inputting a current from power supply line Vcc to npn transistor Q1 via node N1.

  The inductor L2 is magnetically coupled to the inductor L1, generates a voltage corresponding to the current flowing through the inductor L1, superimposes it on the DC bias voltage of the bias supply circuit B1, and inputs it to the base of the npn transistor Q2. The inductor L2 is connected between the output terminal of the bias voltage of the bias supply circuit B1 and the base of the npn transistor Q2, and when the discharge current from the npn transistor Q1 to the load increases, the npn transistor Q2 When the base voltage is lowered and the discharge current is reduced, a voltage for raising the base voltage of the npn transistor Q2 is generated.

  Resistor R2 and npn transistors Q1 and Q2 have the same connection relationship as the constituent elements having the same reference numerals in FIG.

According to the buffer circuit shown in FIG. 8, a current corresponding to the current flowing through the npn transistor Q1 is generated in the inductor L2 magnetically coupled to the inductor L1, and the voltage of the inductor L2 is the DC bias voltage of the bias supply circuit B1. Is input to the base of the npn transistor Q2.
When the base voltage of the npn transistor Q1 rises according to the output signal of the amplifier circuit AMP1 and the current of the npn transistor Q1 increases, a voltage having a polarity that lowers the base voltage of the npn transistor Q2 is generated in the inductor L2. The current of transistor Q2 decreases. This increases the current discharged from npn transistor Q1 to the load. When the current flowing through npn transistor Q1 decreases, a voltage that raises the base voltage of npn transistor Q2 is generated in inductor L2, contrary to the above, and the current of npn transistor Q2 increases. This increases the current drawn from the load to npn transistor Q2. In other words, the current that can be passed through the load transiently can be increased in both cases where a discharge current flows from npn transistor Q1 to the load and a sink current flows from load to npn transistor Q2. Therefore, even when the capacitance of the load capacitor CL is large or the frequency is high, the output voltage can follow the change of the input voltage at high speed, and distortion of the output voltage waveform can be suppressed.

  Further, according to the buffer circuit shown in FIG. 8, the direct current component of the bias current Ibs flowing through the npn transistor Q2 is kept constant according to the direct current bias voltage generated in the bias supply circuit B1, and the transient load Since it is not necessary to set a large DC component in order to increase the current drawn in, the increase in power consumption can be suppressed.

  Furthermore, according to the buffer circuit shown in FIG. 8, it is possible to omit the resistors R1 and R3 used in the circuit shown in FIG. 2, and the configuration can be further simplified.

  As mentioned above, although some embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Various variations are included.

For example, in the buffer circuit shown in FIG. 2, the resistor R1 is used for detecting the current of the npn transistor Q1, but the present invention is not limited to this. For example, an inductor or other signal that outputs a signal corresponding to the current change of the npn transistor Q1 is used. It may be replaced with a circuit.
In the buffer circuit shown in FIG. 2, an AC component is superimposed on the DC bias voltage input to the npn transistor Q2 through the capacitors C1 and C2, and therefore, between the connection point of the capacitors C1 and C2 and the DC bias voltage supply terminal. Although the resistor R3 is inserted, the present invention is not limited to this. For example, an inductor having a sufficiently large impedance at the frequency of the alternating current component to be superimposed may be used instead of the resistor R3.

In each of the above embodiments, an npn transistor is used in the buffer circuit. However, the present invention is not limited to this, and the present invention can be applied to a circuit that outputs a negative voltage using, for example, a pnp transistor.
Further, the type of transistor is not limited to the bipolar transistor, and various other types of transistors (for example, field effect transistors) may be used.

It is a figure which shows an example of a structure of the buffer circuit which concerns on 1st Embodiment of the amplifier circuit of this invention. It is a figure which shows an example of a structure of the buffer circuit which concerns on 2nd Embodiment of the amplifier circuit of this invention. FIG. 3 is a diagram showing an example of an output voltage waveform of the buffer circuit shown in FIG. 2. FIG. 3 is a first diagram illustrating an application example of the buffer circuit illustrated in FIG. 2. FIG. 3 is a second diagram illustrating an application example of the buffer circuit illustrated in FIG. 2. FIG. 3 is a first diagram illustrating a modification of the buffer circuit illustrated in FIG. 2. FIG. 9 is a second diagram showing a modification of the buffer circuit shown in FIG. 2. It is a figure which shows an example of a structure of the buffer circuit which concerns on 3rd Embodiment of the amplifier circuit of this invention. It is a 1st figure which shows the structural example of a general emitter follower circuit. It is a 2nd figure which shows the structural example of a general emitter follower circuit. It is a figure which shows an example of the output voltage waveform in the conventional emitter follower circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Current detection circuit, 2 ... Bias control circuit, Q1, Q1-1, Q1-2, Q2, Q2-1, Q2-2 ... npn transistor, R1, R1-1, R1-2, R2, R2-1 , R2-2, R3, R3-1, R3-2 ... resistors, B1 ... bias supply circuit, C1, C1-1, C1-2, C2, C2-1, C2-2 ... capacitors, L1, L2 ... inductors

Claims (5)

A first transistor having a control terminal electrically connected to the signal input terminal;
A second transistor having a control terminal electrically connected to the signal output terminal and forming a differential circuit together with the first transistor;
A third transistor electrically connected in common to the first and second transistors for supplying current to the first and second transistors;
A first resistance element electrically connected between the first transistor and a first power supply voltage supply line;
A second resistance element electrically connected between the second transistor and the first power supply voltage supply line;
A third resistance element electrically connected between the third transistor and the second power supply voltage supply line;
A bias supply circuit for supplying a predetermined bias voltage to the control terminal of the third transistor;
A first capacitor electrically connected between a control terminal of the third transistor and the second power supply voltage supply line;
A fourth transistor electrically connected between the first power supply voltage supply line and the signal output terminal;
A fifth transistor electrically connected between the signal output terminal and the second power supply voltage supply line;
A fourth resistance element provided in a current path between the first power supply voltage supply line and the fourth transistor;
A fifth resistance element provided in a current path between the fifth transistor and the second power supply voltage supply ship;
A second capacitor electrically connected between a connection line between the fourth resistance element and the fourth transistor and a control terminal of the fifth transistor;
A third capacitor electrically connected between the control terminal of the fifth transistor and the second power supply voltage supply line;
A sixth resistance element electrically connected between the control terminal of the third transistor and the control terminal of the fifth transistor;
Have
A control terminal of the fourth transistor is electrically connected to a connection line between the second resistance element and the second transistor;
Amplification circuit. A sixth transistor provided in a current path between the first resistance element and the first transistor;
A seventh transistor provided in a current path between the second resistance element and the second transistor;
Further comprising
The control terminal of the sixth transistor and the control terminal of the seventh transistor are connected to each other, and the sixth transistor and the seventh transistor constitute a current mirror circuit.
The amplifier circuit according to claim 1. The first to fourth transistors are npn bipolar transistors;
The sixth and seventh transistors are pnp bipolar transistors;
The amplifier circuit according to claim 2. A first transistor having a control terminal electrically connected to the first signal input terminal;
A second transistor having a control terminal electrically connected to the second signal input terminal;
A first resistance element electrically connected between the first power supply voltage supply line and the first transistor;
A second resistance element electrically connected between the first power supply voltage supply line and the second transistor;
A third transistor electrically connected between the first transistor and a second power supply voltage supply line;
A fourth transistor electrically connected between the second transistor and the second power supply voltage supply line;
A third resistance element provided in a current path between the third transistor and the second power supply voltage supply line;
A fourth resistance element provided in a current path between the fourth transistor and the second power supply voltage supply line;
A fifth resistance element electrically connected between a connection line between the first transistor and the third transistor and a connection line between the second transistor and the fourth transistor. When,
A bias supply circuit for supplying a predetermined bias voltage to the control terminals of the third and fourth transistors;
A first capacitor electrically connected between the control terminals of the third and fourth transistors and the second power supply voltage supply line;
A fifth transistor electrically connected between the first power supply voltage supply line and the first signal output terminal;
A sixth transistor electrically connected between the first signal output terminal and the second power supply voltage supply line;
A sixth resistance element provided in a current path between the first power supply voltage supply line and the fifth transistor;
A seventh resistance element provided in a current path between the sixth transistor and the second power supply voltage supply line;
A second capacitor electrically connected between a connection line between the sixth resistor element and the fifth transistor and a control terminal of the sixth transistor;
A third capacitor electrically connected between the control terminal of the sixth transistor and the second power supply voltage supply line;
An eighth resistance element electrically connected between the control terminals of the third and fourth transistors and the control terminal of the sixth transistor;
A seventh transistor electrically connected between the first power supply voltage supply line and the second signal output terminal;
An eighth transistor electrically connected between the second signal output terminal and the second power supply voltage supply line;
A ninth resistance element provided in a current path between the first power supply voltage supply line and the seventh transistor;
A tenth resistance element provided in a current path between the eighth transistor and the second power supply voltage supply line;
A fourth capacitor electrically connected between a connection line between the ninth resistance element and the seventh transistor and a control terminal of the eighth transistor;
A fifth capacitor electrically connected between the control terminal of the eighth transistor and the second power supply voltage supply line;
An eleventh resistance element electrically connected between the control terminals of the third and fourth transistors and the control terminal of the eighth transistor;
Have
A control terminal of the fifth transistor is electrically connected to a connection line between the second resistance element and the second transistor;
A control terminal of the seventh transistor is electrically connected to a connection line between the first resistance element and the first transistor;
Amplification circuit. The first to eighth transistors are npn bipolar transistors;
The amplifier circuit according to claim 4.

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