JP2007013037A - Method of manufacturing reverse blocking insulated-gate bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a reverse blocking insulated-gate bipolar transistor having low ON-voltage and low switching loss characteristics whereby a high temperature heat treatment time under atmosphere of an oxygen required for forming an isolation layer can considerably be reduced, and the isolation layer can be formed without newly bringing in oxygen working as a cause to variations in the impurity concentration profile of a drift layer. <P>SOLUTION: The method of manufacturing the reverse blocking insulated-gate bipolar transistor includes a step of forming a second conductive isolation layer surrounding a front side active region acting like an active region, on the surface of the drift layer of a first conductive drift layer, by forming a gas phase diffusion layer on the inner surface of trenches formed in advance at a forming positions of the isolation layer, and thereafter by depositing and growing a second conductive epitaxial layer into the trenches. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power semiconductor device used for a power conversion device or the like, and more particularly to a method for manufacturing a reverse blocking IGBT (insulated gate bipolar transistor) having a reverse withstand voltage required for applications such as a matrix converter.

An IGBT (insulated gate bipolar transistor) having a conventional planar MOS structure as shown in FIG. 21 is used under a direct current power source in an inverter circuit or a chopper circuit which is a main application. As long as the breakdown voltage can be secured, there is no problem, and it has been made without considering the reverse breakdown voltage securing from the element design stage.
However, recently, in a semiconductor power converter, in order to perform AC (alternating current) / AC conversion, AC / DC (direct current) conversion, and DC / AC conversion, a bidirectional switching element is used for a matrix converter such as a direct link type conversion circuit. By using the circuit, the circuit has been made smaller, lighter, more efficient, faster responsive, and lower in cost. Therefore, in order to configure the bidirectional switching element as an antiparallel connection of the IGBT, an IGBT having an effective reverse breakdown voltage has been demanded. In addition, naturally, further low on-voltage and low switching loss characteristics are also required.

As described above, the conventional IGBT (FIG. 21) does not employ an element design and manufacturing method for ensuring an effective reverse blocking capability (reverse breakdown voltage). It is necessary to configure a conversion device by connecting a diode. If it does so, the generation | occurrence | production loss including a diode will become large and will cause the fall of the conversion efficiency of a converter. Furthermore, the number of elements increases, making it difficult to reduce the size, weight, and cost of the conversion device. In these respects, the existence significance of the IGBT having the reverse blocking ability arises.
FIG. 21 is a cross-sectional view of a main part of a conventional IGBT that does not substantially have the above-described reverse breakdown voltage. Since this IGBT 200 is manufactured as a device on the premise that it is not reverse-biased, a sign A () in which the electric field tends to concentrate when reverse bias is applied with the emitter electrode 104 as the ground potential and the collector electrode 105 as the negative potential. In the vicinity of the surface of the collector junction 102 shown in FIG. 21), no processing is performed by the cutting portion 103 that is still provided with mechanical cutting strain due to dicing or the like, and of course, sufficient reverse breakdown voltage cannot be obtained.

  FIG. 22 is a cross-sectional view of a main part showing a reverse blocking IGBT 300 having a conventional low on-voltage and low switching loss characteristics. The reverse blocking IGBT 300 is an IGBT in which the separation layer 107 for making the reverse breakdown voltage effective without the influence of the above-described cutting strain on the junction is formed only by diffusion from the surface (one side). When this IGBT is a device having a bidirectional withstand voltage of 600V, the finish can be a thin NPT (Non Punch Through) wafer with a thickness of about 100 μm (wafer thickness of about 200 μm at a withstand voltage of 1200 V). This IGBT has an advantage that a reverse blocking IGBT in which the trade-off relationship between the on-voltage characteristics and the turn-off loss is eliminated can be obtained by further reducing the thickness of the collector layer 106 and controlling the impurity concentration thereof (Japanese Patent Application No. 2005). (See Background Art section of -000147 and FIG. 5).

  However, in the case of the reverse blocking IGBT 300 having the structure shown in FIG. 22, the separation layer 107 is formed by the diffusion of boron from the surface (one side) to an initial thick wafer (about 120 μm). In order to make a separation layer 107 having a depth of 100 μm (finished thickness), if the separation layer width (in the direction parallel to the surface) formed as an opening of the mask oxide film on the wafer surface is 100 μm, thermal diffusion causes In the horizontal direction (the direction parallel to the surface), the width is about 100 μm, and the width is eventually 300 μm. Not only the chip area utilization efficiency is bad, but also the cost is disadvantageous. When the finished wafer (substrate) thickness is 200 μm (withstand voltage 1200V), the separation layer 107 further expands greatly, not only the chip area utilization efficiency deteriorates, but also the diffusion time becomes extremely long, so the productivity is also high. It becomes worse and the practicality decreases.

On the other hand, a technique for forming a separation layer by diffusion from both sides instead of forming a separation layer by single-sided diffusion as described above is also known. According to this method, the diffusion time can be halved at once ( In other words, it can be said that it is only half), and in order to obtain low on-voltage and low switching loss characteristics, the thickness of the semiconductor substrate (wafer) is changed from the stage before separation diffusion to a wafer with a thin finished thickness. Therefore, there is a problem that wafer cracking increases, resulting in an increase in cost.
Further, boron diffusion from the surface (one side) for forming the separation layer shown in the background art section of the Japanese Patent Application No. 2005-000147 and FIG. It is performed in an atmosphere containing gas (this is also the same as the above-described separation and diffusion method from both sides). However, the separation diffusion method from one side particularly has a diffusion time that is about twice as long as the diffusion from both sides, so that a particularly high concentration of oxygen ions is taken into the wafer. It has been found that the incorporated oxygen is converted into a donor when subjected to a heat treatment at 400 ° C. to 500 ° C. This donorization is a major problem because it causes fluctuations in the diffusion profile.

  This donor problem and countermeasures will be described in detail. In the reverse blocking IGBT manufacturing process, a thick n-type semiconductor substrate (wafer) having a thickness of 500 μm or more is put into the process to form a separation (diffusion) layer that requires a high temperature and a long time. After the formation of the active region such as the surface side MOS structure, after the back surface is ground so that the isolation layer is exposed on the back surface, boron ion implantation and annealing treatment are performed on the back surface side to form a p collector layer on the back surface side. A process of forming is required. In this step of forming the p collector layer, annealing heat treatment is usually performed in the range of 400 ° C. to 500 ° C. so as not to damage the surface structure such as the aluminum electrode on the surface side (occurring at 500 ° C. or higher). However, this thermal history at 400 ° C. to 500 ° C. causes oxygen donors to progress as described above, and the drift layer profile varies greatly. Therefore, in order to avoid the aforementioned oxygen donor formation, the back surface annealing temperature must be 400 ° C. or lower. However, in such low-temperature annealing, implanted boron ions are not sufficiently activated, and crystal defects due to ion implantation are not sufficiently repaired, which causes a problem that a large leakage current occurs when a reverse bias is applied. . Moreover, even if the annealing is performed at a low temperature of 400 ° C. or lower, a part of the incorporated oxygen is converted into a donor, so that even if the profile of the drift layer is smaller than the above, fluctuations cannot be completely suppressed. Therefore, it is necessary to anticipate the variation of the profile in advance at the time of device design, and the variation factor of the profile, which is one of the causes that make the device design difficult, cannot be completely eliminated. For this reason, a method for forming a separation layer in which as high a concentration of oxygen as possible is not taken into the drift layer is desired as one of techniques for manufacturing a reverse blocking IGBT having low on-voltage and low switching loss characteristics.

  As one method for forming such a separation layer from which high-concentration oxygen is not taken in, a trench is formed in advance using an insulating film and a photoresist as a mask in accordance with the position where the separation layer of the wafer is formed. The isolation layer is formed by filling the inside with boron-doped epitaxial silicon and forming the boron diffusion layer around the trench at the same time by the heat treatment necessary to form the diffusion layer (functional region) in the active region. An invention has been filed in which the high-temperature diffusion time only for the purpose is substantially eliminated (Claims of Japanese Patent Application No. 2005-000147).

However, as described in Japanese Patent Application No. 2005-000147, it is necessary for filling the trench with p-type epitaxial silicon after the formation of the isolation layer trench and forming a diffusion region of the MOS structure in the active region thereafter. The method of forming a diffusion layer using p-type epitaxial silicon as a diffusion source at the same time around the trench by heat treatment cannot uniformly control the spread of the diffusion layer formed around the trench. As a result, the depletion layer from the separation layer side may partially expand abnormally at the time of reverse blocking, and problems such as making device miniaturization difficult due to the necessity of preventing electrical characteristic defects resulting from it are observed.
The present invention has been made in view of the above points, and an object of the present invention is to greatly shorten the high-temperature heat treatment time in an oxygen atmosphere necessary for forming the separation layer, and to change the impurity concentration profile of the drift layer. In order to prevent oxygen from becoming a source of oxygen, a method of manufacturing a reverse blocking insulated gate bipolar transistor having a low on-voltage and low switching loss characteristics that can form a separation layer without substantially taking in new oxygen is provided. It is to be.

  According to the first aspect of the present invention, the second conductivity type separation layer surrounding the surface side MOS region serving as the active region is formed on the surface of the first conductivity type drift layer. A trench is previously formed at the formation position, a diffusion layer is formed on the inner surface of the trench using an oxide film used as an etching mask as a diffusion mask, and then an epitaxial layer of a second conductivity type is deposited and grown in the trench, and the active The second conductivity type base region selectively formed in the region, the first conductivity type emitter region selectively formed on the surface of the base region, the drift layer, and the emitter region sandwiched between After forming the surface side MOS region having a gate electrode formed on the surface of the base region through a gate insulating film, the back side of the drift layer is ground until the isolation layer is exposed, and after grinding The back surface of the drift layer, by a method for manufacturing a reverse blocking insulated gate bipolar transistors forming a second conductivity type collector layer connected with the exposed the separation layer and surrounding the object is achieved.

  According to the second aspect of the present invention, the first conductivity type drift layer is formed on the second conductivity type semiconductor substrate by epitaxial growth, and the second conductivity type reaches the semiconductor substrate from the drift layer surface. After forming a trench in advance at the formation position of the isolation layer and forming a gas phase diffusion layer on the inner surface of the trench using the oxide film used as an etching mask as a diffusion mask, the second conductivity type is formed in the trench. A second conductive type base region selectively formed in the active region, a first conductive type emitter region selectively formed on the surface of the base region, and the drift layer. And a gate electrode formed on the surface of the base region sandwiched between the emitter region and a gate insulating film to form a surface side MOS region having a reverse blocking type insulated gate type With the manufacturing method of Lee polar transistor, the object of the present invention can be achieved.

According to the third aspect of the present invention, the diffusion layer formed on the inner surface of the isolation layer forming trench is formed by a vapor phase diffusion method. A method of manufacturing a reverse blocking insulated gate bipolar transistor is preferred.
According to the present invention as set forth in claim 4, the inverse of claim 3 according to claim 3, wherein the diffusion layer formed on the inner surface of the isolation layer forming trench is formed by an instantaneous vapor phase diffusion method. It is desirable to have a method of manufacturing a blocking insulated gate bipolar transistor.

  According to the present invention, the high-temperature heat treatment time can be significantly shortened in the oxygen atmosphere necessary for forming the separation layer, and oxygen is effectively added to prevent oxygen from becoming a donor that causes fluctuations in the impurity concentration profile of the drift layer. It is possible to provide a method of manufacturing a reverse blocking insulated gate bipolar transistor capable of forming a separation layer without incorporating a gate electrode.

  1 to 12 are main-portion cross-sectional views of a semiconductor substrate showing a method of manufacturing a reverse blocking insulated gate bipolar transistor (reverse blocking IGBT) according to a first embodiment of the present invention. 13 to 18 are cross-sectional views of main parts of a semiconductor substrate showing a method of manufacturing a reverse blocking IGBT according to Embodiment 2 of the present invention. FIG. 19 is a sectional view showing a general planar type surface side MOS structure, and FIG. 20 is a sectional view showing a general trench type surface side MOS structure.

Hereinafter, a manufacturing method of a reverse blocking insulated gate bipolar transistor (reverse blocking IGBT) according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. Example 1 described below is according to the invention described in claim 1 of the scope of claims.
As shown in FIG. 1, an n-type silicon substrate 1 having an impurity concentration of 1.5 × 10 ¹⁴ cm ⁻³ (about 30 Ωcm) is prepared. A silicon oxide film 2 serving as a mask for selective epitaxial growth in a later step is formed on the surface of the silicon substrate 1 to a thickness of 1.0 μm by a thermal oxidation method or a CVD method. Next, in order to form the opening of the silicon oxide film 2 at the formation position of the isolation layer, a photoresist pattern corresponding to the opening is formed by a predetermined photolithography technique. At this time, since the pattern of the photoresist film 6 is also used as a mask for trench etching, it is desirable that the thickness of the photoresist film 6 is increased to about 10 μm. As shown in FIG. 2, after the opening 8 is formed in the oxide film 6 by etching, the trench 9 is formed by anisotropic etching as shown in FIG. 3 while leaving the photoresist film 6 as it is. When manufacturing a reverse blocking IGBT having a withstand voltage of 600 V using an n-type silicon substrate 1 with an impurity concentration of 1.5 × 10 ¹⁴ cm ⁻³ (about 30 Ωcm), the depth of the trench 9 is suitably 100 μm and the width is 10 μm. It is. For example, in the case of manufacturing a reverse blocking IGBT having a breakdown voltage of 1200 V using an n-type silicon substrate 1 having a resistivity of about 60 to 80 Ωcm, the trench has a depth of 200 μm and a width of 20 μm. The anisotropic etching for forming the trench 9 is performed by a Bosh process. SF ₆ is used as an etching gas, and C ₂ H ₈ gas is supplied to form a sidewall protective film during the formation of the trench 9. By performing such anisotropic etching by the Bosh process, the selectivity ratio between the photoresist and Si is about 50. For example, even when etching of 200 μm is performed, a sufficient margin can be obtained. After the trench 9 is formed, the photoresist 6 is peeled off (FIG. 4).

Next, the silicon substrate 1 after the removal of the photoresist 6 is put into a diffusion furnace (not shown), and a gas such as diborane (B ₂ H ₆ ) as a diffusion source as a p-type impurity is supplied into the diffusion furnace. It is adsorbed on the surface of the silicon substrate and diffused inside the substrate. For example, when diborane gas is supplied to the silicon substrate 1 in the diffusion furnace maintained at 800 ° C., the diborane is separated into boron and hydrogen, and boron is deposited on the surface of the silicon substrate 1 and at the same time silicon that is not masked by the oxide film 2. It is diffused into the substrate 1. The boron concentration is controlled by the flow rate and time of diborane as a diffusion source, and heat treatment conditions (instantaneous gas phase diffusion). By this method, the extremely shallow diffusion layer 10 can be formed only on the inner surface of the trench 9 while ensuring a high boron concentration of about 1 × 10 ²⁰ cm ^{−3 on the} surface of the silicon substrate 1 (FIG. 5). Since the boron diffusion layer 10 by this method can be a uniform, high concentration and shallow diffusion layer of several μm or less only around the periphery of the trench 9, it is also effective for miniaturization of element patterns. In addition, since the instantaneous vapor phase diffusion method can batch-process silicon substrates even in a vertical furnace, the working time in the diffusion process can be greatly reduced as compared with a single wafer processing ion implantation method or the like.

Next, as shown in FIG. 6, a high concentration p-type epitaxial silicon layer 11 having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more is grown in the trench 9 until all the trenches 9 in the silicon substrate surface are completely filled. Let At this time, since epitaxial growth has selectivity, the epitaxial silicon layer 11 is not deposited on the surface of the oxide film 2. Thereafter, as shown in FIG. 7, the oxide film 2 is removed and the surface of the silicon substrate 1 is planarized.
Subsequent processes are the same process as the planar type IGBT without the trench 9, and a p base region, a gate oxide film, and a gate electrode are formed on the surface of the silicon substrate 1 surrounded by the epitaxial silicon layer 11 buried in the trench 9. The active region 12 such as the n emitter region and the emitter electrode is formed to complete the surface side MOS structure. By the diffusion heat treatment when the surface side MOS structure is formed, the epitaxial silicon layer 11 and the diffusion layer 10 become the separation layer 13 (FIG. 8). The structure of the active region 12 may be a planar MOS structure as shown in FIG. 19 or a trench MOS structure as shown in FIG. By the heat treatment at the time of forming the active region 12 as described above, for example, heat treatment for several hours at 1100 ° C. for forming the diffusion of the p base region, the above-described epitaxial silicon layer 11 and the shallow high-concentration diffusion layer 10 therearound are Annealed and driven to function as the separation layer 13. However, since the temperature and time of the heat treatment applied during the formation of this separation layer is negligible compared to the temperature and time required for the conventional separation layer formation only by diffusion from the silicon substrate surface, it is incorporated. There is almost no oxygen.

Further, the problem of an abnormal separation layer boundary (junction) due to non-uniform diffusion, such as the formation of a separation layer from a buried p-type epitaxial silicon layer, in the invention described in Japanese Patent Application No. 2005-000147 is described above. As described above, in the present invention, this can be avoided by providing a more uniform and shallow high-concentration diffusion layer 10 around the buried p-type epitaxial silicon layer.
Next, the separation layer 13 is exposed to the back surface by grinding from the back surface of the silicon substrate 1 to the position indicated by the chain line in FIG. 9 (FIG. 10). As shown in FIG. 11, p-type impurities are ion-implanted into the entire back surface, and annealing is performed at a temperature of 500 ° C. or lower so as not to damage the MOS structure on the front surface side by heat treatment. Form. As shown in FIG. 12, by cutting along the chain line, one chip of reverse blocking IGBT having low on-voltage and low switching loss characteristics according to the present invention is completed.

  As described above in detail, in the present invention, in order to avoid donor formation by a large amount of oxygen incorporated into a silicon substrate due to diffusion formation of a separation layer that conventionally requires high-temperature and long-time heat treatment, With the formation of the separation layer, there is a problem that the collector layer cannot be sufficiently activated or the crystal defects cannot be repaired by ion implantation due to the fact that the annealing temperature of the collector layer must be 400 ° C. or less. The reverse blocking IGBT also substantially eliminates the incorporation of new oxygen, thereby enabling an annealing process at 500 ° C. to eliminate the problem, and further, there is a problem that has occurred in the collector junction that is the boundary of the separation layer in the past. Can be resolved.

Hereinafter, Example 2 to be described relates to the invention described in claim 2 of the claims. 13 to 18 are cross-sectional views of main parts of the semiconductor substrate showing the manufacturing process of the reverse blocking IGBT according to the second embodiment.
First, a high-concentration p-type substrate 21 serving as a collector layer on the back side is used as a silicon substrate, and a low-concentration n drift layer 22 is epitaxially grown on the surface of the p-type substrate 21 (FIG. 13). Similar to the impurity concentration of the silicon substrate 1 described in the first embodiment, the impurity concentration of the low-concentration n drift layer 22 is 1. In the case of manufacturing each reverse blocking IGBT having a breakdown voltage of 600V and 1200V, the impurity concentration is 1. The thickness is 5 × 10 ¹⁴ cm ⁻³ (about 30 Ωcm), 7.66 × 10 ¹³ cm ^{−3 to} 5.745 × 10 ¹³ cm ⁻³ (resistivity is about 60 to 80 Ωcm), and the thickness is 80 μm and 180 μm.

  Thereafter, in order to use the silicon oxide film 23 and the photoresist film 24 as a trench mask from the surface of the drift layer 22 in the same manner as in the first embodiment, an opening 25 is formed in the oxide film 23 at a position where a separation layer is to be formed ( 14), a trench 26 having a depth reaching the silicon substrate layer 21 is formed by anisotropic etching (FIG. 15). As in the first embodiment, a shallow high-concentration p-type diffusion layer 28 is formed in the trench 26 by vapor phase diffusion, and then a p-type epitaxial silicon layer 27 is grown to completely fill the trench 26 (FIG. 16). Is removed to flatten the substrate surface (FIG. 17). A surface MOS structure 29 is formed in the active region on the surface of the drift layer 22 surrounded by the trench buried with the p-type epitaxial silicon layer 27 (FIG. 18). By the heat treatment at the time of forming the surface MOS structure 29, the high-concentration p-type diffusion layer 28 and the p-type epitaxial silicon layer 27 are activated at the same time to form the p-type isolation layer 30. Here, since the p-type isolation layer 30 and the silicon substrate layer 21 are of the same conductivity type, they are integrated to form a collector layer. Cutting at the center of the separation layer 30 completes the reverse blocking IGBT.

  As described above, in the present invention according to the second embodiment described above, as in the first embodiment, it is possible to substantially prevent a large amount of new oxygen from being taken in, and further, it has occurred at the collector junction that is the boundary of the conventional separation layer. It will be possible to solve the problem.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 1). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 2). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 3). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 4). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 5). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 6). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 7). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 8). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 9). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 10). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 11). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 1 of this invention (the 12). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 1). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 2). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 3). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 4). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 5). It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of reverse blocking IGBT concerning Example 2 of this invention (the 6). It is principal part sectional drawing which shows the conventional planar type surface MOS structure. It is principal part sectional drawing which shows the conventional trench type surface MOS structure. It is principal part sectional drawing of the conventional IGBT. It is principal part sectional drawing of the conventional reverse block IGBT.

Explanation of symbols

1 ... Silicon substrate,
2, 23 ... Silicon oxide film,
6, 24, ... Photoresist film 8, 25 ... Opening of oxide film,
9, 26 ... Trench 10, 28 ... p-type diffusion layer 11, 27 ... p-type epitaxial silicon layer 12 ... active layer 13, 30 ... p-type isolation layer 14 ... collector layer.

Claims (4)

The second conductivity type isolation layer surrounding the surface-side MOS region serving as the active region on the surface of the first conductivity type drift layer has a trench formed in advance at the position where the isolation layer is formed, and an oxide film used as an etching mask After forming a diffusion layer on the inner surface of the trench using a diffusion mask as a diffusion mask, a second conductivity type base layer is selectively formed in the active region by depositing and growing a second conductivity type epitaxial layer in the trench. A first conductivity type emitter region selectively formed on the surface of the base region, and a gate electrode formed on the surface of the base region sandwiched between the drift layer and the emitter region via a gate insulating film; After forming the surface side MOS region having, the back side of the drift layer is ground until the isolation layer is exposed, and the exposed isolation layer and the periphery are ground on the back side of the drift layer after grinding. Method for manufacturing a reverse blocking insulated gate bipolar transistor, and forming a second conductivity type collector layer connected. A drift layer of the first conductivity type is formed on the second conductivity type semiconductor substrate by epitaxial growth, and a second conductivity type separation layer reaching the semiconductor substrate from the drift layer surface forms a trench in advance at the formation position of the separation layer Then, after forming a diffusion layer on the inner surface of the trench using the oxide film used as an etching mask as a diffusion mask, a second conductivity type epitaxial layer is deposited and grown in the trench and selectively formed in the active region. A second conductive type base region, a first conductive type emitter region selectively formed on the surface of the base region, a gate insulating film on the surface of the base region sandwiched between the drift layer and the emitter region. A method of manufacturing a reverse blocking insulated gate bipolar transistor, comprising forming a surface side MOS region having a gate electrode formed therebetween. 3. The method of manufacturing a reverse blocking insulated gate bipolar transistor according to claim 1, wherein the diffusion layer formed on the inner surface of the isolation layer forming trench is formed by a vapor phase diffusion method. 4. The method of manufacturing a reverse blocking insulated gate bipolar transistor according to claim 3, wherein the diffusion layer formed on the inner surface of the isolation layer forming trench is formed by an instantaneous vapor phase diffusion method.

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