JP2007003252A - Probe card and method for testing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a probe card capable of implementing normal test measurement and efficient test measurement on semiconductor integrated circuit chips by preventing contact failures of probe needles. <P>SOLUTION: The probe card 1 brings second probe needles 30a-30d made of a metallic material harder than first probe needles 29a-29d to pads 32A-32D of a semiconductor integrated circuit chip 32 to be measured to break oxide films on the surfaces of the pads. Then the probe card 1 is moved in the direction of the arrangement of semiconductor integrated circuits of a wafer to bring the first probe needles 29a-29d having a higher electrical conductivity than the second probe needles 30a-30d into contact with the pads of the semiconductor integrated circuit chip 32. It is thereby possible to bring the first probe needles 29a-29d into contact with the pads of the semiconductor integrated circuit chip 32 with satisfactory electrical conductivity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a probe card used when performing a wafer test process on a plurality of semiconductor integrated circuit chips formed on a semiconductor wafer and a method for testing a semiconductor integrated circuit.

  Conventionally, in the process of manufacturing a semiconductor integrated circuit from a semiconductor wafer having a plurality of semiconductor integrated circuit chips, a wafer test process for determining pass / fail of each semiconductor integrated circuit chip has been performed after the wafer manufacturing process called the wafer first half process is completed. Has been.

  In this wafer test process, an electrical test is performed for each manufactured semiconductor integrated circuit chip in units of one chip. In the wafer test process, when the semiconductor integrated circuit chip is inspected, the quality is judged by an IC tester called a test system.

  Here, in order to inspect a semiconductor integrated circuit chip with an IC tester, a wafer transfer apparatus called a prober for transferring a semiconductor wafer is used. Furthermore, a probe card for electrically connecting a semiconductor integrated circuit chip to be measured to be tested on the prober and an IC tester is used.

  FIG. 9 schematically shows a semiconductor wafer 101 having a plurality of semiconductor integrated circuit chips 102. The semiconductor integrated circuit chips 102 are formed in a vertically and horizontally aligned arrangement on a circular semiconductor wafer 101 in the first half of the wafer process. After the semiconductor integrated circuit chip 102 is manufactured in the first half of the wafer process, the quality is determined in the wafer test process.

  After the completion of the wafer test process, a dicing process for separating the semiconductor integrated circuit chips 102 one by one is performed. After the semiconductor integrated circuit chips 102 are separated one by one in the dicing process, a defect is detected in the wafer test process. The determined defective chip is discarded. On the other hand, non-defective chips determined as non-defective products in the wafer test process are shipped to the customer through an assembly process and a packing process called a second half process after the dicing process is completed.

  FIG. 10 shows a configuration of a general semiconductor integrated circuit chip 102. The semiconductor integrated circuit chip 103 has an internal circuit 104 and a plurality of pads 105 arranged around the internal circuit 104. The plurality of pads 105 are an input for inputting an electric signal to a power supply pad for supplying a power supply voltage for driving the internal circuit 104 of the semiconductor integrated circuit chip 102, a GND pad for supplying a ground potential, and the internal circuit. The pad is an output pad that outputs an electrical output signal of the internal circuit.

  In the inspection of the semiconductor integrated circuit chip 102 in the wafer test process, the probe card is in contact with the pad 105 of the semiconductor integrated circuit chip 102 to electrically connect the IC tester and the semiconductor integrated circuit chip 102 to be measured.

  When a functional test, which is an example of a test of the semiconductor integrated circuit chip 102, is performed, the IC tester supplies a power supply voltage and a ground potential to the measurement target semiconductor integrated circuit chip 102 via the probe card.

  Next, after inputting a test vector as an input signal to the semiconductor integrated circuit chip 102 to be measured, an output signal output from the semiconductor integrated circuit chip 102 is read. Then, by comparing the output signal of the semiconductor integrated circuit chip 102 with the expected value signal set in advance as to whether or not the output signal of the measurement target semiconductor integrated circuit chip 102 has the correct logic. The quality of the semiconductor integrated circuit chip 102 is determined.

  Next, the plan view of FIG. 11 and the cross-sectional view of FIG. 12 show an outline of a probe card used when the semiconductor integrated circuit chip 102 is tested in the wafer test process. Currently, a probe card having a structure called a cantilever system, which is the mainstream, has a circular probe card substrate 107, and a probe card reinforcing plate 108 is installed on the upper surface of the probe card substrate 107. A square frame spacer 111 is attached to the lower surface of the probe card substrate 107. The inside of this square frame-shaped spacer 111 forms an opening 109. A plurality of probe needles 110 made of metal needles are arranged along the four sides of the spacer 111. The plurality of probe needles 110 extend from the spacer 111 toward the opening 109. As shown in FIGS. 11 and 12, the tip of the probe needle 110 contacts each pad 105 of the semiconductor integrated circuit chip 102 to be measured. The probe card reinforcing plate 108 is for preventing the probe card substrate 107 from being deformed by the pressure generated when the probe needle 110 contacts each pad 105 of the semiconductor integrated circuit chip 102.

  When the semiconductor integrated circuit chip 102 to be measured has n pads 105, the probe card has a total of n probe needles such that one probe needle 110 contacts each pad 105. 110.

  In the inspection of the semiconductor integrated circuit chip 102 in the wafer test process, foreign matters such as pad scraps generated when the pads are scraped off when the probe needle 110 of the probe card contacts the pad 105 of the semiconductor integrated circuit chip 102 to be measured. There is a problem of sticking to the probe needle 110.

  If the foreign matter generated at this time adheres between the plurality of probe needles 110 during the test of the semiconductor integrated circuit chip 102 and the probe needles 110 are electrically short-circuited, the test of the semiconductor integrated circuit chip 102 cannot be performed normally. .

  In addition, since the tip of the probe needle 110 of the probe card repeatedly contacts the pad 105 of the semiconductor integrated circuit chip 102, a small amount of pad dust generated when the probe needle 110 contacts the pad 105 gradually accumulates on the probe needle 110. Is done. As a result, even when the insulating property of the probe needle 110 is increased due to the pad scrap deposits, the semiconductor integrated circuit chip 102 cannot be normally tested.

  Normally, when foreign matter such as pad scraps adheres to the probe needle 110 of the above-described probe card, brushing using a brush attached to a prober or polishing of the needle tip with a polishing sheet is performed, and the probe needle of the probe card is performed. The foreign matter that has adhered to the tip is removed. Alternatively, the probe card is removed from the prober, and the foreign matter attached to the probe needle 110 of the probe card is removed by performing manual cleaning using a brush. However, since it takes about 10 seconds to perform one brushing (or needle tip polishing), the brushing was performed every time the test of one semiconductor integrated circuit chip was performed. The throughput in the wafer test process is significantly reduced.

  The wafer test time for one semiconductor wafer varies depending on the category (type) of the semiconductor integrated circuit chip and the number of semiconductor integrated circuit chips formed on the semiconductor wafer, but usually requires about 1 hour of test execution time. Here, when 500 semiconductor integrated circuit chips are formed on one semiconductor wafer, and when brushing is executed for each test of one semiconductor integrated circuit chip, the wafer test of one semiconductor wafer is performed. In this case, the number of brushing executions is 500 times, and the brushing execution time is 500 times × 10 seconds = 5000 seconds (about 1 hour 23 minutes), and the wafer test time of one semiconductor wafer is approximately doubled.

  However, since actual brushing is executed with a frequency of about once or twice for a wafer test of one semiconductor wafer, the increase in wafer test time is slight. Also, if a foreign object adheres to the probe needle 110 of the probe card and the test cannot be performed normally (when there is a symptom that a defective product is continuously generated), an alarm is automatically generated and the wafer test is stopped. To do. The prober has this automatic stop function. When an alarm is generated by the prober, the operator at the production site executes brushing or needle tip polishing using a polishing sheet to remove foreign matter adhering to the probe needle 110.

  In the wafer test process, an alarm function of a prober when defective chips are continuously generated is used as a method for detecting foreign matter adhesion on the probe needle 110. For this reason, abnormality detection cannot be performed depending on the amount of foreign matter adhesion, such as when a defective chip is randomly generated or when the foreign matter attached to the probe needle is peeled off before the alarm is generated and the problem is recovered. In this case, the semiconductor integrated circuit chip that has been determined to be defective by the IC tester due to foreign matter adhesion is discarded as a defective product, resulting in a production loss.

  In order to prevent such a loss, there is a case where only a semiconductor integrated circuit chip determined to be defective every time a wafer test is completed is retested, which causes a reduction in throughput of the wafer test process. Also, only when foreign matter that cannot be removed by brushing adheres, the probe card is removed from the prober, and the operator at the production site performs manual cleaning with a brush to remove the foreign matter. When removing the probe card from the prober and removing foreign matter using a brush, it may take several hours, and the throughput of the wafer test process is greatly reduced.

  Deterioration of contact due to adhesion of foreign matter to the probe needle 110 is a major problem in the wafer test process, but when an aluminum electrode is used as the pad 105 of the semiconductor integrated circuit chip 102, the surface of the aluminum electrode pad is air. When the probe needle 110 of the probe card comes into contact with the pad 105 due to oxidation in the inside, the oxide film on the pad surface cannot be destroyed, and the contact resistance between the probe needle 110 and the pad 105 increases. . As described above, when the contact resistance becomes high, the signal from the IC tester cannot be normally supplied to the semiconductor integrated circuit chip 102 to be measured, so that the semiconductor integrated circuit chip cannot be tested.

  Therefore, in a wafer test of a semiconductor integrated circuit chip using an electrode pad made of aluminum, an alloy material containing tungsten (W) as a material of the probe needle 110 of the probe card for the purpose of destroying the oxide film on the pad surface. Is generally used. This tungsten (W) is inferior in conductivity without using an alloy material containing gold (Au), silver (Ag), copper (Cu) or palladium (Pd) having excellent conductivity, but has high hardness.

  When an alloy material containing tungsten is used as the material of the probe needle 110, there is a problem that the conductivity is deteriorated, and since the hardness is high, it is necessary to contact the pad with a high needle pressure. Therefore, the amount of pad scraps scraped off by the probe needle when the probe needle of the probe card contacts the pad of the semiconductor integrated circuit chip also increases. As described above, this causes a phenomenon in which pad scraps adhere to the probe card, and causes a decrease in the throughput of the wafer test process.

  Therefore, in Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-347565), in the wafer test process, when the probe needle of the probe card contacts the pad of the semiconductor integrated circuit chip, the surface oxide film of the aluminum electrode pad is destroyed, In addition, a method has been proposed in which the probe needle is brought into contact with the pad of the semiconductor integrated circuit chip to be measured without deteriorating the conductivity, and the adhesion of foreign matters such as pad scraps to the probe needle is reduced.

  In this prior art, as shown in the schematic diagram of FIG. 13, two probe needles 160 and 161 are simultaneously in contact with one pad 162 of a semiconductor integrated circuit chip to be measured. The two probe needles 160 and 161 are made of two different types of metal materials. That is, when the probe needle 161 comes into contact with the pad 162 of the semiconductor integrated circuit chip as a sword portion, the oxide film on the pad surface is scraped off, and at the same time, foreign matters such as pad scraps generated at that time are removed so as not to adhere to the probe needle 160. . The probe needle 160 is in contact with the pad surface obtained by removing the oxide film on the pad surface with the probe needle 161, and supplies power from the IC tester and inputs an input signal to the semiconductor integrated circuit chip to be measured. The probe needle 161 is manufactured by using an alloy material rhenium tungsten including tungsten which is a metal material having low conductivity but high hardness in order to scrape off the oxide film on the pad surface. On the other hand, the probe needle 161 is made of gold (Au), silver (Ag), copper (Cu), or palladium (Pd) having excellent conductivity for electrical connection between the IC tester and the pad 162 of the semiconductor integrated circuit chip. Is produced using an alloy material containing However, in this method, since the two probe needles 161 and 160 need to be brought into contact with one pad 162, a highly accurate probe card manufacturing technique is required and the manufacturing cost is increased. Therefore, it is not suitable for mass production of semiconductor integrated circuits that pursue low cost. Further, foreign matter such as pad scraps generated when the probe needle 161 comes into contact with the surface of the pad 162 of the semiconductor integrated circuit chip is scraped away in the direction opposite to the direction in which the probe needle 160 is installed. Although the frequency of foreign matter adhesion to 160 can be reduced, troubles due to foreign matter adhesion cannot be completely prevented.

  Thus, in the conventional semiconductor integrated circuit chip wafer test probe card, foreign matter such as pad scraps generated when the probe needle of the probe card contacts the pad of the semiconductor integrated circuit chip adheres to the probe needle. There is a problem that the test cannot be performed normally.

  In addition, with respect to the problem of foreign matter adhering to the probe needle, it is possible to remove the adhering foreign matter by performing brushing or polishing the tip of the needle with an abrasive sheet, but these methods are used in the wafer test process. Reduce throughput. Further, when the needle tip is polished, the probe needle is worn by the needle tip polishing, and the life of the probe card is reduced. In addition, if the prober's alarm function cannot detect an abnormality due to the adhesion of foreign matter, a non-defective product is judged as defective, resulting in a production yield loss. In addition, the foreign substance removal work using the brush manually reduces the wafer test efficiency significantly.

  In the case of a probe card using an alloy material containing gold (Au), silver (Ag), copper (Cu) or palladium (Pd) having excellent conductivity as the probe needle material, the surface of the aluminum electrode pad is used. Since the oxide film cannot be destroyed, the test cannot be performed normally.

On the other hand, if a hard alloy material containing tungsten is used to destroy the surface oxide film of the aluminum electrode pad, the conductivity deteriorates and the hardness is high, so the probe needle and the semiconductor integrated circuit chip to be measured As the pad scraps scraped off by the probe needle increase when the pad contacts, there is a problem that contact abnormality due to foreign matter adhering to the probe needle is likely to occur.
JP 2004-347565 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a probe card that can realize normal test measurement of a semiconductor integrated circuit chip while preventing contact failure of a probe needle and can efficiently perform test measurement.

In order to solve the above problems, a probe card according to the present invention includes a first probe unit having a first probe needle that contacts a pad of a semiconductor integrated circuit chip;
When the first probe needle is in contact with the pad of the semiconductor integrated circuit chip, one or more semiconductor integrated circuit chips are adjacent to the semiconductor integrated circuit chip or connected to the semiconductor integrated circuit chip. A second probe portion having a second probe needle that contacts a pad of the sandwiched semiconductor integrated circuit chip,
The first probe needle is made of a first metal material;
The second probe needle is made of a second metal material;
The conductivity of the first metal material is higher than the conductivity of the second metal material,
The second metal material is characterized in that the hardness of the second metal material is higher than the hardness of the first metal material.

  According to the probe card of the present invention, first, the second probe needle made of the second metal material having higher hardness than the first metal material is brought into contact with the pad of the semiconductor integrated circuit chip to be measured. Thus, the oxide film on the pad surface is destroyed.

  Thereafter, the probe card is moved in the arrangement direction of the semiconductor integrated circuit on the wafer, and the first probe needle made of the first metal material having higher conductivity than the second metal material is moved to the semiconductor integrated circuit. Touch the chip pad. Therefore, the first probe needle can be brought into contact with the pad of the semiconductor integrated circuit chip with good conductivity. Therefore, it is possible to minimize the occurrence of a problem that a normal test by the IC tester cannot be performed.

  Moreover, the foreign material scraped off from the pad by the second probe needle adheres to the second probe portion. In addition, since the oxide film on the pad surface is broken by the second probe needle, the first probe portion can be electrically connected to the pad even if it is brought into contact with the pad at a low needle pressure. Therefore, the amount of foreign matter such as pad scraps scraped off by the first probe needle can be reduced. Therefore, it is possible to minimize the probability that foreign matter adheres to the first probe needle when the first probe portion contacts the pad.

  Therefore, good power supply and signal transmission can be performed between the IC tester and the semiconductor integrated circuit chip to be measured. Therefore, the throughput in the wafer test process can be improved.

  Therefore, according to the probe card of the present invention, it is possible to realize a probe card capable of preventing normal contact of the probe needle caused by pad scraps and realizing normal test measurement of the semiconductor integrated circuit chip and efficiently performing test measurement.

In one embodiment, the probe card includes a semiconductor integrated circuit chip in which the first probe needle is in contact with the pad when the first probe needle is in contact with the pad of the semiconductor integrated circuit chip; One semiconductor integrated circuit exists between the semiconductor integrated circuit chip in which the second probe needle is in contact with the pad,
Foreign matter adsorption contacting the one semiconductor integrated circuit between the semiconductor integrated circuit chip in which the first probe needle is in contact with the pad and the semiconductor integrated circuit chip in which the second probe needle is in contact with the pad A member was provided.

  According to the probe card of this embodiment, first, the second probe needle made of the second metal material having a hardness higher than that of the first metal material is brought into contact with the pad of the semiconductor integrated circuit chip to be measured. As a result, the oxide film on the pad surface is destroyed.

  Next, the probe card is moved in the arrangement direction of the semiconductor integrated circuits on the wafer, and the foreign substance adsorbing member is made to face the semiconductor integrated circuit chip with which the second probe needle is in contact. The foreign matter adsorbing member is not attached to the second probe portion among foreign matters such as pad scraps generated when the second probe needle of the second probe portion contacts the pad of the semiconductor integrated circuit chip. Adsorbs foreign matter scattered on the surface of the surface. Thereby, foreign matters such as pad scraps generated when the second probe needle of the second probe portion contacts the pad of the semiconductor integrated circuit chip can be completely removed from the semiconductor integrated circuit chip. The foreign matter removing member is made of, for example, an elastic adhesive sheet or adhesive rubber.

  In one embodiment of the probe card, the first metal material is gold (Au), silver (Ag), copper (Cu), or palladium (Pd).

  According to the probe card of this embodiment, the conductivity of the first metal material is particularly high, the conductivity of the first probe needle made of the first metal material is particularly high, and the semiconductor to be measured Electrically stable contact is obtained with the pads of the integrated circuit chip.

  The probe card according to an embodiment includes an alloy material containing a plurality of metals selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd) as the first metal material. It was.

  In the probe card of this embodiment, the conductivity of the first metal material is particularly high, and the conductivity of the first probe needle made of the first metal material is particularly high, so that the semiconductor integrated circuit to be measured Electrically stable contact is obtained with the pads of the chip.

  In one embodiment of the probe card, the second metal material is tungsten (W).

  In the probe card of this embodiment, the second probe needle made of the second metal material can be made particularly hard, and the oxide film on the pad surface can be destroyed efficiently.

  In one embodiment of the probe card, the second metal material is an alloy material containing tungsten (W).

  In the probe card of this embodiment, the second probe needle made of the second metal material can be made particularly hard, and the oxide film on the pad surface can be destroyed efficiently.

  Moreover, the probe card of one Embodiment made the said foreign material adsorption | suction member the elastic adhesive sheet.

  In the probe card of this embodiment, foreign matter such as pad scraps on the semiconductor integrated circuit chip can be removed almost completely without damaging the semiconductor integrated circuit chip by a foreign matter adsorbing member made of an elastic adhesive sheet.

  In one embodiment of the probe card, the foreign material removing member is made of an elastic adhesive rubber.

  In the probe card of this embodiment, foreign matter such as pad scraps on the semiconductor integrated circuit chip can be removed almost completely without damaging the semiconductor integrated circuit chip by the foreign matter adsorbing member made of elastic adhesive rubber.

  In one embodiment of the semiconductor integrated circuit testing method, a wafer test of a semiconductor integrated circuit chip is performed using the probe card.

  According to the test method of the semiconductor integrated circuit of this embodiment, it is possible to prevent the contact failure of the probe needle due to the pad scraps and realize the normal test measurement of the semiconductor integrated circuit chip and perform the test measurement efficiently.

  According to the probe card of the present invention, an electrically stable contact is obtained between the first probe needle of the probe card and the pad of the semiconductor integrated circuit chip to be measured, and foreign matter adheres to the first probe needle. It can be greatly reduced. Thereby, the throughput in the wafer test process can be improved. Further, it is possible to avoid a contact abnormality between the pad and the first probe needle, and to reduce yield loss in the wafer test process such as determining a defective chip as defective.

  In addition, since it is not necessary to perform needle tip polishing using an abrasive sheet, probe needle wear due to needle tip polishing does not occur, prolonging the life of the probe card, and reducing the cost of the probe card it can.

  Therefore, by using the probe card of the present invention, it becomes possible to improve the throughput of the wafer test process of the semiconductor integrated circuit chip, and it becomes possible to reduce the yield loss and the probe card cost in the wafer test process, The manufacturing cost of the semiconductor integrated circuit can be reduced.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 shows a state in which the probe card 1 according to the first embodiment of the present invention is in contact with the pads 31A and 32A of two adjacent semiconductor integrated circuit chips 31 and 32 as viewed from above. Show. FIG. 2 shows a cross section taken along the line AA in FIG. In FIGS. 1 and 2, only two adjacent ones of a plurality of semiconductor integrated circuit chips formed on the wafer are shown.

  As shown in FIG. 1, each of the semiconductor integrated circuit chips 31 and 32 has n pads 31A to 31D and 32A to 32D arranged along four sides.

  On the other hand, as shown in FIGS. 1 and 2, the probe card 1 is attached along the edge of the opening 20A on the probe card board 20 having a substantially square opening 20A in the center and on the upper surface of the probe card board 20. And a substantially square frame-like probe card reinforcing plate 21. The probe card reinforcing plate 21 is a pressure generated when first and second probe needles 29a to 29d and 30a to 30d, which will be described later, contact the pads 31A to 31D and 32A to 32D of the semiconductor integrated circuit chips 31, 32. This prevents the probe card substrate 20 from being deformed.

  As shown in FIG. 2, spacers 25 and 26 are attached to the lower surface of the probe card substrate 20 along two opposite sides of the edge of the opening 20A. Although not shown in FIG. 2, as shown in FIG. 1, two spacers 27, similar to the spacers 25, 26 are formed on the lower surface of the probe card substrate 20 along the remaining two opposite sides of the opening 20A. 28 is attached. The opening 20 </ b> A of the substrate 20, the reinforcing plate 21, and the four spacers 25 to 28 constitute the opening 1 </ b> A of the probe card 1.

  The probe card 1 is arranged along one side of the opening 1A and a plurality of first probe needles 29a and 29c protruding from the peripheral portion 1B of the probe card 1 through the spacer 25 and projecting into the opening 1A. Have As shown in FIG. 1, the plurality of first probe needles 29 a are in contact with pads 31 </ b> A arranged along one side of the semiconductor integrated circuit chip 31. Each of the plurality of first probe needles 29c is in contact with a pad 31C arranged along one side facing the one side.

  Further, as shown in FIG. 1, the probe card 1 is arranged along two opposing sides of the opening 1A, and penetrates the spacers 27 and 28 from the peripheral portion 1B of the probe card 1 so as to open the opening. A plurality of first probe needles 29b and 29d protruding to 1A are provided. The plurality of first probe needles 29b and 29d are in contact with pads 31B and 31D arranged along two opposing sides of the semiconductor integrated circuit chip 31, respectively. The first probe needles 29a to 29d constitute a first probe portion.

  As shown in FIGS. 1 and 2, the probe card 1 is arranged along one side of the opening 1A and protrudes from the peripheral portion 1B of the probe card 1 through the spacer 26 to the opening 1A. And a plurality of second probe needles 30a and 30c. As shown in FIG. 1, the plurality of second probe needles 30 a are in contact with pads 32 </ b> A arranged along one side of the semiconductor integrated circuit chip 32. The plurality of second probe needles 30c are in contact with the pads 32C arranged along one side facing the one side.

  As shown in FIG. 1, the probe card 1 is arranged along two opposing sides of the opening 1A and protrudes from the peripheral portion 1B of the probe card 1 through the spacer 27 to the opening 1A. A plurality of second probe needles 30b and 30d. The plurality of second probe needles 30b and 30d are in contact with pads 32B and 32D arranged along two opposing sides of the semiconductor integrated circuit chip 32, respectively. The second probe needles 30a to 30d constitute a second probe portion.

  The first probe needles 29a to 29d are made of a first metal material selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd). The first metal material for producing the first probe needles 29a to 29d contains a plurality of metals selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd). An alloy material may be used.

  The second probe needles 30a to 30d were made of a second metal material having a hardness higher than that of the first metal material. For example, the second metal material is an alloy material containing tungsten (W). The second metal material may be tungsten (W). In short, the second metal material may be a material having a higher hardness than the first metal material, and the first metal material is a material having a higher conductivity than the first metal material. I just need it.

  A procedure for testing a semiconductor wafer in which a plurality of semiconductor integrated circuit chips similar to the semiconductor integrated circuit chips 31 and 32 are formed using the probe card 1 having the above-described configuration is shown in the flowchart of FIG. This will be described with reference to the wafer map.

  Note that the probe card 1 is fixed to a prober (not shown), and the probe card 1 is moved relative to the wafer 59 by moving the wafer stage on which the wafer 59 is placed in the prober. .

  When performing a wafer test on one semiconductor wafer 59, in step S1, the wafer stage is moved to move the wafer 59 relative to the probe card 1, and the probe card 1 is moved to the wafer 59 in the wafer map of FIG. Are moved to the row in which the semiconductor integrated circuit chips “1” to “4” in the uppermost row are arranged. The numbers in “” indicate the order in which the tests are performed.

  Next, proceeding to step S2, the wafer stage is moved, the probe card 1 is moved to the left in the wafer map of FIG. 6 with respect to the wafer 59, and the second probe needles 30a to 30d are moved. The leftmost semiconductor integrated circuit chip “1” (or “5”, “13”, “23”...) Is positioned to face each pad.

  In step S2, the second probe needles 30a to 30d are brought into contact with the pads of the leftmost semiconductor integrated circuit chip “1” (or “5”, “13”, “23”. The oxide film formed in the air on the pad surface of the semiconductor integrated circuit chip is destroyed. At that time, foreign matter such as pad scraps scraped off by the second probe needles 30a to 30d adheres to the second probe portion or is scattered to a position where there is no pad on the chip.

  At this time, the first probe needles 29a to 29d are in contact with a portion on the semiconductor wafer where the semiconductor integrated circuit chip is not formed.

  In step S3, the wafer stage is moved leftward in FIG. 6 to move the wafer 59 relative to the probe card 1 in the leftward direction by one pitch of the horizontal array of semiconductor integrated circuit chips. . As a result, the probe card 1 moves the measurement position with respect to the wafer 59 to the right by the one pitch in FIG. As a result, the second probe needles 30a to 30d of the probe card 1 contact each pad of the semiconductor integrated circuit chip “1 + i” (or “5 + i”, “13 + i”, “23 + i”...) In the wafer map of FIG. To do. Here, i represents the number of executions of step S3 in each row, and is the number of movements of the measurement position of the probe card 1 in each row in the right direction. For example, in the first line, when the execution of step S3 is the first time and the number of times of movement in the right direction is the first time, the above “1 + i” is “1 + 1”, so “2” in the wafer map of FIG. Represents.

  Accordingly, in this step S3, the second probe needles 30a to 30d of the probe card 1 are placed on the respective pads of the semiconductor integrated circuit chip indicated by reference numerals “1 + i” (or “5 + i”, “13 + i”, “23 + i”...) In FIG. The oxide film on each pad surface of the semiconductor integrated circuit chip “1 + i” (or “5 + i”, “13 + i”, “23 + i”...) Is destroyed.

  On the other hand, the first probe needles 29a to 29d are in contact with the pads of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) In the wafer map of FIG. Since each pad of the semiconductor integrated circuit chip of the symbol “i” (or “4 + i”, “12 + i”, “22 + i”...) Has a surface oxide film destroyed by the second probe needles 30a to 30d, The first probe needles 29a to 29d can be brought into contact with the pads of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) With high conductivity. Therefore, it is possible to minimize the occurrence of a problem that a normal test by the IC tester cannot be performed.

  In addition, the foreign matter scraped from each pad of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) By the second probe needles 30a to 30d is second probe needles 30a to 30d. It adheres to 30d. Further, the oxide films on the pad surfaces of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) Are destroyed by the second probe needles 30a to 30d. In addition, since the constituent material of the first probe needles 29a to 29d is low in hardness, the first probe needles 29a to 29d are connected to the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “ 22 + i ”...)) Can be electrically connected to the pads even if they are brought into contact with each pad at a low needle pressure. Accordingly, the amount of foreign matter such as pad scraps scraped off by the first probe needles 29a to 29d can be reduced.

  Also, the lengths of the tip portions 29a-1 to 29d-1 of the first probe needles 29a to 29d are longer than the lengths of the tip portions 30a-1 to 30d-1 of the second probe needles 30a to 30d of FIGS. When the length is set to be shorter by about 5 μm to 10 μm, it is possible to further reduce the generation amount of foreign matters such as pad scraps generated when the first probe unit contacts the pads of the semiconductor integrated circuit chip.

  Therefore, when the first probe needles 29a to 29d come into contact with the pads of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...), Foreign matter adheres to the first probe needles 29a to 29d. The probability of doing can be minimized.

  Therefore, in this step S3, the first probe needles 29a to 29d can be brought into electrical stable contact with good conductivity to each pad of the semiconductor integrated circuit chip.

  In the next step S4, the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) Is measured from the IC tester via the first probe needles 29a to 29d of the probe card 1. A power supply voltage and a ground potential for driving the internal circuit of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) Are supplied. An electrical signal is input from the IC tester to the internal circuit of the semiconductor integrated circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”... A signal is output from the internal circuit of the circuit chip “i” (or “4 + i”, “12 + i”, “22 + i”...) To the IC tester, and an electrical test is performed.

  According to the probe card 1, since the signal can be transmitted satisfactorily, the throughput in the wafer test process can be improved. That is, according to this probe card 1, normal test measurement of the semiconductor integrated circuit chip can be realized in an electrically stable state by preventing contact failure of the probe needles 29a to 29d caused by pad scraps, and at the same time, efficient test measurement. Can be done.

  Next, the process proceeds to step S5, where the semiconductor integrated circuit chips that are in contact with the first probe needles 29a to 29d of the probe card 1 are the semiconductor integrated circuit chips “4” and “12” at the right end in the wafer map of FIG. .., “22”..., And if it is confirmed that it is the rightmost semiconductor integrated circuit chip, the process proceeds to the next step S6. On the other hand, if it is confirmed in step S5 that the semiconductor integrated circuit chip with which the first probe needles 29a to 29d are in contact is not the rightmost semiconductor integrated circuit chip, the process returns to step S3.

  In step S6, the wafer stage is driven to move the position of the probe card 1 relative to the wafer 59 downward by one pitch of the vertical arrangement of the semiconductor integrated circuit chips in FIG.

  Next, the process proceeds to step S7, where it is confirmed whether or not the measurement target semiconductor integrated circuit exists in the moved row. If it exists, the process returns to step S2, and if it does not exist, the wafer test is terminated. To do.

  In the probe card 1 of the first embodiment, the first probe needles 29a to 29d are arranged on the left side and the second probe needles 30a to 30d are arranged on the right side in FIG. One probe needle 29a to 29d may be disposed on the right side, and the second probe needles 30a to 30d may be disposed on the left side. In this case, the execution order of the wafer test of the semiconductor integrated circuit chips formed in one wafer starts from the semiconductor integrated circuit chip formed at the right end in FIG. 6, all the semiconductor integrated circuit chips formed on the semiconductor wafer are tested while moving leftward in FIG. 6.

  Further, in FIG. 1, the first probe needles 29a to 29d are arranged on the upper side in the opening 1A of the probe card 1, and the second probe needles 30a to 30d are arranged on the lower side in the opening 1A. Good. That is, in FIG. 1, the probe card 1 may be rotated clockwise by 90 °. In this case, the wafer test can be performed in the order shown in the wafer map of FIG. That is, in the wafer 55 shown in FIG. 5, the semiconductor integrated circuit chips “2”, “1” formed sequentially on the right side from the semiconductor integrated circuit chip “1” located at the upper left (the semiconductor integrated circuit chip to be tested first). 3 ”and“ 4 ”will be tested (right index). Then, after the test of the rightmost semiconductor integrated circuit chip “4” (the fourth semiconductor integrated circuit chip to be tested) is completed, the rightmost semiconductor integrated circuit chip “5” (the fifth lowermost) The semiconductor integrated circuit chips to be tested are tested, and the semiconductor integrated circuit chips “6”, “7”... Formed on the left side are sequentially tested (left index). In this manner, all the semiconductor integrated circuit chips formed on the semiconductor wafer are sequentially tested while alternately repeating the right index and the left index. Since the probe card is fixed to the prober, the semiconductor integrated circuit chip is brought into contact with the probe card by moving the wafer stage to an arbitrary position by moving the wafer stage on which the wafer is placed in the prober. Has been replaced.

  In short, the first probe needles 29a to 29d are brought into contact with the pads of the semiconductor integrated circuit chip to be tested in the wafer test after the second probe needles 30a to 30d are brought into contact with each other, as described above. Electrically stable contact is obtained between the first probe needles 29a to 29d and each pad of the semiconductor integrated circuit chip to be measured, and an electrical test by a tester can be normally performed.

(Second embodiment)
Next, FIG. 3 shows a second embodiment of a probe card for wafer test of a semiconductor integrated circuit chip according to the present invention. FIG. 3 shows a state in which the probe card 72 is in contact with three adjacent semiconductor integrated circuit chips 49, 50, 51 when viewed from above. FIG. 4 shows a cross section taken along the line AA of FIG. 3 and 4, only three adjacent ones of a plurality of semiconductor integrated circuit chips formed on the wafer are shown.

  As shown in FIG. 3, the semiconductor integrated circuit chips 49 and 51 have n pads 49 </ b> A to 49 </ b> D and 51 </ b> A to 51 </ b> D arranged along the four sides. Similarly to the semiconductor integrated circuit chips 49 and 51, the semiconductor integrated circuit chip 50 also has n pads arranged along the four sides.

  On the other hand, as shown in FIGS. 3 and 4, the probe card 72 is attached along the edge of the opening 45A on the upper surface of the probe card board 45 and a probe card board 45 having a substantially square opening 45A in the center. And a substantially square frame-shaped probe card reinforcing plate 44. The probe card reinforcing plate 44 is a pressure generated when first and second probe needles 46a to 46d and 47a to 47d described later contact the pads 49A to 49D and 51A to 51D of the semiconductor integrated circuit chips 49 and 51, respectively. This prevents the probe card substrate 45 from being deformed.

  As shown in FIG. 4, spacers 42 and 43 are attached to the lower surface of the substrate 45 along two opposing sides of the edge of the opening 45A. Although not shown in FIG. 4, as shown in FIG. 3, two spacers 52, similar to the spacers 42, 43, are provided on the lower surface of the probe card substrate 45 along the remaining two opposite sides of the opening 45A. 53 is attached. The opening 45A of the probe card substrate 45, the reinforcing plate 44, and the four spacers 42, 43, 52, 53 constitute the opening 72A of the probe card 72.

  The probe card 72 is arranged along one side of the opening 72A, penetrates the spacer 42 from the peripheral portion 45B of the probe card substrate 45, and protrudes into the opening 72A. 46c. As shown in FIG. 3, the plurality of first probe needles 46 a are in contact with pads 49 </ b> A arranged along one side of the semiconductor integrated circuit chip 49. Each of the plurality of first probe needles 46c is in contact with a pad 49C arranged along one side facing the one side.

  Further, as shown in FIG. 3, the probe card 72 is arranged along two opposing sides of the opening 72A, and penetrates the spacers 52 and 53 from the peripheral portion 72B of the probe card 72, thereby opening the opening. A plurality of first probe needles 46b and 46d projecting to 72A are provided. The plurality of first probe needles 46b and 46d are in contact with pads 49B and 49D arranged along two opposing sides of the semiconductor integrated circuit chip 49, respectively. The first probe needles 46a to 46d constitute a first probe portion.

  As shown in FIGS. 3 and 4, the probe card 72 is arranged along one side of the opening 72A and protrudes from the peripheral portion 72B of the probe card 72 through the spacer 43 to the opening 72A. A plurality of second probe needles 47a and 47c. As shown in FIG. 3, the plurality of second probe needles 47 a are in contact with pads 51 </ b> A arranged along one side of the semiconductor integrated circuit chip 51. The plurality of second probe needles 47c are in contact with the pads 51C arranged along one side facing the one side.

  Further, as shown in FIG. 3, the probe card 72 is arranged along two opposing sides of the opening 72A and protrudes from the peripheral portion 72B of the probe card 72 through the spacer 43 to the opening 72A. And a plurality of second probe needles 47b and 47d. The plurality of second probe needles 47b and 47d are in contact with pads 51B and 51D arranged along two opposing sides of the semiconductor integrated circuit chip 51, respectively. The second probe needles 47a to 47d constitute a second probe portion.

  The first probe needles 46a to 46d are made of a first metal material selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd). The first metal material for producing the first probe needles 46a to 46d contains a plurality of metals selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd). An alloy material may be used.

  Further, the second probe needles 47a to 47d were made of a second metal material having a hardness higher than that of the first metal material. For example, the second metal material is an alloy material containing tungsten (W). The second metal material may be tungsten (W). In short, the second metal material may be a material having a higher hardness than the first metal material, and the first metal material is a material having higher conductivity than the first metal material. I just need it. Furthermore, the second embodiment includes a foreign matter adsorbing member 48 disposed between the first probe portion and the second probe portion. The foreign matter adsorbing member 48 is attached to the probe card substrate 45 and has a substantially rectangular parallelepiped shape as shown in FIGS. 3 and 4 and is located between the semiconductor integrated circuit chips 49 and 51. Contact 50 surfaces. The foreign matter adsorbing member 48 is made of an elastic adhesive sheet or adhesive rubber. The foreign material adsorbing member 48 adsorbs foreign materials such as pad scraps attached to the surface of the semiconductor integrated circuit chip 50. The foreign material adsorbing member 48 is not limited to an adhesive sheet or an adhesive rubber, and may be made of another adhesive material.

  A procedure for testing a semiconductor wafer in which a plurality of semiconductor integrated circuit chips similar to the semiconductor integrated circuit chips 49, 50, 51 are built using the probe card 72 having the above-described configuration is shown in the flowchart and FIG. 6 will be described with reference to the wafer map 6. The probe card 72 is fixed to a prober (not shown), and the probe card 72 is moved relative to the wafer 59 by moving the wafer stage on which the wafer 59 is placed in the prober. .

  When performing a wafer test on one semiconductor wafer 59, in step S11, the wafer stage is moved to move the wafer 59 relative to the probe card 72, and the probe card 72 is moved to the wafer 59 on the wafer map of FIG. Are moved to the row in which the semiconductor integrated circuit chips “1” to “4” in the uppermost row are arranged. The numbers in “” indicate the order in which the tests are performed.

  Next, proceeding to step S12, the wafer stage is moved, the probe card 72 is moved leftward in the wafer map of FIG. 6 with respect to the wafer 59, and the second probe needles 47a to 47d are moved. The leftmost semiconductor integrated circuit chip “1” (or “5”, “13”, “23”...) Is positioned to face each pad.

  In this step S12, the second probe needles 47a to 47d are brought into contact with the pads of the leftmost semiconductor integrated circuit chip “1” (or “5”, “13”, “23”. The oxide film on the pad surface of the semiconductor integrated circuit chip is destroyed. At that time, foreign matters such as pad scraps scraped by contact between the second probe needles 47a to 47d of the probe card 72 and the pad are scattered on the second probe portion or scattered to a position where no pad exists on the chip.

  At this time, the first probe needles 46 a to 46 d and the foreign matter adsorbing member 48 come into contact with a portion on the semiconductor wafer 59 where the semiconductor integrated circuit chip is not formed.

  Next, the process proceeds to step S13, and in FIG. 6, the wafer stage is moved leftward to move the wafer 59 relative to the probe card 72 in the leftward direction by one pitch of the horizontal array of semiconductor integrated circuit chips. . As a result, the probe card 72 moves the measurement position relative to the wafer 59 to the right by the one pitch in FIG. As a result, the second probe needles 47a to 47d of the probe card 72 contact each pad of the semiconductor integrated circuit chip “2” (or “6”, “14”, “24”...) In the wafer map of FIG. Then, the oxide film formed in the air on the surface of each pad is destroyed.

  On the other hand, the foreign matter adsorbing member 48 contacts each pad of the semiconductor integrated circuit chip “1” (or “5”, “13”, “23”...) In the wafer map of FIG. Each pad of the semiconductor integrated circuit chip denoted by reference numeral “1” (or “5”, “13”, “23”...) Has its surface oxide film destroyed by the second probe needles 47a to 47d. The foreign matter adsorbing member 48 remains on the surface of the semiconductor integrated circuit chip “1” (or “5”, “13”, “23”...) Without being attached to the second probe needles 47a to 47d and scattered pad scraps. Adsorb foreign matter such as Thereby, the foreign matter on the surface of the semiconductor integrated circuit chip “1” (or “5”, “13”, “23”...) Can be almost completely removed. In this step S <b> 13, the first probe needles 46 a to 46 d come into contact with a portion on the semiconductor wafer 59 where no semiconductor integrated circuit chip is formed.

  In step S14, the wafer stage is moved leftward in FIG. 6 to move the wafer 59 relative to the probe card 72 in the leftward direction by one pitch of the horizontal array of semiconductor integrated circuit chips. . As a result, the probe card 72 moves the measurement position relative to the wafer 59 to the right by the one pitch in FIG. Accordingly, the second probe needles 47a to 47d of the probe card 72 contact each pad of the semiconductor integrated circuit chip “2 + j” (or “6 + j”, “14 + j”, “24 + j”...) In the wafer map of FIG. Then, the oxide film on the surface of each pad is destroyed. Here, j represents the number of executions of step S14 in each row, and is the number of times the measurement position of the probe card 72 in each row is moved to the right. For example, when the execution of step S14 is the first time in the first row and the number of times of movement in the right direction is the second time, “2 + j” is “2 + 1”, so “3” in the wafer map of FIG. Represents.

  On the other hand, the foreign matter adsorbing member 48 contacts each pad of the semiconductor integrated circuit chip “1 + j” (or “5 + j”, “13 + j”, “23 + j”...) In the wafer map of FIG. The surface oxide film of each pad of the semiconductor integrated circuit chip of the symbol “1 + j” (or “5 + j”, “13 + j”, “23 + j”...) Is destroyed by the second probe needles 47a to 47d. The foreign matter adsorbing member 48 is left on the surface of the semiconductor integrated circuit chip “1 + j” (or “5 + j”, “13 + j”, “23 + j”...)) Without being attached to the second probe needles 47a to 47d and scattered pad scraps Adsorb foreign matter such as Thereby, the foreign matter on the surface of the semiconductor integrated circuit chip “1 + j” (or “5 + j”, “13 + j”, “23 + j”...) Can be removed almost completely.

  In step S14, the first probe needles 46a to 46d are in contact with the pads of the semiconductor integrated circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”...). Each pad of the semiconductor integrated circuit chip of the symbol “j” (or “4 + j”, “12 + j”, “22 + j”...) Has its surface oxidized film destroyed by the second probe needles 47a to 47d, and foreign matter is adsorbed. Residual foreign matter such as pad scraps on the surface is removed almost completely by the member 48.

  In addition, since the material of the first probe needles 46a to 46d has a low hardness, the first probe portion can be brought into contact with each pad with a low needle pressure, and the pad generated when contacting the pad of the semiconductor integrated circuit chip. There is little generation of foreign matter such as scrap. Further, compared with the lengths of the tip portions 47a-1 to 47d-1 of the second probe needles 47a to 47d in FIGS. 3 and 4, the tip portions 46a-1 to 46d-1 of the first probe needles 46a to 46d-1 are compared. When the length is set to be shorter by about 5 μm to 10 μm, it is possible to further reduce the generation amount of foreign matters such as pad scraps generated when the first probe unit contacts the pads of the semiconductor integrated circuit chip. Therefore, foreign matter adhesion to the first probe portion can be reduced to a minimum.

  Therefore, in this step S14, the first probe needles 46a to 46d are electrically stable on the pads of the semiconductor integrated circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”...). Good contact. Therefore, it is possible to minimize the occurrence of a problem that a normal test by the IC tester cannot be performed.

  In step S15, the semiconductor integrated circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”) is measured from the IC tester via the first probe needles 46a to 46d of the probe card 72. ..) Is supplied with a power supply voltage and a ground potential for driving the internal circuit of the semiconductor integrated circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”...). Then, an electrical signal is input from the IC tester to the internal circuit of the semiconductor integrated circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”... A signal is output from the internal circuit of the circuit chip “j” (or “4 + j”, “12 + j”, “22 + j”...) To the IC tester, and an electrical test is performed.

  According to the probe card 72, the signal can be transmitted satisfactorily, so that the throughput in the wafer test process can be improved. That is, according to this probe card 72, it is possible to realize normal test measurement of the semiconductor integrated circuit chip in an electrically stable state by preventing contact failure of the first probe needles 46a to 46d caused by pad scraps, and also efficiently test. Can measure.

  Next, the process proceeds to step S16, and the semiconductor integrated circuit chip in contact with the first probe needles 46a to 46d of the probe card 72 is the rightmost semiconductor integrated circuit chip "4", "12" in the wafer map of FIG. , “22”..., And if it is confirmed that it is the rightmost semiconductor integrated circuit chip, the process proceeds to the next step S17. On the other hand, if it is confirmed in step S16 that the semiconductor integrated circuit chip in contact with the first probe needles 46a to 46d is not the rightmost semiconductor integrated circuit chip, the process returns to step S14.

  In step S17, the wafer stage is driven to move the position of the probe card 72 relative to the wafer 59 downward by one pitch of the vertical arrangement of the semiconductor integrated circuit chips in FIG.

  Next, the process proceeds to step S18, where it is confirmed whether or not the semiconductor integrated circuit to be measured exists in the moved row. If it exists, the process returns to step S12, and if it does not exist, the wafer test is terminated. To do.

  In the probe card 72 of the second embodiment, in FIG. 3, the first probe needles 46a to 46d are arranged on the left side and the second probe needles 47a to 47d are arranged on the right side. The first probe needles 46a to 46d may be arranged on the right side, and the second probe needles 47a to 47d may be arranged on the left side. In this case, the wafer test execution order of the semiconductor integrated circuit chips formed in one wafer starts from the semiconductor integrated circuit chip formed at the right end in FIG. 6, all the semiconductor integrated circuit chips formed on the semiconductor wafer are tested while moving leftward (leftward index) in FIG. 6.

  Further, in FIG. 3, the first probe needles 46a to 46d are arranged above the opening 72A of the probe card 72, and the second probe needles 47a to 47d are arranged below the opening 72A. Good. That is, in FIG. 3, the probe card 72 may be rotated 90 ° clockwise. In this case, the wafer test can be performed in the order shown in the wafer map of FIG. That is, in FIG. 5, the semiconductor integrated circuit chips “2”, “3”, “1” formed sequentially on the right side from the semiconductor integrated circuit chip “1” located at the upper left (the semiconductor integrated circuit chip to be tested first). 4 ”(right index). Then, after the test of the rightmost semiconductor integrated circuit chip “4” (the fourth semiconductor integrated circuit chip to be tested) is completed, the rightmost semiconductor integrated circuit chip “5” (the fifth lowermost) The semiconductor integrated circuit chips to be tested are tested, and the semiconductor integrated circuit chips “6”, “7”... Formed on the left side are sequentially tested (left index). In this manner, all the semiconductor integrated circuit chips formed on the semiconductor wafer are sequentially tested while alternately repeating the right index and the left index. Since the probe card is fixed to the prober, the semiconductor integrated circuit chip is brought into contact with the probe card by moving the wafer stage to an arbitrary position by moving the wafer stage on which the wafer is placed in the prober. Has been replaced.

  The point is that the foreign substance adsorbing member 48 and the first probe needles 46a to 46d are sequentially brought into contact with the pads of the semiconductor integrated circuit chip to be tested in the wafer test after the second probe needles 47a to 47d are in contact with each other. Thus, as described above, an electrically stable contact is obtained between the first probe needles 46a to 46d and the pads of the semiconductor integrated circuit chip to be measured, and the electrical test by the tester is normally performed. Is possible.

It is a top view of 1st Embodiment of the probe card of this invention. It is AA sectional drawing of FIG. It is a top view of 2nd Embodiment of the probe card of this invention. It is AA sectional drawing of FIG. It is the schematic which showed typically an example of the order of the general chip | tip measurement in the case of implementing a wafer test using a probe card. It is the schematic which showed typically an example of the order of the general chip | tip measurement in the case of implementing a wafer test using the probe card of 1st, 2nd embodiment of this invention. It is a flowchart which shows an example of the procedure which implements a wafer test using the probe card of 1st Embodiment of this invention. It is a flowchart which shows an example of the procedure which implements a wafer test using the probe card of 2nd Embodiment of this invention. 1 is a schematic view of a semiconductor wafer having a plurality of semiconductor integrated circuit chips. It is a figure which shows the structure of a general semiconductor integrated circuit chip. It is a top view which shows the outline of the conventional probe card. It is AA sectional drawing of FIG. It is a partial schematic diagram which shows the part of the probe needle of another conventional probe card.

Explanation of symbols

1, 72 Probe cards 29a-29d, 46a-46d First probe needles 30a-30d, 47a-47d Second probe needles 31, 32, 49, 50, 51 Semiconductor integrated circuit chips 31A-31D, 32A-32D Pads 49A-49D, 51A-51D Pad 20, 45 Probe card substrate 20A, 45A Opening 21, 44 Probe card reinforcing plate 25-28, 42, 43, 52, 53 Spacer 48 Foreign matter adsorption member 59 Wafer

Claims (9)

A first probe portion having a first probe needle in contact with a pad of a semiconductor integrated circuit chip;
When the first probe needle is in contact with the pad of the semiconductor integrated circuit chip, one or more semiconductor integrated circuit chips are adjacent to the semiconductor integrated circuit chip or connected to the semiconductor integrated circuit chip. A second probe portion having a second probe needle that contacts a pad of the sandwiched semiconductor integrated circuit chip,
The first probe needle is made of a first metal material;
The second probe needle is made of a second metal material;
The conductivity of the first metal material is higher than the conductivity of the second metal material,
The probe card, wherein the hardness of the second metal material is higher than the hardness of the first metal material. The probe card according to claim 1,
When the first probe needle is in contact with the pad of the semiconductor integrated circuit chip, the semiconductor integrated circuit chip in which the first probe needle is in contact with the pad and the second probe needle are in contact with the pad There is one semiconductor integrated circuit between the semiconductor integrated circuit chip and
Foreign matter adsorption contacting the one semiconductor integrated circuit between the semiconductor integrated circuit chip in which the first probe needle is in contact with the pad and the semiconductor integrated circuit chip in which the second probe needle is in contact with the pad A probe card comprising a member. The probe card according to claim 1 or 2,
A probe card, wherein the first metal material is gold (Au), silver (Ag), copper (Cu), or palladium (Pd). The probe card according to claim 1 or 2,
The probe card, wherein the first metal material is an alloy material containing a plurality of metals selected from gold (Au), silver (Ag), copper (Cu), and palladium (Pd). The probe card according to claim 1 or 2,
A probe card, wherein the second metal material is tungsten (W). The probe card according to claim 1 or 2,
A probe card, wherein the second metal material is an alloy material containing tungsten (W). The probe card according to claim 2,
A probe card characterized in that the foreign substance removing member is an elastic adhesive sheet. The probe card according to claim 2,
A probe card, wherein the foreign matter removing member is an elastic adhesive rubber. A semiconductor integrated circuit test method for performing a wafer test of a semiconductor integrated circuit chip using the probe card according to claim 1.

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