CN114487791A - SOC chip test system and test method - Google Patents
SOC chip test system and test method Download PDFInfo
- Publication number
- CN114487791A CN114487791A CN202210352655.XA CN202210352655A CN114487791A CN 114487791 A CN114487791 A CN 114487791A CN 202210352655 A CN202210352655 A CN 202210352655A CN 114487791 A CN114487791 A CN 114487791A
- Authority
- CN
- China
- Prior art keywords
- port
- soc chip
- tested
- resistor
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a system and a method for testing an SOC chip, which relate to the technical field of SOC chip testing, and are characterized in that at the first time when the SOC chip to be tested is accessed into the SOC chip testing system, a first IO port, a second IO port and a third IO port of an MCU module are tested and controlled to output corresponding levels, so that corresponding analog voltages are generated at two ends of a first collector resistor of the SOC chip testing system, and finally, the access state of the SOC chip to be tested is judged by a voltage value of a digital signal converted from the analog voltage input by an AD port, thereby preventing the SOC chip to be tested from being mistakenly accessed into a testing circuit, damaging the SOC chip to be tested in the testing process and solving the problem of wasting testing time due to poor contact. The SOC chip test system provided by the invention realizes multiple functions of three access state tests, power-on, power-off and the like through a simple structure, and has the advantage of low cost.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a system and a method for testing an SOC chip.
Background
In the test system of the SOC chip, after a manipulator of a tester puts a chip to be tested into a target position, a test needle contacts the chip to be tested to send a signal for starting the test. In this connection, the test system usually cannot determine whether the chip under test is in good contact with the test circuit for the first time.
The general processing method comprises the following steps: if the test system does not establish correct communication or obtain correct test data within a specified time, the test machine replaces the chip to be tested and accesses the test circuit again to perform a second test. But in this process: if the SOC chip to be tested is only in poor contact with the test circuit, the position of the chip to be tested has no problem, the test can be carried out only by contacting the test needle with the contact of the chip to be tested again, the chip to be tested does not need to be placed again, and the test time of the chip can be wasted. If the SOC chip to be tested is connected back into the test circuit, there is a risk of damage if the test is started directly.
In addition, in the prior art, image recognition or manual means and the like are usually adopted to distinguish whether the SOC chip to be tested is correctly accessed to the test system, but the above prior art has the disadvantages of high cost and the like.
Disclosure of Invention
The present invention is directed to solve the above problems in the background art, and provides a system and a method for testing an SOC chip.
In order to achieve the above object, the present invention first provides an SOC chip testing system, including: the test control MCU module comprises a first IO port, a second IO port, a third IO port, a first AD port and a second AD port, wherein the first IO port of the test control MCU module is connected with a first end of a first current-limiting resistor R1, the second IO port is connected with a first end of a second current-limiting resistor R5, the third IO port is connected with a first end of a third current-limiting resistor R7, the first AD port is connected with a first end of a first capacitor C1, the second AD port is connected with a second end of a first capacitor C1, a base electrode 37Q 1 of the PNP triode is connected with the first current-limiting resistor R73723, and a first end of the PNP triode Q1 is connected with a first end of a first current-limiting resistor R3, a collector of a PNP transistor Q1 is connected to a second end of a first capacitor C1 and a first end of a first collector resistor R3, a first end of a first capacitor C1 and a second end of a first collector resistor R3 are connected to ground, a base of an NPN transistor Q2 is connected to a second end of a second current-limiting resistor R5, an emitter of the NPN transistor Q2 is connected to ground, a collector of the NPN transistor Q2 is connected to a first end of a second collector resistor R4, a second end of the second collector resistor R4 is connected to a second power terminal, a base of a PNP transistor Q3 is connected to a second end of a third current-limiting resistor R7, an emitter of the PNP transistor Q3 is connected to the first power terminal, a collector of the PNP transistor Q3 is connected to a first end of a third collector resistor R9, a second end of a third collector resistor R9 is connected to a first end of a second capacitor C2 and a collector of a PNP transistor Q1, a second end of a second capacitor C2 is connected to a collector of the transistor Q2, the first end and the second end of the second capacitor C2 are used as the test ends of the SOC chip test system.
Optionally, the method further includes: and the first ends of the lower bias resistor R6 and the lower bias resistor R6 are connected with the second end of the second current-limiting resistor R5, and the second end of the lower bias resistor R6 is connected with the ground end.
Optionally, the method further includes: the first end of the first upper biasing resistor R2 is connected with a first power supply end, the second end of the first upper biasing resistor R2 is connected with the second end of the first current-limiting resistor R1, the first end of the second upper biasing resistor R8 is connected with the first power supply end, and the second end of the second upper biasing resistor R8 is connected with the base electrode of a PNP triode Q3.
The invention also provides a test method using the SOC chip test system, which comprises the following steps:
a first IO port of the test control MCU module outputs high level, a second IO port outputs low level and a third IO port outputs high level;
judging whether the SOC chip to be tested is correctly accessed into the SOC chip test system or not according to a first digital voltage signal generated by analog voltage received by a first AD port and a second AD port, wherein when the first digital voltage signal is a first voltage value, the SOC chip to be tested is correctly accessed into the test system, and when the digital voltage signal is other values, the SOC chip to be tested is not correctly accessed into the test system;
when the SOC chip to be tested is correctly accessed into the test system, the voltages of the first IO port and the second IO port are controlled to power on or power off the SOC chip;
when the SOC chip to be tested is not correctly accessed into the test system, a first IO port of the SOC chip test system outputs a high level, a second IO port outputs a high level, and a third IO port outputs a low level;
the access state of the SOC chip to be tested is further detected according to a second digital voltage signal generated by the analog voltage received by the first AD port and the second AD port, when the second digital voltage signal is a first voltage value, the SOC chip to be tested is wrongly accessed to the test system, and when the second digital voltage signal is a third voltage value, the SOC chip to be tested is in poor contact or is not accessed to the test system.
Optionally, the method further includes: when the second digital voltage signal received by the test control MCU module is the second voltage value, the second reminding signal is sent to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is wrongly and reversely accessed into the test system, and when the second digital voltage signal received by the test control MCU module is the second voltage value, the second reminding signal is sent to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is in poor contact or is not accessed into the test system.
Optionally, the method further includes: and when the external display equipment displays the information that the SOC chip to be tested is wrongly accessed into the test system reversely, the position of the SOC chip to be tested is relocated and then tested again.
Optionally, the method further includes: when the external display equipment displays the information that the SOC chip to be tested is in poor contact or is not accessed into the test system, the test pin is re-contacted with the contact of the SOC chip to be tested, and then the test is performed again.
Optionally, the range of the first voltage value is
The second voltage value is 0.7V, the third voltage value is Vcc R3/(R3+ R9), wherein Vcc is a power supply voltage, and R3, R4, and R9 are the first voltages, respectivelyCollector resistance R3, second collector resistance R4, and third collector resistance R9.
Optionally, after the SOC chip to be tested is correctly accessed to the test system, the method further includes the following steps:
and controlling the first IO port to output a low level, the second IO port to output a high level and the third IO port to output a high level to power on the SOC chip to be tested, wherein when the first IO port outputs a low level, the second IO port outputs a high level and the third IO port outputs a high level, the PNP triode Q1 and the NPN triode Q2 are in a conducting state, the PNP triode Q3 is in a stopping state, and the second capacitor C2 is used for powering on the SOC chip to be tested.
Optionally, the method further includes: the SOC chip to be tested is powered down by controlling the first IO port to output high level, the second IO port to output high level and the third IO port to output high level, wherein when the first IO port outputs high level, the second IO port outputs high level and the third IO port outputs high level, the PNP triodes Q1 and Q3 are in a cut-off state, the NPN triode Q2 is in a conducting state, and the SOC chip to be tested is powered down through a current loop formed by the second power supply end, the second collector resistor, the SOC chip to be tested, the first collector resistor and the ground end.
The invention has the beneficial effects that:
the SOC chip testing system and the testing method provided by the embodiment of the invention have the advantages that at the first time when the SOC chip to be tested is connected into the SOC chip testing system, the first IO port, the second IO port and the third IO port of the MCU module are tested and controlled to output corresponding levels, so that corresponding analog voltages are generated at two ends of a first collector resistor of the SOC chip testing system, finally, the access state of the SOC chip to be tested is judged by the voltage values of digital signals converted from the analog voltages input from the first AD port and the second AD port, wherein when the obtained first digital signal is the first voltage value, the SOC chip to be tested is judged to be correctly connected into the SOC chip testing system, when the obtained first digital signal is not the first voltage value, the SOC chip to be tested is judged not to be correctly connected into the SOC chip testing system, the levels of the first IO port, the second IO port and the third IO port are readjusted, and when the obtained second digital signal is the second voltage value, the SOC chip to be tested is judged to be wrongly reversely accessed into the test system, when the acquired second digital signal is the third voltage value, the SOC chip to be tested is judged to be in poor contact or not accessed into the test system, and three access states can be tested through one SOC chip test system, so that the problem that the SOC chip to be tested is mistakenly accessed into the test circuit to be damaged in the test process is solved, and the problem that the test time is wasted because all the SOC chips to be tested which are not correctly accessed into the SOC chip test system need to be replaced is solved.
The SOC chip testing system provided by the embodiment of the invention has the function of controlling the SOC chip to be tested to be powered on and powered off, so that the time sequence requirement of the SOC chip entering a testing state is conveniently established.
The features and advantages of the present invention will be described in detail by embodiments in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a schematic circuit diagram of an SOC chip test system according to an embodiment of the present invention;
FIG. 2 is a second schematic circuit diagram of an SOC chip test system according to an embodiment of the present invention;
FIG. 3 is a third schematic circuit diagram of a SOC chip test system according to an embodiment of the present invention;
FIG. 4 is a fourth schematic circuit diagram of an SOC chip test system according to an embodiment of the present invention;
FIG. 5 is a block diagram of a testing method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to specific examples in order to facilitate understanding by those skilled in the art.
The embodiment of the invention provides an SOC chip testing system which can detect whether an SOC chip to be tested is correctly accessed into the SOC chip testing system or not so as to reduce the risk that the SOC chip wrongly accessed into the testing system is damaged in the subsequent power-on testing process and solve the problem that the testing time is wasted because all SOC chips to be tested which are not correctly accessed into the SOC chip testing system need to be replaced. Meanwhile, the SOC chip testing system provided by the embodiment of the invention has the function of controlling the SOC chip to be tested to be powered on and powered off, so that the time sequence requirement of the SOC chip entering a testing state is conveniently established.
Referring to fig. 1, a schematic circuit diagram of an SOC chip testing system according to an embodiment of the present invention is shown, in which the SOC chip testing system includes: the testing control MCU module, a PNP triode Q1, an NPN triode Q2, a PNP triode Q3, a first collector resistor R3, a second collector resistor R4, a third collector resistor R9, a first current-limiting resistor R1, a second current-limiting resistor R5, a third current-limiting resistor R7, a first capacitor C1 and a second capacitor C2.
The first IO port IO1 of the test control MCU module is connected with the first end of the first current limiting resistor R1, the second IO port IO2 of the test control MCU module is connected with the first end of the second current limiting resistor R5, and the third IO port IO3 of the test control MCU module is connected with the first end of the third current limiting resistor R7.
The first AD port A0 of the test control MCU module is connected with the first end of the first capacitor C1, and the second AD port A1 of the test control MCU module is connected with the second end of the first capacitor C1.
The base of the PNP triode Q1 is connected to the second end of the first current-limiting resistor R1, the emitter of the PNP triode Q1 is connected to the first power terminal VCC1, the collector of the PNP triode Q1 is connected to the second end of the first capacitor C1 and the first end of the first collector resistor R3, and the first end of the first capacitor C1 and the second end of the first collector resistor R3 are connected to ground.
A base of the NPN transistor Q2 is connected to the second end of the second current-limiting resistor R5, an emitter of the NPN transistor Q2 is connected to ground, a collector of the NPN transistor Q2 is connected to a first end of the second collector resistor R4, and a second end of the second collector resistor R4 is connected to the second power supply terminal VCC 2.
The base of the PNP triode Q3 is connected to the second end of the third current-limiting resistor R7, the emitter of the PNP triode Q3 is connected to the first power supply terminal VCC1, the collector of the PNP triode Q3 is connected to the first end of the third collector resistor R9, the second end of the third collector resistor R9 is connected to the first end of the second capacitor C2 and the collector of the PNP triode Q1, and the second end of the second capacitor C2 is connected to the collector of the NPN triode Q2.
An ESD protection circuit is arranged between the power pin and the ground pin of the SOC chip to be tested, and the ESD protection circuit is equivalent to D1 in fig. 1. The SOC chip testing system provided by the embodiment of the invention realizes multiple functions of testing, power-on, power-off and the like of multiple access states by matching with the D1.
In one embodiment, the resistance of the first collector resistor R3 is 10K Ω, the resistance of the second collector resistor R4 is 1K Ω, and the resistance of the third collector resistor R9 is 10K Ω.
Referring to fig. 2, in another embodiment, the SOC chip testing system further includes: the circuit comprises a lower bias resistor R6, a first upper bias resistor R2 and a second upper bias resistor R8.
The first end of the lower bias resistor R6 is connected with the second end of the second current limiting resistor R5, and the second end of the lower bias resistor R6 is connected with the ground end. When the input end is in a high-resistance state, external electromagnetic interference is short-circuited to the ground by the lower bias resistor R6 so as to prevent the interference triode from triggering by mistake.
A first terminal of the first upper biasing resistor R2 is connected to a first power supply terminal VCC1, and a second terminal of the first upper biasing resistor R2 is connected to a second terminal of the first current limiting resistor. A first terminal of the second upper biasing resistor R8 is connected to the first power supply terminal VCC1, and a second terminal of the second upper biasing resistor R8 is connected to the base of the PNP transistor Q3.
Referring to fig. 5, an embodiment of the present invention further provides a testing method using the SOC chip testing system, including the following steps:
and step S10, testing and controlling the first IO port of the MCU module to output high level, the second IO port to output low level and the third IO port to output high level.
Specifically, the first IO port is connected to the base of the PNP transistor Q1 through the first current limiting resistor R1, the high level output from the first IO port just enables the PNP transistor Q1 to be in a cut-off state, the second IO port is connected to the base of the NPN transistor Q2 through the second current limiting resistor R5, the low level output from the second IO port just enables the NPN transistor Q2 to be in a cut-off state, the third IO port is connected to the base of the PNP transistor Q3 through the third current limiting resistor R7, and the high level output from the third IO port just enables the PNP transistor Q3 to be in a cut-off state, so that the PNP transistor Q1, the NPN transistor Q2, and the PNP transistor Q3 are in a cut-off state.
Step S20, the test control MCU module determines whether the SOC chip to be tested has been correctly accessed to the SOC chip test system according to the first digital voltage signal generated from the analog voltage received by the first AD port and the second AD port.
When the test control MCU module detects that the first digital voltage signal is a first voltage value, namely
And if the test control MCU module detects that the digital voltage signal is other values, judging that the SOC chip to be tested is not correctly accessed into the test system.
Referring to fig. 2, when the SOC chip to be tested is correctly connected to the test system, since the ESD protection circuit between the power pin and the ground pin of the SOC chip to be tested is equivalent to a diode D1, the diode D1 is connected to the NPN transistor Q2 at its positive electrode and the PNP transistor Q1 at its negative electrode, and is connected to the SOC chip test system according to the embodiment of the present invention.
At this time, the PNP transistor Q1, the NPN transistor Q2, and the PNP transistor Q3 are all in the off state, so that a current path is formed between the second power supply terminal VCC2, the second collector resistor R4, the diode D1, the first collector resistor R3, and the ground terminal GND, a current flows from the second power supply terminal VCC2 through the second collector resistor R4, the diode D1, the first collector resistor R3 to the ground terminal GND in this order, and a voltage Vx = (VCC-0.7V) = R3/(R3+ R4) is generated across the first collector resistor R3.
The voltage Vx is transmitted into a first AD port and a second AD port of the test control MCU module through a first capacitor C1, the test control MCU module carries out analog-to-digital conversion on the received analog voltage to obtain a first digital voltage signal VDWhen the first digital voltage signal VDThe correct access is judged within a certain range of (Vcc-0.7V) R3/(R3+ R4), and the wrong access is not judged within the range. In the present embodiment, the range is plus or minus 0.2V. In other embodimentsIn the example, the range can be adjusted appropriately according to the situation to meet the actual need.
And step S30, when the SOC chip to be tested is correctly accessed into the test system, controlling the voltage of the first IO port and the second IO port to power on or power off the SOC chip.
Step S40, when the SOC chip to be tested is not correctly accessed into the test system, the first IO port of the SOC chip test system outputs high level, the second IO port outputs high level, and the third IO port outputs low level.
Specifically, the first IO port is connected to the base of the PNP transistor Q1 through the first current limiting resistor R1, the high level output from the first IO port just enables the PNP transistor Q1 to be in a cut-off state, the second IO port is connected to the base of the NPN transistor Q2 through the second current limiting resistor R5, the high level output from the second IO port just enables the NPN transistor Q2 to be in a conduction state, the third IO port is connected to the base of the PNP transistor Q3 through the third current limiting resistor R7, and the low level output from the third IO port just enables the PNP transistor Q3 to be in a conduction state, so that the PNP transistor Q1 is in a cut-off state, and the NPN transistor Q2 and the PNP transistor Q3 are in conduction states.
Step S50, further detecting the access state of the SOC chip to be tested according to the second digital voltage signal generated by the analog voltage received by the first AD port and the second AD port.
And when the second digital voltage signal is a second voltage value, judging that the SOC chip to be tested is wrongly accessed into the test system, and when the second digital voltage signal is a third voltage value, judging that the SOC chip to be tested is in poor contact or is not accessed into the test system. In this embodiment, the second voltage value is 0.7V, and the third voltage value is Vcc R3/(R3+ R9), where Vcc is a power supply voltage, and R3, R4, and R9 are resistance values of the first collector resistor R3, the second collector resistor R4, and the third collector resistor R9, respectively.
Referring to fig. 3, when the power pin and the ground pin of the SOC chip to be tested are connected in reverse, that is, the diode D1 equivalent to the ESD protection circuit between the power pin and the ground pin of the SOC chip to be tested is connected to the PNP transistor Q1 at its positive electrode and the NPN transistor Q2 at its negative electrode, and is connected to the SOC chip testing system according to the embodiment of the present invention.
At this time, the PNP transistor Q1 is off, and the NPN transistor Q2 and the PNP transistor Q3 are on. However, the diode D1 is connected reversely, so the voltage generated across the first collector resistor R3 is clamped to 0.7V by the diode D1, and the second digital voltage signal obtained by the test control MCU module is also 0.7V.
Referring to fig. 4, when the SOC chip to be tested is in poor contact or is not connected to the test system, the PNP transistor Q1 is in an off state, the NPN transistor Q2 and the PNP transistor Q3 are in an on state, a voltage Vx = Vcc R3/(R3+ R9) is across the R3, and a second digital voltage signal obtained by the test control MCU module is also Vcc R3/(R3+ R9).
When the second digital voltage signal received by the test control MCU module is 0.7V, the test control MCU module sends a first reminding signal to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is wrongly accessed to the test system reversely, and when the external display equipment displays the information that the SOC chip to be tested is wrongly accessed to the test system reversely, the position of the SOC chip to be tested is relocated and then tested again. When the second digital voltage signal received by the test control MCU module is Vcc R3/(R3+ R9), a second reminding signal is sent to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is in poor contact or is not accessed to the test system, and when the external display equipment displays the information that the SOC chip to be tested is in poor contact or is not accessed to the test system, the test pin is re-contacted with the contact of the SOC chip to be tested and then re-tested to change the access state of the SOC chip to be tested.
In an embodiment, when the SOC chip to be tested is correctly accessed to the SOC chip test system, the first IO port outputs a low level, the second IO port outputs a high level, and the third IO port outputs a high level, so as to power up the SOC chip.
Specifically, when the first IO port outputs a low level, the second IO port outputs a high level, and the third IO port outputs a high level, the PNP transistor Q1 and the NPN transistor Q2 are in a conducting state, the PNP transistor Q3 is in a blocking state, the SOC chip is powered on through the second capacitor C2, and at this time, the power supply of the SOC chip to be tested is equivalent to VCC and GND.
In an embodiment, when the detection mode of the SOC chip needs to be adjusted and the SOC chip to be tested needs to be powered up again, the first IO port outputs a high level, the second IO port outputs a high level, and the third IO port outputs a high level, so as to power down the SOC chip to be tested.
Specifically, when the first IO port outputs a high level, the second IO port outputs a high level, and the third IO port outputs a high level, the PNP triodes Q1 and Q3 are in a cut-off state, the NPN triode Q2 is in a conduction state, and the SOC chip is powered down through a current loop formed by the second power supply terminal, the second collector resistor, the SOC chip, the first collector resistor, and the ground terminal.
In the testing method of the embodiment of the invention, the testing of the access state of the SOC chip to be tested is realized by testing and controlling the first IO port, the second IO port and the third IO port of the MCU module to output corresponding level signals and matching with the SOC chip testing system, and when the first digital voltage signal is used as the first digital voltage signal
And judging that the SOC chip to be tested is correctly accessed into the SOC chip test system, and executing subsequent operations such as power-on or power-off on the SOC chip to be tested. When the first digital voltage signal is 0.7V, the SOC chip to be tested is judged to be wrongly accessed into the SOC chip testing system, the SOC chip to be tested is judged to be wrongly accessed into the testing system, and when the second digital voltage signal is Vcc R3/(R3+ R9), the SOC chip to be tested is judged to be in poor contact or not accessed into the testing system.
To sum up, in the SOC chip testing system and the testing method of the embodiments of the present invention, at the first time when the SOC chip to be tested is connected to the SOC chip testing system, the first IO port, the second IO port, and the third IO port of the MCU module are controlled to output corresponding levels, so as to generate corresponding analog voltages at two ends of the first collector resistor of the SOC chip testing system, and finally determine the connection state of the SOC chip to be tested according to the voltage value of the digital signal converted from the analog voltage input by the AD port, wherein when the obtained first digital signal is the first voltage value, it is determined that the SOC chip to be tested is correctly connected to the SOC chip testing system, when the obtained second digital signal is the second voltage value, it is determined that the SOC chip to be tested is incorrectly connected to the testing system in the reverse direction, and when the obtained second digital signal is the third voltage value, it is determined that the SOC chip to be tested is poorly connected or not connected to the testing system, therefore, the SOC chip to be tested is prevented from being mistakenly connected into the test circuit, so that the SOC chip to be tested is damaged in the test process, and the problem of waste of test time caused by poor contact is solved.
The SOC chip testing system provided by the embodiment of the invention realizes multiple functions of access state testing, power-on, power-off and the like through a simple structure, and has the advantage of low cost.
The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above embodiments are illustrative of the present invention, and are not intended to limit the present invention, and any simple modifications of the present invention are within the scope of the present invention. The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. An SOC chip test system, comprising: the test control MCU module comprises a first IO port, a second IO port, a third IO port, a first AD port and a second AD port, wherein the first IO port of the test control MCU module is connected with a first end of a first current-limiting resistor R1, the second IO port is connected with a first end of a second current-limiting resistor R5, the third IO port is connected with a first end of a third current-limiting resistor R7, the first AD port is connected with a first end of a first capacitor C1, the second AD port is connected with a second end of a first capacitor C1, a base electrode 37Q 1 of the PNP triode is connected with the first current-limiting resistor R73723, and a first end of the PNP triode Q1 is connected with a first end of a first current-limiting resistor R3, a collector of a PNP transistor Q1 is connected to a second end of a first capacitor C1 and a first end of a first collector resistor R3, a first end of a first capacitor C1 and a second end of a first collector resistor R3 are connected to ground, a base of an NPN transistor Q2 is connected to a second end of a second current-limiting resistor R5, an emitter of the NPN transistor Q2 is connected to ground, a collector of the NPN transistor Q2 is connected to a first end of a second collector resistor R4, a second end of the second collector resistor R4 is connected to a second power terminal, a base of a PNP transistor Q3 is connected to a second end of a third current-limiting resistor R7, an emitter of the PNP transistor Q3 is connected to the first power terminal, a collector of the PNP transistor Q3 is connected to a first end of a third collector resistor R9, a second end of a third collector resistor R9 is connected to a first end of a second capacitor C2 and a collector of a PNP transistor Q1, a second end of a second capacitor C2 is connected to a collector of the transistor Q2, the first end and the second end of the second capacitor C2 are used as the test ends of the SOC chip test system.
2. The SOC chip test system of claim 1, further comprising: and the first ends of the lower bias resistor R6 and the lower bias resistor R6 are connected with the second end of the second current-limiting resistor R5, and the second end of the lower bias resistor R6 is connected with the ground end.
3. The SOC chip test system of claim 1, further comprising: the first end of the first upper biasing resistor R2 is connected with a first power supply end, the second end of the first upper biasing resistor R2 is connected with the second end of the first current-limiting resistor R1, the first end of the second upper biasing resistor R8 is connected with the first power supply end, and the second end of the second upper biasing resistor R8 is connected with the base electrode of the PNP triode Q3.
4. A test method using the SOC chip test system of claim 1, comprising the steps of:
a first IO port of the test control MCU module outputs high level, a second IO port outputs low level and a third IO port outputs high level;
judging whether the SOC chip to be tested is correctly accessed into the SOC chip test system or not according to a first digital voltage signal generated by analog voltage received by a first AD port and a second AD port, wherein when the first digital voltage signal is a first voltage value, the SOC chip to be tested is correctly accessed into the test system, and when the digital voltage signal is other values, the SOC chip to be tested is not correctly accessed into the test system;
when the SOC chip to be tested is correctly accessed into the test system, the voltages of the first IO port and the second IO port are controlled to power on or power off the SOC chip;
when the SOC chip to be tested is not correctly accessed into the test system, a first IO port of the SOC chip test system outputs a high level, a second IO port outputs a high level, and a third IO port outputs a low level;
the access state of the SOC chip to be tested is further detected according to a second digital voltage signal generated by the analog voltage received by the first AD port and the second AD port, when the second digital voltage signal is a first voltage value, the SOC chip to be tested is wrongly accessed to the test system, and when the second digital voltage signal is a third voltage value, the SOC chip to be tested is in poor contact or is not accessed to the test system.
5. The test method of claim 4, further comprising: when the second digital voltage signal received by the test control MCU module is the second voltage value, the second reminding signal is sent to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is wrongly and reversely accessed into the test system, and when the second digital voltage signal received by the test control MCU module is the second voltage value, the second reminding signal is sent to the external display equipment to enable the external display equipment to display the information that the SOC chip to be tested is in poor contact or is not accessed into the test system.
6. The test method of claim 5, further comprising: and when the external display equipment displays the information that the SOC chip to be tested is wrongly accessed into the test system reversely, the position of the SOC chip to be tested is relocated and then tested again.
7. The test method of claim 5, further comprising: when the external display equipment displays the information that the SOC chip to be tested is in poor contact or is not accessed into the test system, the test pin is re-contacted with the contact of the SOC chip to be tested, and then the test is performed again.
8. The test method of claim 4, wherein the first voltage value ranges from
The second voltage value is 0.7V, and the third voltage value is Vcc R3/(R3+ R9), where Vcc is the power supply voltage, and R3, R4, and R9 are resistance values of the first collector resistor R3, the second collector resistor R4, and the third collector resistor R9, respectively.
9. The testing method of claim 4, wherein when the SOC chip under test is correctly connected to the testing system, further comprising the steps of:
and controlling the first IO port to output a low level, the second IO port to output a high level and the third IO port to output a high level to power on the SOC chip to be tested, wherein when the first IO port outputs a low level, the second IO port outputs a high level and the third IO port outputs a high level, the PNP triode Q1 and the NPN triode Q2 are in a conducting state, the PNP triode Q3 is in a stopping state, and the second capacitor C2 is used for powering on the SOC chip to be tested.
10. The test method of claim 7, further comprising: the SOC chip to be tested is powered down by controlling the first IO port to output high level, the second IO port to output high level and the third IO port to output high level, wherein when the first IO port outputs high level, the second IO port outputs high level and the third IO port outputs high level, the PNP triode Q1 and the Q3 are in a cut-off state, the NPN triode Q2 is in a conducting state, and the SOC chip to be tested is powered down through a current loop formed by the second power supply end, the second collector resistor, the SOC chip to be tested, the first collector resistor and the ground end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210352655.XA CN114487791B (en) | 2022-04-06 | 2022-04-06 | SOC chip test system and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210352655.XA CN114487791B (en) | 2022-04-06 | 2022-04-06 | SOC chip test system and test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114487791A true CN114487791A (en) | 2022-05-13 |
| CN114487791B CN114487791B (en) | 2022-09-06 |
Family
ID=81487274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210352655.XA Active CN114487791B (en) | 2022-04-06 | 2022-04-06 | SOC chip test system and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114487791B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480271A1 (en) * | 2003-05-23 | 2004-11-24 | STMicroelectronics S.r.l. | Method of analysis of the quality of contacts and vias in multi-level metallisation fabrication processes of semiconductor devices, and corresponding test chip architecture |
| JP2007003252A (en) * | 2005-06-22 | 2007-01-11 | Sharp Corp | Probe card and method for testing semiconductor integrated circuit |
| CN108572312A (en) * | 2018-04-12 | 2018-09-25 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | SoC chip test method, device, system and SoC chip test witness plate |
| CN211928111U (en) * | 2019-12-05 | 2020-11-13 | 景德镇昌航航空高新技术有限责任公司 | Detection system for relay coil transient suppression diode |
| CN112798984A (en) * | 2021-02-01 | 2021-05-14 | 深圳市拓迈特科技有限公司 | Symmetric positive and negative connection detection circuit |
| CN112965012A (en) * | 2021-02-25 | 2021-06-15 | 广州亚美智造科技有限公司 | Power supply polarity reverse connection testing device, testing system and testing method |
| CN213990642U (en) * | 2020-12-09 | 2021-08-17 | 杭州恒芯微电子科技有限公司 | Automatic test system based on high-precision ADC chip |
| CN113391238A (en) * | 2021-05-27 | 2021-09-14 | 浙江伊控动力系统有限公司 | Novel high-voltage interlocking connection state detection circuit |
| CN113933618A (en) * | 2021-09-10 | 2022-01-14 | 荣耀终端有限公司 | Test device, radio frequency device and detection system |
| CN215678636U (en) * | 2021-03-24 | 2022-01-28 | 深圳佰维存储科技股份有限公司 | Chip test circuit and chip test system |
-
2022
- 2022-04-06 CN CN202210352655.XA patent/CN114487791B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480271A1 (en) * | 2003-05-23 | 2004-11-24 | STMicroelectronics S.r.l. | Method of analysis of the quality of contacts and vias in multi-level metallisation fabrication processes of semiconductor devices, and corresponding test chip architecture |
| JP2007003252A (en) * | 2005-06-22 | 2007-01-11 | Sharp Corp | Probe card and method for testing semiconductor integrated circuit |
| CN108572312A (en) * | 2018-04-12 | 2018-09-25 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | SoC chip test method, device, system and SoC chip test witness plate |
| CN211928111U (en) * | 2019-12-05 | 2020-11-13 | 景德镇昌航航空高新技术有限责任公司 | Detection system for relay coil transient suppression diode |
| CN213990642U (en) * | 2020-12-09 | 2021-08-17 | 杭州恒芯微电子科技有限公司 | Automatic test system based on high-precision ADC chip |
| CN112798984A (en) * | 2021-02-01 | 2021-05-14 | 深圳市拓迈特科技有限公司 | Symmetric positive and negative connection detection circuit |
| CN112965012A (en) * | 2021-02-25 | 2021-06-15 | 广州亚美智造科技有限公司 | Power supply polarity reverse connection testing device, testing system and testing method |
| CN215678636U (en) * | 2021-03-24 | 2022-01-28 | 深圳佰维存储科技股份有限公司 | Chip test circuit and chip test system |
| CN113391238A (en) * | 2021-05-27 | 2021-09-14 | 浙江伊控动力系统有限公司 | Novel high-voltage interlocking connection state detection circuit |
| CN113933618A (en) * | 2021-09-10 | 2022-01-14 | 荣耀终端有限公司 | Test device, radio frequency device and detection system |
Non-Patent Citations (2)
| Title |
|---|
| NORBERG, G 等: "Very high density interconnect elastomer chip sockets", 《IEEE TRANSACTIONS ON ADVANCED PACKAGING》 * |
| 陈思立: "SOC接触测试不良导致良品率低的改善及研究", 《电子技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114487791B (en) | 2022-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8095714B2 (en) | Electronic device capable of automatically switching between a master mode and a slave mode | |
| US7629775B2 (en) | Battery connection detection circuit | |
| US9201832B2 (en) | Electronic device with USB interface and method for starting USB communication therefor | |
| US8443130B2 (en) | USB port detecting circuit | |
| US20080288662A1 (en) | Identification address configuration circuit and method without use of dedicated address pins | |
| CN101949988A (en) | Detection device of level-type signal disconnection fault | |
| CN110988571B (en) | Load insertion detection circuit, system and method | |
| CN103426478A (en) | Read circuit of flash memory | |
| CN114487791B (en) | SOC chip test system and test method | |
| KR100377919B1 (en) | Logic and Leakage Current Test Device of Digital Logic Circuit | |
| CN213903759U (en) | Load open circuit detection circuit | |
| US8803544B2 (en) | Integrated circuit chip and testing method capable of detecting connection error | |
| CN116662232A (en) | Electronic equipment and detection method | |
| EP4135196A1 (en) | Digital output circuit, digital output device, and digital output system | |
| CN115267493A (en) | Pin state detection device, method and programmer | |
| US10784968B2 (en) | Optical module | |
| TWI726332B (en) | Motherboard battery detection device | |
| US20200303946A1 (en) | Power circuit and driving method thereof | |
| CN102385018B (en) | External equipment connection sensing circuit | |
| CN218956772U (en) | Signal output circuit and intelligent power module | |
| CN101353237B (en) | Micro-current sensing circuit and micro-current switch circuit | |
| CN116540146B (en) | GPIO short circuit detection method and GPIO short circuit detection system | |
| CN111435154B (en) | Electric leakage detection circuit, electric leakage detection device and electric leakage detection method for flash memory | |
| CN117686006A (en) | Signal input circuit compatible with NPN signal and PNP signal | |
| CN215894733U (en) | Voltage signal detection circuit, power supply device and electric device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |