JP2006352295A - Solid state imaging device, its driving method and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging device in which the phenomenon of shutter level difference can be prevented, and to provide a driving method of the solid state imaging device and an imaging apparatus employing the solid state imaging device. <P>SOLUTION: Phenomenon of shutter level difference is prevented by operating a current source 13 connected with each vertical signal line 111 over the pixel operation period of reading row and the pixel operation period of shutter row, turning a reset transistor on by activating the reset pulse S_Rst of the shutter row, and turning a transfer transistor on by activating a transfer pulse S_Trf with a lag of predetermined period, thereby making the potential of the vertical signal line during pixel operation period of the shutter row in the vertical blanking period comparable to the potential of the vertical signal line during pixel operation period of the reading row. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an imaging device, and more particularly to a solid-state imaging device that performs an electronic shutter operation, a driving method for the solid-state imaging device, and an imaging device that uses the solid-state imaging device as an imaging device. .

  FIG. 12 shows a basic configuration of, for example, a CMOS type solid-state imaging device. As illustrated in FIG. 12, pixels 101 including photoelectric conversion elements are two-dimensionally arranged in a matrix to form a pixel array unit (imaging region) 102. The pixel array section 102 is provided with a vertical signal line 103 for each column and a plurality of drive control lines 104 for each row with respect to the matrix-like pixel arrangement. As peripheral circuits of the pixel array unit 102, a vertical scanning circuit 105, a column circuit (column parallel signal processing circuit) 106, a horizontal scanning circuit 107, and an output circuit 108 are provided.

  The vertical scanning circuit 105 scans each pixel 101 of the pixel array unit 102 in the vertical direction (vertical direction) in units of rows for each shutter row and readout row, and for the shutter row, sweeps out the signals of the pixels in that row. In addition to supplying a shutter pulse for performing reading, a reading pulse for reading a signal of a pixel in the row is supplied to the reading row.

  The column circuit 106 performs predetermined signal processing on signals output from the pixels 101 in the readout row selected by the vertical scanning by the vertical scanning circuit 105 through the vertical signal line 103 and temporarily holds the signals. The horizontal scanning circuit 107 horizontally scans the column circuit 106 and sequentially outputs signals of pixels for one row (one line) temporarily held in the column circuit 106. The output circuit 108 processes and outputs a signal from the column circuit 106. A MOS transistor is connected as the current source 109 outside the imaging area of the vertical signal line 103.

  FIG. 13 shows the scanning timing of the pixel array unit 102. In FIG. 13, the vertical axis indicates the row address Vaddr of the pixel array unit 102, and the horizontal axis indicates time. Vsync is a vertical synchronization signal, and Hsync is a horizontal synchronization signal.

  First, at the generation timing of the vertical synchronization pulse Vsync, the vertical scanning circuit 105 starts scanning the readout row. Note that the scanning of the shutter row is started from a timing before the scanning of the readout row. A scanning period from the shutter row to the readout row is an exposure time (signal accumulation time) of the photoelectric conversion element of the pixel 101.

  Here, a period from when the readout row scans the pixel array portion 102 to the last row until the scanning is started again from the first row is referred to as a vertical blanking period (VBLK). Further, a period from when the shutter row scans the pixel array unit 102 to the last row to when scanning starts again from the first row is called a shutter blanking period (SBLK).

  In the solid-state imaging device that performs the electronic shutter operation described above, a horizontal band is generated on the captured image due to the stop of the output of the shutter pulse within the vertical video period, and the horizontal band is moved up and down according to the shutter speed. It is known that a so-called moving shutter step occurs.

  In order to prevent this shutter step from occurring, conventionally, a dummy stage is added to both the vertical scanning system and the shutter scanning system, and a dummy pixel is added to the imaging region (pixel array unit), and the vertical scanning system is used. In the shutter scanning system, the shutter pulse is continuously output from the dummy stage at least during the vertical video period after the end of the vertical scanning (see, for example, Patent Document 1).

JP 2001-8109 A

  On the other hand, the inventor of the present application has found that a shutter step occurs even in a factor / situation other than the stop of the output of the shutter pulse within the vertical video period. The reason for this is that the amount of sweeping of the signal differs slightly in the row scanned as the shutter row during the vertical blanking period, so that when the row is scanned as the next readout row, the amount of sweeping differs. Only the signal amount is different. This factor also causes a shutter step (horizontal band) (see FIG. 13). The shutter level difference cannot be solved by the prior art according to Patent Document 1 because the generation factors are different.

  Here, the reason why the signal sweep-out amount is different will be considered. In FIG. 13, since there is no readout row in the vertical blanking period, the potential of the vertical signal line 103 is different from that when the readout row exists, and the pixels in the shutter row to which the vertical signal line 103 is connected are affected. Will receive. In the physical pixel structure, the vertical signal line 103 is in electrical contact with a metal wiring, a contact hole, and a diffusion layer in the semiconductor, and is a large structure.

  If the potential change of the vertical signal line 103 immediately before the signal of the pixel in the shutter row is swept away or the potential of the vertical signal line 103 at the time of sweeping is different, the pixel in the pixel of the shutter row being swept away The potential distribution is influenced by electrostatic capacitive coupling and other subtle effects, and the signal charge sweep-out amount has a slight effect of several to several tens of electrons. This slight difference in the amount of sweep-out causes a horizontal band to appear on the captured image when a very dark scene is imaged with a large gain, resulting in a shutter step.

  Hereinafter, a mechanism in which a shutter step occurs due to a slightly different amount of signal sweeping will be described in more detail.

  FIG. 14 is a circuit diagram illustrating an example of the configuration of the pixel 101. As shown in FIG. 14, the pixel 101 according to this example includes a photodiode 201 that is a photoelectric conversion element, a transfer transistor 202, a reset transistor 203, a floating diffusion portion (FD portion) 204 that is a voltage conversion portion, and an amplification transistor 205. It is configured. The amplification transistor 205 forms a source follower with the MOS transistor of the current source 109.

  For this pixel 101, a transfer control line 206, a reset control line 207, and a drain control line 208 are wired for each row as drive control lines 104 (see FIG. 12). Then, a transfer pulse Trf is supplied via the transfer control line 206, a reset pulse Rst is supplied via the reset control line 207, and a drain voltage Drain is supplied via the drain control line 208 to each pixel in the shutter row and the readout row. . The drain control line 208 is wired in common for all pixels. In addition, a load pulse Load is applied to the MOS transistor constituting the current source 109.

  FIG. 15 shows a timing relationship among pixel drive pulses according to a conventional example, that is, a horizontal synchronization pulse Hsync, a load pulse Load, a drain voltage Drain, a reset pulse Rst, and a transfer pulse Trf. Here, the reset pulse Rst and the transfer pulse Trf are shown as a reset pulse R_Rst and a transfer pulse R_Trf for the readout row, a reset pulse S_Rst and a transfer pulse S_Trf for the shutter row, respectively.

  In the pixel 101 having the above-described configuration, first, the drain voltage Drain common to all the pixels rises (becomes active), and at the same time, the load pulse Load rises, thereby turning on the MOS transistor of the current source 109 that forms the amplification transistor 205 and the source follower. It becomes a state. Thereafter, the reset pulse R_Rst in the read row becomes active, so that the reset transistor 203 is turned on and the FD unit 204 is reset. The potential of the FD unit 204 at the time of resetting is output to the vertical signal line 103 as a reset level by the amplification transistor 206.

  Next, when the transfer pulse R_Trf in the reading row becomes active, the transfer transistor 202 is turned on, and the signal charge photoelectrically converted by the photodiode 201 is transferred to the FD unit 204. The potential of the FD unit 204 at the time of signal transfer is output to the vertical signal line 103 as a signal level by the amplification transistor 206.

  The column circuit 106 calculates the difference between the reset level and the signal level sequentially supplied from the pixel 101 through the vertical signal line 103, and outputs the difference as a signal for photoelectric conversion. Since the signal output from the pixel 101 is completed, the load pulse Load falls (becomes inactive).

  Thereafter, the reset pulse R_Rst for the readout row and the reset pulse S_Rst for the shutter row become active. As a result, the FD sections 204 in both rows are reset. At this time, since the transfer pulse S_Trf is also active in the shutter row, the signal of the photodiode 201 is swept away.

  Since the drain voltage Drain falls after the transfer pulse S_Trf of the shutter row becomes inactive, the potential of the FD portion 204 of the readout row and the shutter row becomes low level, so that the amplification transistor 205 is turned off and the readout row And each pixel 101 in the shutter row is electrically disconnected from the vertical signal line 103.

  Finally, the readout row reset pulse R_Rst and the shutter row reset pulse S_Rst become inactive. Thereafter, a horizontal video period in which a signal temporarily held in the column circuit 106 is scanned by the horizontal scanning circuit 107 is entered. Then, this operation is repeated while sequentially scanning the rows in the vertical direction.

  Here, since there is no readout row in the vertical blanking period, the transfer pulse R_Trf and the reset pulse R_Rst are in an inactive state, and no signal is output to the vertical signal line 103. That is, the potential of the vertical signal line 103 immediately before the shutter operation is different between the case of the vertical blanking period and the case of not being the vertical blanking period. As a result, the potential of the vertical signal line 103 during the shutter operation remains affected, which causes the shutter step.

  Therefore, the present invention performs sweeping by changing the potential of the vertical signal line immediately before sweeping out the signal charges of the pixels in the electronic shutter row, or by changing the potential of the vertical signal line when sweeping. It is an object of the present invention to provide a solid-state imaging device capable of improving the influence exerted on pixels in a shutter row and preventing a shutter step phenomenon, a driving method of the solid-state imaging device, and an imaging device using the solid-state imaging device.

  In order to achieve the above object, the present invention provides a pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix and signal lines are wired for each pixel column with respect to the matrix-like pixel arrangement. And sequentially scanning a shutter row that resets the signal charges of the pixels and a readout row that reads the signal charges of the pixels with respect to the pixel array unit, and a pixel operation period of the shutter rows and a pixel operation period of the readout rows In a solid-state imaging device including a scanning circuit that operates at different timings, the potential of the signal line in the pixel operation period of the shutter row in the vertical blanking period is approximately the same as the potential of the signal line in the pixel operation period of the readout row. The configuration to be set is adopted.

  In the solid-state imaging device having the above configuration or an imaging device using the solid-state imaging device as an imaging device, the signal line potential in the pixel operation period of the shutter row in the vertical blanking period is the same as the signal line potential in the pixel operation period of the readout row. By setting the level to about the same level, the signal line potential does not change between the vertical blanking period and the vertical video period, so that it is possible to improve the influence on the pixels of the shutter row that is being swept away.

  According to the present invention, sweeping is performed by changing the potential of the signal line immediately before the signal charge of the pixel in the electronic shutter row is swept away or by changing the potential of the vertical signal line when sweeping away. Since the influence on the pixels in the shutter row can be improved, the phenomenon of the shutter step can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a system configuration diagram showing the configuration of a solid-state imaging device, for example, a MOS type solid-state imaging device according to the first embodiment of the present invention.

  As shown in FIG. 1, the MOS type solid-state imaging device 10 according to this embodiment includes a pixel array unit (imaging region) 11 in which pixels 20 including photoelectric conversion elements 20 are two-dimensionally arranged in a matrix (matrix). In addition, the peripheral circuit includes a vertical scanning circuit 12, a current source 13, a column circuit (column parallel signal processing circuit) 14, a horizontal scanning circuit 15, an output circuit 16, and a control circuit 17.

  Here, in order to simplify the drawing, the arrangement of the pixels 20 in the pixel array unit 11 is set to 4 rows and 6 columns. With respect to this matrix pixel arrangement, vertical signal lines 111 are wired for each column, and drive control lines such as a transfer control line 112, a reset control line 113, and a drain control line 114 are wired for each row. The drain control line 114 is wired in common for all pixels.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel 20. As shown in FIG. 2, the pixel 20 according to this example is a pixel circuit having three transistors, for example, a transfer transistor 22, a reset transistor 23, and an amplification transistor 24 in addition to a photoelectric conversion element, for example, a photodiode 21. Yes. Here, as these transistors 22 to 24, for example, N-channel MOS transistors are used.

  The transfer transistor 22 is connected between the cathode of the photodiode 21 and an FD section (floating diffusion section) 25 that is a voltage conversion section, and is photoelectrically converted by the photodiode 21 and accumulated in the signal charge (here, Electron) is transferred to the FD section 25 when a transfer pulse Trf is applied to the gate.

  The reset transistor 23 has a drain connected to the drain control line 114 and a source connected to the FD unit 25, and a reset pulse Rst is applied to the gate prior to transfer of signal charges from the photodiode 21 to the FD unit 25. The potential of the FD unit 25 is reset. The drain control line 114 is supplied with a drain voltage Drain which is active and has a power supply level, and inactive and has a GND level.

  The amplification transistor 24 has a source follower configuration in which a gate is connected to the FD unit 25, a drain is connected to the drain control line 114, and a source is connected to the vertical signal line 111, and the operation state is activated when the drain voltage Drain becomes active. The pixel 20 is selected, the potential of the FD section 25 after resetting by the reset transistor 23 is output to the vertical signal line 111 as a reset level, and the signal charge is transferred from the photodiode 21 by the transfer transistor 12 The potential of the FD unit 25 is output to the vertical signal line 111 as a signal level.

  Returning to FIG. The vertical scanning circuit 12 is configured by a shift register, an address decoder, or the like, and scans each pixel 20 of the pixel array unit 11 in the vertical direction (up and down direction) for each shutter row and readout row for each shutter row. In addition, a shutter pulse for sweeping out the signals of the pixels in the row is supplied, and a readout pulse for reading out the signals of the pixels in the row is supplied to the readout row.

  Although not shown here, the vertical scanning circuit 12 sequentially selects the pixels 20 in units of rows and performs a reading operation for reading a signal of each pixel 20 in the selected row, and the reading scanning. An electronic shutter scanning system for performing an electronic shutter operation that discards (resets) charges accumulated so far in the photodiodes 21 of the pixels 20 in the same row a time corresponding to the shutter speed before the readout scanning by the system It has composition which has.

  The period from the timing when the unnecessary charge of the photodiode 21 is reset by the shutter scanning by the electronic shutter scanning system to the timing when the signal of the pixel 20 is read by the reading scanning by the readout scanning system is the period of the signal charge in the pixel 20. Accumulation time (exposure time). That is, the electronic shutter operation is an operation of resetting the signal charge accumulated in the photodiode 21 and newly starting accumulation of signal charge.

  As is clear from FIG. 2 in particular, the current source 13 is composed of a load MOS transistor 131 connected between the vertical signal line 111 and the ground. A load pulse Load is selectively applied to the gate of the load MOS transistor 131 via the load line 132. The load MOS transistor 131 is electrically connected to the amplification transistor 24 of the pixel in the selected row via the vertical signal line 111, thereby forming a source follower circuit with the amplification transistor 24.

  The column circuit 14 is composed of a circuit group arranged for each pixel column of the pixel array unit 11, that is, with a one-to-one correspondence with the pixel column, and is selected by the vertical scanning by the vertical scanning circuit 12. A predetermined signal processing is performed on a signal output from each pixel 20 through the vertical signal line 111 and temporarily held.

  More specifically, the column circuit 14 receives a signal output from each pixel 20 for one row for each pixel column, and removes a fixed pattern noise peculiar to the pixel from the signal. Performs signal processing such as Double Sampling (correlated double sampling) and signal amplification. It is also possible to adopt a configuration in which the column circuit 14 has an A / D (analog / digital) conversion function.

  The horizontal scanning circuit 15 includes a shift register, an address decoder, or the like, scans each circuit of the column circuit 14 in order, and signals of pixels for one row (one line) temporarily held in the column circuit 14. Are output sequentially. The output circuit 16 performs predetermined processing on the signal output from the column circuit 15, for example, buffering only, or processing such as black level adjustment, correction of variation for each column, and signal amplification before buffering.

  The control circuit 17 receives data for instructing the operation mode of the solid-state imaging device 10 from a host device (not shown), outputs data including information on the solid-state imaging device 10 to the host device, and also generates a vertical synchronization signal Vsync. Based on the horizontal synchronization signal Hsync and the master clock MCK, a clock signal, a control signal, and the like that become a reference for operations of the vertical drive circuit 12, the current source 13, the column circuit 14, and the horizontal scanning circuit 15 are generated. Give against.

  FIG. 3 shows a timing relationship among pixel drive pulses in the solid-state imaging device 10 according to the first embodiment, that is, the horizontal synchronization pulse Hsync, the load pulse Load, the drain voltage Drain, the reset pulse Rst, and the transfer pulse Trf. Here, the reset pulse Rst and the transfer pulse Trf are shown as a reset pulse R_Rst and a transfer pulse R_Trf for the readout row, a reset pulse S_Rst and a transfer pulse S_Trf for the shutter row, respectively.

  Next, the operation of the solid-state imaging device 10 according to the first embodiment will be described using the timing chart of FIG. In the timing chart of FIG. 3, the two-dot chain line indicates the conventional operation timing.

  First, the drain voltage Drain common to all the pixels becomes active (power supply level), and at the same time, the load pulse Load becomes active, so that the load MOS transistor 131 that forms the source follower circuit with the amplification transistor 24 is turned on. Thereafter, when the reset pulse R_Rst of the read row becomes active, the reset transistor 22 is turned on and the FD unit 25 is reset. The potential of the FD unit 25 at the time of resetting is output to the vertical signal line 111 as a reset level by the amplification transistor 24.

  Next, when the transfer pulse R_Trf in the readout row becomes active, the transfer transistor 22 is turned on, and the signal charge photoelectrically converted by the photodiode 21 is transferred to the FD unit 25. The potential of the FD unit 25 at the time of signal transfer is output to the vertical signal line 111 as a signal level by the amplification transistor 24. As a result, the signal output operation in the pixel 20 is completed, but the load MOS transistor 131 of the current source 13 is kept on. Thereafter, the reset pulse R_Rst for the readout row and the reset pulse S_Rst for the shutter row are activated, whereby the FD units 25 of both rows are reset.

  Here, in the operation timing of the conventional pixel readout / electronic shutter, as apparent from the timing chart of FIG. 15, the signal charges are swept for the photodiodes 21 in the shutter row at the same timing as the reset timing of the FD unit 25. I was throwing away.

  On the other hand, at the operation timing according to this embodiment, the reset timing of the FD unit 25, that is, the reset pulse S_Rst is activated, and the shutter row transfer is performed at a timing delayed by a predetermined period t from the timing when the reset transistor 23 is turned on. By activating the pulse S_Trf and turning on the transfer transistor 22, signal charges are swept away from the photodiode 21 in the shutter row.

  Since the load MOS transistor 131 is in the ON state during the electronic shutter pixel operation period, the potential of the vertical signal line 111 follows the potential of the FD section 25. Therefore, even if there is no readout row in the vertical blanking period, the electronic shutter The row reset pulse S_Rst becomes active, and the reset level of the electronic shutter row appears on the vertical signal line 111.

  That is, even when there is no readout row in the vertical blanking period, the reset level appears on the vertical signal line 111, and the signal charge is swept away from the photodiode 21 after the potential of the vertical signal line 111 is stabilized. Therefore, even if the potential of the vertical signal line 111 immediately before the electronic shutter operation is different from the vertical blanking period, the signal charge is swept away from the photodiode 21 without being affected by the influence.

  Since the drain voltage Drain falls after the transfer pulse S_Trf of the shutter row becomes inactive, the potential of the FD portion 25 of the readout row and the shutter row becomes low level, so that the amplification transistor 24 is turned off and the readout row Each pixel 20 in the shutter row is electrically disconnected from the vertical signal line 111. Further, the load pulse Load becomes inactive at the timing when the drain voltage Drain falls.

  Finally, the readout row reset pulse R_Rst and the shutter row reset pulse S_Rst become inactive. Thereafter, a horizontal video period in which the signal temporarily held in the column circuit 14 is scanned by the horizontal scanning circuit 15 is entered. Then, this operation is repeated while sequentially scanning the rows in the vertical direction.

  As described above, in the MOS solid-state imaging device 10 in which the current source 13 is connected to the vertical signal line 111, the current source 13 is operated over the pixel operation period of the readout row and the pixel operation period of the shutter row. The reset pulse S_Rst of the shutter row is activated to turn on the reset transistor 23, and then the transfer pulse S_Trf is activated to delay the predetermined time period t and then the transfer transistor 22 is turned on, so that the shutter is activated in the vertical blanking period. The potential of the vertical signal line 111 in the pixel operation period of the row can be made substantially the same as the potential of the vertical signal line 111 in the pixel operation period of the readout row.

  As a result, the potential change of the vertical signal line 111 immediately before the signal charge of the pixel 20 in the shutter row is swept away or the potential of the vertical signal line 111 when the sweep is swept away is different. Since the influence exerted on the pixels 20 in the shutter row, that is, the electrostatic capacitive coupling of the potential distribution in the pixels 20 and other subtle effects can be improved, the phenomenon of the shutter step can be prevented.

  In the above embodiment, the pixel 20 has a three-transistor configuration in which the amplification transistor 24 also serves as a pixel selection transistor. However, the pixel 20 is not limited to the three-transistor configuration. Apart from that, any structure having at least the transfer transistor 22 and the reset transistor 23 may be used, such as a four-transistor structure having a selection transistor.

[Second Embodiment]
FIG. 4 is a system configuration diagram showing the configuration of the MOS type solid-state imaging device according to the second embodiment of the present invention. In FIG. 4, the same parts as those in FIG.

  The MOS type solid-state imaging device 30 according to the present embodiment uses, as each pixel of the pixel array unit 11, a pixel 20 ′ having a four-transistor configuration having a selection transistor in addition to the amplification transistor 24, a voltage source circuit 31, a changeover switch. 32 and the switch circuit 33 are newly provided as components. The rest of the configuration is basically the same as that of the solid-state imaging device 10 according to the first embodiment, and a description thereof will be omitted because it is redundant.

  As shown in FIG. 5, the pixel 20 ′ has a four-transistor configuration having a selection transistor 26 in addition to the transfer transistor 22, the reset transistor 23, and the amplification transistor 24. The drain voltage Drain is fixed at the power supply level.

  The selection transistor 26 is connected between the source of the amplification transistor 24 and the vertical signal line 111, and is supplied with a selection pulse Select via the selection control line 115 to be turned on to select the pixel 20 '. . It is also possible to adopt a configuration in which the selection transistor 26 is connected between the drain control line 114 and the drain of the amplification transistor 24.

  The voltage source circuit 31 can output an arbitrary voltage, and the output voltage can be adjusted by setting from the outside. The output voltage of the voltage source circuit 31 is set to a voltage near the reset level (corresponding to signal zero) of the pixel 20 '.

  The changeover switch 32 has the output voltage of the voltage source circuit 31 as one input and the GND level as the other input, and when the changeover pulse V1 applied from the control circuit 17 becomes active, the output voltage of the voltage source circuit 31 Is supplied to each circuit of the switch circuit 33 via the control line 34.

  Each circuit of the switch circuit 33 is configured by a MOS transistor 331 connected between the power supply and the vertical signal line 111, and the output voltage of the voltage source circuit 31 is applied to the gate of the MOS transistor 331 via the changeover switch 32. Then, by controlling the high level of the gate voltage, a potential near the reset level of the pixel 20 ′ is supplied to the vertical signal line 111.

  FIG. 6 shows timings of pixel drive pulses in the solid-state imaging device 30 according to the second embodiment, that is, horizontal synchronization pulse Hsync, load pulse Load, drain voltage Drain, selection pulse Select, reset pulse Rst, transfer pulse Trf, and switching pulse V1. Show the relationship.

  Here, the selection pulse Select, the reset pulse Rst, and the transfer pulse Trf are shown as a read row selection pulse R_Select, a reset pulse R_Rst and a transfer pulse R_Trf, a shutter row selection pulse S_Select, a reset pulse S_Rst, and a transfer pulse S_Trf.

  Next, the operation of the solid-state imaging device 30 according to the second embodiment will be described using the timing chart of FIG.

  In the readout row of the pixel array unit 11, the selection pulse R_Select is activated in synchronization with the load pulse Load to select each pixel 20 ′ in the readout row. In this selection state, the reset pulse R_Rst is the same as in the prior art. As the transfer pulse R_Trf becomes active in sequence, the reset level (corresponding to signal zero) and the signal level of the pixel 20 ′ are sequentially output to the vertical signal line 111. Thereafter, before the pixel operation of the shutter row at a different timing starts, the selection pulse R_Select is deactivated, so that each pixel 20 ′ in the readout row is disconnected from the vertical signal line 111.

  Next, before the pixel operation of the shutter row starts, that is, before the transfer pulse R_Trf, the reset pulse S_Rst, and the transfer pulse S_Trf become active, the changeover pulse V1 becomes active, whereby the changeover switch 32 causes the voltage source circuit 31 to become active. And the output voltage is supplied to the switch circuit 33.

  As a result, a voltage near the reset level of the pixel 20 ′ is always supplied to the vertical signal line 111 during the pixel operation period of the shutter row, that is, the period during which the signal of the photodiode 21 is swept away. Here, the high level of the gate voltage of the MOS transistor 331 is controlled by the output voltage of the voltage source circuit 31, and a potential almost at the reset level is supplied to the vertical signal line 111.

  The high level of the gate voltage of the MOS transistor 331 may be set to be substantially the same as the gate voltage of the amplification transistor 24 when the reset level of the selected row is output. As a result, the potential of the vertical signal line 111 does not become a different potential even during the electronic shutter row operation period of the vertical blanking period, so that no shutter step occurs. After the pixel operation period of the electronic shutter row ends, the switching pulse V1 becomes inactive, whereby the voltage supply from the voltage source circuit 31 to the vertical signal line 111 is stopped.

  Here, the potential supplied to the vertical signal line 111 is ideally set to the same potential as the reset level, but the inventors of the present application can obtain an obvious effect by setting the difference to 500 mV or less. It has been confirmed that there is practically no problem by setting the difference to 100 mV or less.

  When the voltage source circuit 31 has an output voltage adjustment function as in this example, an operation for setting a condition that makes it easy to confirm the shutter step and controlling the voltage supplied to the vertical signal line 111 so as to disappear. Should be done.

  As is apparent from the above description of the operation, the voltage source circuit 31, the changeover switch 32, and the switch circuit 33 change the potential of the vertical signal line 111 during the pixel operation period of the shutter row in the vertical blanking period and the pixel operation period of the readout row. Functions as a potential setting means for setting the same level as the potential of the vertical signal line 111 in FIG.

  As described above, before the pixel operation of the shutter row starts in the vertical blanking period, the output voltage of the voltage source circuit 31, that is, the voltage near the reset level of the pixel 20 ′ is supplied to each of the vertical signal lines 111. In addition, the potential of the vertical signal line 111 during the pixel operation period of the shutter row can be made substantially equal to the potential of the vertical signal line 111 during the pixel operation period of the readout row.

  As a result, the potential change of the vertical signal line 111 immediately before the signal charge of the pixel 20 'in the shutter row is swept away or the potential of the vertical signal line 111 at the time of sweeping is different, so that the sweep is performed. Since the influence on the pixels 20 'in the shutter row, that is, the electrostatic capacitive coupling of the potential distribution in the pixels 20' and other subtle effects can be improved, the shutter step phenomenon can be prevented.

  In the above embodiment, the pixel 20 ′ is a four-transistor configuration having the selection transistor 26 in addition to the amplification transistor 24. However, the pixel 20 ′ is not limited to the four-transistor configuration. As in the embodiment, the amplifier transistor 24 may have at least the transfer transistor 22 and the reset transistor 23, such as a three-transistor structure that also serves as the pixel selection transistor 26.

[Third Embodiment]
FIG. 7 is a system configuration diagram showing the configuration of the MOS type solid-state imaging device according to the third embodiment of the present invention. In FIG. 7, the same parts as those in FIG.

  The MOS type solid-state imaging device 40 according to the present embodiment is configured to newly include a voltage sampling circuit 41 and a switch circuit 42 as components. As each pixel of the pixel array unit 11, a pixel 20 ′ having a four-transistor configuration is used as in the solid-state imaging device 30 according to the second embodiment. Of course, other pixel configurations such as a three-transistor configuration may be used. The rest of the configuration is basically the same as that of the solid-state imaging device 10 according to the first embodiment, and a description thereof will be omitted because it is redundant.

  The voltage sampling circuit 41 includes a sampling switch 411 having one end connected to a certain column of vertical signal lines 111, a hold capacitor 412 connected between the other end of the sampling switch 411 and the ground, and a buffer 413. The potential of a vertical signal line 111 in one column, specifically, the reset level output from the pixel 20 ′ to the vertical signal line 111 is sampled and held.

  The switch circuit 42 includes pixel columns of switches 421 connected between the output line 43 of the voltage sampling circuit 41 and the vertical signal line 111 of each column, and the reset level sampled and held by the voltage sampling circuit 41 is set. , And supplied to each of the vertical signal lines 111 before the pixel operation of the electronic shutter row starts.

  FIG. 8 shows pixel drive pulses in the solid-state imaging device 40 according to the third embodiment, that is, horizontal synchronization pulse Hsync, load pulse Load, drain voltage Drain, selection pulse Select, reset pulse Rst, transfer pulse Trf, sampling pulse Va, and switch. The timing relationship of the pulse Vb is shown.

  Here, the selection pulse Select, the reset pulse Rst, and the transfer pulse Trf are shown as a read row selection pulse R_Select, a reset pulse R_Rst and a transfer pulse R_Trf, a shutter row selection pulse S_Select, a reset pulse S_Rst, and a transfer pulse S_Trf.

  Next, the operation of the solid-state imaging device 40 according to the third embodiment will be described using the timing chart of FIG.

  First, the load pulse Load is activated, and in synchronization with this, the selection pulse R_Select is activated, whereby each pixel 20 ′ in the readout row is selected. Thereafter, when the reset pulse R_Rst of the read row becomes active, the reset transistor 22 is turned on and the FD unit 25 is reset. The potential of the FD unit 25 at the time of resetting is output to the vertical signal line 111 as a reset level by the amplification transistor 24.

  Next, when the sampling pulse Va becomes active, the voltage sampling circuit 41 samples the reset level output from the pixel 20 ′ to a certain vertical signal line 111 by the sampling switch 411 and holds it in the hold capacitor 412. To do.

  Next, when the transfer pulse R_Trf in the read row becomes active, the transfer transistor 22 is turned on, and the signal charge photoelectrically converted by the photodiode 21 is transferred to the FD unit 25. The potential of the FD unit 25 at the time of signal transfer is output to the vertical signal line 111 as a signal level by the amplification transistor 24.

  Thereafter, before the pixel operation of the shutter row at a different timing starts, the selection pulse R_Select is deactivated, so that each pixel 20 ′ in the readout row is disconnected from the vertical signal line 111.

  Next, immediately before the pixel operation of the electronic shutter row, the switch pulse Vb becomes active, so that each switch 421 of the switch circuit 42 is turned on, and the sampling potential in the voltage sampling circuit 41, that is, the reset level is vertical. This is supplied to each of the signal lines 111.

  Thereafter, the pixel operation period of the electronic shutter row starts. That is, when the reset pulse R_Rst for the readout row and the reset pulse S_Rst for the shutter row become active, the FD units 25 of both rows are reset. At this time, since the transfer pulse S_Trf is also active in the shutter row, the signal of the photodiode 21 is swept away.

  After the transfer pulse S_Trf for the shutter row becomes inactive, the reset pulse R_Rst for the readout row and the reset pulse S_Rst for the shutter row become inactive, and finally the switch pulse Vb becomes inactive.

  Thereafter, a horizontal video period in which the signal temporarily held in the column circuit 14 is scanned by the horizontal scanning circuit 15 is entered. Then, this operation is repeated while sequentially scanning the rows in the vertical direction.

  As is apparent from the above description of the operation, the voltage sampling circuit 41 and the switch circuit 42 use the potential of the vertical signal line 111 in the pixel operation period of the shutter row in the vertical blanking period and the vertical signal line in the pixel operation period of the readout row. It functions as a potential setting means for setting the same level as the potential of 111.

  As described above, the reset level output from the pixel 20 'to the vertical signal line 111 is sampled, and the sampling potential, that is, the reset level is set to the vertical signal before the pixel operation of the shutter row starts in the vertical blanking period. By supplying to each of the lines 111, the potential of the vertical signal line 111 in the pixel operation period of the shutter row can be made substantially equal to the potential of the vertical signal line 111 in the pixel operation period of the readout row.

  Thus, the potential of the vertical signal line 111 is not different from that in the vertical video period even in the vertical blanking period, and the influence exerted on the pixel 20 'in the shutter row that is being swept away, that is, the potential distribution in the pixel 20'. Since the electrostatic capacitive coupling and other subtle effects can be improved, the shutter step phenomenon can be prevented.

  In this embodiment, a voltage sampling circuit 41 is provided for a certain vertical signal line 111, and the potential of the vertical signal line 111 of a certain column is sampled and the sampling potential is applied to all the vertical signal lines 111. However, it is also possible to employ a configuration in which a voltage sampling circuit 41 is provided for each vertical signal line 111, the potential is sampled for each vertical signal line 111, and the sampling potential is supplied to the sampled vertical signal line 111. It is. According to this, for each vertical column, the potential of the vertical signal line 111 in the pixel operation period of the shutter row can be set in a form closer to the potential of the vertical signal line 111 in the pixel operation period of the readout row.

[Fourth Embodiment]
FIG. 9 is a system configuration diagram showing the configuration of the MOS type solid-state imaging device according to the fourth embodiment of the present invention. In FIG. 9, the same parts as those in FIG.

  The MOS type solid-state imaging device 50 according to the present embodiment includes a dummy pixel region 11A that does not contribute to imaging in addition to an effective pixel region that contributes to imaging in the pixel array unit 11, and the vertical scanning circuit 12 includes the dummy pixel region. 11A includes a dummy pixel scanning circuit 12A that scans each row of 11A. In the dummy pixel region 11A, one or more dummy pixels exist as rows that do not affect the imaging result during the period from the end of the vertical scanning of the readout row to the start of the next scanning.

  As each pixel of the pixel array unit 11, a pixel 20 having a three-transistor configuration is used as in the solid-state imaging device 10 according to the first embodiment. However, it is needless to say that other pixel configurations such as a 4-transistor configuration may be used. The rest of the configuration is basically the same as that of the solid-state imaging device 10 according to the first embodiment, and a description thereof will be omitted because it is redundant.

  FIG. 10 is a timing chart for explaining the operation of the MOS type solid-state imaging device 50 according to the present embodiment. As is clear from this timing chart, in the MOS type solid-state imaging device 50 according to the present embodiment, driving for selecting each dummy pixel in the dummy pixel region 11A in units of rows is performed in the vertical blanking period.

  That is, unlike the prior art according to Patent Document 1, dummy pixel rows are also provided in selected rows. The signal output from each dummy pixel in the dummy pixel row is equivalent to the signal output from each pixel 20 in the normal readout row. Therefore, the potential of the vertical signal line 11 does not change between the vertical blanking period and the vertical video period.

  As described above, one or more dummy pixel regions 11A are provided in the pixel array unit 11, and a dummy pixel row that does not affect the imaging result is provided until the next scanning starts after the readout row has been vertically scanned. By selecting and continuing the reading operation, the potential of the vertical signal line 11 does not change between the vertical blanking period and the vertical video period, and the influence exerted on the pixels 20 in the shutter row that is being swept away, that is, in the pixels 20 Since the electrostatic capacitive coupling of the potential distribution and other subtle effects can be improved, the shutter step phenomenon can be prevented.

[Application example]
The solid-state imaging devices 10, 30, 40, and 50 according to the first, second, third, and fourth embodiments described above are video cameras, digital still cameras, and camera modules for mobile devices such as mobile phones. The imaging apparatus is suitable for use as the imaging device.

  FIG. 11 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 11, the imaging apparatus according to the present example includes an optical system including a lens 61, an imaging device 62, a camera signal processing circuit 63, and the like.

  The lens 61 forms image light from the subject on the imaging surface of the imaging device 62. The imaging device 62 outputs an image signal obtained by converting the image light imaged on the imaging surface by the lens 61 into an electrical signal in units of pixels. As the imaging device 62, the solid-state imaging devices 10, 30, 40, and 50 according to the first, second, third, and fourth embodiments described above are used. The camera signal processing unit 63 performs various signal processes on the image signal output from the imaging device 62.

  As described above, in an imaging apparatus such as a video camera, an electronic still camera, and a camera module for mobile devices such as a mobile phone, the first, second, third, and fourth embodiments described above as the imaging device 62 are used. By using the solid-state imaging devices 10, 30, 40, and 50, the solid-state imaging devices 10, 30, 40, and 50 prevent the phenomenon of the shutter step that occurs due to a slightly different signal sweep amount. Therefore, there is an advantage that the image quality of the captured image can be further improved.

1 is a system configuration diagram illustrating a configuration of a MOS type solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows an example of the circuit structure of a pixel. 6 is a timing chart illustrating a timing relationship of pixel drive pulses in the solid-state imaging device according to the first embodiment. It is a system block diagram which shows the structure of the MOS type solid-state imaging device concerning 2nd Embodiment of this invention. It is a circuit diagram which shows the other example of the circuit structure of a pixel. It is a timing chart which shows the timing relationship of the pixel drive pulse in the solid-state imaging device concerning a 2nd embodiment. It is a system block diagram which shows the structure of the MOS type solid-state imaging device concerning 3rd Embodiment of this invention. It is a timing chart which shows the timing relationship of the pixel drive pulse in the solid-state imaging device concerning a 3rd embodiment. It is a system block diagram which shows the structure of the MOS type solid-state imaging device concerning 4th Embodiment of this invention. It is a timing chart for explanation of operation of a MOS type solid-state imaging device concerning a 4th embodiment. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. 1 is a system configuration diagram showing a basic configuration of a CMOS type solid-state imaging device. It is a timing chart which shows the scanning timing of the pixel array part which concerns on a prior art example. It is a circuit diagram which shows an example of a structure of a pixel. It is a timing chart which shows the timing relationship of the pixel drive pulse which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 30, 40, 50 ... MOS type solid-state imaging device, 11 ... Pixel array part, 11A ... Dummy pixel area, 12 ... Vertical scanning circuit, 12A ... Dummy pixel scanning circuit, 13 ... Current source, 14 ... Column circuit, 15 ... horizontal scanning circuit, 16 ... output circuit, 17 ... control circuit, 20, 20 '... pixel, 21 ... photodiode, 22 ... transfer transistor, 23 ... reset transistor, 24 ... amplification transistor, 25 ... FD section (floating diffusion section) , 26 ... selection transistor, 31 ... voltage source circuit, 32 ... changeover switch, 33 ... switch circuit, 41 ... voltage sampling circuit, 42 ... switch circuit

Claims (7)

A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and signal lines are wired for each pixel column with respect to the matrix-like pixel arrangement;
The pixel operation period of the shutter row is different from the pixel operation period of the readout row while sequentially scanning the shutter row that resets the signal charge of the pixel and the readout row that reads out the signal charge of the pixel with respect to the pixel array unit. A scanning circuit performed in
And a potential setting means for setting the potential of the signal line in the pixel operation period of the shutter row in the vertical blanking period to the same level as the potential of the signal line in the pixel operation period of the readout row. Imaging device. The pixel includes a transfer transistor that transfers charge from the photoelectric conversion element to a voltage conversion unit and a reset transistor that resets the voltage conversion unit,
The potential setting means operates the current source connected to each of the signal lines over the pixel operation period of the readout row and the pixel operation period of the shutter row, and turns on the reset transistor of the shutter row, The solid-state imaging device according to claim 1, wherein the transfer transistor is turned on after being delayed by a predetermined period. The potential setting means includes a voltage source circuit that generates a voltage near a reset level output from the pixel after the reset transistor is turned on, and the voltage before the pixel operation of the shutter row starts in a vertical blanking period. The solid-state imaging device according to claim 1, wherein an output voltage of a source circuit is supplied to each of the signal lines. The potential setting means has a sampling circuit that samples a reset level output from the pixel after the reset transistor is turned on, and before the pixel operation of the shutter row starts in the vertical blanking period, the sampling potential of the sampling circuit The solid-state imaging device according to claim 1, wherein the signal line is supplied to each of the signal lines. The pixel array unit has a dummy pixel region that does not affect the imaging result,
2. The solid state according to claim 1, wherein the potential setting unit selects a dummy pixel row in the dummy pixel region and continues the reading operation for a period until the next scanning starts after the scanning of the reading row is completed. Imaging device. A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and signal lines are wired for each pixel column with respect to the matrix-like pixel arrangement;
The pixel operation period of the shutter row is different from the pixel operation period of the readout row while sequentially scanning the shutter row that resets the signal charge of the pixel and the readout row that reads out the signal charge of the pixel with respect to the pixel array unit. A method of driving a solid-state imaging device comprising:
A driving method of a solid-state imaging device, wherein the potential of the signal line in the pixel operation period of the shutter row in the vertical blanking period is set to the same level as the potential of the signal line in the pixel operation period of the readout row. A solid-state imaging device;
An optical system for forming image light from a subject on the imaging surface of the solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and signal lines are wired for each pixel column with respect to the matrix-like pixel arrangement;
The pixel operation period of the shutter row is different from the pixel operation period of the readout row while sequentially scanning the shutter row that resets the signal charge of the pixel and the readout row that reads out the signal charge of the pixel with respect to the pixel array unit. A scanning circuit performed in
An image pickup apparatus comprising: a potential setting unit configured to set the potential of the signal line in the pixel operation period of the shutter row in the vertical blanking period to the same level as the potential of the signal line in the pixel operation period of the readout row. .

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