JP2006350965A - Microprocessor and electronic apparatus equipped with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance of an entire system by optimizing access timing of an external bus interface circuit for each external device even when one external device selection signal is shared by a plurality of external devices. <P>SOLUTION: An address space corresponding to one chip select signal is divided into a plurality of address spaces at a CS address space setting register section 22. A timing controller 31 enables a bus setting register section 30 to access the external devices from access timing to the external device of an external bus I/F circuit 23 set for each address space divided in the CS address space setting register section 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a microprocessor including a central processing unit that executes instructions and an external bus interface circuit that performs external bus control based on instruction execution by the central processing unit. The present invention relates to a microprocessor suitable for connecting more external devices than the number of external device selection signals included in a processor, and an electronic apparatus including the microprocessor.

  2. Description of the Related Art Conventionally, a microprocessor is mounted on an electronic device such as a mobile phone, and various communication devices connected to the microprocessor are controlled to realize communication operations and application functions of the mobile phone.

  Among the devices connected to the microprocessor, access to the external device connected via the external bus interface circuit is in accordance with the address space accessed by the central processing unit (hereinafter referred to as CPU) from the microprocessor. By outputting an external device control signal (hereinafter referred to as a chip select signal), an external device to be accessed is designated.

  However, in recent years, with the increase in functionality of mobile phone devices, the number of external devices connected to the microprocessor via the external bus interface circuit has increased, and there are cases where the number of chip select signal terminals of the microprocessor increases. In such a case, a plurality of external devices share one chip select signal terminal. Note that sharing a chip select signal terminal means sharing one chip select signal.

  FIG. 14 shows a system configuration example of a conventional mobile phone in which one chip select signal is shared by a plurality of external devices. In this example, the microprocessor 101 has three chip select signals CS1 to CS3, and three CS decode circuits 113 to 115 are arranged corresponding to these three chip select signals CS1 to CS3. Through the CS decode circuits 113 to 115, six external devices, a program ROM 107, a data ROM 108, a memory RAM 109, a tone generator IC 110, a display IC 111, and an application IC 112, are connected to the microprocessor 101.

  The microprocessor 101 includes a central processing unit (hereinafter referred to as CPU) 120 that executes instructions and an external bus I / F circuit 123 that performs external bus control. These are mounted on one semiconductor chip. ing.

  The external bus interface circuit (hereinafter referred to as an external bus I / F circuit) 123 includes an address decoder unit 121, a timing controller 150, a bus setting register unit 130, and an interface (I / F) unit 151, and is necessary for external device control. This is a part that controls input / output of each control signal such as an address / data signal (Address in the figure), the chip select signals CS1 to CS3, a read signal, and a write signal.

  The address decoder unit 121 is a part that defines an address space for the chip select signals CS1 to CS3 of the microprocessor 101, and an address that the CPU 120 that executes an instruction tries to access is an address space that is defined by the address decoder unit 121. If it is, the chip select signal given to the corresponding CS (chip select) address space in the chip select signals CS1 to CS3 is asserted (set to the active state).

  The bus setting register unit 130 has three bus setting registers for CS1 to CS3 corresponding to the chip select signals CS1 to CS3, and the chip select asserted by the address decoder unit 121 by the timing controller 150 is provided. The output of each control signal is controlled according to the timing set in the bus setting register corresponding to the signal.

  The I / F unit 151 outputs chip control signals CS1 to CS3, address / data signals, read signals, write signals, and other control signals, and address signals ADD_20 to ADD_22 input to the CS decode circuits 113 to 115. And an input / output unit that enables the input of a data signal from an external device.

  In the example of FIG. 14, among the six external devices described above, the program ROM 107 and the data ROM 108 are connected to the CS decode circuit 113 to which the chip select signal CS1 is input and share the chip select signal CS1. Yes. The memory RAM 109 and the sound source IC 110 are connected to the CS decode circuit 114 to which the chip select signal CS2 is input and share the chip select signal CS2. The display IC 111 and the application IC 112 receive the chip select signal CS3. The chip select signal CS3 is shared by the CS decode circuit 115.

  For example, the CS decode circuit 113 will be described. The CS select circuit CS1 and the address signal ADD_20 are input to the CS decode circuit 113, and a chip select signal terminal T1 and a chip select signal terminal T2 are provided as output terminals. Yes. Among these, the chip select signal terminal T1 is connected to a chip select signal terminal (not shown) of the program ROM 107, and the chip select signal terminal T2 is connected to a chip select signal terminal (not shown) of the data ROM 108. Thus, the output from the chip select signal terminal T1 or T2 is input to each chip select signal terminal of the program ROM 107 and the data ROM 108 instead of the chip select signal CS1.

  The CS decode circuit 113 asserts either the chip select signal terminal T1 or the chip select signal terminal T2 in accordance with the input of the chip select signal CS1 and the address signal ADD_20 from the microprocessor 101. In this example, when the chip select signal terminal T1 is asserted, the program ROM 107 connected to the chip select signal terminal T1 is activated, and the CPU 120 accesses the program ROM 107. Conversely, when the chip select signal terminal T2 is asserted, the data ROM 108 connected to the chip select signal terminal T2 is activated, and the CPU 120 accesses the data ROM 108.

  The same applies to the CS decode circuits 114 and 115. In this way, one chip select signal can be shared by a plurality of external devices.

  On the other hand, in Patent Document 1, two devices having different synchronization clock frequencies, for example, a high-speed device such as SDRAM corresponding to a synchronization clock of about 150 MHz and a low-speed device requiring a synchronization clock of about 20 MHz are used as a microprocessor. When connecting, supply the necessary clock signals using individual clock wirings, and switch the synchronization signal of the external bus interface circuit inside the microprocessor according to the external access target device or address space by the microprocessor It is disclosed that an external device to be accessed is connected to a microprocessor by control.

Furthermore, in recent years, Synchronous burst pseudo SRAMs such as BURST Cellular RAM can be accessed in both Synchronous write and Asynchronous write access modes for write access when accessing the pseudo SRAM when used in Synchronous mode. Has been developed. Since a conventional microprocessor can access an external device only in one access format, when such a pseudo SRAM is used as an external device, the write access format of the memory takes into consideration the usage method and the synchronous clock frequency. It is set to access with either access method of Synchronous burst write or Asynchronous write.
JP 2002-41452 A (published on February 8, 2002)

  However, in the conventional microprocessor, the bus setting register provided in the bus setting register unit 130 of the external bus I / F circuit 123 is one for one chip select signal. Therefore, as in the system shown in FIG. 14, when the same chip select signal is shared by a plurality of external devices, the optimum access timing cannot be set for each external device. The same timing is used between devices sharing a signal. In addition, in that case, the access timing must be set according to the device having the slowest access speed among a plurality of devices sharing the chip select signal. Therefore, for each external device without sharing the chip select signal. Therefore, the performance of the entire system cannot be denied compared to the case where the optimum access timing can be set.

  Further, as described above, in recent years, in the synchronous burst pseudo SRAM such as the BURST Cellular RAM, a memory device that can be accessed in both the synchronous write mode and the asynchronous write mode when writing in the synchronous mode has been developed. However, in the conventional microprocessor, since one chip select signal can be accessed only in one access format, when the above described Synchronous burst pseudo SRAM is used as an external device and accessed by Synchronous write, it is input to the Synchronous burst pseudo SRAM. If the synchronous clock frequency to be used is high, the performance can be improved by Synchronous write, but if the synchronous clock frequency input to the Synchronous burst pseudo SRAM is low, the performance will be lower than the case of Asynchronous write access. There is. This is because, when accessing with Synchronous write, in the address space with many random writes, the time until the first access of Synchronous write is longer than that of Asynchronous write access.

  The present invention has been made in view of the above problems, and the first object is to optimize each external device even when more external devices than the number of external device selection signals are connected. A second object of the present invention is to provide a microprocessor capable of setting the timing of an external bus interface circuit, and a second object is to further provide an access type when an external device accessible in a plurality of access types is connected. An object is to provide a microprocessor that can be switched.

  In order to solve the above problems, a microprocessor according to the present invention includes a central processing unit that executes instructions and an external bus interface circuit that performs external bus control based on instruction execution by the central processing units. The external bus interface circuit is an external device selection signal activation means for activating an external device selection signal corresponding to an address accessed by the central processing unit from a plurality of external device selection signals; Address space dividing means for further dividing the address space given to the external device selection signal into a plurality of address spaces; and timing setting means for setting the access timing of the external bus interface circuit to the external device for the address space; It is characterized by having. Here, as a method of dividing the address space given to the external device selection signal into a plurality of address spaces, for example, an address can be used.

  According to the above configuration, the address space dividing unit divides the address space given to the external device selection signal into a plurality of address spaces, and the timing setting unit connects the external device to each of the divided address spaces. Since the access timing of the external bus interface circuit necessary for the external device is set, a plurality of access timings of the external bus interface circuit can be set within the address space given to the external device selection signal. Therefore, even when one external device selection signal is shared by a plurality of external devices, it is possible to set the access timing of the external bus interface circuit optimized for each external device. As a result, the performance of the entire system including the microprocessor can be improved.

  In the microprocessor of the present invention, the external bus interface circuit further includes an access format setting means for setting an access format of the external bus interface circuit to the external device for the address space, and a plurality of access formats. It is also possible to connect an external device that can be accessed through the network.

  According to this, since the access format setting means sets the access format (for example, Synchronous or Asynchronous access) for the address space obtained by further dividing the address space given to the external device selection signal. Within the address space given to the device selection signal, the access format can be changed depending on the address space accessed by the central processing unit. Therefore, for example, for devices that can access both asynchronous write and synchronous write, such as writing in synchronous mode such as Cellular RAM, continuous write can be performed according to its usage and synchronous clock frequency. Since it is possible to access the frequently occurring address space with Synchronous write and to access the address space where continuous writes are not often seen with Asynchronous write, it is possible to further improve the performance of the entire system equipped with a microprocessor. become.

  In the microprocessor of the present invention, the external bus interface circuit further includes clock frequency setting means for setting a frequency of a synchronous clock of the external bus interface circuit for each address space. it can.

  According to this, since the clock frequency setting means sets the synchronous clock frequency of the external interface circuit for the address space obtained by further dividing the address space given to the external device selection signal, the synchronous clock frequency Even if one external device selection signal is shared by different external devices, it is possible to connect each with an optimum synchronous clock frequency. Therefore, it is possible to further improve the performance of the entire system including the microprocessor.

  In this case, in addition to the clock frequency setting means, the external bus interface circuit preferably has a clock phase setting means for setting the phase of the synchronous clock of the external bus interface circuit for each address space. Thus, not only the frequency of the synchronous clock but also the phase of the synchronous clock can be changed, and a plurality of different types of devices can be connected by one external device selection signal.

  In the microprocessor of the present invention, the external bus interface circuit can be set to use / unuse the wait signal terminal, and the weight of the external bus interface circuit can be set as an external wait signal input from an external device. It is also possible to have weight setting means for setting the address spaces based on the above.

According to this, the weight setting means converts the weight of the external bus interface circuit to the external wait signal input from the external device with respect to the address space obtained by further dividing the address space given to the external device selection signal. Therefore, even if different external weight signals are inputted to one external device selection signal in the address space, each can be accurately detected, and one external device selection signal can be detected as an external device having a different weight signal specification. It becomes possible to share in. Therefore, the performance of the entire system including the microprocessor can be further improved. The electronic device of the present invention is connected to the microprocessor of the present invention described above and the microprocessor via an external bus interface circuit. And an external device having at least an external device, and an electronic apparatus with excellent performance of the entire system can be obtained.

  A microprocessor according to the present invention is a microprocessor including a central processing unit that executes instructions and an external bus interface circuit that performs external bus control based on instruction execution by the central processing unit. The interface circuit includes an external device selection signal activating means for activating an external device selection signal corresponding to an address accessed by the central processing unit from a plurality of external device selection signals, and an address given to the external device selection signal An address space dividing means for further dividing the space into a plurality of address spaces, and a timing setting means for setting the access timing of the external bus interface circuit to the external device in the address space. Here, as a method of dividing the address space given to the external device selection signal into a plurality of address spaces, for example, an address can be used.

  As a result, even when one external device selection signal is shared by a plurality of external devices, it is possible to set the access timing of the external bus interface circuit optimized for each external device, There is an effect that the performance of the entire system including the microprocessor can be improved.

  In the microprocessor of the present invention, the external bus interface circuit further includes an access format setting means for setting an access format of the external bus interface circuit to the external device for the address space, and a plurality of access formats. It is also possible to connect an external device that can be accessed by the mobile phone. With such a configuration, even if the external device supports a plurality of access formats, one external device can be used. It becomes possible to select the optimum access format for each access by the selection signal, and it is possible to improve the performance of the entire system.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a simplified block diagram showing a system using a microprocessor 1 according to an embodiment of the present invention. FIG. 1 illustrates a system realized by an electronic device such as a mobile phone.

  A wireless unit 2, a power supply unit 3, a battery 4, an operation unit 5, an audio unit 6, and an external I / F 16 are connected to the microprocessor 1. The voice unit 6 includes a microphone, a speaker, and the like, and inputs and outputs voice during a call. The wireless unit 2 performs processing related to transmission / reception of audio data, image data, and the like performed via the base station. For example, an analog signal input from a microphone is encoded into digital audio data and transmitted by the wireless unit 2. On the other hand, the audio data received by the wireless unit 2 from the call destination via the base station is decoded and output from the speaker. The external I / F 16 is an interface for connecting a PC or the like to a mobile phone via a cable or the like.

  The microprocessor 1 includes a program ROM 7 for storing a program, a data ROM 8 for storing data, an external RAM 9 as a work area, a sound source IC 10, a display IC 11, and an application IC 12. 1 is connected to a bus via an external bus interface circuit (hereinafter referred to as an external bus I / F circuit) 23, which will be described later.

  The program ROM 7 stores a control program such as a system program or an application program, and the microprocessor 1 operates based on the control program stored in the program ROM 7. The data ROM 8 stores data necessary for system control, image data, and the like, and the RAM 9 is used as a work area during system operation. The sound source IC 10 is an IC for reproducing music data and the like, the display IC 11 is an IC for displaying the result of operation input in the operation unit 5 on the screen, and the application IC 12 is an application function of a mobile phone such as a camera. IC.

  Although the configuration of the microprocessor 1 will be described later, the microprocessor 1 outputs an external device control signal (hereinafter referred to as a chip select signal) in accordance with the address space to be accessed, and a plurality of bus-connected external devices. Specify an external device to access from among Since the microprocessor 1 outputs three types of CS1 to CS3 as chip select signals, it is necessary to share one chip select signal between the two external devices in order to connect the six external devices described above. Here, CS decode circuits 13-15 are arranged corresponding to the respective chip select signals CS1-CS3, and external devices are connected via these CS decode circuits 13-15.

  Specifically, the program ROM 7 and the data ROM 8 are connected to the CS decode circuit 13 to which the chip select signal CS1 is input, and the external RAM 9 and the sound source IC 10 are connected to the CS decode circuit 14 to which the chip select signal CS2 is input. A display IC 11 and an application IC 12 are connected to a CS decode circuit 15 to which the chip select signal CS3 is input.

  Focusing on the CS decode circuit 13 and more specifically, the chip select signal terminal (not shown) of the program ROM 7 is connected to the chip select signal terminal T1 of the CS decode circuit 13, and the chip select signal terminal of the CS decode circuit 13 is connected. A chip select signal terminal (not shown) of the data ROM 8 is connected to T2. Thereby, instead of the chip select signal CS1 from the microprocessor 1, the output of the chip select signal terminal T1 or the chip select signal terminal T2 of the CS decode circuit 13 is input to each chip select signal terminal of the program ROM 7 and the data ROM 8. Is done.

  In addition to the chip select signal CS1 from the microprocessor 1, an address signal ADD_20 is also input to the CS decode circuit 13. According to these input signals, the CS decode circuit 13 receives the chip select signal terminal T1 or T2. Assert one of the following. When the chip select signal terminal T1 is asserted, the program ROM 7 connected to the chip select signal terminal T1 is activated, and the CPU 20 accesses the program ROM 7. Similarly, when the chip select signal terminal T2 is asserted, the data ROM 8 connected to the chip select signal terminal T2 is activated, and the CPU 20 accesses the data ROM 8.

  Although the CS decode circuit 13 has been described here, the same applies to the external RAM 9 and sound source IC 10 connected to the CS decode circuit 14, and the display IC 11 and application IC 12 connected to the CS decode circuit 15. That is, the CS decode circuit 14 asserts either the chip select signal terminal T1 or the chip select signal terminal T2 according to the input chip select signal CS2 and the address signal ADD_21, and the chip select signal terminal T1 is asserted. When the external RAM 9 is activated and the external RAM 9 is accessed and the chip select signal terminal T2 is asserted, the sound source IC is activated and the sound source IC is accessed. Similarly, the CS decode circuit 15 asserts either the chip select signal terminal T1 or the chip select signal terminal T2 according to the input chip select signal CS3 and the address signal ADD_22, and the chip select signal terminal T1 is asserted. When the display IC is activated and the sound source IC is accessed, and the chip select signal terminal T2 is asserted, the application IC is activated and the application IC is accessed.

  On the other hand, the microprocessor 1 has one central processing unit (hereinafter referred to as a CPU) 20 that executes instructions and one external bus I / F circuit 23 that controls an external bus based on instruction execution by the CPU 20. The semiconductor chip is mounted on the semiconductor chip.

  The external bus I / F circuit 23 includes an address decoder unit 21, a CS address space setting register unit 22, a timing controller 31, a bus setting register unit 30, and an interface (I / F) unit 32, which are necessary for external device control. This is a part for controlling input / output of an address / data signal (Address in the figure), the chip select signals CS1 to CS3, a read signal, a write signal, an address valid signal, a clock signal, a wait signal, and the like.

  The address decoder unit 21 is a part that defines a CS address space for the chip select signals CS1 to CS3 of the microprocessor 1, and constitutes an external device selection signal activation means in the present invention. In the address decoder unit 21, the address to which the CPU 20 is to access based on the address signal sent from the CPU 20 through the address bus (Address bus in the figure) is the address of CS1 to CS3 defined by the address decoder unit 21. If it is in the space, the chip select signal given to the corresponding CS address space is asserted (set to the active state).

  The CS address space setting register unit 22 sets the address spaces of CS1 to CS3 defined by the address decoder unit 21 to be further divided into a plurality of address spaces, and includes a plurality of address space setting registers. Here, since each of the address spaces CS1 to CS3 defined by the address decoder unit 21 is divided into two address spaces, CS1-1, CS1-2, CS2-1, CS2-2, A total of six address space setting registers CS3-1 and CS3-2 are provided.

  For example, if the address space of CS1 to CS3 is allocated by the address decoder unit 21 as shown in FIG. 2, the CS address space setting register unit 22 sets the address space of CS1 to CS1 if the address signal ADD20 = 0. The address space of CS1 is further divided on the basis of the address signal ADD20, such as the address space of -1 and the address space of CS1-2 if ADD20 = 1. The same applies to each address space of CS2 and CS3. The address space of CS2 is divided as the address space of CS2-1 when ADD21 = 0, and the address space of CS2-2 when ADD21 = 1, and the address space of CS3 is If ADD22 = 0, the address space is CS3-1, and if ADD22 = 1, the address space is CS3-2.

  The bus setting register unit 30 includes a bus setting register that sets the output timing of a control signal to an external device for each address space divided by the CS address space setting register unit 22. 1, CS1-2, CS2-1, CS2-2, CS3-1, CS3-2 corresponding to each address space, for CS1-1, for CS1-2, for CS2-1, for CS2-2 , CS3-1 and CS3-2 for a total of six bus setting registers.

  These bus setting registers provided in the bus setting register unit 30 can set not only the number of waits but also the output timing of each control signal. As a specific example of setting parameters, as shown in FIG. 3A, at the time of reading, between address and CS (tsACS1, thACS1), between CS and RD (tsCSRD, thCSRD), RD = L section (twlRD) As shown in FIG. 4B, at the time of writing, parameters are between address-CS (tsACS2, thACS2), between CS-WR (tsCSWR, thCSWR), WR = L section (twlWR), and the like.

  The timing controller 31 is a control center in the external bus I / F circuit 23, and an address signal is input from the CPU 20 through the address bus in the same manner as the address decoder unit 21. The timing controller 31 refers to the CS address space setting register unit 22 based on the address to be accessed by the CPU 20 and determines which address space set by the CS address space setting register unit 22 corresponds to the address. Based on the determination result (bus setting register selection signal), the corresponding bus setting register in the bus setting register unit 30 is selected, and a control signal is output to the external device at the timing set in the register. The CS address space setting register section 22 and the timing controller 31 constitute address space dividing means in the present invention, and the bus setting register section 30 and the timing controller 31 constitute the timing setting means of the present invention.

  The I / F unit 32 outputs chip control signals CS1 to CS3, control signals such as address / data signals, read signals, and write signals, and address signals ADD_20 to ADD_22 input to the CS decode circuits 13 to 15. And an input / output unit that enables the input of a data signal from an external device.

  Thus, even when the external bus I / F circuit 23 accesses the same CS address space, the CS address space setting register unit 22 indicates the timing of each control signal output to the external device by the address to which the CPU 20 tries to access. It is possible to change for each address space set in step 1, and for each bus setting register for CS1-1, CS1-2, CS2-1, CS2-2, CS3-1, and CS3-2 The various control signals can be output in accordance with the set timing.

  By configuring the microprocessor 1 in such a configuration, for example, in the system of FIG. 1, when the CPU 20 accesses the address 0x00001000 (CS1-1 address space) which is the address space of CS1, the timing controller 31 performs CS With reference to the address space setting register unit 22, it is determined that the access destination of the CPU 20 is the address space of CS1-1. Based on this determination result (bus setting register selection signal), CS1 in the bus setting register unit 30 The -1 bus setting register is selected, and the I / F unit 32 outputs various control signals to the device according to the timing set in the register.

  On the other hand, at this time, by inputting the address ADD20 = 0 and the active signal of the chip select signal CS1, only the output of the chip select signal terminal T1 of the CS decode circuit 13 to which the chip select signal terminal of the program ROM 7 is connected is asserted. Is done. As a result, the program ROM 7 is activated, and the CPU 20 accesses the program ROM 7. The access timing at this time is the timing set in the CS1-1 bus setting register.

  Further, when the CPU 20 accesses the address 0x00101000 (CS1-2 address space) which is the CS1 address space, the timing controller 31 refers to the CS address space setting register unit 22 and the access destination of the CPU 20 is CS1. -2 address space, the bus setting register for CS1-2 in the bus setting register unit 30 is selected based on the determination result (bus setting register selection signal), and the I / F unit 32 Various control signals are output to the external device in accordance with the timing set in the register.

  On the other hand, at this time, by inputting the address ADD20 = 1 and the active signal of the chip select signal CS1, only the output of the chip select signal terminal T2 of the CS decode circuit 13 to which the chip select signal terminal of the data ROM 8 is connected is asserted. Is done. As a result, the data ROM 8 is activated, and the CPU 20 accesses the data ROM 8. The access timing at this time is the timing set in the CS1-2 bus setting register.

  FIG. 4 shows a timing example of each control signal at this time. In FIG. 4, even in the access within the address space of the same chip select signal CS1, in the CS1-1 address space where the chip select signal terminal T1 is asserted, the interval between the fall of the chip select signal CS1 and the fall of the read signal is There is 1 CLK of the internal CLK of the external bus I / F circuit 23, the low pulse period of the read signal is 4 CLK, and the rise of the read signal and the rise of the chip select signal CS1 are set at the same time. Furthermore, in the address space of CS1-2 where the chip select signal terminal T2 is asserted, the fall interval of the chip select signal CS1 and the fall interval of the read signal are equal to 2CLK of the internal CLK of the external bus I / F circuit 23. The low pulse period of the read signal is set to 3 CLK, and the read signal rising edge and the rising interval of the chip select signal CS1 are set to 2 CLK.

  In this manner, the microprocessor 1 can access a plurality of devices (here, the program ROM 7 and the data ROM 8) connected to the chip select signal CS1 at optimized timings.

  Although no further detailed description will be given, the timing of the control signal in each address space of CS2-1 and CS2-2 when the CPU 20 accesses the address space of the chip select signal CS2 and the CS decoding circuit 14 The operation, the timing of the control signal in each address space of CS3-1 and CS3-2 when the CPU 20 accesses the address space of CS3, and the operation of the CS decode circuit 15 are also described above. 2 operates based on the same operation principle as the timing of the control signal in each address space 2 and the operation of the CS decode circuit 13. Therefore, the microprocessor 1 can access each external device connected via the external bus I / F circuit 23 at an optimized timing.

  As described above, according to the microprocessor 1 of the present embodiment, even when accessing the address space in the same chip select signal, it becomes possible to access the external device with different timing settings depending on the address space. . Therefore, even if multiple external devices are connected to a single chip select signal, it is not necessary to access all devices with timing settings that match the slowest access speed among the connected devices. On the other hand, it is possible to access at an optimized timing, so that the performance of the entire system can be improved.

[Embodiment 2]
Another embodiment of the present invention will be described below with reference to FIGS.

  In the first embodiment, the case where the address space specified by the chip select signal is divided into a plurality of address spaces and a bus setting register is provided for each address space has been described. In contrast, in the present embodiment, a case where a clock setting register for setting the synchronous clock frequency of the external bus I / F circuit is provided for each address space obtained by further dividing the address space specified by the chip select signal. To do.

  FIG. 5 is a block diagram schematically showing a system using the microprocessor 51 according to this embodiment. The difference from the block diagram of the first embodiment shown in FIG. 1 is that the microprocessor 51 includes an external bus I / F circuit 33 instead of the external bus I / F circuit 23. The program ROM 7 uses a synchronous burst read accessible flash memory (clock frequency 52 MHz), and the data ROM 8 uses a synchronous burst read accessible flash memory (clock frequency 26 MHz).

  The external bus I / F circuit 33 has a configuration in which a clock setting register unit 34 is newly provided in the external bus I / F circuit 23 described above. The clock setting register unit 34 includes a clock setting register that sets the frequency of the synchronous clock signal of the external bus I / F circuit 33 for each address space divided by the CS address space setting register unit 22. Then, corresponding to each address space of CS1-1, CS1-2, CS2-1, CS2-2, CS3-1, CS3-2, for CS1-1, for CS1-2, for CS2-1, A total of six clock setting registers for CS2-2, CS3-1, and CS3-2 are provided.

  As in the first embodiment, the timing controller 31 refers to the CS address space setting register unit 22 based on the address to be accessed by the CPU 20, and to which address space set by the CS address space setting register unit 22 Determine whether the address is applicable. In this embodiment, the timing controller 31 selects the corresponding bus setting register in the bus setting register unit 30 based on the determination result (setting register selection signal), and the corresponding clock in the clock setting register unit 34. A setting register is selected, and a control signal is output to an external device at a timing set in the selected bus setting register, using a synchronous clock having a frequency set in the selected clock setting register. That is, the clock setting register unit 34 and the timing controller 31 constitute clock frequency setting means in the present invention.

  In the present embodiment, the CS1-1 clock setting register of the clock setting register unit 34 sets the synchronous clock frequency of the external bus I / F circuit 33 when accessing the CS1-1 address space allocated to the program ROM 7. Is set to 52 MHz, and the CS1-2 clock setting register of the clock setting register unit 34 sets the synchronous clock frequency of the external bus I / F circuit 33 when accessing the address space of the CS1-2 assigned to the data ROM 8 Is set to 26 MHz.

  By configuring the microprocessor 51 in such a configuration, for example, in the system of FIG. 5, the CPU 20 is a CS1 address space, and among them, a program assigned to the CS1-1 address space (address ADD20 = 0). When trying to access the ROM 7, the timing controller 31 refers to the CS address space setting register unit 22 to determine that the access destination of the CPU 20 is the address space of the CS 1-1, and this determination result (bus setting register selection) Signal), the CS1-1 bus setting register in the bus setting register unit 30 is selected, and the CS1-1 clock setting register in the clock setting register unit 34 is selected. As a result, the synchronous clock frequency of the external bus I / F 33 of the microprocessor 51 becomes 52 MHz set by the CS1-1 clock setting register of the clock setting register unit 34, and the I / F unit 32 uses the 52 MHz synchronous clock signal. In accordance with the timing set in the address space of CS1-1, various control signals are output to the external device.

  As in the first embodiment, when the address signal ADD20 = 0 and the active signal of the chip select signal CS1 are input, the chip select signal terminal T1 of the CS decode circuit 13 to which the chip select signal terminal of the program ROM 7 is connected. As a result, the program ROM 7 is activated, and the CPU 20 accesses the program ROM 7.

  Further, when the CPU 20 tries to access the data ROM 8 allocated to the address space of CS1 and among them, the address space of CS1-2 (address ADD20 = 1), the timing controller 31 sets the CS address space setting register. Referring to section 22, it is determined that the access destination of CPU 20 is the address space of CS1-2. Based on the determination result (bus setting register selection signal), the bus for CS1-2 in bus setting register section 30 is determined. While the setting register is selected, the CS1-2 clock setting register of the clock setting register unit 34 is selected. As a result, the synchronization clock frequency of the external bus I / F 33 of the microprocessor 51 becomes 26 MHz set by the CS1-2 clock setting register of the clock setting register unit 34, and the I / F unit 32 uses the 26 MHz synchronization clock signal. In accordance with the timing set in the address space of CS1-2, various control signals are output to the external device.

  As in the first embodiment, when the address signal ADD20 = 1 and the active signal of the chip select signal CS1 are input, the chip select signal terminal T2 of the CS decode circuit 13 to which the chip select signal terminal of the data ROM 8 is connected. As a result, the data ROM 8 is activated, and the CPU 20 accesses the data ROM 8.

  FIG. 6 shows changes in each control signal and address at this time. The ADV signal in FIG. 6 is a signal that informs the external device of the timing at which the microprocessor 51 latches the address signal (Address).

  As described above, according to the present embodiment, for a plurality of devices connected to the chip select signal CS1, the synchronous clock frequency of the external bus I / F circuit 23 of the microprocessor 51 according to the specifications of each device. Can be set. In addition to changing the clock frequency, it is possible to set timings of various control signals optimized for each device in each bus setting register. Therefore, even when a synchronous device having a different synchronous clock frequency is connected to one chip select signal CS, it becomes possible to access each device at an optimal synchronous clock frequency, and various control signals Since the timing setting can be optimized for each device, the performance of the entire system can be improved.

[Embodiment 3]
Other embodiments of the present invention will be described below with reference to FIGS.

  FIG. 7 is a block diagram schematically showing a system using the microprocessor 52 of the present embodiment. The difference from the block diagram of the first embodiment shown in FIG. 1 is that the microprocessor 52 includes an external bus I / F circuit 35 instead of the external bus I / F circuit 23. The program ROM 7 outputs an active low wait signal, and the data ROM 8 outputs an active high wait signal.

  The external bus I / F circuit 35 has a wait 1 terminal and a wait 2 terminal added to the external bus I / F circuit 23 described above, and a wait terminal setting register unit 36 and a wait setting register unit 37 are newly provided. It is a configuration. The wait terminal setting register unit 36 includes wait setting registers for the wait 1 terminal and the wait 2 terminal for setting the polarities of the wait 1 terminal and the wait 2 terminal, respectively. The wait setting register unit 37 does not use an external wait, uses a wait 1 terminal, or uses a wait 2 terminal for each external device assigned to each address space set by the CS address space setting register unit 22. Each of the address spaces of CS1-1, CS1-2, CS2-1, CS2-2, CS3-1, and CS3-2 are provided. 6, a total of six wait setting registers for CS1-1, CS1-2, CS2-1, CS2-2, CS3-1, and CS3-2 are provided. Further, the wait setting register unit 37 can also set a wait operation specification (for example, an operation timing after deassert of a weight).

  As in the first embodiment, the timing controller 31 refers to the CS address space setting register unit 22 based on the address to be accessed by the CPU 20, and to which address space set by the CS address space setting register unit 22 Determine whether the address is applicable. In this embodiment, the timing controller 31 selects the corresponding bus setting register in the bus setting register unit 30 based on the determination result (setting register selection signal), and the corresponding Wait in the wait setting register unit 37. A setting register is selected, and a control signal is output to an external device at the timing set in the selected bus setting register using the Wait setting set in the selected Wait setting register. That is, the wait setting means in the present invention comprises the wait setting register section 37, the wait terminal setting register section 36, and the timing controller 31.

  In this embodiment, the wait signal of the program ROM 7 is input to the wait 1 terminal of the microprocessor 52, and the wait signal of the data ROM 8 is input to the wait 2 terminal of the microprocessor 52. In the wait terminal setting register unit 36, the wait1 terminal is set to active low (L) and the wait2 terminal is set to active high (H). In the wait setting register unit 37, the wait setting register for CS1-1 is wait1. The terminal is set to use, and the CS1-2 wait setting register is set to use the wait2 terminal.

  In such a configuration, when the program ROM 7 outputs a wait signal while accessing the program ROM 7, an L level signal is input to the wait1 terminal. The Wait1 terminal is set to L active by the wait terminal setting register unit 36, and is set to use the input signal of the external wait1 terminal as a wait when the CS1-1 address space is accessed by the CS1-1 wait setting register. Therefore, the wait output of the program ROM 7 is detected by the microprocessor 52, and the number of access cycles to the program ROM 7 in the microprocessor 52 increases.

  On the other hand, when the data ROM 8 outputs a wait signal while accessing the data ROM 8, an H level signal is input to the wait2 terminal. The wait2 terminal is set to H active in the wait terminal setting register unit 36, and is set to use the input signal of the external wait2 terminal as a wait when accessing the CS1-2 address space in the CS1-2 wait setting register. Therefore, the wait output of the data ROM 8 is detected by the microprocessor 52, and the number of access cycles to the data ROM 8 in the microprocessor 52 increases. FIG. 8 shows a timing chart at this time.

  As described above, according to the present embodiment, it is possible to connect two external devices with different weight polarities to the same chip select signal. Further, if the polarities of the weights output from a plurality of external devices are the same, it is possible to input all wait signals to the wait1 terminal. Even in this case, the timing related to the wait signal can be set in accordance with each external device by the wait setting register unit 37.

[Embodiment 4]
Still another embodiment of the present invention will be described below with reference to FIGS.

  FIG. 9 is a block diagram schematically showing a system using the microprocessor 53 of this embodiment. A difference from the block diagram of the first embodiment shown in FIG. 1 is that the microprocessor 53 includes an external bus I / F circuit 38 instead of the external bus I / F circuit 23, and an external bus I / F circuit 38 is provided. As the device external RAM 9, a Cellular RAM that can be accessed by either of the access formats of Asynchronous access and Synchronous burst access is used.

  The external bus I / F circuit 38 includes a CS address space setting register unit 22 ′ instead of the CS address space setting register unit 22. The CS address space setting register unit 22 ′ is configured to divide only the address space of CS2 into three address spaces. Here, CS1-1, CS1-2, CS2-1, CS2-2, CS2-3 , CS3-1, CS3-2, a total of seven address space setting registers. Therefore, the bus setting register unit 30 ′ is adapted for CS1-1, CS1-2, CS2-1, CS2-2, CS2-3, CS3-1, and CS3-2. A total of seven bus setting setting registers are provided.

  Then, the access format setting register unit 39 newly provided in the external bus I / F circuit 38 is provided for each external device assigned to each address space set by the CS address space setting register unit 22 ′. An access format setting register for setting an access format such as Asynchronous access or Synchronous access is provided. Here, CS1-1, CS1-2, CS2-1, CS2-2, CS2-3, CS3-1, CS3- 2 for each address space of 2 for CS1-1, CS1-2, CS2-1, CS2-2, CS2-3, CS3-1, CS3-2 An access format setting register is provided.

  As in the first embodiment, the timing controller 31 refers to the CS address space setting register unit 22 ′ based on the address to be accessed by the CPU 20, and determines which address space is set by the CS address space setting register unit 22 ′. It is determined whether or not the address is applicable. In this embodiment, the timing controller 31 selects a corresponding bus setting register in the bus setting register unit 30 based on the determination result (setting register selection signal), and corresponds in the access format setting register unit 39. The access format setting register is selected, and a control signal is output to the external device at the timing set in the selected bus setting register in the access format set in the selected access format setting register. The access format setting means in the present invention comprises the access format setting register unit 39 and the timing controller 31.

  In the present embodiment, the address space of the external RAM 9 is divided into an address space 1 and an address space 2 by ADD_19 as shown in FIG. The address space 1 is used for accesses that do not frequently occur, such as update of debug information, and the address space 2 is used for accesses that frequently occur such as image data. The address space 1 of the external RAM 9 is assigned with the CS2-1 address space, and the address space 2 is assigned with the CS2-2 address space. As for the address space of CS2-1, since the frequency of continuous access is low, the access format is set to Asynchronous access in the access format setting register for CS2-1, and for the address space of CS2-2, Since continuous access occurs frequently, the access format is set to Synchronous burst access in the access format setting register for CS2-2.

  Further, as shown in FIG. 9, the CS decoding circuit 14 is connected to the chip select signal terminal of the external RAM 9 when accessing the address space of the CS 2-1 and CS 2-2. The chip select signal terminal T1 in the CS decode circuit 14 is asserted, and at the time of CS2-3 address space access, the chip select signal terminal T2 in the CS decode circuit 14 connected to the chip select signal terminal of the sound source IC 10 is asserted. The circuit configuration is as follows.

  Also, when considering the access format, from the viewpoint of improving the overall system performance, Synchronous burst access is effective for improving the performance of accesses that cause continuous access such as image data, but updating of debug information, etc. In the case of access where continuous access does not occur frequently, Synchronous burst access has a long first-access latency, and there is a concern about performance degradation.

  Therefore, in this embodiment, for access where continuous access such as update of debug information does not occur frequently, the address space 1 of the external RAM 9 is accessed by Asynchronous access by using the address space of CS2-1. In addition, with respect to accesses such as read / write of image data that occur frequently, the entire system can be obtained by using the CS2-2 address space and accessing the external RAM 9 address space 2 using Synchronous burst access. Optimized access to improve performance can be achieved. FIG. 11 shows a timing chart at this time.

  In the first to fourth embodiments described above, the address space given to the chip select signal is further divided into a plurality of address spaces, and a bus setting register unit 30 is provided for each of the divided address spaces. In the case where the bus setting register unit 30 and the clock setting register unit 34 are provided, the bus setting register unit 30, the wait terminal setting register unit 36, and the wait setting register unit 37 are provided. The case where the access format setting register unit 39 is provided has been described.

  However, the present invention is not limited to this, and for example, a clock phase setting unit may be provided in addition to the bus setting register unit 30 and the clock setting register unit 34. In this case, as shown in FIG. 13, even when accessing the same chip select signal in the address space, the phase of the synchronous clock output from the external bus I / F circuit to the external device is changed depending on the address space accessed by the CPU 20. Is possible.

  In FIG. 13, when accessing the address space of CS1-1, each control signal (Address, CS, ADV, read signal, write signal) changes at the rising edge of CLK, and when accessing the address space of CS1-2. Each control signal (Address, CS, ADV, read signal, write signal) changes at the falling edge of CLK. As a result, the number of combinations of devices connectable to one chip select signal of the microprocessor is increased, and the chip select signal terminals of the limited microprocessor can be used effectively.

  Furthermore, in the first, second, and third embodiments described above, the example has been described in which the address space of one chip select signal CS is divided into two, but the number of divisions is not limited to two. In this way, the CS address space setting register unit 22A divides the address space into arbitrary N (an integer greater than or equal to 2), and the bus setting register unit 30A can set the bus for each address space. Also good.

  Here, all the address spaces corresponding to the chip select signals CS1 to CS3 are further divided by the CS address space setting register unit 22, but the address space corresponding to at least one chip select signal is further divided. The CS address space setting register unit may be divided into small address spaces.

  Similarly, in Embodiments 2 to 4 described above, all of the clock setting register unit 34, wait setting register unit 37, access format setting register unit 39, etc. are divided by the CS address space setting register unit 22 (22 ′). A constant register is provided for each address space so that it can be individually set. However, these setting units other than the bus setting register unit 30 do not necessarily have to be provided in correspondence with each address space. What is necessary is just to provide.

  In other words, the present invention can also be expressed as follows.

  That is, a microprocessor according to the present invention includes a central processing unit that executes instructions and an external bus interface circuit that performs external bus control based on instruction execution by the central processing unit on a single semiconductor chip. The external bus interface circuit can activate an external device selection signal corresponding to an address accessed by the central processing unit from a plurality of external device selection signals, and is supplied to the external device selection signal. An address space that is divided into a plurality of address spaces by a specific address and includes an external bus interface timing setting means for each of the divided address spaces, and is given to one external device selection signal Multiple external bus interface timing within It can be set.

  The microprocessor according to the present invention is a microprocessor having a central processing unit for executing instructions and an external bus interface circuit for performing external bus control based on instruction execution by the central processing unit on a single semiconductor chip. The external bus interface circuit can be connected to a plurality of accessible devices, and the address space given to the external device selection signal is divided into a plurality of address spaces by a specific address, By providing external bus interface timing setting means and access format setting means for each divided address space, when connecting an external device capable of multiple access formats and a microprocessor, for each specific address space External devices with different access types And can be accessed.

  Further, in the microprocessor, an address space given to a certain device selection signal is divided into a plurality of address spaces by a specific address, and a synchronous clock frequency setting means for an external bus interface is provided for each address space. It is also possible to output different clock frequencies for each specific address space even within the address space given to the device selection signal.

  In the microprocessor, the address space given to one device selection signal is divided into a plurality of address spaces by a specific address, and the clock phase setting of the clock output from the external bus interface is made for each address space. It is also possible to provide means for outputting clocks having different phases for each specific address space even within the address space given to the same device selection signal.

  In the above microprocessor, the address space given to a certain device selection signal is divided into a plurality of address spaces by a specific address, and from each external device input to the external bus interface for each address space. Provided with the same device selection signal with means to set the wait according to the external wait signal specifications (active low / active high, etc.) and the means to set whether to use or not use the microcomputer wait signal terminal In the address space, it is possible to input different external wait signals for each specific address space.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention, and is a block diagram illustrating a simplified electrical configuration of an electronic device using a microprocessor. It is a figure which shows the memory MAP example which shows the address space allocated to the chip select signal. It is a figure which shows the parameter of the control signal output timing which can be set in the bus setting register part in the external bus interface circuit of the said microprocessor. FIG. 2 is a timing chart schematically showing access timing of an external bus interface circuit in the electronic device of FIG. 1. FIG. 24 is a block diagram illustrating another embodiment of the present invention and showing a simplified electrical configuration of an electronic apparatus using a microprocessor. FIG. 6 is a timing chart schematically showing access timing of an external bus interface circuit in the electronic device of FIG. 5. FIG. 29 is a block diagram showing a simplified electrical configuration of an electronic apparatus using a microprocessor according to still another embodiment of the present invention. FIG. 8 is a timing chart schematically showing access timing of an external bus interface circuit in the electronic device of FIG. 7. FIG. 29 is a block diagram showing a simplified electrical configuration of an electronic apparatus using a microprocessor according to still another embodiment of the present invention. It is a figure which shows the example of a division | segmentation of the address space of external RAM in the electronic device of FIG. FIG. 10 is a timing chart showing the access timing of the external bus interface circuit in the electronic device of FIG. 9 in a simplified manner, and is an example of a timing chart of access to the external RAM when access to the external RAM occurs. FIG. 16 is a block diagram illustrating a configuration of a microprocessor that divides an address space of one chip select signal into arbitrary N pieces in an address space setting register unit according to still another embodiment of the present invention. FIG. 29 is a block diagram showing a simplified electrical configuration of an electronic apparatus using a microprocessor according to still another embodiment of the present invention. It is a block diagram which shows the electric constitution of the conventional mobile telephone.

Explanation of symbols

1 Microprocessor 1 'Microprocessor 7 Program ROM
8 Data ROM
9 External RAM
10 IC for sound source
11 Display IC
12 Application IC
20 CPU (Central Processing Unit)
21 Address decoder section (external device selection signal activation means)
22 CS address space setting register section (address space dividing means)
22 'CS address space setting register section (address space dividing means)
22A CS address space setting register section (address space dividing means)
23 External bus interface circuit 23 'External bus interface circuit 30 Bus setting register section (timing setting means)
30 'bus setting register section (timing setting means)
30A bus setting register section (timing setting means)
33 External bus interface circuit 34 Clock setting register section (clock frequency setting means)
35 External bus interface circuit 36 Wait terminal setting register section (wait setting means)
37 Wait setting register (wait setting means)
38 External bus interface circuit 39 Access format setting register section (access format setting means)
31 Timing controller (address space dividing means, timing setting means,
Clock frequency setting means, wait setting means, access format setting means,
Clock phase setting means)
51 Microprocessor 52 Microprocessor 53 Microprocessor

Claims (6)

A central processing unit for executing instructions;
A microprocessor including an external bus interface circuit that performs external bus control based on instruction execution by the central processing unit;
The external bus interface circuit is
External device selection signal activation means for activating an external device selection signal corresponding to an address accessed by the central processing unit from a plurality of external device selection signals;
Address space dividing means for further dividing the address space given to the external device selection signal into a plurality of address spaces;
A microprocessor comprising: timing setting means for setting an access timing of the external bus interface circuit to an external device in the address space.   The external bus interface circuit has an access format setting means for setting the access format of the external bus interface circuit to the external device with respect to the address space, and can connect an external device accessible in a plurality of access formats. The microprocessor according to claim 1, wherein:   2. The microprocessor according to claim 1, wherein the external bus interface circuit includes clock frequency setting means for setting a frequency of a synchronous clock of the external bus interface circuit for each address space.   4. The microprocessor according to claim 3, wherein the external bus interface circuit includes clock phase setting means for setting a phase of a synchronous clock of the external bus interface circuit for each address space.   The external bus interface circuit can set use / non-use of the wait signal terminal, and set the weight of the external bus interface circuit for each address space based on an external wait signal input from an external device. The microprocessor according to claim 1, further comprising a weight setting unit that performs the setting. A microprocessor according to any one of claims 1 to 5;
An electronic device comprising at least an external device connected to the microprocessor via an external bus interface circuit.

Images