JP5768703B2 - Electronic device and synchronous reset control program - Google Patents

Description

  The present invention relates to an electronic device and a synchronous reset control program.

  In recent years, electronic devices such as mobile phones have been improved in functionality, but on the other hand, it is required to suppress power consumption. Therefore, in the development of LSI (Large Scale Integration) installed in electronic devices, clock signals are selectively supplied to the circuits to be used instead of always supplying clock signals to a plurality of circuits in the LSI. Power-saving design is being done.

  Such a power saving design is also applied to a synchronous reset circuit that stops output of a signal in synchronization with a clock signal. The synchronous reset circuit has, for example, a clock buffer and a flip-flop circuit. For example, when the synchronous reset circuit receives a clock control signal (CLKEN) generated by a CPU (Central Processing Unit), the synchronous reset circuit supplies the received clock control signal (CLKEN) to the clock buffer. When receiving the clock control signal (CLKEN), the clock buffer generates a clock signal and supplies the generated clock signal to the flip-flop circuit. The synchronous reset circuit receives a synchronous reset control signal (XSYNCRST) generated by the CPU. When the synchronous reset circuit receives the synchronous reset signal while the clock signal is supplied to the flip-flop circuit, the synchronous reset circuit stops outputting the signal from the flip-flop circuit in synchronization with the clock signal.

  As described above, the clock reset signal is selectively supplied by using the clock control signal (CLKEN) instead of always supplying the clock signal to the flip-flop circuit, so that the power saving design of the synchronous reset circuit can be performed. it can.

JP-A-10-242808

  However, the prior art does not take into account the power saving of the synchronous reset circuit and the reliable reset.

  That is, since the synchronous reset circuit resets in synchronization with the clock signal, it is required that the clock signal is supplied to the flip-flop circuit at the timing of resetting. On the other hand, software control related to the supply of the clock control signal (CLKEN) and software control related to the supply of the synchronous reset control signal (XSYNCRST) are performed separately. For this reason, if there is a defect in the supply order of the clock control signal (CLKEN) and the synchronous reset control signal (XSYNCRST), there is a possibility that the synchronous reset will not be performed.

  For example, when the clock control signal (CLKEN) is supplied to the synchronous reset circuit first, and then the synchronous reset control signal (XSYNCRST) is supplied, the flip-flop circuit is supplied when the synchronous reset control signal (XSYNCRST) is supplied. Is supplied with a clock signal. Therefore, when the synchronous reset control signal (XSYNCRST) is supplied, the synchronous reset circuit can stop outputting the signal from the flip-flop circuit (perform a synchronous reset) in synchronization with the clock signal.

  On the other hand, when the synchronous reset control signal (XSYNCRST) is supplied to the synchronous reset circuit first, and then the clock control signal (CLKEN) is supplied, the flip-flop circuit is supplied when the synchronous reset control signal (XSYNCRST) is supplied. Thus, no clock signal is supplied. For this reason, the synchronous reset circuit may not be able to stop outputting the signal from the flip-flop circuit (perform a synchronous reset) even if the synchronous reset control signal (XSYNCRST) is supplied.

  The disclosed technology has been made in view of the above, and it is an object of the present invention to realize an electronic device and a synchronous reset control program that can realize power saving of the synchronous reset circuit and can reliably perform the synchronous reset. And

  In one aspect, an electronic device disclosed in the present application includes a reset generation circuit that generates a reset control signal that stops output of a signal, and a clock generation circuit that generates a clock control signal that starts output of a clock signal. The electronic device also includes a clock buffer that starts outputting the clock signal when the clock control signal generated by the clock generation circuit is received or when the reset control signal generated by the reset generation circuit is received. In addition, the electronic device includes a reset circuit that stops output of the signal when receiving the reset control signal generated by the reset generation circuit while receiving the clock signal output from the clock buffer.

  According to one aspect of the electronic device disclosed in the present application, it is possible to realize the power saving of the synchronous reset circuit and reliably perform the synchronous reset.

FIG. 1 is a diagram illustrating a hardware configuration of a mobile phone. FIG. 2 is a diagram illustrating the configuration of the digital baseband unit and the reset / clock control unit. FIG. 3 is a diagram illustrating a configuration of the synchronous reset control circuit according to the first embodiment. FIG. 4 is a diagram illustrating a time chart of the synchronous reset control circuit according to the first embodiment. FIG. 5 is a diagram illustrating a time chart of the synchronous reset control circuit according to the first embodiment. FIG. 6 is a diagram illustrating a configuration of a synchronous reset control circuit of a comparative example. FIG. 7 is a diagram illustrating a time chart of the synchronous reset control circuit of the comparative example. FIG. 8 is a diagram illustrating an RTL description example of the synchronous reset control circuit according to the first embodiment. FIG. 9 is a diagram illustrating the configuration of the synchronous reset control circuit according to the second embodiment. FIG. 10 is a diagram illustrating a time chart of the synchronous reset control circuit according to the second embodiment. FIG. 11 is a diagram illustrating a time chart of the synchronous reset control circuit according to the second embodiment. FIG. 12 is a diagram illustrating an RTL description example of the synchronous reset control circuit according to the second embodiment.

  Embodiments of an electronic device and a synchronous reset control program disclosed in the present application will be described below in detail with reference to the drawings. The disclosed technology is not limited by this embodiment. For example, in the following embodiments, a mobile phone will be described as an example of an electronic device. However, the present invention is not limited to this, and the present invention is not limited to this. In contrast, the following embodiments can be applied.

  FIG. 1 is a diagram illustrating a hardware configuration of a mobile phone. As shown in FIG. 1, the mobile phone 100 of this embodiment includes an antenna 102, a radio unit 110, a digital baseband unit 120, a reset / clock control unit 130, an audio input / output unit 140, a speaker 142, and a microphone 144. . In addition, the mobile phone 100 includes a storage unit 150, a display unit 160, and a processor 170.

  The wireless unit 110 performs wireless communication of various data such as voice and characters via the antenna 102. The digital baseband unit 120 converts the signal received by the radio unit 110 into a baseband signal, and converts the converted signal into a digital signal by an A (Analog) / D (Digital) converter. The digital baseband unit 120 performs various processes such as a demodulation process and an error correction process on the converted digital signal. The digital baseband unit 120 is realized by, for example, a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). Details of the digital baseband unit 120 will be described later.

  For example, the reset clock control unit 130 receives a clock control signal (CLKEN) output from the processor 170 and also receives a synchronous reset control signal (XSYNCRST) output from the processor 170. Then, the reset clock control unit 130 outputs the received clock control signal (CLKEN) and synchronous reset control signal (XSYNCRST) to the digital baseband unit 120. Details of the reset clock controller 130 will be described later.

  The audio input / output unit 140 is an input / output interface that inputs voice via the microphone 144 and outputs voice via the speaker 142. The storage unit 150 includes a ROM (Read Only Memory) that stores data for executing various functions of the mobile phone 100 and various programs for executing various functions of the mobile phone 100. The storage unit 150 includes a RAM (Random Access Memory) that stores programs to be executed among various programs stored in the ROM. The display unit 160 is an output interface that displays various types of information such as characters and images.

  The processor 170 is an arithmetic processing unit such as a CPU (Central Processing Unit) that executes various programs stored in the storage unit 150. The processor 170 executes various programs stored in the storage unit 150 to control the wireless unit 110, the digital baseband unit 120, the reset / clock control unit 130, the audio input / output unit 140, the display unit 160, and the like. To do. Further, the processor 170 generates a clock control signal (CLKEN) and a synchronous reset control signal (XSYNCRST) and outputs them to the reset clock control unit 130 in order to control the synchronous reset of each unit of the digital baseband unit 120. The program executed by the processor 170 is not only stored in the storage unit 150 but also recorded in a storage medium that can be distributed such as a CD (Compact Disc) -ROM or a memory medium, and read from the storage medium for execution. can do. In addition, the program is stored in a server connected via a network so that the program operates on the server, and a service is requested in response to a request from the mobile phone 100 connected via the network. It can also be provided to the mobile phone 100.

  Next, details of the digital baseband unit 120 and the reset / clock control unit 130 will be described. FIG. 2 is a diagram illustrating the configuration of the digital baseband unit and the reset / clock control unit. As shown in FIG. 2, the digital baseband unit 120 includes a cell search unit 121, a demodulation unit 122, a decoding unit 123, a code generation unit 124, and a modulation unit 125.

  The cell search unit 121 executes processing for establishing synchronization with the base station (cell) on the signal received via the radio unit 110. For example, the detection of the downlink frame timing and the identification of the scrambling code assigned to the base station (cell) are performed. The cell search unit 121 includes a synchronous reset control circuit 121a.

  The demodulator 122 demodulates the signal processed by the cell search unit 121. The demodulator 122 has a synchronous reset control circuit 122a. The decoding unit 123 performs a decoding process on the signal demodulated by the demodulation unit 122. The decoding unit 123 includes a synchronous reset control circuit 123a.

  The code generation unit 124 generates a code of a signal to be transmitted to the outside via the wireless unit 110. The code generation unit 124 includes a synchronous reset control circuit 124a. Further, the modulation unit 125 performs modulation processing on the signal generated by the code generation unit 124. The modulation unit 125 includes a synchronous reset control circuit 125a.

  On the other hand, the reset / clock control unit 130 includes a reset generation register 132 and a clock EN (enable) generation register 134. The reset generation register 132 generates a synchronous reset control signal (XSYNCRST) for each of the cell search unit 121, the demodulation unit 122, the decoding unit 123, the code generation unit 124, and the modulation unit 125. Specifically, the reset generation register 132 generates a synchronous reset control signal (XSYNCRESET_A) for the cell search unit 121, a synchronous reset control signal (XSYNCRESET_B) for the demodulation unit 122, and a synchronous reset control signal (XSYNCRESET_C) for the decoding unit 123. To do. The reset generation register 132 generates a synchronous reset control signal (XSYNCRESET_D) for the code generation unit 124 and a synchronous reset control signal (XSYNCRESET_E) for the modulation unit 125. The reset generation register 132 can be formed by, for example, a flip-flop circuit or a logic circuit.

  The clock EN generation register 134 generates a clock control signal (CLKEN) for each of the cell search unit 121, the demodulation unit 122, the decoding unit 123, the code generation unit 124, and the modulation unit 125. Specifically, the clock EN generation register 134 generates a clock control signal (CLKEN_A) for the cell search unit 121, a clock control signal (CLKEN_B) for the demodulation unit 122, and a clock control signal (CLKEN_C) for the decoding unit 123. The clock EN generation register 134 generates a clock control signal (CLKEN_D) for the code generation unit 124 and a clock control signal (CLKEN_E) for the modulation unit 125. The clock EN generation register 134 can be formed by, for example, a flip-flop circuit or a logic circuit.

  As described above, the digital baseband unit 120 includes a synchronous reset control circuit in each functional block (the cell search unit 121, the demodulation unit 122, the decoding unit 123, the code generation unit 124, and the modulation unit 125). Therefore, the reset / clock control unit 130 determines the clock signal supply timing and synchronous reset timing for each of the cell search unit 121, the demodulation unit 122, the decoding unit 123, the code generation unit 124, and the modulation unit 125. Can be controlled.

  Next, a synchronous reset control circuit according to the first embodiment will be described. FIG. 3 is a diagram illustrating a configuration of the synchronous reset control circuit according to the first embodiment. FIG. 3 shows, as an example, a synchronous reset control circuit 121a provided in the cell search unit 121 as a representative, but a synchronous reset control circuit of another block (such as the demodulation unit 122) of the digital baseband unit 120 is also illustrated. It is the same. For convenience of explanation, the clock control signal input to the synchronous reset control circuit 121a is described as a clock control signal (CLKEN), and the synchronous reset control signal input to the synchronous reset control circuit 121a is described as a synchronous reset control signal (XSYNCRST). To do.

  The synchronous reset control circuit 121a includes AND circuits 202 and 206, OR circuits 204 and 208, a clock buffer 210, and a D flip-flop circuit 212. The AND circuit 202 receives an EN (enable) signal and a DIN (datain) signal. The AND circuit 202 outputs a signal corresponding to the logic of the EN signal and the DIN signal. The output signal of the AND circuit 202 and the output signal of the D flip-flop circuit 212 are input to the OR circuit 204. The OR circuit 204 outputs a signal corresponding to the logic of the output signal of the AND circuit 202 and the output signal of the D flip-flop circuit 212.

  The AND circuit 206 receives the output signal of the OR circuit 204 and the synchronous reset control signal (XSYNCRST) output from the reset generation register 132. The AND circuit 206 outputs a signal corresponding to the logic of the output signal of the OR circuit 204 and the synchronous reset control signal (XSYNCRST).

  A signal obtained by inverting the logic of the clock control signal (CLKEN) output from the clock EN generation register 134 and the synchronous reset control signal (XSYNCRST) output from the reset generation register 132 is input to the OR circuit 208. The OR circuit 208 outputs a signal corresponding to the logic of a signal obtained by inverting the logic of the clock control signal (CLKEN) and the synchronous reset control signal (XSYNCRST).

  A clock signal (CLOCK) is input to the clock port (CLK) of the clock buffer 210. The output signal of the OR circuit 208 is input to the clock enable port (CEN) of the clock buffer 210. When the clock enable port becomes active (for example, when an H (HIGH) signal is input), the clock buffer 210 starts outputting the clock signal from the output port (GCLK).

  In the D flip-flop circuit 212, the output signal of the AND circuit 206 is input to the D input port (D). In the D flip-flop circuit 212, the clock signal output from the output port (GCLK) of the clock buffer 210 is input to the clock port (ENCK). When the clock signal is input to the clock port (ENCK), the D flip-flop circuit 212 operates as a D flip-flop circuit. Therefore, the D flip-flop circuit 212 responds to the input signal to the D input port (D) according to the Q output port (Q ) To output a signal. On the other hand, the D flip-flop circuit 212 does not operate as a D flip-flop circuit when no clock signal is input to the clock port (ENCK). In this manner, power can be saved by selectively supplying the clock signal to the D flip-flop circuit 212 by the clock control signal (CLKEN).

  Next, a time chart of the synchronous reset control circuit according to the first embodiment will be described. 4 and 5 are time charts of the synchronous reset control circuit according to the first embodiment. The time chart of FIG. 4 shows a time chart when the clock reset signal (CLKEN) is first supplied to the synchronous reset control circuit and then the synchronous reset control signal (XSYNCRST) is supplied. On the other hand, the time chart of FIG. 5 shows a time chart when the synchronous reset control signal (XSYNCRST) is first supplied to the synchronous reset control circuit and then the clock control signal (CLKEN) is supplied.

  First, the time chart of FIG. 4 will be described. As shown in FIG. 4, first, the clock control signal (CLKEN) rises from the L (LOW) signal to the H (HIGH) signal and becomes active (step S101). Thus, the clock control signal (CLKEN) is input to the OR circuit 208, and the H (HIGH) signal is input to the clock enable port (CEN). As a result, the clock signal is output from the output port (GCLK) of the clock buffer 210 at the next clock rising timing when the clock control signal (CLKEN) becomes active (step S102). Thereafter, the synchronous reset control signal (XSYNCRST) falls from the H (HIGH) signal to the L (LOW) signal and becomes active (step S103). As a result, the synchronous reset control signal (XSYNCRST) becomes active while the clock signal is input to the clock port (ENCK). The output of the signal from the output port (Q) is stopped (synchronous reset is performed) (step S104).

  Next, the time chart of FIG. 5 will be described. As shown in FIG. 5, first, the synchronous reset control signal (XSYNCRST) is changed from the H (HIGH) signal to the L (LOW) while the clock control signal (CLKEN) remains in the L (LOW) signal and is not active. The signal falls and becomes active (step S201). Thus, the H (HIGH) signal obtained by inverting the logic of the synchronous reset control signal (XSYNCRST) is input to the OR circuit 208, and the H (HIGH) signal is input to the clock enable port (CEN). Thus, the clock signal is output from the output port (GCLK) at the next clock rising timing when the synchronous reset control signal (XSYNCRST) becomes active (step S202). As a result, the synchronous reset control signal (XSYNCRST) becomes active while the clock signal is input to the clock port (ENCK), so that the output of the signal from the Q output port (Q) is stopped (synchronous reset is not performed). (Step S203).

  On the other hand, a time chart of the synchronous reset control circuit of the comparative example and the synchronous reset control circuit of the comparative example will be described. FIG. 6 is a diagram illustrating a configuration of a synchronous reset control circuit of a comparative example. FIG. 7 is a diagram illustrating a time chart of the synchronous reset control circuit of the comparative example.

  As shown in FIG. 6, the synchronous reset control circuit of the comparative example does not include the OR circuit 208 and directly supplies the clock control signal (CLKEN) to the clock enable port of the clock buffer 210 as compared with the synchronous reset control circuit of FIG. 3. (CEN) is different. Further, as shown in FIG. 6, the synchronous reset control circuit of the comparative example does not input a signal obtained by logically inverting the synchronous reset control signal (XSYNCRST) to the clock buffer 210 as compared with the synchronous reset control circuit of FIG. Is different. Since the other configuration is the same as that of the synchronous reset control circuit of FIG. 3, the description of the same configuration as that of the synchronous reset control circuit of FIG. 3 is omitted.

  7 is a time chart when the synchronous reset control signal (XSYNCRST) is first supplied to the synchronous reset control circuit, and then the clock control signal (CLKEN) is supplied, as in FIG. Is shown.

  As shown in FIG. 7, first, the synchronous reset control signal (XSYNCRST) is changed from the H (HIGH) signal to L (LOW) while the clock control signal (CLKEN) remains L (LOW) signal and not active. The signal falls and becomes active (step S301). However, in this state, since the clock control signal (CLKEN) is not active, the clock signal is not output from the output port (GCLK) at the next clock rising timing after the synchronous reset control signal (XSYNCRST) becomes active. (Step S302). As a result, since the synchronous reset control signal (XSYNCRST) becomes active when no clock signal is input to the clock port (ENCK), the output of the signal from the Q output port (Q) is not stopped (synchronous reset is not performed). Not performed) (step S303).

  As described above, the synchronous reset control circuit according to the first embodiment inputs not only the clock control signal (CLKEN) but also the synchronous reset control signal (XSYNCRST) to the clock buffer 210. Then, the clock buffer 210 starts outputting a clock signal when either the clock control signal (CLKEN) or the synchronous reset control signal (XSYNCRST) becomes active. Therefore, according to the synchronous reset control circuit of the first embodiment, even when the synchronous reset control signal (XSYNCRST) is supplied to the synchronous reset control circuit first and then the clock control signal (CLKEN) is supplied. Thus, the synchronous reset can be surely performed. Also, when designing a control program related to clock control and reset control, the control program can be designed without being aware of the timing of clock control and reset control, thus preventing reset leakage due to control software design errors. it can. Further, since the synchronous reset control signal (XSYNCRST) also serves as a clock control signal (CLKEN) for generating a clock signal, it is possible to design without supplying the clock control signal (CLKEN).

  Next, an RTL description example of the synchronous reset control circuit according to the first embodiment will be described. FIG. 8 is a diagram illustrating an RTL description example of the synchronous reset control circuit according to the first embodiment. The RTL description example in FIG. 8 includes a description indicating the signal (1) output from the OR circuit 208 in FIG. That is, as shown in (1) of FIG. 8, when the clock control signal (CLKEN) becomes “1” (active) or the synchronous reset control signal (XSYNCRST) becomes “0” (active), A clock signal is output from the output port (GCLK).

  Next, a mobile phone according to the second embodiment will be described. The mobile phone of the second embodiment is different from the first embodiment only in the synchronous reset control circuit of each part of the digital baseband unit, and the other configurations are the same as those of the first embodiment. Therefore, only a different part from Example 1 is demonstrated and description is abbreviate | omitted about another structure.

  In the first embodiment, since the clock buffer 210 is enabled while the synchronous reset control signal (XSYNCRST) is active, the clock signal continues to be supplied to the D flip-flop circuit 212. For example, when the synchronous reset control signal (XSYNCRST) is a pulse signal as shown in FIG. 5, an increase in power consumption can be suppressed even in the synchronous reset control circuit of the first embodiment. On the other hand, when the synchronous reset control signal (XSYNCRST) is a level signal that remains active across a plurality of clocks, the clock signal is continuously supplied to the D flip-flop circuit 212 while the synchronous reset control signal (XSYNCRST) is active. For this reason, when the synchronous reset control signal (XSYNCRST) is a level signal, the clock signal may continue to be supplied and the power consumption may increase despite the provision of the clock buffer. The synchronous reset control circuit of the second embodiment is an embodiment made in view of this point.

  FIG. 9 is a diagram illustrating the configuration of the synchronous reset control circuit according to the second embodiment. As shown in FIG. 9, the synchronous reset control circuit 121a includes a clock buffer unit 121a-1 and flip-flop units 121a-2, 121a-2,... 121a-n (n is an integer of 3 or more). .

  The clock buffer unit 121a-1 includes a conversion circuit 301 that converts a synchronous reset control signal (XSYNCRST) into a pulse signal having a length corresponding to one cycle of the clock signal, an AND circuit 312, an OR circuit 314, and a clock buffer. 316. The conversion circuit 301 includes D flip-flop circuits 302 and 310 and AND circuits 304, 306, and 308.

  The D flip-flop circuit 302 receives the clock signal (CLOCK) input to the clock buffer unit 121a-1 and the synchronous reset control signal (XSYNCRST). The D flip-flop circuit 302 outputs a signal in response to the input of the synchronous reset control signal (XSYNCRST).

  A signal obtained by inverting the logic of the output signal of the D flip-flop circuit 302 and a synchronous reset control signal (XSYNCRST) are input to the AND circuit 304. The AND circuit 304 outputs a signal obtained by inverting the logic of the output signal of the D flip-flop circuit 302 and a signal corresponding to the logic of the synchronous reset control signal (XSYNCRST).

  The AND circuit 306 receives a signal obtained by inverting the logic of the output signal of the D flip-flop circuit 302 and the synchronous reset control signal (XSYNCRST). The AND circuit 306 outputs a signal corresponding to the logic of the output signal of the D flip-flop circuit 302 and the signal obtained by inverting the logic of the synchronous reset control signal (XSYNCRST).

  A signal obtained by inverting the logic of the output signal of the AND circuit 304 and a signal obtained by inverting the logic of the output signal of the AND circuit 306 are input to the AND circuit 308. The AND circuit 308 outputs a signal corresponding to a signal obtained by inverting the logic of the output signal of the AND circuit 304 and a signal obtained by inverting the logic of the output signal of the AND circuit 306.

  The D flip-flop circuit 310 receives the clock signal (CLOCK) input to the clock buffer unit 121 a-1 and the output signal of the AND circuit 308. The D flip-flop circuit 310 outputs a signal according to the input of the output signal of the AND circuit 308.

  The AND circuit 312 receives the synchronous reset control signal (XSYNCRST) and the output signal of the D flip-flop circuit 310. The AND circuit 312 outputs a signal corresponding to the logic of the synchronous reset control signal (XSYNCRST) and the output signal of the D flip-flop circuit 310 as the synchronous reset control signal (XSYNCRST).

  The OR circuit 314 receives a clock control signal (CLKEN) output from the clock EN generation register 134 and a signal obtained by inverting the logic of the output signal of the D flip-flop circuit 310. The OR circuit 208 outputs a signal corresponding to the logic of the clock control signal (CLKEN) and a signal obtained by inverting the logic of the output signal of the D flip-flop circuit 310.

  A clock signal (CLOCK) is input to the clock port (CLK) of the clock buffer 316. The output signal of the OR circuit 314 is input to the clock enable port (CEN) of the clock buffer 316. When the clock enable port becomes active (when the H (HIGH) signal is input), the clock buffer 316 starts outputting the clock signal from the output port (GCLK).

  The flip-flop unit 121a-2 includes AND circuits 318 and 322, an OR circuit 320, and a D flip-flop circuit 324. The AND circuit 318 receives an EN (enable) signal and a DIN (datain) signal. The AND circuit 318 outputs a signal corresponding to the logic of the EN signal and the DIN signal. The output signal of the AND circuit 318 and the output signal of the D flip-flop circuit 324 are input to the OR circuit 320. The OR circuit 320 outputs a signal corresponding to the logic of the output signal of the AND circuit 318 and the output signal of the D flip-flop circuit 324.

  The output signal of the OR circuit 320 and the synchronous reset control signal (XSYNCRST) output from the AND circuit 312 are input to the AND circuit 322. The AND circuit 322 outputs a signal corresponding to the output signal of the OR circuit 320 and the logic of the synchronous reset control signal (XSYNCRST).

  In the D flip-flop circuit 324, the output signal of the AND circuit 322 is input to the D input port (D). In the D flip-flop circuit 324, the clock signal output from the output port (GCLK) of the clock buffer 316 is input to the clock port (ENCK). Since the D flip-flop circuit 324 operates as a D flip-flop circuit when a clock signal is input to the clock port (ENCK), the D flip-flop circuit 324 operates according to the input signal to the D input port (D). ) To output a signal. On the other hand, the D flip-flop circuit 324 does not operate as a D flip-flop circuit when no clock signal is input to the clock port (ENCK). In this manner, power can be saved by selectively supplying the clock signal to the D flip-flop circuit 324 by the clock control signal (CLKEN). Note that the flip-flop units 121a-3 to 121a-n have the same configuration as the flip-flop unit 121a-2, and thus the description thereof is omitted.

  Next, a time chart of the synchronous reset control circuit according to the second embodiment will be described. 10 and 11 are time charts of the synchronous reset control circuit according to the second embodiment. The time chart of FIG. 10 shows a time chart when the synchronous reset control signal (XSYNCRST) is first supplied to the synchronous reset control circuit and then the clock control signal (CLKEN) is supplied. Further, the time chart of FIG. 10 is a time chart in the case of resetting when reset is released (at reset negation). The time chart of FIG. 11 is a time chart when the synchronous reset control signal (XSYNCRST) is supplied to the synchronous reset control circuit while the clock control signal (CLKEN) is not supplied. Further, the time chart of FIG. 11 is a time chart when resetting (when reset is asserted).

  First, the time chart of FIG. 10 will be described. As shown in FIG. 10, first, the synchronous reset control signal (XSYNCRST) is changed from the L (LOW) signal to H (HIGH) while the clock control signal (CLKEN) remains L (LOW) signal and is not active. The signal rises and becomes active (step S401). As a result, the output from the AND circuit 304 falls from the H (HIGH) signal to the L (LOW) signal (step S402). The synchronous reset control signal (XSYNCRST) is a level signal that once becomes active and then continues in an active state over a plurality of clocks.

  Subsequently, at the next clock rising timing when the synchronous reset control signal (XSYNCRST) becomes active, the output signal of the D flip-flop circuit 302 rises from the L (LOW) signal to the H (HIGH) signal (step S403). In response, the output from the AND circuit 304 rises from the L (LOW) signal to the H (HIGH) signal, and the output from the D flip-flop circuit 310 falls from the H (HIGH) signal to the L (LOW) signal ( Step S404). As a result, an H (HIGH) signal obtained by logically inverting the output signal of the D flip-flop circuit 310 is input to the OR circuit 314, and an H (HIGH) signal is input to the clock enable port (CEN). As a result, the clock signal is output from the output port (GCLK) at the next clock rising timing when the output from the D flip-flop circuit 310 falls from the H (HIGH) signal to the L (LOW) signal (step S405). . As a result, the synchronous reset control signal (XSYNCRST) becomes active while the clock signal is input to the clock port (ENCK), so that the output of the signal from the Q output port (Q) is stopped (synchronous reset is not performed). (Step S406).

  Next, the time chart of FIG. 11 will be described. As shown in FIG. 11, first, the synchronous reset control signal (XSYNCRST) is changed from the H (HIGH) signal to L (LOW) while the clock control signal (CLKEN) remains L (LOW) signal and not active. The signal falls and becomes active (step S501). As a result, the output from the AND circuit 306 falls from the H (HIGH) signal to the L (LOW) signal (step S502). The synchronous reset control signal (XSYNCRST) is a level signal that once becomes active and then continues in an active state over a plurality of clocks.

  Subsequently, at the next clock rising timing when the synchronous reset control signal (XSYNCRST) becomes active, the output signal of the D flip-flop circuit 302 falls from the H (HIGH) signal to the L (LOW) signal (step S503). In response to this, the output from the AND circuit 306 rises from the L (LOW) signal to the H (HIGH) signal, and the output from the D flip-flop circuit 310 falls from the H (HIGH) signal to the L (LOW) signal ( Step S504). As a result, an H (HIGH) signal obtained by logically inverting the output signal of the D flip-flop circuit 310 is input to the OR circuit 314, and an H (HIGH) signal is input to the clock enable port (CEN). As a result, the clock signal is output from the output port (GCLK) at the next clock rise timing when the output from the D flip-flop circuit 310 falls from the H (HIGH) signal to the L (LOW) signal (step S505). . As a result, the synchronous reset control signal (XSYNCRST) becomes active while the clock signal is input to the clock port (ENCK), so that the output of the signal from the Q output port (Q) is stopped (synchronous reset is not performed). (Step S506).

  As described above, the synchronous reset control circuit according to the second embodiment inputs not only the clock control signal (CLKEN) but also the synchronous reset control signal (XSYNCRST) output via the conversion circuit 301 to the clock buffer 316. The clock buffer 316 starts outputting the clock signal when either the clock control signal (CLKEN) or the synchronous reset control signal (XSYNCRST) output via the conversion circuit 301 becomes active. Therefore, according to the synchronous reset control circuit of the second embodiment, even when the synchronous reset control signal (XSYNCRST) is supplied to the synchronous reset control circuit first and then the clock control signal (CLKEN) is supplied. Thus, the synchronous reset can be surely performed.

  In addition, since the conversion circuit 301 is provided in the second embodiment, the synchronous reset control signal (XSYNCRST), which is a level signal that continues in an active state over a plurality of clocks, has a length corresponding to one cycle of the clock signal. It can be converted into a pulse signal. For this reason, according to the synchronous reset control circuit of the second embodiment, even if the synchronous reset control signal (XSYNCRST) is a level signal, the clock signal continues to be supplied to the D flip-flop circuit 324 and the power consumption increases. Can be suppressed.

  Next, an RTL description example of the synchronous reset control circuit according to the second embodiment will be described. FIG. 12 is a diagram illustrating an RTL description example of the synchronous reset control circuit according to the second embodiment. The RTL description example in FIG. 12 includes a signal (1) output from the D flip-flop circuit 302 in FIG. 9, a signal (2) output from the AND circuit 304, and a signal (3) output from the AND circuit 306. Is included. The RTL description example in FIG. 12 includes a description indicating the signal (4) output from the D flip-flop circuit 310 in FIG. 9 and the signal (5) output from the OR circuit 314. That is, as shown in (5) of FIG. 12, the clock control signal (CLKEN) becomes “1” (active) or the synchronous reset control signal (XSYNCRST) becomes “0” (active). When the output signal of the D flip-flop circuit 302 becomes “0” due to the above, a clock signal is output from the output port (GCLK).

  The first and second embodiments have been described mainly with respect to the mobile phone 100. However, the present invention is not limited to this, and by executing a synchronous reset control program prepared in advance on an electronic device, Similar functions can be realized. That is, the synchronous reset control program causes the electronic device to execute a process of generating a reset control signal that stops the output of the signal. In addition, the synchronous reset control program causes the electronic device to execute a process of generating a clock control signal for starting output of the clock signal. Further, the synchronous reset control program causes the electronic device to receive the generated clock control signal or to execute a process of starting output of the clock signal when the generated reset control signal is received. The synchronous reset control program causes the electronic device to execute a process of stopping the output of the signal when the generated reset control signal is received in a state where the output clock signal is received. The synchronous reset control program can be distributed to electronic devices via a communication network such as the Internet. The synchronous reset control program is recorded on a memory, a hard disk, or other computer-readable recording medium provided in the electronic device, and can be read from the recording medium and executed by the electronic device.

100 cellular phone 120 digital baseband unit 121a, 122a, 123a, 124a, 125a synchronous reset control circuit 130 reset / clock control unit 132 reset generation register 134 clock EN generation register 210, 316 clock buffer 212, 324 D flip-flop circuit 301 conversion circuit

Claims (3)

A reset generation circuit for generating a reset control signal for stopping output of the signal;
A clock generation circuit for generating a clock control signal for starting output of the clock signal;
A clock buffer that receives the clock control signal generated by the clock generation circuit or receives the reset control signal generated by the reset generation circuit, and starts outputting the clock signal;
When receiving the reset control signal generated by the reset generation circuit in the state of receiving the clock signal output from the clock buffer, a reset circuit for stopping output of the signal;
An electronic device comprising: A conversion circuit that converts the reset control signal generated by the reset generation circuit into a pulse signal having a length corresponding to one period of the clock signal;
The clock buffer starts outputting a clock signal when receiving a pulse signal converted by the conversion circuit or receiving a reset control signal generated by the reset generation circuit. The electronic device as described in. Electronic equipment,
Generate a reset control signal to stop signal output,
Generate a clock control signal that starts the output of the clock signal,
When receiving the generated clock control signal or receiving the generated reset control signal, start outputting the clock signal;
A synchronous reset control program that, when receiving the generated reset control signal while receiving the output clock signal, executes a process of stopping signal output.

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