JP2003330570A - Data processor, data processor control method, data processor control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor, a data processor control method, and a data processor control program which can change the frequency of the clock signal of a CPU incorporated in the data processor into various frequencies without impairing the performance of the data processor. <P>SOLUTION: The data processor (26) which operates according to the clock signal, the data processor comprising a clock frequency variable means (30) which can change the frequency of the clock signal, and a clock frequency control means which uses the clock frequency variable means to control the frequency of the clock signal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device that operates according to a clock signal, and more particularly to a data processing device that operates at a fixed clock frequency and a variable clock frequency.
The present invention relates to a data processing device control method and a data processing device control program.

[0002]

2. Description of the Related Art In recent years, a global positioning system (GPS: Gl) is a data processing device for processing data from artificial satellites.
The obal Positioning System) may be installed not only in car navigation systems but also in mobile terminals and watches.

[0003]

In the global positioning system mounted on various devices as described above, it is important to reduce power consumption as much as possible. Therefore, in order to reduce power consumption, a CPU (Cent
If the frequency of the clock signal of the ral processing unit) is lowered, the frequency of the clock signal of other electronic elements of the data processing device also changes. , Error correction, etc.), but the performance as a data processing device may be impaired, such as not operating properly.

In view of the above problems, the present invention provides data that can change the frequency of the clock signal of the CPU incorporated in the data processing device to various frequencies without impairing the performance of the data processing device. An object is to provide a processing device, a data processing device control method, and a data processing device control program.

[0005]

According to a first aspect of the present invention, there is provided a data processing device (2) which operates according to a clock signal.
6) The clock frequency changing means (30) for changing the frequency of the clock signal, and the clock frequency controlling means for controlling the frequency of the clock signal by using the clock frequency changing means. Is characterized by.

According to the first aspect of the invention, the clock control of the clock frequency control means makes it possible to change the clock frequency of, for example, the CPU in the data processing apparatus to various frequencies without deteriorating the performance of the data processing apparatus. A data processing device can be provided.

According to a second aspect of the present invention, in the data processing device, the first processing unit (3) operating at a fixed clock frequency.
4) and a second processing unit (32) capable of operating with a variable clock frequency, and converting the clock frequency of the second processing unit (32) to the clock frequency of the first processing unit (34). And a reference clock conversion means (33) for performing.

According to the second aspect, since only the clock frequency of the second processing unit whose clock frequency is variable can be changed, the performance of the data processing device is not impaired.
It is possible to provide a data processing device that can change the clock frequency of the second processing unit in the data processing device, for example, the CPU clock frequency to various frequencies.

The invention according to claim 3 is characterized in that the clock frequency control means controls the clock frequency based on a predetermined condition.

According to the third aspect, it is possible to provide a data processing device which makes it possible to set a condition for controlling the clock frequency and to control the clock frequency according to the condition.

The invention according to claim 4 is characterized in that the predetermined condition is a condition based on a magnitude of a load on the second processing section.

According to the fourth aspect, it is possible to provide a data processing device capable of increasing the clock frequency when the load is large and decreasing the clock frequency when the load is small.

According to a fifth aspect of the present invention, there is provided a method of controlling a data processing device which operates according to a clock signal, wherein the frequency of the clock signal is controlled according to the processing load of the data processing device. Characterize.

According to the fifth aspect, it is possible to provide a control method of a data processing device capable of increasing the clock frequency when the load is large, and lowering the clock frequency when the load is small.

A sixth aspect of the present invention is a data processing device control program for causing a computer to execute a procedure for controlling the frequency of a clock signal according to the processing load of the data processing device.

According to the sixth aspect, it is possible to provide a control program for a data processing device capable of increasing the clock frequency when the load is large and decreasing the clock frequency when the load is small.

The reference numerals are merely examples, and the present invention is not limited to these reference numerals.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a car navigation system (hereinafter referred to as a car navigation system) equipped with a global positioning system according to an embodiment of the present invention.

The car navigation system 100 includes an antenna 10 and a CP.
It has a U (Central Processing Unit) 12, a display 16, a ROM 18, a RAM 20, and a CD-ROM drive 22. The antenna 10 receives radio waves from GPS satellites. The display 16 is a screen that displays information. The GPS unit 12 has an antenna 10
Information such as position and speed is obtained from the information from
The information obtained in 14 is output. The CPU 14 outputs, for example, position information on a map to the display 16 or the ROM 18 based on the information input from the receiving device.
Car navigation 10 such as execution of programs recorded in
Controls the entire 0. The RAM 20 is a storage device that expands programs and data and temporarily holds them. The CD-ROM drive 22 stores a CD-ROM on which map information is recorded, and reads the map information on the CD-ROM. The CD-ROM drive may be a DVD drive, in which case a DVD-ROM on which map information is recorded is read.

Of these, the details of the GPS unit 12 are
This will be described with reference to FIG. As shown in FIG. 2, the GPS unit 12 includes a GPS signal input section 24 to which a GPS signal from the antenna 10 is input, and a GPS signal input section 24.
The GPS signal received by the ASIC is input, calculations such as positioning are performed, and the calculated ASIC is output to the CPU 32 through the bus.
ication Specific Integrated Circuit) 26 and AS
Crystal oscillator 28 that supplies a reference clock to the IC 26
Composed of and. The clock here is ASI.
It shows a signal of a constant cycle which serves as a reference for operating the electronic element of C26 or the CPU 32. A clock signal serves as a reference for operating them at a fixed timing, and the frequency of this clock signal is the clock frequency.

Next, the structure of the ASIC 26 will be described with reference to FIG. The ASIC 26 includes a variable frequency divider 30 that can change the clock frequency supplied from the crystal oscillator 28 to various frequencies, a fixed frequency divider 31 that fixes the supplied clock frequency to a specific frequency, and a CPU.
32, a reference clock converter 33, and a GPS baseband unit 34 that extracts a signal from a received radio wave and corrects an error.

Among them, the variable frequency divider 30 supplies the clock signal to the CPU 32 by changing the clock frequency by multiplying the supplied clock by 1/2 or 1/3. And the clock frequency changed like this,
It is the reference clock converter 33 that converts the clock frequency to the reference frequency of the GPS baseband unit 34 or the like.

Next, the load on the CPU 32 will be described before the processing for changing the clock frequency of the CPU 32 in the ASIC 26 based on the load on the CPU 32 will be described with reference to the flowchart of FIG. CPU
The load on 32 can also be recognized by the processing being performed by the ASIC 26 at that time. For example, C
Examples of the processing that puts a load on the PU 32 include positioning processing when the car navigation system 100 starts up. As described above, the load on the CPU 32 can be recognized in the processing state. Therefore, in the following description, the processing state is used as the load state on the CPU 32. Of course, the load of the CPU 32 may be actually measured without using the processing state.

The flowchart of FIG. 4 will be described below. First, the ASIC 26 reads the processing state in step S101. This reading can be done by referring to the status register or the like. Then, when the processing state is not changed in step S102, the ASIC 26 reads the processing state in step S101 again. If the change in the processing state can be confirmed in step S102, the ASIC 26 changes the clock in accordance with the processing state in step S103. After that, the ASIC 26 again executes step S101.
The processing status of is read and processing continues.

Next, the details of the processing performed in step S103 will be described with reference to the flowchart of FIG. In this flowchart, the processing state of the CPU 32 is represented by three states A, B, and C, and the states A, B, and C are shown.
It is assumed that the processing state is such that the load on the CPU 32 is reduced in the order of. In this case, an example of the state A is a positioning process at the time of starting the car navigation system 100 that is heavy in processing, an example of a state B is a normal positioning process other than the time of starting, and a state C
As an example, there is a positioning process in a state where a car equipped with the car navigation system 100 hardly moves.

The flow chart will be described below. AS
The IC 26 determines in step S201 whether or not the state is the state A. In the state A, the process is the heaviest, so in step S202, the CPU 32 is operated at the same magnification without dropping the clock. In step S201, AS
If the IC 26 determines that the state is not A, the ASIC 2
The step 6 judges whether or not the state is the state B in the step S203. If the ASIC 26 determines in step S203 that the state is the state B, the state B is not so heavy processing, and therefore in step S204, the ASIC 26 operates the CPU 32 at 1/2 the supplied clock.
When it is determined in step S203 that the ASIC 26 is not in the state B, the ASIC 26 determines in step S20.
At 5, the CPU 32 is operated at 1/4 times the supplied clock.

In this way, the ASIC 26 controls the clock of the CPU 32 according to the load on the CPU 32, so that the power consumption can be suppressed not only in the ASIC 26 but also in the car navigation system 100 as a whole.

As described above, since the clock frequency of the CPU 32 can be changed without changing the clock frequency of another electronic element of the data processing device, for example, the GPS baseband section, not only the power consumption is suppressed but also the power consumption is suppressed. On the contrary, when speeding up the car navigation processing, it can be realized without changing the circuit. In addition, car navigation 1
00 stored in the ROM 18 of the CPU 1
It is possible to freely change the clock frequency of the CPU 32 even when No. 4 is running.

As shown in FIG. 6, if the electronic element 37 does not malfunction even if the clock frequency changes slightly, only the variable frequency divider 30 needs to be provided, and the reference clock converter 30 and the like need not be provided. The configuration is not required.

[0030]

As described above, the C which is built in the data processing device without impairing the performance of the data processing device.
A data processing device, a data processing device control method, and a data processing device control program capable of changing the frequency of a PU clock signal to various frequencies are obtained.

[Brief description of drawings]

FIG. 1 is a hardware configuration diagram of a car navigation system according to an embodiment of the present invention.

FIG. 2 is a hardware configuration diagram of a GPS unit.

FIG. 3 is a hardware configuration diagram of an ASIC.

FIG. 4 is a flowchart showing processing of an ASIC.

FIG. 5 is a flowchart showing a process of an ASIC.

FIG. 6 is a hardware configuration diagram of an ASIC.

[Explanation of symbols]

10 ... Antenna 12 ... GPS unit 14, 32 ... CPU 16 ... Display 16a, 16b, 16c ... Input keys 18 ... ROM 20 ... RAM 22 ... CD-ROM drive 24 ... GPS signal input section 26 ... ASIC 28 ... Crystal oscillator 30 ... Variable frequency divider 31 ... Fixed divider 33 ... Reference clock converter 34 ... GPS baseband section 37 ... Electronic element

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Watarube Kouki             1601 Sakai, Atsugi, Kanagawa Mitsumi Electric Co., Ltd.             Company Atsugi Office F term (reference) 5B079 AA05 BA03 BB10 BC01                 5J062 AA03 AA13 BB01 CC07 DD12                       DD21

Claims (6)

[Claims] 1. A data processing device that operates according to a clock signal, comprising: a clock frequency varying means for varying the frequency of the clock signal; and a clock frequency varying means for controlling the frequency of the clock signal. A data processing device comprising a clock frequency control means. 2. The data processing device includes a first processing unit that operates at a fixed clock frequency, and a second processing unit that can operate with a variable clock frequency. From the clock frequency of the second processing unit, A data processing device, comprising: a reference clock conversion means for converting the clock frequency of the first processing unit. 3. The data processing device according to claim 1, wherein the clock frequency control means controls the clock frequency based on a predetermined condition. 4. The data processing device according to claim 3, wherein the predetermined condition is a condition based on a magnitude of a load on the second processing unit. 5. A method of controlling a data processing device which operates according to a clock signal, wherein the frequency of the clock signal is controlled according to the processing load of the data processing device. Method. 6. A data processing device control program for causing a computer to execute a procedure for controlling a frequency of a clock signal according to a processing load of the data processing device.