JP2004030506A - Portable communication terminal and method for sharing its memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a portable communication terminal in which a plurality of CPUs for executing processing for performing communication by a plurality of communication systems can share a memory with a simple configuration and the whole contents of the memory can be easily changed, and to provide a method for sharing the memory. <P>SOLUTION: This portable communication terminal is provided with a CPU 21 for W-CDMA (wideband code division multiple access) communication, which executes processing for performing communication by a W-CDMA communication system, a CPU 31 for PDC (personal digital cellular) communication, which executes processing for performing communication by a PDC communication system, and the shared memory 10 connected to the CPU 21 for W-CDMA communication and the CPU 31 for PDC communication by a shared memory bus 100. When the CPU 21 for W-CDMA communication accesses the shared memory 10, a connection part of the CPU 31 for PDC communication is made to be in a high impedance state. When the CPU 31 for PDC communication accesses the shared memory 10, a connection part of the CPU 21 for W-CDMA communication is made to be in a high impedance state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a portable communication terminal that performs communication using a plurality of communication schemes and a method for sharing a memory thereof, and more particularly to a technique for sharing a memory between a plurality of processors assigned to a plurality of communication schemes.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, portable mobile communication terminals such as a mobile phone and a PDA (Personal Data Assistant) that perform wireless communication have been known. In this portable communication terminal, a PDC (Personal Digital Cell) adopting a PDC (Personal Digital Cell) using technology such as TDMA (Time Division Multiple Access) or FDMA (Frequency Division Multiple Access), which is called a second generation communication method.
[0003]
In recent years, W-CDMA (Wideband-CDMA) using CDMA (Code Division Multiplex Access) technology called CDMA (Code Division Multiplex Access) technology, which is called a third generation communication system with a focus on realizing an internationally unified standard and supporting high-speed data communication, etc., is being adopted. . Therefore, in consideration of user's convenience, a dual-type portable communication terminal has been developed in which one portable communication terminal can perform communication using both of these communication methods.
[0004]
As a related technique, Japanese Patent Application Laid-Open No. 2000-13274 discloses a multi-mode wireless device. In this multi-mode wireless device, a mode switch is provided at the input of the quadrature modulator of the transmission system of the dual-mode mobile phone terminal of the wideband CDMA / PDC, the quadrature modulator and the power control amplifier are shared, and the mode of the A switch is provided to supply a signal to a transmission circuit in a different mode. Further, a 1/2 frequency dividing circuit is provided between the output of the second local oscillator and the input of the quadrature modulator, and the operation state of the 1/2 frequency dividing circuit is set so as to be controlled by mode switching. With the 分 frequency divider with mode switching, the frequency control range of the voltage controlled oscillator of the second local oscillator can be narrowed, and the switching of the voltage controlled oscillator of the second local oscillator becomes unnecessary. With this configuration, in the conventional wideband CDMA / PDC dual mode mobile phone terminal, there is little common use of the radio section, and the transmission system has two complete systems, and it is extremely difficult to reduce the size, weight, and power consumption. Has been eliminated.
[0005]
Japanese Patent Application Laid-Open No. 2001-292090 discloses a mobile phone and a semiconductor device for a mobile phone. In this technique, a memory for storing transmission / reception data is shared for storing reception data and transmission data. As a result, an increase in memory capacity can be suppressed, power consumption can be reduced, and a decrease in system performance can be prevented. Japanese Patent Application Laid-Open No. 2000-244885 discloses a dual-type communication device that can automatically select a line with a low communication fee without having to execute a complicated process in a large-capacity memory or a CPU, and a communication device therefor. A medium recording a control program and a communication method are disclosed.
[0006]
Japanese Patent Application Laid-Open No. 11-355197 discloses a communication signal processing system in which only a single shared storage element unit is provided for a digital signal processing unit and a host CPU unit, and the power consumption and the board area are small. Further, Japanese Patent Application Laid-Open No. H11-146449 discloses a CPU / DSP shared memory in which both a CPU instruction code and a DSP instruction code corresponding to two or more communication systems are written, thereby reducing the circuit scale of the mobile communication terminal. In addition, a mobile communication terminal with a low device price and a control method thereof are disclosed.
[0007]
[Problems to be solved by the invention]
The conventional dual-type portable communication terminal described above includes a PDC communication CPU that executes a process for performing communication using the PDC communication system, and a W-CDMA that executes a process for performing communication using the W-CDMA communication system. And a communication CPU. Each of the PDC communication CPU and the W-CDMA communication CPU has a separate memory.
[0008]
By the way, a portable communication terminal is required to reduce the number of components and the mounting area in order to reduce the size and weight. Therefore, it is conceivable to share a memory used by the CPU for PDC communication and the CPU for W-CDMA communication. An arbiter circuit for arbitrating bus requests from a plurality of CPUs is known as a technique for sharing the memory. However, the use of the arbiter circuit requires a circuit for switching the bus outside the CPU, which has the disadvantage of increasing the number of components and the mounting area.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described disadvantages, and an object of the present invention is to allow a plurality of CPUs that execute processing for performing communication by a plurality of communication methods to share a memory with a simple configuration, Another object of the present invention is to provide a portable communication terminal capable of easily changing the entire contents of a memory and a method of sharing the memory.
[0010]
[Means for Solving the Problems]
The means for solving the problem will be described below using the numbers and symbols used in [Embodiments of the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Embodiments of the Invention]. It should not be used to interpret the technical scope of the described invention.
[0011]
In order to achieve the above object, a portable communication terminal according to a first aspect of the present invention includes a first CPU (21) that executes processing for performing communication using a first communication method, and communication using a second communication method. A second CPU (31) for executing processing for performing the processing, a memory (10) connected to the first CPU (21) and the second CPU (31) by a bus (100), and the first CPU (21) includes a memory (10). ), The connection of the second CPU (31) to the bus (100) is set to a high impedance state, and when the second CPU (31) accesses the memory (10), the bus (100) of the first CPU (21) is accessed. ) Is set to a high impedance state.
[0012]
The portable communication terminal according to the first aspect further includes a memory division control circuit (11) that generates an upper address signal (101) of the address signals sent to the memory (10), 11) can be configured to generate an upper address signal such that the area of the memory (10) accessed by the first CPU (21) and the area of the memory (10) accessed by the second CPU (31) are different.
[0013]
Further, in the portable communication terminal according to the first aspect, when the software stored in the memory (10) is changed, the first CPU (21) controls the memory (10). ) Can be configured to generate an upper address signal capable of accessing the entire area.
[0014]
In addition, the method of sharing a memory of a portable communication terminal according to a second aspect of the present invention includes a first CPU (21) that executes a process for performing communication by a first communication method, and a communication by a second communication method. A second CPU (31) for performing processing for performing the first CPU (21) and a memory (10) connected to the first CPU (21) and the second CPU (31) by the bus (100) are provided. The step of setting the connection of the second CPU (31) to the bus (100) to a high impedance state when accessing the memory (10), and the step of setting the first CPU (when the second CPU (31) accesses the memory (10)). 21) bringing the connection to the bus (100) into a high impedance state.
[0015]
The method for sharing a memory of a portable communication terminal according to the second aspect further includes a step of generating an upper address signal among address signals to be sent to the memory (10), and the step of: It can be configured to generate an upper address signal such that the area of the memory (10) accessed by the first CPU (21) and the area of the memory accessed by the second CPU (31) are different.
[0016]
Further, in the method for sharing a memory of a portable communication terminal according to the second aspect, the step of generating the upper address signal includes the step of generating the first CPU (1) when the software stored in the memory (10) is changed. 21) can be configured to generate an upper address signal capable of accessing the entire area of the memory (10).
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 1 is a block diagram showing a configuration of a portable communication terminal according to an embodiment of the present invention. This portable communication terminal includes a W-CDMA communication unit 1, a PDC communication unit 2, a shared memory 10, a memory division control circuit 11, a main control CPU 12, an inverter 13, and a shared memory bus 100.
[0019]
The W-CDMA communication unit 1 includes a W-CDMA radio unit 20, a W-CDMA communication CPU 21, and a control signal line 200 connecting between them. The control signal line 200 transmits and receives a W-CDMA radio unit control signal between the W-CDMA radio unit 20 and the W-CDMA communication CPU 21.
[0020]
The W-CDMA radio unit 20 modulates the W-CDMA radio unit control signal received from the W-CDMA communication CPU 21 via the control signal line 200 in accordance with the W-CDMA communication method, and emits the modulated signal from the antenna (not shown) into the air. . Further, a W-CDMA radio unit control signal obtained by demodulating a signal received from the air with an antenna (not shown) in accordance with the W-CDMA communication method is transmitted to the W-CDMA communication CPU 21 via the control signal line 200. .
[0021]
The W-CDMA communication CPU 21 executes a process for performing communication by the W-CDMA communication method according to an instruction from the main control CPU 12 while referring to the shared memory 10. Further, the W-CDMA communication CPU 21 sends the CPU upper address signal 102 and the address priority signal 103 to the memory division control circuit 11. The CPU upper address signal 102 is used as a memory upper address signal 101 constituting the upper bits of the memory address signal sent from the memory division control circuit 11 to the shared memory 10. The address priority signal 103 specifies whether the CPU upper address signal 102 as the memory upper address signal 101 is valid or invalid. When the address priority signal 103 is at H level, the CPU upper address signal 102 is valid, and when it is at L level, it is invalid.
[0022]
The PDC communication unit 2 includes a PDC wireless unit 30, a PDC communication CPU 31, and a control signal line 300. The control signal line 300 transmits and receives a PDC wireless unit control signal between the PDC wireless unit 30 and the PDC communication CPU 31.
[0023]
The PDC radio unit 30 modulates the PDC radio unit control signal received from the PDC communication CPU 31 via the control signal line 300 according to the PDC communication method, and emits the modulated signal from the antenna (not shown) into the air. Further, a PDC radio unit control signal obtained by demodulating a signal received from the air with an antenna (not shown) according to the PDC communication method is transmitted to the PDC communication CPU 31 via the control signal line 300.
[0024]
The PDC communication CPU 31 executes a process for performing communication by the PDC communication method while referring to the shared memory 10 in accordance with an instruction from the main control CPU 12. Details of the processing by the PDC communication CPU 31 will be described later.
[0025]
The W-CDMA communication CPU 21, the PDC communication CPU 31, and the shared memory 10 are connected by a shared memory bus 100. The shared memory bus 100 includes a signal line for transmitting and receiving a memory lower address signal, a data signal, and a control signal for controlling the shared memory 10, which constitute lower bits of a memory address to be sent to the shared memory 10.
[0026]
The connection between the W-CDMA communication CPU 21 and the shared memory bus 100 is constituted by a first tri-state buffer 22. The connection between the PDC communication CPU 31 and the shared memory bus 100 is constituted by a second tri-state buffer 32. The first tri-state buffer 22 and the second tri-state buffer 32 are exclusively enabled according to a bus valid signal 104 from the main control CPU 12.
[0027]
Specifically, when the W-CDMA communication CPU 21 operates, the first tristate buffer 22 is enabled by setting the bus valid signal 104 to a high level (hereinafter, referred to as “H level”), The second tri-state buffer 32 is set to a high impedance state. As a result, only the CPU 21 for W-CDMA communication can use the shared memory 10. On the other hand, when the PDC communication CPU 31 operates, the bus enable signal 104 is set to a low level (hereinafter, referred to as “L level”) to enable the second tri-state buffer 32 and to enable the first tri-state buffer 22. Are brought into a high impedance state. As a result, only the PDC communication CPU 31 can use the shared memory 10.
[0028]
The main control CPU 12 is connected to a W-CDMA communication CPU 21 and a PDC communication CPU 31 by a system control bus 105. The main control CPU 12 uses the system control bus 105 to exclusively operate the W-CDMA communication CPU 21 and the PDC communication CPU 31.
[0029]
Further, the main control CPU 12 sends the bus valid signal 104 to the W-CDMA communication CPU 21, the memory division control circuit 11, and the inverter 13. The inverter 13 inverts the received bus valid signal 104 and sends it to the PDC communication CPU 31. As a result, control is performed so that the first tristate buffer 22 and the second tristate buffer 32 are exclusively enabled.
[0030]
The shared memory 10 includes a ROM section and a RAM section. A memory lower address signal is sent from the W-CDMA communication CPU 21 or the PDC communication CPU 31 to the shared memory 10 via the shared memory bus 100. Further, a memory upper address signal 101 used for memory division is sent from the memory division control circuit 11.
[0031]
The memory division control circuit 11 generates a memory upper address signal based on the bus enable signal 104 from the main control CPU 12, the CPU upper address signal 102 and the address priority signal 103 from the W-CDMA communication CPU 21, and Send to
[0032]
Specifically, when the invalidation of the CPU upper address signal 102 is designated by the address priority signal 103, the memory division control circuit 11 outputs the memory upper address signal 101 in response to the bus valid signal 104. On the other hand, when the validity of the CPU upper address signal 102 is designated by the address priority signal 103, the CPU upper address signal 102 from the CPU 21 for W-CDMA communication is output as the memory upper address signal 101. In this case, the entire area of the shared memory 10 can be accessed from the CPU 21 for W-CDMA communication.
[0033]
Next, the operation of the portable communication terminal according to the embodiment of the present invention will be described with reference to the drawings.
[0034]
Which of the W-CDMA communication unit 1 and the PDC communication unit 2 is made valid (operating) is determined according to, for example, the type of communication system related to the incoming call. When an incoming call is confirmed in the W-CDMA communication unit 1, for example, the main control CPU 12 is called by an interrupt signal, and if the W-CDMA communication unit 1 is not enabled, a process for enabling it is executed. . Similarly, when an incoming call is confirmed in the PDC communication unit 2, for example, the main control CPU 12 is called by an interrupt signal, and if the PDC communication unit 2 is not enabled, a process for enabling it is executed.
[0035]
As a specific example, an operation performed when the PDC communication unit 2 is switched from a state in which the W-CDMA communication unit 1 is enabled to a state in which the PDC communication unit 2 is enabled will be described with reference to FIGS.
[0036]
FIG. 2 is a flowchart showing an operation in a case where the W-CDMA communication unit 1 is switched from a valid state to a PDC communication unit 2 in a valid state.
[0037]
First, it is assumed that the W-CDMA communication unit 1 is valid, that is, in operation (step S10). In this case, the main control CPU 12 outputs the H level as the bus valid signal 104. Accordingly, the first tri-state buffer 22 is enabled, the second tri-state buffer 32 is in a high impedance state, and only the CPU 21 for W-CDMA communication can use the shared memory 10. At this time, the address priority signal 103 is at the L level (normal state), and the memory division control circuit 11 outputs the L level as the memory upper address signal 101 because the bus valid signal 104 is at the H level.
[0038]
In this state, the main control CPU 12 sends a W-CDMA communication unit stop request to the W-CDMA communication CPU 21 via the system control bus 105 (step S11). Thereafter, the main control CPU 12 waits while checking whether there is a response by ACK indicating that the W-CDMA communication unit stop request has been received from the W-CDMA communication CPU 21 (step S12). The W-CDMA communication CPU 21 that has received the W-CDMA communication unit stop request from the main control CPU 12 stops the operation of the W-CDMA radio unit 20, and instructs the main control CPU 12 via the system control bus 105. , ACK.
[0039]
When determining that the ACK has been received from the W-CDMA communication CPU 21 in step S12, the main control CPU 12 sends the W-CDMA communication CPU 21 to the W-CDMA communication CPU 21 via the system control bus 105. A CPU sleep request for putting the CPU 21 into the sleep state is sent (step S13). This causes the W-CDMA communication CPU 21 to immediately enter the sleep state and stop its operation.
[0040]
Next, the main control CPU 12 changes the bus valid signal 104 from H level to L level (step S14). Thereby, the state where the W-CDMA communication unit 1 is valid is switched to the state where the PDC communication unit 2 is valid. The change of each signal at this time is shown in the timing chart of FIG. That is, as shown in FIG. 3A, when the bus valid signal 104 changes from H level to L level, the first tri-state buffer 22 that connects the CPU 21 for W-CDMA communication and the shared memory bus 100 As shown in FIG. 3 (E), the state becomes a high impedance state, and the second tri-state buffer 32 connecting the PDC communication CPU 31 and the shared memory bus 100 is enabled as shown in FIG. 3 (F). . As a result, the PDC communication CPU 31 can access the shared memory 10 via the shared memory bus 100.
[0041]
Further, as shown in FIG. 3C, the CPU upper address signal 102 enters a high impedance state. At this time, since the address priority signal 103 remains at the L level as shown in FIG. 3D, the memory division control circuit 11 sets the bus valid signal 104 to the L level, As shown in (B), the memory upper address signal 101 is changed from L level to H level.
[0042]
Next, the main control CPU 12 sends a CPU wake-up request via the system control bus 105 to activate the PDC communication CPU 31 (step S15). As a result, the PDC communication CPU 31 is immediately enabled, and starts its operation. Next, the main control CPU 12 sends a PDC communication unit activation request to the PDC communication CPU 31 via the system control bus 105 (step S16).
[0043]
Thereafter, the main control CPU 12 waits while checking whether there is a response by ACK indicating that the PDC communication unit activation request has been received from the PDC communication CPU 31 (step S17). The PDC communication CPU 31 activates the PDC radio unit 30 in response to the PDC communication unit activation request, and sends an ACK to the main control CPU 12. Thereafter, the PDC communication unit 2 is in operation (step S18). On the other hand, upon receiving the ACK, the main control CPU 12 recognizes that the PDC communication unit 2 is valid (operating), and prepares for a case where the W-CDMA communication unit 1 next confirms an incoming call.
[0044]
FIGS. 4 and 5 are diagrams showing the allocation state of the shared memory 10 when the W-CDMA communication unit 1 and the PDC communication unit 2 operate exclusively, as described above. When the W-CDMA communication unit 1 is enabled, the memory upper address signal 101 is set to L level, so that the lower half area of the shared memory 10 is allocated to the W-CDMA communication CPU 21 as shown in FIG. Area. In this case, even if the W-CDMA communication CPU 21 attempts to access the upper half area of the shared memory 10, the lower half area is physically accessed, so the W-CDMA communication unit 1 Cannot access allocated space.
[0045]
On the other hand, when the PDC communication unit 2 is enabled, the memory upper address signal 101 is set to the H level, so that the upper half area of the shared memory 10 is allocated to the PDC communication CPU 31 as shown in FIG. become. In this case, even if the PDC communication CPU 31 attempts to access the lower half area of the shared memory 10, the upper half area is physically accessed, so the PDC communication unit 2 is allocated to the W-CDMA communication CPU 21. Cannot access the area.
[0046]
Next, the operation when changing the software stored in the ROM of the shared memory 10 will be described with reference to the flowchart shown in FIG. 6 and the timing chart shown in FIG.
[0047]
When the software is changed, the main control CPU 12 activates the W-CDMA communication CPU 21 by activating the software change mode (step S20). At this time, the W-CDMA radio unit 20 is stopped. The CPU 21 for W-CDMA communication changes the address priority signal 103 from L level to H level by activating the software change mode (step S21). As a result, the CPU upper address signal 102 is output as the memory upper address signal 101, and the entire area of the shared memory 10 can be accessed from the W-CDMA communication CPU 21.
[0048]
In this state, the software is changed (step S22). Thereafter, the W-CDMA communication CPU 21 changes the address priority signal 103 from H level to L level (step S23). Thereby, the software change mode ends (step S24), and the state returns to the state where the W-CDMA communication unit 1 and the PDC communication unit 2 operate exclusively.
[0049]
FIG. 7 is a timing chart showing changes in signals when the W-CDMA communication unit 1 and the PDC communication unit 2 switch from a state in which they operate exclusively to a software change mode activation state. In the software change mode activation state, as shown in FIG. 7D, the address priority signal 103 is at the L level. The memory upper address signal 101 shown in FIG. 7B is at the L level because the bus valid signal 104 shown in FIG. 7A is at the H level. As shown in FIG. 7D, when the address priority signal 103 changes from the L level to the H level, as shown in FIG. 7B, the CPU upper level signal shown in FIG. An address signal 102 is output.
[0050]
As described above, according to the portable communication terminal according to the embodiment of the present invention, when W-CDMA communication section 1 and PDC communication section 2 operate exclusively, output from main control CPU 12 is performed. The first tri-state buffer 22 of the CPU 21 for W-CDMA communication and the second tri-state buffer 32 of the CPU 31 for PDC communication are exclusively set to a high impedance state by the bus valid signal 104, so that the W-CDMA communication is performed. Control is performed so that only one of the unit 1 and the PDC communication unit 2 can access the shared memory 10. As a result, an external arbiter circuit for switching the CPU and a circuit for switching the bus become unnecessary, so that the memory can be easily shared, and the number of components and the mounting area can be reduced.
[0051]
In particular, in the case of a portable communication terminal having two communication systems such as the W-CDMA communication unit 1 and the PDC communication unit 2 as in the above-described embodiment, the memory division control circuit can be realized by a simple logic circuit.
[0052]
Further, in the portable communication terminal according to the above-described embodiment, since the memory upper address signal is changed in response to the bus valid signal 104, the area of one shared memory 10 can be divided and used by two CPUs. . Moreover, by using the address priority signal 103, the entire area of the shared memory 10 can be accessed from the W-CDMA communication CPU 21, and the software can be easily changed.
[0053]
In the portable communication terminal according to the above-described embodiment, the W-CDMA communication CPU 21 is configured to supply the address priority signal 103 and the CPU upper address signal 102 to the memory division control circuit 11, but FIG. As shown, the PDC communication CPU 31 can be modified so as to supply the address priority signal 103 and the CPU upper address signal 102 to the memory division control circuit 11. The operation of the portable communication terminal according to this modified example is the same as the operation of the portable communication terminal according to the above-described embodiment except that the PDC communication CPU 31 outputs the address priority signal 103 and the CPU upper address signal 102. Is the same.
[0054]
In addition, the portable communication terminal according to the above-described embodiment is configured to communicate using two communication systems such as the W-CDMA communication unit 1 and the PDC communication unit 2, but performs communication using a communication system other than the above. It can be configured as follows. Further, the number of communication systems is not limited to two, and communication can be performed using three or more communication systems. Further, the shared memory 10 may be divided so that a plurality of CPUs can access the entire area of the shared memory 10 without using the memory upper address signal 103.
[0055]
【The invention's effect】
As described above in detail, according to the present invention, a memory can be shared by a plurality of CPUs that execute processing for performing communication by a plurality of communication methods with a simple configuration, and the entire contents of the memory can be easily stored. A portable communication terminal that can be changed and a method of sharing the memory thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a portable communication terminal according to an embodiment of the present invention.
FIG. 2 is a flowchart for explaining an operation of the portable communication terminal according to the embodiment of the present invention.
FIG. 3 is a timing chart for explaining an operation of the portable communication terminal according to the embodiment of the present invention.
FIG. 4 is a diagram showing an allocation state of a shared memory in a state where a W-CDMA communication unit is valid in the portable communication terminal according to the embodiment of the present invention.
FIG. 5 is a diagram showing an allocation state of a shared memory in a state where a PDC communication unit is valid in the portable communication terminal according to the embodiment of the present invention.
FIG. 6 is a flowchart illustrating an operation when changing software in the portable communication terminal according to the embodiment of the present invention.
FIG. 7 is a timing chart illustrating an operation when changing software in the portable communication terminal according to the embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a modification of the portable communication terminal according to the embodiment of the present invention.
[Explanation of symbols]
1 W-CDMA communication unit
2 PDC communication unit
10 Shared memory
11 Memory division control circuit
12 Main control CPU
13 Inverter
20 W-CDMA radio unit
21 W-CDMA communication CPU
22 1st tri-state buffer
30 PDC radio section
31 CPU for PDC communication
32 2nd tri-state buffer
100 shared memory bus
101 Memory upper address signal
102 CPU upper address signal
103 Address priority signal
104 Bus valid signal
105 System control bus

Claims (6)

A first CPU that executes processing for performing communication by the first communication method,
A second CPU that executes processing for performing communication by the second communication method,
A memory connected to the first CPU and the second CPU by a bus;
When the first CPU accesses the memory, the connection of the second CPU to the bus is set to a high impedance state, and when the second CPU accesses the memory, the connection of the first CPU to the bus is high. A portable communication terminal that changes to an impedance state. A memory division control circuit that generates an upper address signal of the address signals to be sent to the memory,
2. The portable communication terminal according to claim 1, wherein the memory division control circuit generates an upper address signal such that an area of the memory accessed by the first CPU is different from an area of the memory accessed by the second CPU. 3. . The portable memory according to claim 2, wherein the memory division control circuit generates an upper address signal that allows the first CPU to access an entire area of the memory when software stored in the memory is changed. Communication terminal. A first CPU that executes processing for performing communication by the first communication method,
A second CPU that executes processing for performing communication by the second communication method,
A memory connected to the first CPU and the second CPU by a bus;
Setting the connection of the second CPU to the bus to a high impedance state when the first CPU accesses the memory;
Setting a connection portion of the first CPU to the bus to a high impedance state when the second CPU accesses the memory;
A method for sharing a memory of a portable communication terminal, comprising: Generating an upper address signal of the address signals to be sent to the memory,
5. The mobile phone according to claim 4, wherein the step of generating the upper address signal generates an upper address signal such that an area of the memory accessed by the first CPU is different from an area of the memory accessed by the second CPU. Sharing method for mobile communication terminals. 6. The mobile phone according to claim 5, wherein the step of generating the upper address signal generates an upper address signal that allows the first CPU to access an entire area of the memory when software stored in the memory is changed. Sharing method for mobile communication terminals.

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