JP2006350573A - Data transfer controller, data transfer control method, data transfer device, image forming device, data transfer control program and computer-readable recording medium recording control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform band guarantee to a prescribed bus master while suppressing that a system design becomes difficult. <P>SOLUTION: When each of the bus masters each controlling data transfer via a bus circuit outputs data transfer requirement, an arbitration circuit 42 makes one bus master execute the data transfer on the basis of each priority set in each bus master performing the output. The arbitration circuit 42 includes: a band measurement circuit 52 measuring an effective band about the data transfer by the bus master outputting band guarantee requirement; and a priority decision circuit 51 changing the priority set in the bus master outputting the band guarantee requirement according to the measured effective band. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device for controlling data transfer via a bus, a data transfer device including the data transfer control device, an image forming apparatus including the data transfer device, a data transfer control method, a data transfer control program, and The present invention relates to a computer-readable recording medium on which the control program is recorded.

  Conventionally, in a computer system, a configuration has been realized in which each of a plurality of devices communicate with each other via a single bus circuit. In such a system, a bus master and a bus target are connected to the bus circuit.

  The bus master has a function of acquiring a right to use a data transfer path in the bus circuit (access right to the transfer path) by outputting a data transfer request and controlling data transfer via the bus circuit. The device includes a CPU (Central Processing Unit) interface, a DMA (Direct Memory Access) controller, and the like.

  The bus target is a device that reads data from a transfer source device or writes data to a transfer destination device in data transfer controlled by the bus master. A (Random Access Memory) controller, a ROM (Read Only Memory) controller, an I / O (Input / Output) controller, and the like are applicable.

  In such a computer system, the bus master controls data transfer (data communication) between the bus master and the bus target by accessing the bus target via the bus circuit.

  In the computer system described above, arbitration by the bus arbiter is performed in order to avoid a situation in which a plurality of bus masters simultaneously use the same data transfer path. This arbitration will be described below. When attempting to access a bus target, the bus master first outputs a data transfer request (bus use request). On the other hand, the bus arbiter gives transfer permission (bus use permission) to the bus master that has output the data transfer request. The bus master can use the data transfer path included in the bus circuit by obtaining this transfer permission, can access the bus target via the bus circuit, and can connect the bus master and the bus target. The data transfer between them can be controlled.

  Here, the priority of the right to use the data transfer path is assigned to each bus master. When two or more bus masters simultaneously output data transfer requests, the bus arbiter has the highest priority (hereinafter, “ Transfer permission is given only to a bus master for which "the highest priority" is set. In this way, the bus arbiter arbitrates the data transfer request from each bus master, and avoids a situation in which a plurality of bus masters simultaneously use the data transfer path included in the bus circuit.

  By the way, when the computer system as described above is applied to, for example, a printer, a video display device, or the like, it is preferable to guarantee the bandwidth of the bus master to some extent (referred to as “bandwidth guarantee”). The bus master bandwidth indicates the amount of transfer data that the bus master can secure per unit time.

Here, the reason why the bandwidth should be guaranteed for a predetermined bus master will be described below using a printer as an example. In the case of a printer, if image data of a predetermined amount or more per unit time is not continuously transmitted to a printer engine that is executing print processing, supply of image data to the printer engine will not be in time for the above print processing, and print There is a possibility that the displayed image will be abnormal. Therefore, it is preferable to guarantee the bandwidth for the bus master that controls the transfer of image data to the printer engine.
JP-A-8-63429 (published March 8, 1996) JP 11-184807 A (published July 9, 1999) JP 2000-207355 A (released July 28, 2000) JP 2001-117861 A (published on April 27, 2001)

  Here, techniques for arbitrating the data transfer request of each bus master are disclosed in Patent Documents 1 to 4 described above.

  According to Patent Document 1 or Patent Document 3, a method is disclosed in which the priority assigned to each bus master is switched periodically without being fixed, and the frequency assigned the highest priority for each bus master is set. Yes.

  However, if this method is used to guarantee the bandwidth of a given bus master, not only the performance of each bus master and bus, the limit value of the bandwidth of each bus master, the frequency of transfer requests of each bus master, etc. After predicting the bandwidth of a given bus master, it is necessary to set the frequency of assigning the highest priority for each bus master and the algorithm for switching the priority, and such setting will lead to system design obfuscation. Problems arise.

  Further, Patent Document 2 discloses a method of limiting the output time of a bus master data transfer request (request time per request) so as to be different for each bus master. Further, according to Patent Document 4, a method is disclosed in which each bus master can set a different usage time of a bus circuit for each bus master.

  However, even when these methods are used to guarantee the bandwidth of a predetermined bus master, not only the performance of each bus master and the bus, the limit value of the bandwidth of each bus master, the frequency of transfer requests of each bus master, etc. It is necessary to set the request time of data transfer request and the use time of the bus circuit in each bus master after predicting the bandwidth of the bus master, and such setting causes a problem that the system design becomes difficult. .

  The present invention relates to a data transfer control device, a data transfer control method, a data transfer device, an image forming apparatus, and a data transfer control capable of guaranteeing a bandwidth for a predetermined transfer control unit (bus master) while suppressing the difficulty of system design. It is an object of the present invention to provide a program and a computer-readable recording medium on which the control program is recorded.

  In the data transfer control device of the present invention, in order to achieve the above object, a plurality of transfer control units that control data transfer through the transfer circuit share the transfer circuit, and each transfer control unit requests a data transfer request. In the data transfer control device that executes data transfer by any one transfer control unit based on each priority set in each transfer control unit, a predetermined one of the plurality of transfer control units For data transfer by the transfer control unit, the measuring means for measuring the transfer data amount per unit time and the priority set in the predetermined transfer control unit according to the measured transfer data amount per unit time are changed. Priority control means.

  According to the above configuration, the amount of transfer data per unit time can be measured in real time for data transfer by a predetermined transfer control unit among a plurality of transfer control units (hereinafter, the amount of transfer data measured per unit time is measured). The priority set in the predetermined transfer control unit can be changed according to the effective bandwidth.

  Therefore, if the execution frequency of the data transfer by the predetermined transfer control unit is adjusted by appropriately changing the priority set in the predetermined transfer control unit so that the effective bandwidth is maintained to some extent, the predetermined bandwidth Bandwidth guarantee can be performed for the transfer control unit.

  Further, according to the above configuration, since the bandwidth can be guaranteed for the predetermined transfer control unit only by providing the measuring unit and the priority changing unit, the system after predicting the band of the predetermined transfer control unit No need to design. Therefore, there is an effect that it is possible to guarantee the bandwidth for a predetermined transfer control unit while suppressing the obfuscation of the system design.

  Therefore, in addition to the above configuration, the data transfer control device according to the present invention is configured so that the priority control means is connected to the predetermined transfer control unit when the effective bandwidth is equal to or less than the target value, rather than exceeding the target value. It is preferable to improve the priority to be set.

  According to the above configuration, when the effective bandwidth in the predetermined transfer control unit becomes equal to or less than the target value, it is possible to increase the execution frequency of data transfer by the predetermined transfer control unit. Therefore, it is possible to suppress the effective band of the predetermined transfer control unit from being excessively reduced from the target value, and it becomes easy to maintain the effective band to a certain extent. Further, according to this configuration, when the effective bandwidth of the predetermined transfer control unit exceeds the target value, the priority set in the predetermined transfer control unit is lower than in the case of the target value or less. The frequency of execution of data transfer by the transfer control unit can be reduced. Therefore, when the effective bandwidth of a predetermined transfer control unit is excessive beyond the target value, it is possible to give room for other transfer control units to control data transfer. Therefore, although the effective bandwidth in the predetermined transfer control unit is excessive, the data transfer by the predetermined transfer control unit has the highest priority, and the bandwidth of the other transfer control unit is squeezed meaninglessly. Can be suppressed.

  Further, in the data transfer control device of the present invention, in addition to the above configuration, the priority control means sets the highest priority to the predetermined transfer control unit when the effective bandwidth is equal to or less than a target value. Is preferred.

  According to the above configuration, when the effective bandwidth in the predetermined transfer control unit falls below the target value, data transfer by the predetermined transfer control unit can be performed with the highest priority, and the effective bandwidth of the predetermined transfer control unit can be maintained. It becomes easier.

  In addition to the above configuration, the data transfer control device of the present invention is given a priority according to a predetermined rule for each transfer control unit, and the priority control means has the effective bandwidth of a target value or less. In this case, a priority higher than each priority according to the predetermined rule is set as the highest priority in the predetermined transfer control unit, and the other transfer control unit is given to the other transfer control unit. And when the effective bandwidth exceeds a target value, the priority given to the predetermined transfer control unit according to the predetermined rule is set to the predetermined transfer control unit. The configuration may be such that the priority given to the other transfer control unit is set to the other transfer control unit according to the predetermined rule.

  According to the above configuration, the priority given to the transfer control unit is always set to the transfer control unit other than the predetermined transfer control unit according to the predetermined rule. Also, in the predetermined transfer control unit, when the effective bandwidth exceeds the target value, the priority given to the predetermined transfer control unit is set according to a predetermined rule. On the other hand, when the effective bandwidth is equal to or less than the target value, a priority higher than each priority according to the predetermined rule is set in the predetermined transfer control unit. Thereby, when the effective band is equal to or less than the target value, the priority set in the predetermined transfer control unit can be improved as compared with the case where the effective band exceeds the target value, and the predetermined transfer control unit Can be given the highest priority.

  Further, in the data transfer control device of the present invention, when there are a plurality of predetermined transfer control units whose effective bandwidth is equal to or less than the target value, to which predetermined transfer control unit the highest priority should be set Occurs. This is because if the highest priority is set for each of the plurality of transfer control units, the data transfer control device cannot determine which predetermined transfer control unit should perform data transfer. It is.

  Therefore, when there are a plurality of predetermined transfer control units whose effective bandwidth is equal to or less than the target value, the data transfer control device of the present invention is based on each priority given to each predetermined transfer control unit according to the predetermined rule. Thus, a higher priority than each priority according to the predetermined rule may be set only in any one predetermined transfer control unit. Thus, the data transfer control device can determine which predetermined transfer control unit should perform data transfer.

  In the data transfer control device of the present invention, when there are a plurality of predetermined transfer control units whose effective bandwidth is equal to or less than the target value, the deficiency parameter indicating the deficiency of the transfer data amount with respect to the target value is the highest. A configuration may be adopted in which only a predetermined transfer control unit is given a priority higher than each priority according to the predetermined rule. As a result, it is possible to give the highest priority to data transfer by the transfer control unit having the highest degree of effective bandwidth shortage with respect to the target value and the highest necessity for data transfer.

  The deficiency parameter may be an absolute value of a difference between the target value and the transfer data amount. Thereby, the highest priority can be given to data transfer by a predetermined transfer control unit whose effective bandwidth is farthest from the target value.

  Further, the deficiency parameter may be a value obtained by dividing an absolute value of a difference between the target value and the transfer data amount by the target value. Thereby, the highest priority can be given to the data transfer of a predetermined transfer control unit in which the ratio of the insufficient amount of the effective bandwidth to the target value is the largest. Such a configuration is suitable when each of the predetermined transfer control units greatly differs from the target value.

  In the data transfer control device of the present invention, the predetermined transfer control unit is preferably a transfer control unit that outputs a bandwidth guarantee request.

  According to the above configuration, the priority change process described above is performed only for the transfer control unit that outputs the bandwidth guarantee request. Therefore, only the transfer control unit requiring bandwidth guarantee can be targeted, and the priority changing process described above can be performed only when bandwidth guarantee is necessary.

  Furthermore, in addition to the above-described configuration, the data transfer control device of the present invention controls the measurement unit to control the predetermined transfer control unit only during a period in which the predetermined transfer control unit outputs the bandwidth guarantee request. It is preferable to measure the effective bandwidth for the data transfer to be performed.

  According to the above configuration, the measuring unit measures the effective band only during the period in which the band guarantee request is output. As a result, the measurement means performs measurement only within a necessary period without always performing measurement, and can suppress an increase in error due to continued measurement, thereby enabling more accurate measurement. It can be performed.

  In addition to the above-described configuration, the data transfer control device of the present invention preferably has a configuration in which the measurement unit resets the measured effective band every predetermined period.

  According to the above configuration, since the effective bandwidth measured every predetermined period is reset, even if an error occurs in the effective band being measured, the error can be canceled every predetermined period. .

  The present invention can also be expressed as a data transfer device including the data transfer control device, the transfer circuit, and the plurality of transfer control units sharing the transfer circuit. It is possible to achieve substantially the same effect as the data transfer control device.

  Furthermore, the data transfer apparatus of the present invention can be applied to an image forming apparatus including a printing unit that performs processing for printing an image and an image data transfer control unit that controls transfer of image data to the printing unit. . In this case, if the image data transfer control unit is configured as the predetermined transfer control unit, the image data transfer bandwidth can be guaranteed by the image data transfer control unit. The above image data can be supplied. Therefore, it is possible to suppress printing defects due to insufficient supply of image data to the printing unit.

  Further, according to the present invention, a plurality of transfer control units that control data transfer through the transfer circuit share the transfer circuit. When a data transfer request is received from each transfer control unit, the transfer control unit sets the transfer control unit. In the data transfer control method for executing data transfer by any one transfer control unit based on each priority, data transfer by a predetermined transfer control unit among the plurality of transfer control units per unit time A data transfer control method comprising: a step of measuring a transfer data amount of: and a step of changing a priority set in the predetermined transfer control unit in accordance with the measured transfer data amount per unit time Can be expressed. This data transfer control method can achieve substantially the same effect as the above-described data transfer control device.

  The present invention may be realized by a computer. In this case, a data transfer control program that causes the computer to operate as each of the above means falls within the scope of the present invention, and the computer that records this data transfer control program A readable recording medium falls within the scope of the present invention.

  As described above, the data transfer control device according to the present invention includes the measuring unit that measures the transfer data amount per unit time for the data transfer by the predetermined transfer control unit among the plurality of transfer control units, and the above-described measurement. Priority control means for changing the priority set in the predetermined transfer control unit in accordance with the transfer data amount per unit time.

  Therefore, by appropriately changing the priority set in the predetermined transfer control unit so that the effective band of the data transfer by the predetermined transfer control unit is maintained to some extent, the data transfer by the predetermined transfer control unit is changed. By adjusting the execution frequency, it is possible to guarantee the bandwidth to a predetermined transfer control unit.

  Further, according to the above configuration, since the bandwidth can be guaranteed for the predetermined transfer control unit only by providing the measuring unit and the priority changing unit, the system after predicting the band of the predetermined transfer control unit No need to design. Therefore, there is an effect that it is possible to guarantee the bandwidth for a predetermined transfer control unit while suppressing the obfuscation of the system design.

  The data transfer control method, data transfer apparatus, image forming apparatus, data transfer control program, and computer-readable recording medium on which the control program is recorded are also substantially the same as the above-described data transfer control apparatus of the present invention. The effect of.

  Hereinafter, an embodiment of a data transfer control device of the present invention will be described with reference to the drawings. In the present embodiment, an arbitration circuit provided in a printer controller in the printer will be described as the data transfer control device.

  First, an outline of the internal configuration of the printer will be described. FIG. 2 is a block diagram showing the internal configuration of the printer. As shown in FIG. 2, the printer 10 includes a printer controller 11 and a printer engine 12.

  A printer (image forming apparatus) 10 is an apparatus that forms an image on paper based on data input from the outside. For example, an electrophotographic copying machine, an ink jet printer, an MFP (Multi Function Printer), a photo printing apparatus Etc.

  The printer controller 11 is a control device (information processing device) that comprehensively controls the operation of the printer 10, and as shown in the figure, is a computer composed of a CPU, RAM, ROM, I / O device, system controller, and the like. is there. Further, the printer controller 11 executes processing for receiving data indicated in the printer language from the outside, converting the received data into image data in a bitmap format, and sending the image data to the printer engine 12.

  The printer engine (printing unit) 12 is an apparatus that receives image data from the printer controller 11 and performs processing for forming an image on a sheet based on the received image data.

  Next, the internal configuration of the printer controller 11 will be described in detail. As shown in FIG. 2, the printer controller 11 includes a CPU 21, a RAM 22, a ROM 23, an I / O device 24, and a system controller 25. Each of the CPU 21, RAM 22, ROM 23, I / O device 24, and printer engine 12 is connected to the system controller 25.

  The CPU 21 performs information processing such as data conversion / processing and various arithmetic processes. Specifically, the CPU 21 performs processing / conversion / calculation processing of various data expanded in the RAM 22 by accessing the RAM 22. Further, the CPU 21 gives a command to the system controller 25 to change any one of the RAM 22, ROM 23, and I / O device 24 to any one of the RAM 22, ROM 23, I / O device 24, and printer engine 12. Data can be transferred.

  The RAM 22 is a memory in which various control programs in the printer controller 11 and predetermined data necessary for executing the control programs are written, and various data sent from the outside are written. The ROM 23 is a read-only storage device and stores various data. The I / O device 24 performs data input / output with the outside, and corresponds to a communication interface, a keyboard, a display device, and the like.

  The system controller 25 realizes data (including a program) transfer between the CPU 21, RAM 22, ROM 23, I / O device 24, and printer engine 12, and is configured by, for example, LSI (Large Scale Integration). Is done.

  Hereinafter, the CPU 21, RAM 22, ROM 23, I / O device 24, and printer engine 12 that may be the data transfer destination or data transfer destination may be referred to as “devices”.

  Further, as shown in FIG. 2, the system controller (data transfer device) 25 includes a bus circuit 37 for performing data transfer, and further, a CPU interface 31a, a DMA controller 31b, an engine connected to the bus circuit 37. The configuration includes an interface 31c, a ROM controller 32a, a RAM controller 32b, and an I / O controller 32c.

  The CPU interface 31 a is connected to the CPU 21, the engine interface 31 c is connected to the printer engine 12, the ROM controller 32 a is connected to the ROM 23, the RAM controller 32 b is connected to the RAM 22, and the I / O controller 32 c is connected to the I / O device 24. Connected.

  The CPU interface 31a, DMA controller 31b, and engine interface 31c control data transfer realized by the system controller 25.

  Specifically, the CPU interface 31 a or the DMA controller 31 b controls data transfer between the ROM 23, RAM 22, and I / O device 24. In the data transfer controlled by the CPU interface 31, data is transferred from the transfer source device to the CPU 21 via the bus circuit 37 and the CPU interface 31, and from the CPU 21 to the transfer destination device via the CPU interface 31 and the bus circuit 37. Forwarded to In data transfer controlled by the DMA controller 31b, data is transferred from the transfer source device to the DMA controller 31b via the bus circuit 37, and transferred from the DMA controller 31b to the transfer destination device via the bus circuit 37. .

  The engine interface (image data transfer control unit) 31c controls data transfer from the RAM 22 to the printer engine 12. In this data transfer, the data is transferred from the RAM 22 to the engine interface 31c via the bus circuit 37, and transferred from the engine interface 31c to the printer engine 12.

  Further, the CPU interface 31a, the DMA controller 31b, and the engine interface 31c transmit a data transfer request signal (hereinafter referred to as “data transfer request”) to the bus circuit 37 before each data transfer is controlled. As will be described later, the bus circuit 37 gives a transfer permission signal (hereinafter referred to as “transfer permission”) to the CPU interface 31a, the DMA controller 31b, and the engine interface 31c that have transmitted the data transfer request. The CPU interface 31a, the DMA controller 31b, and the engine interface 31c can obtain the right to use the data transmission path included in the bus circuit 37 and control the data transfer via the bus circuit 37 by receiving the transfer permission. it can.

  In this embodiment, a CPU interface 31a having a function of acquiring a right to use a data transfer path included in the bus circuit 37 by outputting a data transfer request and controlling data transfer via the bus circuit 37. The DMA controller 31b and the engine interface 31c may be referred to as bus masters (transfer control units).

  The ROM controller 32a, RAM controller 32b, and I / O controller 32c have a function of reading data from a transfer source device and writing data to a transfer destination device in data transfer controlled by the bus master 31. It is what you have.

  Specifically, the ROM controller 32 a reads data from the ROM 23. The RAM controller 32 b reads data from the RAM 22 or writes data to the RAM 22. The I / O controller 32 c reads data from the I / O device 24 or writes data to the I / O device 24.

  In the present embodiment, in the data transfer activated by the bus master, the ROM controller 32a, the RAM controller 32b, and the like read out data from the transfer source device or write data to the transfer destination device. Each of the I / O controllers 32c may be referred to as a bus target.

  The engine interface 31c is a bus master that controls data transfer from the RAM 22 to the printer engine 12. Writing data to the printer engine 12 that is a transfer destination device is performed by the engine interface 31c itself. Therefore, the engine interface 31c is a bus master and also has a function as a bus target connected to the transfer destination device.

  When receiving a data transfer request from the bus master 31, the bus circuit 37 gives a transfer permission to the bus master that has output the data transfer request. Further, the bus circuit 37 is connected to a bus target connected to a transfer source device and a transfer destination device in order to perform data transfer controlled by a bus master that has given permission to transfer. A bus target is selected, and a data read command or write command is transmitted to the selected bus target.

  Then, data is read from the transfer source device by the bus target connected to the transfer source device, and the read data is transferred to the transfer destination device via the bus circuit 37 and the bus master 31 that controls data transfer. It is transmitted to the connected bus target 32. Further, the bus target 32 connected to the transfer destination device writes the data transmitted via the bus circuit 37 to the transfer destination device. In this way, data transfer between devices is realized.

  However, in data transfer controlled by the engine interface 31c, the engine interface 31c functions as a bus master and a bus target of the transfer destination device. Therefore, in this case, the data read from the transfer source device (RAM 22) is transmitted to the engine interface 31c via the bus circuit 37, and then the data is written to the printer engine 12 by the engine interface 31c.

  Next, the configuration of the bus circuit 37 described above will be described in detail. FIG. 3 is a block diagram showing the configuration of the bus circuit 37. As shown in the figure, the bus circuit 37 includes a transfer circuit 41 and an arbitration circuit 42.

  The transfer circuit 41 is connected to each bus master and each bus target, and has a function as a data transmission path between the bus master and the bus target. That is, the bus masters 31 a, 31 b, and 31 c share the transfer circuit 41 included in the bus circuit 37 and control data transfer through the transfer circuit 41.

  If the bus circuit 37 is an LSI, the transfer circuit 41 can be configured by integrating a selector and a control circuit. Further, the transfer circuit 41 may be a data line made of a hard wire, for example.

  The arbitration circuit (data transfer control device) 42 is connected to each of the bus masters 31a, 31b, and 31c, receives a data transfer request from the bus master 31, and gives a transfer permission to the bus master 31 that has output the data transfer request. Circuit. Here, when the arbitration circuit 42 receives a data transfer request from each of the plurality of bus masters 31... At the same time, the arbitration circuit 42 grants transfer permission only to any one of the bus masters 31. Arbitrary data transfer request.

  Here, each of the bus masters 31 cannot start and control the data transfer without receiving the transfer permission. Therefore, the arbitration circuit 42 performs the above arbitration, thereby avoiding a situation in which data transfer by a certain bus master 31 and data transfer by another bus master 31 are simultaneously executed in the transfer circuit 41 included in the bus circuit 37. .

  Next, details of the arbitration circuit 42 will be described. FIG. 1 is a block diagram showing the configuration of the arbitration circuit 42.

  As illustrated in FIG. 1, the arbitration circuit 42 includes a priority determination circuit 51.

  The priority determination circuit 51 is connected to each of the bus masters 31a, 31b, and 31c. When a data transfer request is received from each of the bus masters 31a, 31b, and 31c, the priority determination circuit 51 is given in advance to each of the bus masters 31a, 31b, and 31c according to a predetermined rule. Each priority level is set in each of the bus masters 31a, 31b, and 31c, the priority levels set are compared, the bus master that should be given the highest priority is determined, and transfer permission is transmitted only to the bus master 31 that should be given the highest priority. (That is, data transfer permission is transmitted to any one of the bus masters 31).

  In FIG. 1, "transfer request a" indicates a data transfer request output by the bus master 31a, "transfer request b" indicates a data transfer request output by the bus master 31b, and "transfer request c" is output by the bus master 31c. The data transfer request is shown. Further, in FIG. 1, “transfer permission a” indicates a transfer permission transmitted to the bus master 31a, “transfer permission b” indicates a transfer permission transmitted to the bus master 31b, and “transfer permission c” transmits to the bus master 31c. The transfer permission to be performed is shown.

  Further, the priority determination circuit 51 may receive each priority (information indicating the priority) given to each bus master 31 from each bus master 31a, 31b, 31c according to the predetermined rule. You may read from the storage device which does not.

  In FIG. 1, “priority a” is information indicating the priority given to the bus master 31a according to the predetermined rule, and “priority b” is given to the bus master 31b according to the predetermined rule. The information indicating the priority, and the “priority c” is information indicating the priority given to the bus master 31c according to the predetermined rule.

  Next, the priorities and predetermined rules described above will be described. In the present embodiment, “priority a” has higher priority than “priority b” and “priority c”, and “priority b” has higher priority than “priority c”. The predetermined rule described above is a rule (also referred to as “fixed priority rule”) in which the priority given to each bus master 31a, 31b, and 31c is fixed. That is, “priority a” is a priority given only to the bus master 31a, “priority b” is a priority given only to the bus master 31b, and “priority c” is given only to the bus master 31c. Priority.

  Next, processing in the priority determination circuit 51 will be described. FIG. 4 illustrates the timing at which the priority determination circuit 51 receives a data transfer request from each of the bus masters 31a, 31b, and 31c, and the priority determination circuit 51 that uses the bus masters 31a and 31b when the fixed priority rule is applied. -It is a timing chart which showed the timing which transmits transfer permission to each of 31a.

  In the “transfer data” column of the same figure, a frame indicating “A” indicates that the data transfer controlled by the bus master 31a has been executed once, and a frame indicating “B” indicates the bus master 31b. The controlled data transfer is executed once, and the frame indicating “C” indicates that the data transfer controlled by the bus master 31c is executed once.

  As shown in the figure, when the priority determination circuit 51 receives a data transfer request from each of the bus masters 31a, 31b, and 31c at the same time, each priority given to each of the bus masters 31a, 31b, and 31c according to the predetermined rule. Get the priority. The priority determination circuit 51 sets the priority given to each of the bus masters 31a, 31b, and 31c. That is, the priority determination circuit 51 receives “priority a” from the bus master 31a, sets this “priority a” to the bus master 31a, receives “priority b” from the bus master 31b, and receives this “priority”. “b” is set to the bus master 31b, “priority b” is received from the bus master 31c, and this “priority c” is set to the bus master 31b.

  Then, when the priority determination circuit 51 compares the set “priority a”, “priority b”, and “priority c” and determines that “priority a” is the highest, the setting of “priority a” is performed. The given bus master 31a is given the highest priority, and transfer permission is transmitted only to the bus master 31a. While the transfer permission is being transmitted to the bus master 31a, data transfer is performed by the bus master 31a.

  When the priority determination circuit 51 receives a transfer request from each of the bus masters 31a and 31b at the same time, the priority determination circuit 51 should give priority to the bus master 31b by comparing the above "priority b" and "priority c". And the transfer permission is transmitted only to the bus master 31b. While the transfer permission is transmitted to the bus master 31b, data transfer is performed by the bus master 31b.

  Furthermore, when the priority determination circuit 51 receives a transfer request from only the bus master 31c, the priority determination circuit 51 transmits a transfer permission to the bus master 31c. While the transfer permission is transmitted to the bus master 31c, the data transfer by the bus master 31c is performed.

  As described above, the priority determination circuit 51 grants transfer permission only to any one of the bus masters 31 based on the respective priorities set for the respective bus masters 31a, 31b, and 31c.

  Then, the priority determination circuit 51, after giving the transfer permission, the bus target 32 connected to the transfer source device designated by the bus master 31 that gave the transfer permission, and the bus connected to the transfer destination device. The target 32 is selected, and a data read command and a write command are output to each selected bus target (see FIG. 1). The data transfer request output by each bus master 31 includes information on the transfer source device and the transfer destination device, and the priority determination circuit 51 has already been sent from the bus master 31 that has given transfer permission. The bus target 32 is selected based on the data transfer request.

  Further, in the arbitration circuit 42 according to the present embodiment, a bandwidth guarantee mode that actively guarantees the bandwidth can be set for any one or more of the bus masters 31a, 31b, and 31c. Hereinafter, this bandwidth guarantee mode will be described in detail.

  First, each of the bus masters 31a, 31b, and 31c is set to output a bandwidth guarantee request signal (hereinafter referred to as a “bandwidth guarantee request”) only during a period when the necessity of bandwidth guarantee occurs. . Each of the bus masters 31a, 31b, and 31c can set the band guarantee mode by outputting the band guarantee request.

  As shown in FIG. 1, the arbitration circuit 42 includes, in addition to the priority determination circuit 51, band measurement circuits 52 a, 52 b, and 52 c connected to the priority determination circuit 51. Hereinafter, the band measurement circuits 52a, 52b, and 52c will be described in order from the band measurement circuit 52c.

  The band measurement circuit 52c is connected to the bus master (engine interface) 31c and includes a timer and a transfer counter as shown in FIG.

  When the bandwidth measuring circuit 52c receives the bandwidth guarantee request c and the target bandwidth c (information indicating the target bandwidth for data transfer of the bus master 31c) output from the bus master 31c, the bandwidth measuring circuit 52c performs the bus master for the period during which the bandwidth guarantee request c is received. The effective bandwidth (transfer data amount per unit time) of the data transfer by 31c is measured, the difference between the target bandwidth c and the effective bandwidth is calculated, and a difference signal indicating this difference is transmitted to the priority determination circuit 51. To do.

  The bandwidth measuring circuit 52c counts the elapsed time with a timer for the period during which the bandwidth guarantee request c is received, counts the number of data transfers of the bus master 31c with a transfer counter, and calculates the effective bandwidth from the results of these counts. Is estimated. Further, without performing the above estimation, the number of transfers per unit time itself may be estimated as the “transfer data amount per unit time”.

  Further, the transfer counter performs the above-mentioned counting by obtaining a data transfer flag (a flag indicating which bus master is performing transfer control) from the data transferred in the transfer circuit 41. The band measurement circuit 52c receives the target band c from the bus master 31c. However, the target band c may be acquired from a storage device (not shown).

  The priority determination circuit 51 determines whether or not the effective band for data transfer by the bus master 31c is equal to or less than the target band c. If the effective band is equal to or less than the target band c, The “priority S” is set in the bus master 31c without setting the “priority c” according to the predetermined rule. Further, when the effective band exceeds the target band c, the priority determination circuit 51 sets “priority c” according to the predetermined rule without setting “priority S” in the bus master 31c. To do.

  The “priority S” is higher in priority than “priority a”, “priority b”, and “priority c” given to each bus master 31... According to the predetermined rule. Is high.

  Further, as shown in FIG. 1, each of the bandwidth measuring circuits 52a and 52b includes a timer and a transfer counter, like the bandwidth measuring circuit 52c. The band measuring circuit 52a is connected to the bus master 31a and receives the band guarantee request a and the target band a (information indicating the target band for data transfer of the bus master 31a) output from the bus master 31a. 52b is connected to the bus master 31b and receives the bandwidth guarantee request b and the target bandwidth b (information indicating the target bandwidth for data transfer of the bus master 31b) output from the bus master 31b.

  As in the case of the bandwidth measuring circuit 52c, the bandwidth measuring circuit 52a measures the effective bandwidth of data transfer by the bus master 31a, calculates the difference between the target bandwidth a and the effective bandwidth, and indicates this difference. The difference signal is transmitted to the priority determination circuit 51.

  Then, the priority determination circuit 51 determines whether or not the effective band for data transfer by the bus master 31a is equal to or less than the target band a based on the difference signal, and when the effective band is equal to or less than the target band a, The “priority S” is set in the bus master 31c without setting the “priority a” according to the predetermined rule. Further, when the effective band exceeds the target band a, the priority determination circuit 51 sets “priority a” in accordance with the predetermined rule without setting “priority S” in the bus master 31c. To do.

  Further, similarly to the bandwidth measuring circuits 52a and 52c, the bandwidth measuring circuit 52b measures the effective bandwidth of the data transfer by the bus master 31b, and further calculates the difference between the target bandwidth b and the effective bandwidth. Is transmitted to the priority determination circuit 51.

  Then, the priority determination circuit 51 determines whether or not the effective band for data transfer by the bus master 31b is equal to or less than the target band b. If the effective band is equal to or less than the target band b, In the bus master 31b, the “priority S” is set without setting the “priority b” according to the predetermined rule. Further, when the effective band exceeds the target band b, the priority determination circuit 51 sets “priority b” according to the predetermined rule without setting “priority S” to the bus master 31c. Set.

  According to the above configuration, when any one of the bus masters 31 a, 31 b, and 31 c is outputting a bandwidth guarantee request, the bandwidth measuring circuit 52 connected to the bus master 31 is connected to the bus master 31. The effective bandwidth is measured, and the difference between the measured execution bandwidth and the target bandwidth is calculated.

  Then, the priority determination circuit 51 determines whether or not the effective bandwidth of the bus master 31 outputting the bandwidth guarantee request is equal to or less than the target bandwidth based on the calculated difference. When the effective bandwidth of the bus master 31 outputting the bandwidth guarantee request is equal to or less than the target bandwidth, the priority determination circuit 51 sets the priority S for the bus master 31 and does not output the bandwidth guarantee request. The priority given to the bus master 31 is set according to a predetermined rule. Therefore, when the effective bandwidth of the bus master 31 outputting the bandwidth guarantee request is equal to or less than the target bandwidth, the priority determination circuit 51 always transfers the data to the bus master 31 while the bus master 31 is outputting the data transfer request. It will give permission.

  Further, when the effective bandwidth of the bus master 31 outputting the bandwidth guarantee request exceeds the target bandwidth, the priority determination circuit 51 gives the bus master 31 outputting the bandwidth guarantee request to the bus master according to a predetermined rule. The given priority is set, and the priority given to the bus master is set according to a predetermined rule to the bus master 31 that has not output the bandwidth guarantee request. Therefore, in this case, transfer permission is not always given to the bus master 31 that outputs the bandwidth guarantee request, and transfer permission may be given to other bus masters 31 in some cases.

  Next, when only the bus master 31c outputs a bandwidth guarantee request, the transition of the effective bandwidth of the bus master 31c will be described with reference to the drawings. FIG. 5 shows the data transfer request timing of each bus master 31a, 31b, 31c, the bandwidth guarantee request timing of the bus master 31c, the transfer permission timing output to each bus master 31, and the bus master outputting the bandwidth guarantee request. It is a timing chart which showed transition of the effective band of 31c.

  In the “transfer data” column of FIG. 5, a frame indicating “A” indicates that data transfer has been performed once by the bus master 31a, and a frame indicating “B” indicates that data transfer has been performed once by the bus master 31b. The frame indicating “C” indicates that data transfer has been performed once by the bus master 31c. Further, the value shown in the column “transfer counter” in FIG. 5 indicates the count value of the transfer counter included in the band measuring circuit 52c connected to the bus master 31c. Further, the value shown in the “timer” column of FIG. 5 indicates the count value of the timer included in the band measuring circuit 52c. In the graph shown in FIG. 5, the horizontal axis indicates the elapsed time, and the vertical axis indicates the effective bandwidth for data transfer by the bus master 31c.

  In FIG. 5, first, at the timing α, each of the bus masters 31a, 31b, and 31c outputs a data transfer request, but none of the bus masters 31 outputs a bandwidth guarantee request. In this case, each bus master 31a, 31b, and 31c is set with a priority according to a predetermined rule, so that transfer permission is given to the bus master 31a with the priority a set.

  Thereafter, at timing β, the bus master 31c starts outputting the bandwidth guarantee request c. As a result, the bandwidth measuring circuit 52c connected to the bus master 31c starts measuring the effective bandwidth of data transfer by the bus master 31c. And while this band guarantee request | requirement c is output, this measurement is performed continuously.

  Since the measured effective bandwidth is equal to or less than the target bandwidth c, the priority of the bus master 31c is set to “priority S”, and the data transfer request of the bus master 31c is the data transfer of any other bus master 31a / 31b. Takes precedence over requests. As a result, even if each of the bus masters 31a, 31b, and 31c outputs a data transfer request, transfer permission is continuously given to the bus master 31c, and data transfer by the bus master 31c is repeated. As a result, the effective bandwidth for data transfer by the bus master 31c increases.

  Thereafter, when the effective bandwidth for data transfer by the bus master 31c exceeds the target bandwidth c at timing γ, the priority set for the bus master 31c is changed from “priority S” to “priority c”. As a result, the data transfer request of the bus masters 31a and 31b in which “priority a” and “priority b” are set has priority over the data transfer request of the bus master 31c. Since any of the bus masters 31a, 31b, and 31c outputs a data transfer request, transfer permission is given to the bus master 31a, and data transfer by the bus master 31c is stopped. As a result, the effective bandwidth of data transfer by the bus master 31c is reduced.

  If the effective bandwidth for data transfer by the bus master 31c continues to decrease and the effective bandwidth for data transfer by the bus master 31c falls below the target bandwidth c at timing δ, the priority set for the bus master 31c is changed from “priority c” to “ The priority is changed again to “S”. Thereby, even when each of the bus masters 31a, 31b, and 31c outputs a data transfer request, transfer permission is given to the bus master 31c, and data transfer by the bus master 31c is performed. As a result, the effective bandwidth of data transfer by the bus master 31c increases.

  By repeating the above processing, the effective bandwidth of the data transfer by the bus master 31c that outputs the bandwidth guarantee request can maintain a value near the target bandwidth c as shown in FIG. 5, and the bandwidth guarantee is given to the bus master 31c. It can be carried out.

  According to the embodiment described above, the bus masters 31a, 31b, and 31c that control data transfer through the transfer circuit 41 share the transfer circuit 41, and the arbitration circuit 42 is connected to the bus masters 31a, 31b, and 31c. When the data transfer request is received, the data transfer by the bus master 31 having given the transfer permission is performed by giving the transfer permission to any one of the bus masters 31 based on the respective priorities set for the bus masters 31a, 31b and 31c. Control to be executed. Further, the arbitration circuit 42 measures the above-described measurement with a bandwidth measuring circuit (measuring means) 52c that measures an effective bandwidth, which is a transfer data amount per unit time, for data transfer by the bus master 31 that outputs a bandwidth guarantee request. And a priority determination circuit (priority control means) 51 that changes the priority set for the bus master 31 outputting the bandwidth guarantee request according to the effective bandwidth.

  Therefore, for data transfer by the bus master 31c outputting the bandwidth guarantee request, the bandwidth measuring circuit 52c measures the effective bandwidth in real time, and the priority determination circuit 51 sets the priority set in the bus master 31c according to the effective bandwidth. You can change the degree. Therefore, if the execution frequency of the data transfer by the bus master 31c is adjusted by appropriately setting the priority set to the bus master 31c outputting the bandwidth guarantee request so that the effective bandwidth is maintained to some extent, Band guarantee can be performed for the bus master 31c.

  Further, according to the embodiment described above, the priority determination circuit 51 outputs the band guarantee request when the effective band is equal to or less than the target band (target value) than when the effective band exceeds the target band. The priority set in is improved.

  Therefore, when the effective bandwidth in the bus master 31 outputting the bandwidth guarantee request is equal to or less than the target bandwidth, the execution frequency of data transfer by the bus master 31 outputting the bandwidth guarantee request can be increased. Therefore, it is possible to suppress the effective bandwidth of the bus master 31 that is outputting the bandwidth guarantee request from being excessively reduced from the target value, and this makes it easy to maintain the effective bandwidth to a certain extent. If the effective bandwidth exceeds the target bandwidth, the priority set for the bus master 31 outputting the bandwidth guarantee request is lower than when the effective bandwidth is less than the target value. The frequency can be reduced. Therefore, when the effective bandwidth of the bus master 31 outputting the bandwidth guarantee request is becoming excessive beyond the target bandwidth, it is possible to give another bus master 31 a room for controlling data transfer. Therefore, although the effective bandwidth of the bus master 31 that outputs the bandwidth guarantee request is excessive, the data transfer by the bus master 31 is given the highest priority, and the bandwidth of the other bus masters 31 is compressed without meaning. The situation that it is done can be suppressed.

  In addition, when the effective bandwidth of the bus master 31 that outputs the bandwidth guarantee request is equal to or less than the target bandwidth, the priority determination circuit 51 sends each of the bus masters 31 that output the bandwidth guarantee request according to the predetermined rules. “Priority S” which is a priority higher than the priority is set.

  As a result, when the effective bandwidth in the bus master 31 outputting the bandwidth guarantee request is equal to or less than the target bandwidth, the data transfer by the bus master 31 outputting the bandwidth guarantee request can be performed with the highest priority. It becomes even easier to maintain the effective bandwidth of the bus master 31 that is outputting.

  Further, according to the above configuration, the priority according to the predetermined rule is given to each of the bus masters 31a, 31b, and 31c, and the bus master 31 that has not output the bandwidth guarantee request is always in accordance with the predetermined rule. The priority given to the bus master 31 is set. Also in the bus master 31 outputting the bandwidth guarantee request, when the effective bandwidth of the bus master 31 exceeds the target bandwidth, the priority given to the bus master 31 is set according to a predetermined rule. On the other hand, when the effective bandwidth is equal to or less than the target bandwidth, priority S that is higher than each priority according to the predetermined rule is set in the bus master 31 that outputs the bandwidth guarantee request. . As a result, when the effective bandwidth is equal to or less than the target bandwidth, the highest priority can be set for the bus master 31 outputting the bandwidth guarantee request.

  Further, according to the embodiment described above, the priority changing process described above is performed only for the bus master 31 that outputs the bandwidth guarantee request. Accordingly, the priority change process described above can be performed only for the bus master 31c that requires bandwidth guarantee and only during the period that requires bandwidth guarantee.

  Further, in the embodiment described above, each band measuring circuit 52... May measure the effective band only during the period when the bus master 31 connected to each band outputs a band guarantee request. preferable. In this way, the bandwidth measuring circuit 52 measures the effective bandwidth only during the period when the bandwidth guarantee request is output. As a result, the band measurement circuit 52 performs the measurement only within a necessary period without always performing the measurement, and can suppress the expansion of the error due to the continuing measurement. Measurements can be made.

  In the embodiment described above, the bandwidth measuring circuit 52 is preferably configured to reset the measured effective bandwidth every predetermined period. In this way, even if an error occurs in the effective bandwidth during measurement, the error can be canceled every predetermined period.

  Further, in FIG. 5 of the embodiment described above, the mode in which only the bus master 31c outputs a bandwidth guarantee request and the bandwidth guarantee mode is set only for the bus master 31c has been described. Of course, the bus masters 31a and 31b are also set. Similarly, it is possible to set the bandwidth guarantee mode.

  Here, when there are a plurality of bus masters 31 that output a bandwidth guarantee request and whose effective bandwidth is equal to or less than the target bandwidth, a problem arises as to which bus master 31 should be set with “priority S”. This is because if the “priority S” is set for each of the plurality of bus masters 31, the priority determination circuit 51 cannot determine which bus master 31 should be given the highest priority. Therefore, in such a case, the priority S may be set for only one of the bus masters 31 based on the priority given to each of the bus masters 31 according to the predetermined rule.

  Also, when there are a plurality of bus masters 31 that output a bandwidth guarantee request and whose effective bandwidth is equal to or less than the target bandwidth, priority is given only to the bus master 31 having the largest absolute value (deficiency parameter) of the difference between the target bandwidth and the effective bandwidth. The degree S may be set. This makes it possible to give the highest priority to data transfer by the bus master 31 whose execution band is farthest from the target value and has the highest necessity for data transfer.

  Further, when there are a plurality of bus masters 31 that output a bandwidth guarantee request and whose effective bandwidth is equal to or less than the target bandwidth, only the bus master 31 having the largest (target bandwidth-effective bandwidth) / target bandwidth value (insufficient parameter) The priority S may be set. Thereby, the highest priority can be given to the data transfer of the bus master 31 in which the ratio of the shortage of the effective bandwidth to the target bandwidth is the largest. Such a configuration is suitable when each of the plurality of bus masters 31 has a substantially different target bandwidth.

  Further, in the embodiment described above, the engine interface 31c as a bus master outputs a bandwidth guarantee request, and performs bandwidth guarantee for data transfer of the engine interface 31c. Here, the engine interface (image data transfer control unit) 31c performs transfer control of image data to the printer engine (printing unit) 12 that performs processing for printing an image. Therefore, a predetermined amount or more of image data can be continuously supplied to the printer engine 12. Therefore, printing defects due to insufficient supply of image data to the printer engine 12 can be suppressed. Further, if setting is made so that a bandwidth guarantee request is output from the engine interface 31c from the start to the end of the printing process of the printer engine 12, it is possible to realize the bandwidth guarantee of the engine interface 31c in real time during the printing process. .

  Further, in the embodiment described above, the system controller 25 is configured in the printer 10, but is not limited to the printer 10, and may be configured in a general-purpose computer or various devices based on computer control. It can also be configured (video display device, communication device, various home appliances).

  Further, in the embodiment described above, the above-mentioned predetermined rule relating to the priority is a rule that the priority given to each of the bus masters 31a, 31b, and 31c is fixed. However, the present invention is not limited to such a rule. For example, as the predetermined rule, each priority given to each of the bus masters 31a, 31b, 31c ("priority a", "priority b", "priority c") ) May be applied between the bus masters 31a, 31b, and 31c (also referred to as “cyclic priority rule”).

  When this cyclic priority rule is applied, when the priority given to the bus master 31a switches in the order of “priority a” → “priority b” → “priority c” in a certain period, for example, the bus master 31b The priority given to is switched in the order of “priority b” → “priority c”, and the priority given to the bus master 31c is switched in the order of “priority c” → “priority a” → “priority b”. Change. That is, in each of the bus masters 31a, 31b, and 31c, the given priority is switched in order, but at the same timing, different priority is given to each of the bus masters 31a, 31b, and 31c.

  A specific example of processing of the priority determination circuit 51 when the above cyclic priority rule is applied will be described with reference to FIG. FIG. 6 illustrates the timing at which the priority determination circuit 51 receives a data transfer request from each of the bus masters 31a, 31b, and 31c, and the priority determination circuit 51 that uses the bus masters 31a, 31b, and 31c when the cyclic priority rule is applied. It is a timing chart which showed the timing which transmits transfer permission to each of 31c.

  In the period indicated by reference symbol X shown in FIG. 6, each of the bus masters 31a, 31b, and 31c continuously outputs a data transfer request, while the bus master 31a, the bus master 31b, the bus master 31c, the bus master 31a, and so on. Permission is granted. This means that “priority a” is given in the order of bus master 31a → bus master 31b → bus master 31c → bus master 31a.

  In the above-described embodiment, as shown in FIG. 3, each bus master 31a / 31b / 31c and each bus target 32a / 32b / 32c share one transfer circuit 41. It is not limited to such a configuration. The present invention can be applied to the arbitration circuit 42 connected to the transfer circuit 41 shared by a plurality of bus masters.

  For example, as shown in FIG. 7, in the bus circuit 37, the same number of transfer circuits 41 as the bus targets 32 are formed, and a separate transfer circuit 41 is connected to each of the bus targets 32a, 32b, and 32c. 41. A configuration in which a separate arbitration circuit 42 is connected for each time may be employed. Further, in this configuration, each of the transfer circuits 41... And the arbitration circuits 42 is connected to all the bus masters 31a, 31b, and 31c. Furthermore, in the case of this configuration, one arbitration circuit 42 corresponds to an embodiment of the data transfer control circuit of the present invention.

  The configuration of FIG. 7 is different from the configuration of FIG. 3 in the following points. In the configuration of FIG. 3, when a plurality of bus masters 31... Simultaneously output transfer requests, arbitration by the arbitration circuit 42 is always performed, and transfer permission is given to only one bus master 31. However, in the configuration of FIG. 7, even when a plurality of bus masters 31... Are simultaneously outputting transfer requests, the transfer circuit 41 used in data transfer and the selected bus target 32 are connected to each bus master 31. When the transfer requests are different from each other, arbitration by the arbitration circuit 42 is not performed, and transfer permission may be simultaneously given to each bus master 31. According to the configuration shown in FIG. 7, a separate transfer circuit 41 is provided for each bus target 32, and a separate arbitration circuit 42 is provided for each transfer circuit 41. Therefore, a plurality of bus masters 31 are provided. Even if a data transfer request is made at the same time, depending on the data transfer path, it may not occur that one transfer circuit 41 and one bus target 32 are simultaneously used and selected by a plurality of bus masters 31. In this case, there is no problem even if data transfer by a plurality of bus masters 31... Is performed simultaneously without performing arbitration by the arbitration circuits 42. Therefore, it can be said that the configuration of FIG. 7 has better system performance than the configuration of FIG.

  In the configuration of FIG. 7, arbitration by the arbitration circuit 42 is performed by a plurality of bus masters 31 simultaneously requesting data transfer, and the transfer circuit 41 to be used transfers data to each bus master 31. In this case, arbitration is performed by the arbitration circuit 42 connected to the transfer circuit 41 to be used.

  In the above embodiment, the arbitration circuit 42 is realized by hardware. However, the function performed by the arbitration circuit 42 can also be realized by an arithmetic circuit such as a processor executing a program stored in a storage unit such as a ROM or RAM and controlling various peripheral circuits, sensors, and the like. . Therefore, the computer having the above arithmetic circuit, peripheral circuit, and the like realizes various functions and various processes of the arbitration circuit 42 of the present embodiment only by reading the recording medium storing the program and executing the program. Can do. In addition, by recording the program on a removable recording medium, the various functions and various processes described above can be realized on an arbitrary computer.

  Examples of the recording medium include tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, and disks including optical disks such as CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  Further, the printer 10 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments can be obtained by appropriately combining the respective technical means disclosed in the above-described embodiments. The form is also included in the technical scope of the present invention.

  Further, in the above-described embodiment, the bandwidth guarantee of the bus master is more accurately performed based on the actual number of transfer data without excessively compressing the transfer bandwidth of other bus masters that do not require the bandwidth guarantee. The necessary bandwidth guarantee can be realized with the minimum system performance. In addition, at the time of system design, it is possible to easily obtain the performance required for the system based on the target guaranteed bandwidth, and to make the optimum design, without excessively overdesigning by speculative accumulation.

  In the embodiment described above, a transfer bandwidth that is almost the same as the target bandwidth can be secured for the specific bus master, and the transfer bandwidth of other bus masters is not unnecessarily compressed. In addition, when designing a system, it is possible to design the master with the minimum guaranteed bandwidth at the same time as a guaranteed bandwidth requirement, thereby eliminating the need for an unnecessarily overspec system design.

  On the other hand, in the conventional method of switching the priority regularly (methods disclosed in Patent Documents 1 and 3), it is only possible to set the ratio to which the highest priority is allocated, and transfer permission is given. It is not possible to indicate the ratio. This means the frequency at which transfer permission is given to the bus masters when all the bus masters are constantly generating transfer requests.

  In addition, the time required for each bus master to transfer once may be different for each bus master, and this time may be different for each bus master for each transfer. Therefore, if the transfer bandwidth of a specific master is to be guaranteed, the priority setting algorithm must be determined after assuming the required bandwidth of the bus master, the time required for each bus master to transfer, and the worst value of the transfer permission frequency. Yes, it is difficult to set up, and the overall system is over-designed.

  In addition, the method of limiting the bandwidth used for each bus master (the methods disclosed in Patent Documents 2 and 4) is based on the concept of guaranteeing the bandwidth of the target bus master by limiting the bandwidth other than the target bus master. Therefore, in order to guarantee the bandwidth of the target bus master, it is necessary to determine the necessary bandwidth of all the other bus masters and to determine the ratio of the bandwidth allocated to each bus master assuming the worst value. For this reason, in this case as well, the overall system becomes an overspec design.

  Note that the arbitration circuit of the present embodiment is an arbitration circuit that arbitrates transfer requests from a plurality of bus masters, measures the number of data and time actually transferred for each bus master, and based on the effective bandwidth calculated as needed. It can also be expressed as controlling transfer permission to each bus master. As a result, arbitration can be performed so that the excess or deficiency is always reduced with respect to the target bandwidth while measuring the actual transfer bandwidth, so that optimum design can be performed at the time of design, and bandwidth guarantee is required at the time of operation. Never oversqueeze another master's transfer.

  In the arbitration circuit described above, the bus master that does not output the bandwidth request performs arbitration based on a predetermined priority process, and the bus master that outputs the bandwidth request performs arbitration based on the measured effective bandwidth. It is good. This makes it possible to determine an arbitration method when no bus master issues a bandwidth guarantee request and when a bus master that issues a bandwidth guarantee request does not issue a transfer request.

  Also, in the above arbitration circuit, for the bus master that is outputting the bandwidth request, if the effective bandwidth has reached the target bandwidth, arbitration based on the predetermined priority processing, and if the target bandwidth has not been reached, Transfer permission may be given in preference to predetermined priority processing. Thereby, the arbitration in the case where the bandwidth guarantee is necessary and the case where it is not necessary can be combined and operated in one arbitration circuit without any contradiction.

  Further, in the above arbitration circuit, when there are a plurality of bus masters that output a bandwidth guarantee request and have not reached the target bandwidth, the priority among the bus masters may be determined according to the shortage with respect to each target bandwidth. . As a result, when multiple bus masters request bandwidth guarantee and issue a transfer request, which one should be given priority for transfer permission depends on the lack of bandwidth, that is, the urgency of the need for data transfer Can be decided.

  Furthermore, in the above arbitration circuit, if there are multiple bus masters that output a bandwidth request and have not reached the target bandwidth, the priority between the bus masters is determined by the absolute value of the shortage with respect to each target bandwidth. Also good. As a result, when multiple bus masters request bandwidth guarantee and issue a transfer request, which one should be given priority for transfer permission depends on the lack of bandwidth, that is, the urgency of the need for data transfer Can be decided. At this time, fair arbitration can be performed by determining the degree of urgency based on the number of data lacking at the present time.

  In the above arbitration circuit, when there are a plurality of bus masters that output a bandwidth request and have not reached the target bandwidth, the priority between the bus masters may be determined by the ratio of the shortage to each target bandwidth. Good. As a result, when multiple bus masters request bandwidth guarantee and issue a transfer request, which one should be given priority for transfer permission depends on the lack of bandwidth, that is, the urgency of the need for data transfer Can be decided. At this time, different characteristics such as transfer data size, time required for one transfer request, and the like can be absorbed and more fair arbitration can be performed.

  The data transfer control device of the present invention can be applied to all computers including a bus to which data transfer is performed, and various image forming devices (printers, facsimiles, etc.) that are controlled by a computer, and various videos that are controlled by a computer. The present invention can be applied to display devices, and can be widely applied to various home appliances that are controlled by a computer.

It is the block diagram which showed the arbitration circuit which is one Embodiment of the data transfer circuit of this invention. 1 is a block diagram illustrating a configuration of a printer according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a bus circuit included in the printer illustrated in FIG. 2. Timing chart showing when the priority determination circuit receives a data transfer request from each of the bus masters and when the priority determination circuit transmits a transfer permission to each of the bus masters when the fixed priority rule is applied It is. 6 is a chart showing changes in effective bandwidth of a bus master outputting a bandwidth guarantee request. Timing chart showing the timing when the priority determination circuit receives a data transfer request from each of the bus masters and the timing when the priority determination circuit transmits a transfer permission to each of the bus masters when the cyclic priority rule is applied It is. FIG. 4 is a block diagram showing a bus circuit having a different form from the bus circuit shown in FIG. 3.

Explanation of symbols

10 Printer (image forming device)
11 Printer Controller 12 Printer Engine (Printing Section)
21 CPU
22 RAM
23 ROM
24 I / O device 25 System controller (data transfer device)
31a CPU interface (bus master, transfer control unit)
31b DMA controller (bus master, transfer control unit)
31c Engine interface (bus master, bus target, transfer control unit, image data transfer control unit)
32a ROM controller (bus target)
32b RAM controller (bus target)
32c I / O controller (bus target)
37 bus circuit 41 transfer circuit 42 arbitration circuit (data transfer control device)
51 Priority judgment circuit (priority control means)
52 Band measurement circuit (measuring means)

Claims (16)

A plurality of transfer control units that control data transfer via the transfer circuit share the transfer circuit. When a data transfer request is received from each transfer control unit, each priority is set to each transfer control unit. Based on the data transfer control device for executing the data transfer by any one transfer control unit,
Measuring means for measuring the amount of transfer data per unit time for data transfer by a predetermined transfer control unit among the plurality of transfer control units;
Priority control means for changing the priority set in the predetermined transfer control unit according to the measured transfer data amount per unit time;
A data transfer control device comprising: The priority control means is:
2. The data transfer according to claim 1, wherein when the transfer data amount per unit time is equal to or less than a target value, the priority set in the predetermined transfer control unit is improved as compared with a case where the transfer value exceeds the target value. Control device. The priority control means is:
3. The data transfer control device according to claim 2, wherein when the transfer data amount per unit time is equal to or less than a target value, the highest priority is set in the predetermined transfer control unit. A priority according to a predetermined rule is given to each transfer control unit,
The priority control means is:
When the transfer data amount per unit time is less than or equal to a target value, the priority higher than each priority according to the predetermined rule is set as the highest priority in the predetermined transfer control unit, and another transfer In the control unit, set the priority according to the predetermined rule given to the other transfer control unit,
When the amount of transfer data per unit time exceeds the target value, the priority given to the predetermined transfer control unit is set in the predetermined transfer control unit according to the predetermined rule, and the other transfer control unit is set. 4. The data transfer control device according to claim 3, wherein a priority given to the other transfer control unit is set according to the predetermined rule. The priority control means is:
When there are a plurality of predetermined transfer control units whose transfer data amount per unit time is less than or equal to the target value, one of the predetermined transfer control units is determined based on each priority given to each predetermined transfer control unit according to a predetermined rule 5. The data transfer control device according to claim 4, wherein the highest priority is set only for the transfer control unit. The priority control means is:
When there are a plurality of predetermined transfer control units whose transfer data amount per unit time is less than or equal to a target value, only the predetermined transfer control unit having the highest deficiency parameter indicating the deficiency of the transfer data amount with respect to the target value 5. The data transfer control device according to claim 3 or 4, wherein the highest priority is set.   The data transfer control device according to claim 6, wherein the deficiency parameter is an absolute value of a difference between the target value and the transfer data amount.   The data transfer control device according to claim 6, wherein the deficiency parameter is a value obtained by dividing an absolute value of a difference between the target value and the transfer data amount by the target value.   9. The data transfer control device according to claim 1, wherein the predetermined transfer control unit is a transfer control unit that outputs a bandwidth guarantee request. The measuring means is
The transfer data amount per unit time for data transfer controlled by the predetermined transfer control unit is measured only during a period when the predetermined transfer control unit outputs the bandwidth guarantee request. Item 12. The data transfer control device according to Item 9. The measuring means is
11. The data transfer control device according to claim 1, wherein the measured transfer data amount per unit time is reset every predetermined period.   A data transfer device including the data transfer control device according to any one of claims 1 to 11, comprising the transfer circuit and the plurality of transfer control units sharing the transfer circuit. A data transfer device. An image forming apparatus comprising: the data transfer device according to claim 12; and a printing unit that performs processing for printing an image.
The predetermined transfer control unit is an image data transfer control unit that controls transfer of image data to the printing unit. A plurality of transfer control units that control data transfer via the transfer circuit share the transfer circuit. When a data transfer request is received from each transfer control unit, each priority is set to each transfer control unit. Based on the data transfer control method for executing data transfer by any one transfer control unit,
A step of measuring a transfer data amount per unit time for data transfer by a predetermined transfer control unit among the plurality of transfer control units;
Changing the priority set in the predetermined transfer control unit according to the measured transfer data amount per unit time;
A data transfer control method comprising:   A data transfer control program for causing a computer to function as each means according to any one of claims 1 to 11.   A computer-readable recording medium on which the control program according to claim 15 is recorded.

Images