JP2013250622A - Image processor - Google Patents

Abstract

【Task】
Provided is an image processing apparatus capable of performing a pre-setting process in a short period from the completion of reading of a document page to the start of reading of the next document page.
[Solution]
A plurality of processing units having a circuit capable of direct memory access and connected to a common bus, the processing unit generated based on a control unit that controls the entire device and an image on a document An image input unit for inputting image data, and at least one image processing unit for performing image processing on the image data input by the image input unit, monitoring an input state of the image data by the image input unit, and a control unit And a priority setting unit for setting the priority of the right to use the common bus by the processing unit other than the control unit, and based on the respective request signals output from the control unit and the processing unit other than the control unit according to the priority. An image processing apparatus comprising: a control unit; and a bus arbitration unit that arbitrates the right to use a common bus of a processing unit other than the control unit.
[Selection] Figure 1

Description

  The present invention relates to an image processing apparatus applied to a multifunction peripheral (MFP) in which some or all of processing functions are combined, such as a digital copying machine, a facsimile machine, or a scanner.

  For example, when storing image data generated using a reading unit such as a scanner in a predetermined storage unit such as a memory, when a CPU (Central Processing Unit) controls a large amount of data transfer such as image data, A lot of time is spent on the transfer process, which is not efficient. In view of this, a technique has been proposed in which a device equipped with a DMA (Direct Memory Access) circuit directly accesses a storage device such as a memory without going through the control of the CPU, thereby reducing the burden on the processing of the CPU.

  In general, devices and CPUs equipped with the above-described DMA circuit are connected to a common bus via various signal lines. For example, Patent Document 1 discloses a regular use opportunity for a low-order device common bus. A bus use arbitration system that achieves fairness of the bus bandwidth of a plurality of devices by ensuring the above is described.

JP 2000-259556 A

  By the way, in the image processing apparatus, it is necessary to change the CPU bandwidth in the apparatus and the bus band of the image processing device according to the state of the apparatus operation. For example, in an image processing apparatus to which image data generated by reading means such as a scanner is input, the next original page is started between the completion of reading the original page and the start of reading the next original page. The pre-setting for this is performed by the CPU. In order to improve the overall processing speed of the image processing apparatus, it is preferable to further reduce the time required from the completion of reading of a document page to the start of reading of the next document page. For this purpose, it is necessary to perform the pre-setting process in this section in a short time.

  However, in the conventional bus use arbitration system, the bus bandwidth cannot be changed according to the processing status, and thus it has not been possible to realize an operation in which the pre-setting process is performed in a short time.

  The present invention has been made in view of such circumstances, and an object of the present invention is to change the bus band according to the processing status, so that the next original page can be read after the completion of reading the original page. It is an object of the present invention to provide an image processing apparatus capable of performing a pre-setting process in a section until it is started in a short time.

  In order to solve the above-described problem, an image processing apparatus according to the present invention is an image processing apparatus in which a plurality of processing units including a circuit capable of direct memory access are connected to a common bus, and the processing unit includes: A control unit that controls the entire apparatus; an image input unit that inputs image data generated based on the read image on the document; and at least one image process that processes the image data input by the image input unit. A priority order for monitoring the input state of the image data by the image input section and setting the priority order of the right to use the common bus by the control section and a processing section other than the control section. In accordance with the priority set by the setting unit and the priority setting unit, the control unit and the control unit based on the request signals output from the control unit and processing units other than the control unit. It is characterized in that it comprises a bus arbitration unit for arbitrating a right to use the common bus of the processing unit other than the control unit.

  The image processing apparatus according to the present invention is an image processing apparatus in which a plurality of processing units having a circuit capable of direct memory access are connected to a common bus, and the processing unit controls the entire apparatus. A control unit; an image input unit that inputs image data generated based on the read image on the document; and at least one image processing unit that performs image processing on the image data input by the image input unit; An image output unit for outputting the image data processed by the image processing unit to the outside as print data, and an input state of the image data by the image input unit or an output state of the print data by the image output unit A priority order setting unit that sets a priority order of the right to use the common bus by the control unit and a processing unit other than the control unit, and the priority order setting unit, According to the priority order to be determined, the right to use the common bus of the control unit and the processing unit other than the control unit is arbitrated based on the request signals output from the control unit and the processing unit other than the control unit. And a bus arbitration unit.

  According to the present invention, by changing the bus band in accordance with the processing status, the pre-setting process in the section from the completion of reading the original page to the start of reading the next original page can be performed in a short time. A possible image processing apparatus can be provided.

It is a functional block diagram explaining the structure of an image processing apparatus. It is a figure which shows the structural example of a priority information signal. It is a flowchart explaining operation | movement of an image processing apparatus. It is a timing chart explaining bus arbitration operation. It is a flowchart explaining operation | movement of an image processing apparatus. It is a functional block diagram explaining the structure of an image processing apparatus. It is a figure which shows the structural example of a priority information signal. It is a flowchart explaining operation | movement of an image processing apparatus. It is a flowchart explaining operation | movement of an image processing apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

[First Embodiment]
In the description of the first embodiment, an image processing apparatus that inputs image data generated by an image reading unit such as a scanner apparatus reading an image on a document will be described.

  FIG. 1 is a functional block diagram illustrating the configuration of the image processing apparatus 100 according to the first embodiment. As shown in FIG. 1, the image processing apparatus 100 includes an image input unit DMA 102, a CPU 103 as a control unit, an image processing 1 DMA 104, an image processing 2 DMA 105 as an image processing unit, a memory controller 106, and a priority setting unit 108. A bus arbitration unit 111 and a common bus 112. The image processing apparatus 100 is connected to the scanner 101 via the image input unit DMA 102 and to the memory 107 via the memory controller 106. In the present embodiment, an example in which an image processing unit is configured by two image processing DMAs of image processing 1 DMA 104 and image processing 2 DMA 105 equipped with a DMA circuit will be described. However, the number of image processing DMAs is limited to two. It is not something.

  The scanner 101 receives at least a light source that irradiates light on a document, a lens that collects light reflected by the document, light received by the lens, and converts the received light into image data that is an electrical signal. It has a photoelectric conversion element such as a CCD (Charge Coupled Device) for conversion, scans an image on a document, and generates image data based on the read image.

  The image input unit DMA 102 is connected to a scanner 101 as an image reading unit, and receives image data output from the scanner 101. The image input unit DMA 102 includes a DMA circuit, and can directly write image data received via the common bus 112 and the memory controller 106 into the memory 107. At this time, the image input unit DMA 102 outputs an image data input state signal indicating the input state of the image data to the priority order setting unit 108.

  The CPU 103 comprehensively controls the image processing apparatus 100. In particular, the CPU 103 performs in-page processing of software by reading predetermined data from the memory 107 via the common bus 112 and the memory controller 106 and writing predetermined data to the memory 107.

  The image processing 1 DMA 104 acquires the image data written in the memory 107 via the common bus 112 and the memory controller 106, performs predetermined image processing, and writes the image data in the memory 107 again.

  The image processing 2DMA 105 acquires the image data written in the memory 107 via the common bus 112 and the memory controller 106, performs predetermined image processing, and writes it again in the memory 107.

  Note that the image input unit DMA 102, the CPU 103, the image processing 1 DMA 104, or the image processing 2 DMA 105 is connected to the common bus 112. Hereinafter, these four blocks connected to the common bus 112 are referred to as a bus master.

  The memory controller 106 controls reading or writing of data with respect to the memory 107.

  The memory 107 is a rewritable storage device such as a dynamic random access memory (DRAM), a hard disk drive (HDD), or a universal serial bus (USB) flash memory.

  The priority order setting unit 108 outputs a priority order information signal to the bus arbitration unit 111. FIG. 2 is a diagram illustrating a configuration example of the priority order information signal. As shown in FIG. 2, the priority order information signal is composed of four tables, and the priority order of permission to use the common bus is set in order from Table 1 to Table 4 according to the input state of the image data input state signal. Yes. Each table indicates one of the image input unit DMA102, CPU103, image processing 1DMA104, or image processing 2DMA105.

  The bus arbitration unit 111 receives a bus use request signal for the common bus 112 from each bus master, and outputs a bus use permission signal for permitting the use of the common bus 112.

  The common bus 112 includes an address bus, a data bus, and a control bus including various control signal lines. As described above, the common bus 112 is connected to the bus master including the image input unit DMA 102, the CPU 103, the image processing 1 DMA 104, and the image processing 2 DMA 105. These bus masters are connected via the common bus 112 and the memory controller 106. The memory 107 can be accessed.

  Next, the operation of the image processing apparatus 100 having the above configuration as an image input apparatus will be described with reference to the flowchart of FIG.

  First, in step S300, the image input unit DMA102 receives input of image data output from the scanner 101. The image input unit DMA 102 writes the image data into the memory 107 via the common bus 112 and the memory controller 106. In addition, the image input unit DMA 102 outputs an image data input state signal indicating an input state of image data to the priority order setting unit 108.

  In step S301, the image processing 1DMA 104 acquires the image data written in the memory 107 via the common bus 112 and the memory controller 106, performs predetermined image processing, and writes the image data in the memory 107 again.

  In step S302, the image processing 2DMA 105 acquires the image data written in the memory 107 via the common bus 112 and the memory controller 106, performs predetermined image processing, and writes the image data in the memory 107 again.

  By the way, the CPU 103 reads predetermined data from the memory 107 via the common bus 112 and the memory controller 106 and writes predetermined data to perform in-page processing of software (step S303).

  The operation of the image input unit DMA102 (step S300), the operation of the image processing 1DMA104 (step S301), and the operation of the image processing 2DMA105 (step S302) are sequentially executed in predetermined units of document image data. Note that the operation of the CPU 103 in Step S303 is executed in parallel with the operations according to Step S300, Step S301, and Step S302. These operations are repeatedly executed until the processing for one page of the document is completed.

  When the process for one page of the original is completed (Y in step S304), and then the process for all pages of the original is completed (Y in step S305), the series of processes ends. On the other hand, if processing for all pages of the document has not been completed (N in step S305), the CPU 103 executes processing between document pages (step S306). In the process between the manuscript pages, the CPU 103 executes pre-setting of each part of the apparatus until the manuscript page is read and image data input based on the manuscript page is received. Then, the image input unit DMA102, the image processing 1DMA104, the image processing 2DMA105, and the CPU 103 repeatedly execute the operations according to step S300, step S301, step S302, and step S303, respectively.

  Next, the bus arbitration operation by the bus arbitration unit 111 will be described using the timing chart of FIG. The example shown in FIG. 4 shows an example based on the priority information signal when the image data input state signal is “image input in progress”.

  A bus master including the image input unit DMA102, the CPU 103, the image processing 1DMA104, and the image processing 2DMA105 makes a bus use request for the common bus 112 to the bus arbitration unit 111 via a bus use request signal.

  The bus arbitration unit 111 selects one bus master with the highest priority based on the priority order signal shown in FIG. 2 among the bus masters making a bus use request, and gives the bus use permission. As described above, the priority order signal is set by the priority order setting unit 108. In the example illustrated in FIG. 2, the priority is set so that the image input unit DMA102 has the highest priority in the “image input” state, and then the image processing 1DMA104, the image processing 2DMA105, and the CPU103 decrease in this order.

  In cycle 3 of FIG. 4, the CPU 103 asserts a bus use request signal. At this time, since the other bus masters do not assert the bus use request signal, in cycle 4, the bus arbitration unit 111 asserts the bus use permission signal for the CPU 103. Since the CPU 103 has obtained the bus use permission, the CPU 103 starts the operation on the common bus 112.

  In cycle 5, the CPU 103 deasserts the bus use request signal in response to the assertion of the bus use permission signal. In cycle 5, the image input unit DMA102 and the image processing 1DMA104 assert the bus use request signal. However, since the CPU 103 is still using the common bus 112, the bus arbitration unit 111 The bus use permission is not given to the DMA 102 and the image processing 1 DMA 104.

  In cycle 8, the CPU 103 completes the operation for the common bus 112. In response to this, the bus arbitration unit 111 deasserts the bus use permission signal for the CPU 103. Subsequently, since the bus use request signal is asserted from the image input unit DMA102 and the image processing 1DMA104, the bus arbitration unit 111 asserts a bus use permission signal to the image input unit DMA102 having a high priority. Since the image input unit DMA102 has received the bus use permission, the image input unit DMA102 starts the operation on the common bus 112.

  In cycle 9, in response to the bus use permission signal being asserted, the image input unit DMA102 deasserts the bus use permission signal.

  In cycle 12, the image input unit DMA 102 completes the operation for the common bus 112. In response to this, the bus arbitration unit 111 deasserts the bus use permission signal for the image input unit DMA102. Subsequently, since the bus use permission signal is asserted from the image processing 1 DMA 104, the bus arbitration unit 111 asserts the bus use permission signal to the image processing 1 DMA 104. Since the image processing 1DMA 104 has received the bus use permission, the operation for the common bus 112 is started.

  In cycle 13, in response to the assertion of the bus use permission signal, the image processing 1DMA 102 deasserts the bus use permission signal.

  Next, the operation of the image processing apparatus 100 will be described using the flowchart of FIG.

  First, in step S500, the image processing apparatus 100 starts accepting input of image data output from the scanner 101. Also, the image input unit DMA102 notifies the priority setting unit 108 that image data is being input via the image data input state signal. Between step S500 and step S501, since the image data input state signal is “image input in progress”, the bus master with the highest priority is the image input unit DMA102.

  In step S501, the image processing apparatus 100 completes input of image data corresponding to the current document page. That is, the image input unit DMA102 completes the operation related to the image input and notifies the priority setting unit 108 that the image data is not being input via the image data input state signal. Between step S501 and step S502, since the image data input state signal is “no image input”, the bus master with the highest priority is the CPU 103.

  As described above, according to the first embodiment, the priority of each bus master is changed when using the common bus 112 in accordance with the image data input state signal. Can be changed.

  For example, in FIG. 5, during the reading of a document page (between steps S500 and S501), the input speed of image data output from the scanner 101 is improved by temporarily increasing the bus bandwidth of the image input unit DMA102. Can be made. On the other hand, between document pages (between step S501 and step S502), it is necessary to perform pre-setting processing for each unit in the apparatus in order to start reading the next document page by the scanner 101. In the first embodiment, by temporarily increasing the bus bandwidth of the CPU 103, pre-setting processing related to reading the next document page can be preferentially performed. It is possible to further reduce the time required until the reading of the image is started, and to improve the processing speed of the image processing apparatus.

[Second Embodiment]
The image processing apparatus 600 according to the second embodiment includes an image output unit DMA 613 as an image output unit in addition to the configuration of the image processing apparatus 100 according to the first embodiment, and can be interlocked with the print control unit 614. It is comprised so that it may become.

  FIG. 6 is a functional block diagram illustrating the configuration of the image processing apparatus 600 according to the second embodiment. As shown in FIG. 6, the image processing apparatus 600 includes an image input unit DMA 602, a CPU 603 as a control unit, an image processing 1 DMA 604 as an image processing unit, an image processing 2 DMA 605, a memory controller 606, and a priority setting unit 608. A bus arbitration unit 611 and a common bus 612. The image processing apparatus 600 is connected to the scanner 601 via the image input unit DMA 602, the memory 607 via the memory controller 606, and the print control unit 614 via the image output unit DMA 613. In the present embodiment, an example in which an image processing unit is configured by two image processing DMAs of image processing 1 DMA 604 and image processing 2 DMA 605 equipped with a DMA circuit will be described. However, the number of image processing DMAs is limited to two. It is not something.

  The image input unit DMA 602 is connected to a scanner 601 serving as an image reading unit, and receives image data output from the scanner 601. The image input unit DMA 602 includes a DMA circuit and can directly write image data received via the common bus 612 and the memory controller 606 into the memory 607. At this time, the image input unit DMA 602 outputs an image data input state signal indicating the input state of the image data to the priority order setting unit 608.

  The CPU 603 comprehensively controls the image processing apparatus 600. In particular, the CPU 603 performs in-page processing of software by reading predetermined data from the memory 607 via the common bus 612 and the memory controller 606 and writing predetermined data to the memory 607.

  The image processing 1 DMA 604 acquires the image data written in the memory 607 via the common bus 612 and the memory controller 606, performs predetermined image processing, and writes it again in the memory 607.

  The image processing 2 DMA 605 acquires the image data written in the memory 607 via the common bus 612 and the memory controller 606, performs predetermined image processing, and writes it again in the memory 607.

The memory controller 606 controls reading or writing of data with respect to the memory 607.
The memory 607 is a rewritable storage device such as a DRAM, HDD, or USB flash memory.

  The priority order setting unit 608 outputs a priority order information signal to the bus arbitration unit 611. FIG. 7 is a diagram illustrating a configuration example of the priority order information signal. As shown in FIG. 7, the priority order information signal is composed of five tables, and the priority order of common bus use permission is set in order from Table 1 to Table 5 in accordance with the input state of the image data input state signal. Yes. Each table indicates any one of the image input unit DMA602, the CPU 603, the image processing 1DMA604, the image processing 2DMA605, or the image output unit DMA613.

  The bus arbitration unit 611 receives a bus use request signal for the common bus 612 from each bus master, and outputs a bus use permission signal for permitting use of the common bus 612.

  The common bus 612 includes an address bus, a data bus, and a control bus including various control signal lines. A bus master including an image input unit DMA 602, a CPU 603, an image processing 1 DMA 604, an image processing 2 DMA 605, and an image output unit DMA 613 is connected to the common bus 612. These bus masters are connected via the common bus 612 and the memory controller 606. The memory 607 can be accessed.

  The image output unit DMA 613 acquires the image data written in the memory 607 via the common bus 612 and the memory controller 606, and outputs the acquired image data to the connected print control unit 614. At this time, the image output unit DMA 613 outputs an image data output state signal indicating the output state of the image data to the priority order setting unit 608.

  For example, the print control unit 614 can control an electrophotographic print engine (not shown) to form an image based on the image data input from the image output unit DMA 613 on a predetermined recording medium.

  Next, the operation of the image processing apparatus 600 having the above configuration as a copying apparatus will be described with reference to the flowchart of FIG.

  First, in step S800, the image input unit DMA602 receives input of image data output from the scanner 601. Then, the image input unit DMA 602 writes the image data to the memory 607 via the common bus 612 and the memory controller 606. The image input unit DMA 602 outputs an image data input state signal indicating the input state of the image data to the priority order setting unit 608.

  In step S <b> 801, the image processing 1 DMA 604 acquires the image data written in the memory 607 via the common bus 612 and the memory controller 606, performs predetermined image processing, and writes the image data in the memory 607 again.

  In step S <b> 802, the image processing 2 DMA 605 acquires the image data written in the memory 607 via the common bus 612 and the memory controller 606, performs predetermined image processing, and writes the image data in the memory 607 again.

  In step S 807, the image output unit DMA 613 acquires the image data written in the memory 607 by the image processing 2 DMA 605 via the common bus 612 and the memory controller 606, and outputs the acquired image data to the print control unit 614. The image output unit DMA 613 outputs an image data output state signal indicating the output state of the image data to the priority order setting unit 608.

  By the way, the CPU 603 reads the predetermined data from the memory 607 via the common bus 612 and the memory controller 606, and writes the predetermined data to perform in-page processing of the software (step S803).

  The operation of the image input unit DMA602 (step S800), the operation of the image processing 1DMA604 (step S801), the operation of the image processing 2DMA805 (step S602), and the operation of the image output unit DMA613 (step S803) It is executed sequentially in units of. Note that the operation of the CPU 603 in step S803 is executed in parallel with the operations according to step S800, step S801, step S802, and step S807. These operations are repeatedly executed until the processing for one page of the document is completed.

  When processing for one page of the document is completed (Y in step S804), and then processing for all pages of the document is completed (Y in step S805), the series of processing ends. On the other hand, if processing for all pages of the document has not been completed (N in step S805), the CPU 603 executes processing between document pages (step S806). In the process between the original pages, the CPU 803 executes pre-setting of each part of the apparatus until the original page is read and the input of image data based on the original page is received. Then, the image input unit DMA 602, the image processing 1 DMA 604, the image processing 2 DMA 605, the image output unit DMA 613, and the CPU 603 repeatedly execute the operations according to step S800, step S801, step S802, step S807, and step S803, respectively.

  Note that the bus arbitration operation by the bus arbitration unit 611 according to the second embodiment can be performed in the same manner as the bus arbitration operation according to the first embodiment, and thus description thereof is omitted here.

  Next, the operation of the image processing apparatus 600 will be described using the flowchart of FIG.

  First, in step S900, the image processing apparatus 600 starts accepting input of image data output from the scanner 601. Also, the image input unit DMA 602 notifies the priority setting unit 608 that image data is being input via the image data input state signal. Between step S900 and step S901, since the image data input state signal is “image input in progress”, the bus master with the highest priority is the image input unit DMA602.

  Next, the image processing apparatus 600 starts outputting image data corresponding to the current document page (step S901). Specifically, the image output unit DMA 613 acquires the image data written in the memory 607 by the image processing 2 DMA 605 via the common bus 612 and the memory controller 606 and outputs the acquired image data to the print control unit 614. The image output unit DMA 613 outputs an image data output state signal indicating the output state of the image data to the priority order setting unit 608. Between step S901 and step S902, the image data input status signal is “image input in progress” and the image data output status signal is “image output in progress”. Therefore, the bus master with the highest priority is the image input section. It becomes DMA602.

  In step S902, the image processing apparatus 600 completes input of image data corresponding to the current document page. That is, the image input unit DMA 602 completes the operation related to the image input and notifies the priority setting unit 608 that the image data is not being input via the image data input state signal. Between step S902 and step S903, the image data input state signal is “no image input” and the image data output state signal is “image output in progress”, so the bus master with the highest priority is the image output unit. It becomes DMA613.

  In step S903, the image processing apparatus 600 completes outputting image data corresponding to the current document page. That is, the image output unit DMA 613 completes the operation related to the image output and notifies the priority setting unit 608 that the image data is not being output via the image data output state signal. Between step S903 and step S903, since the image data input state signal is “no image input” and the image data output state signal is “no image output”, the bus master with the highest priority is the CPU 603. .

  As described above, according to the second embodiment, the priority order of each bus master is changed in using the common bus 612 according to the image data input state signal and the image data output state signal. The bus bandwidth can be changed according to the situation.

  For example, in FIG. 9, during the reading of a document page (between steps S900 and S901), the input speed of image data output from the scanner 601 is improved by temporarily increasing the bus bandwidth of the image input unit DMA602. Can be made.

  In addition, between the original pages (between step S901 and step S902), the bus bandwidth between the image input unit DMA602 and the image output unit DMA613 is temporarily increased, so that input of image data and output of image data are prioritized. To do. By preferentially inputting and outputting image data, the input speed of image data input from the scanner 601 and the output speed output to the print control unit 614 can be improved.

  Further, between document pages (between step S902 and step S903), a pre-setting process relating to output of image data and reading of the next document page is performed by temporarily increasing the bus bandwidth between the image output unit DMA613 and the CPU 603. Is given priority. By preferentially performing the pre-setting process relating to the output of image data and the reading of the next original page, the output speed of the image data to the print control unit 614 is improved and the next original page is read after the completion of reading the original page It is possible to further reduce the time required until the reading of the image is started, and to improve the processing speed of the image processing apparatus.

  Furthermore, between the original pages (between step S903 and step S904), it is necessary to perform a pre-setting process for each unit in the apparatus in order to start reading the next original page by the scanner 601. In the second embodiment, by temporarily increasing the bus bandwidth of the CPU 603, pre-setting processing related to reading the next document page can be preferentially performed. It is possible to further reduce the time required until the reading of the image is started, and to improve the processing speed of the image processing apparatus.

  In the description of the present embodiment, an example in which the present invention is applied to a reading device such as a scanner, a multifunction device, and the like has been described. However, the present invention is not limited thereto, and can be applied to, for example, a FAX device. It is.

DESCRIPTION OF SYMBOLS 100,600 Image processing apparatus 101,601 Scanner 102,602 Image input part DMA
103,603 CPU
104,604 Image processing 1 DMA
105,605 Image processing 2DMA
106,606 Memory controller 107,607 Memory 108,608 Priority setting unit 613 Image output unit DMA
614 Print Control Unit

Claims (4)

A plurality of processing units having a circuit capable of direct memory access, an image processing apparatus connected to a common bus,
The processor is
A control unit for controlling the entire apparatus;
An image input unit for inputting image data generated based on the read image on the document;
Having at least one image processing unit that performs image processing on the image data input by the image input unit;
A priority setting unit that monitors an input state of the image data by the image input unit, and sets a priority order of the right to use the common bus by a processing unit other than the control unit and the control unit;
The common of the control unit and the processing unit other than the control unit based on the respective request signals output from the control unit and the processing unit other than the control unit according to the priority order set by the priority order setting unit An image processing apparatus comprising: a bus arbitration unit that arbitrates a right to use the bus. The priority order setting unit includes:
While the image input unit inputs the image data, the priority of the right to use the common bus by the image input unit is increased, and during the other periods, the priority of the right to use the common bus by the control unit is increased. The image processing apparatus according to claim 1, wherein the image processing apparatus is raised. A plurality of processing units having a circuit capable of direct memory access, an image processing apparatus connected to a common bus,
The processor is
A control unit for controlling the entire apparatus;
An image input unit for inputting image data generated based on the read image on the document;
At least one image processing unit that performs image processing on the image data input by the image input unit;
An image output unit that outputs the image data processed by the image processing unit as print data to the outside;
The input state of the image data by the image input unit or the output state of the print data by the image output unit is monitored, and the priority order of the right to use the common bus by the control unit and a processing unit other than the control unit A priority setting section for setting
The common of the control unit and the processing unit other than the control unit based on the respective request signals output from the control unit and the processing unit other than the control unit according to the priority order set by the priority order setting unit An image processing apparatus comprising: a bus arbitration unit that arbitrates a right to use the bus. The priority order setting unit includes:
The period during which the image input unit inputs the image data is increased in priority of the right to use the common bus by the image input unit, and the period during which the image output unit outputs the print data is the common by the image output unit. The image processing apparatus according to claim 3, wherein the priority of the right to use the bus is increased, and the priority of the right to use the common bus by the control unit is increased during the other period.