JP2006349616A - Decoder circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoder circuit capable of easily performing a test inclusive of the state of a transistor added for the test. <P>SOLUTION: Among transistors 1-4 and 5-8 for establishing a function of a decoder 21 as an ordinary decoder, a test transistor 22 is inserted into the side of the transistors 5-8 connected in series, and a test transistor 11 is connected in parallel to the transistor group including the transistors 22. The open-failure of the transistors 1-4 is detected by the combination of on- and off-states of the two test transistors 22, 11, and the open-failure and the short-failure of the transistor 11 and the short-failure of the transistor 22 are also detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention includes a plurality of first transistors connected in series between a power supply and a decode signal output line, and a plurality of second transistors connected in parallel between the decode signal output line and a ground. The present invention relates to a decoder circuit.

A decoder circuit that is built in a memory such as a ROM and outputs a decode signal in order to select a memory cell according to an address given from the outside. This causes a problem of multiple selection that causes selection. When performing a test for detecting this multiple selection, if a bit line or word line is in a high impedance state due to a malfunction, the read data value depends on the result of the cycle executed before that, and so on. It cannot be detected by reading data. For this reason, it is necessary to create a test pattern consisting of a combination of address and data taking into account the occurrence pattern of the defect, and to perform a test by reading the memory cell. In a mask ROM or the like that cannot be set, it is necessary to prepare a test pattern according to the contents of each ROM, and much labor is required to create the test pattern.

As one of conventional techniques for solving such a problem, there is a technique disclosed in Patent Document 1. As shown in FIG. 4A, this technique is applied to a 4-input NOR gate configured as a decoder 9 by a combination of four n-channel MOS transistors 1 to 4 and four p-channel MOS transistors 5 to 8. On the other hand, a test p-channel MOS transistor 11 (high on-resistance) is connected between the power supply Vcc and the decode signal output line 10 (Oi, i = 1 to 16), and a test signal is connected to the gate of the transistor 11. , The test of the decoder 9 is performed.
That is, when the test transistor 11 is turned on, the decode signal output line is high when the 4-bit input addresses A0 to A3 or their inverted signals are all at a high level and all the four transistors 1 to 4 are off. If any one of them is turned on, the level of the decode signal output line should be low. Therefore, when the above level change does not occur, an open failure of the transistor can be detected (see FIG. 4B).
Japanese Patent Laid-Open No. 6-18629

However, in the technique disclosed in Patent Document 1, the same output result as that of a normal product can be obtained even when the test transistor 11 itself is not normally connected or does not operate normally. In some cases, the malfunction of the decoder 9 cannot be reliably detected. There is no means for verifying whether the transistor 11 is normally connected in advance.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a decoder circuit capable of easily performing a test including the state of a transistor added for testing.

  According to the decoder circuit of the first aspect, the first test transistor is inserted on the transistor side connected in series among the first and second transistors for functioning as a normal decoder, and the first A second test transistor is connected in parallel to the transistor group including the test transistor. In the above configuration, the second test transistor corresponds to the test transistor in Patent Document 1. By adding the first test transistor, the ON and OFF states of these two test transistors are combined. The test can be done as follows.

(1) ON / OFF of first and second test transistors
→ First test transistor: Open defect detection This is the same setting as when the decoder circuit is operated as a normal decoder, but if the first test transistor is in the ON state, the first test transistor When an input signal is supplied to turn on all the transistor groups including the decode signal output line, the decode signal output line changes to either the power supply level or the ground level connected to the other end side of the transistor group. However, if the first test transistor is open, the level of the decode signal output line does not change at all. Therefore, the open defect can be detected.

(2) First and second test transistors OFF, ON
→ (a) second test transistor: open defect detection → (b) parallel connection side transistor group: open defect detection (a) That is, if the second test transistor is in the ON state, the parallel connection side transistor group When all are OFF, the decode signal output line should be at the level of either the power supply or the ground connected to the other end of the second test transistor. Therefore, if the second test transistor is not turned on in that case, the level of the decode signal output line is maintained at the level when any one of the parallel connection side transistor groups is turned on before that. 2 Open failure of the test transistor is detected.
(B) If the second test transistor is normal and one of the parallel-connected transistors is turned on, the level of the decode signal output line changes to either the ground level or the power source level. To do. Therefore, if the level of the decode signal output line does not change even when any one of the input signals for turning on is given, it is detected that the transistor is in an open failure. It should be noted that the second test transistor needs to have a high ON resistance in order to prevent a short-circuit current from flowing between the power supply and the ground when any one of the parallel connection side transistor groups is turned on. .

(3) First and second test transistors OFF, OFF
→ First and second test transistors: short circuit failure detection In this case, since both of the two test transistors are OFF, when all the parallel connection side transistor groups are OFF, the decode signal output line becomes high impedance, Similarly to the above, the level when any one of them is turned on should be maintained. Therefore, when all of the parallel connection side transistor groups are in the OFF state, if the decode signal output line is at a level opposite to the above level, at least one of the first and second test transistors may be short-circuited. Detected.
As described above, the combination of the ON and OFF states of the first and second test transistors is used to detect the open failure of the parallel connection side transistor group that operates to perform a normal decoder function, and for the first and second test transistors. It becomes possible to detect open and short defects of the transistor.

  According to the decoder circuit of the second aspect, the first test transistor is inserted in the transistor side connected in series among the first and second transistors for functioning as a normal decoder. A test resistance element is connected in parallel to a transistor group including the test transistor. Then, the test can be performed as follows by setting the first test transistor in the OFF state.

(A) Resistance element for test: Open failure detection (b) Parallel connection side transistor group: Open failure detection (a) That is, if the test resistance element is normally connected, all the parallel connection side transistor groups are in the OFF state. In this case, the decode signal output line should be at the level of either the power supply or the ground connected to the other end of the test resistance element. Therefore, in this case, if the test resistance element is in the open state, the decode signal output line becomes high impedance, and the level is maintained when any one of the parallel connection side transistor groups is turned on before that. Therefore, an open failure of the test resistance element is detected.
(B) When the resistance element for testing is normally connected, if any one of the parallel connection side transistor groups is turned on, the level of the decode signal output line is either the ground level or the power source level. To change. Therefore, if the level of the decode signal output line does not change even when any one of the input signals to turn on is applied, it is detected that the transistor is in an open defect.
As described above, by turning off the test transistor, the open failure of the parallel connection side transistor group that operates to function as a normal decoder is detected, as well as the open failure of the test resistance element. Is possible.

According to the decoder circuit of the third aspect, the series circuit of the test transistor and the test resistance element is connected between the decode signal output line and the ground or the power supply (the second test transistor, the second test transistor, and the like). 2 referred to as a resistance element for testing). In this case, the ON / OFF state of the added second test transistor is combined with the ON / OFF state of the test transistor (referred to as the first test transistor) in claim 2 to perform the test as follows. be able to.
(1) First and second test transistors OFF, ON
→ First test transistor: short circuit failure detection In this case, if the first test transistor is OFF, the potential of the decode signal output line is the test resistance element according to claim 2 (referred to as a first test resistance element). However, if a short circuit failure occurs in the first test transistor, the potential of the decode signal output line is at either the power supply level or the ground level. Therefore, a short circuit defect can be detected.

(2) First and second test transistors ON, ON
→ First test transistor: Open failure detection In this case, if the first test transistor is ON, the potential of the decode signal output line is at the level of either the power supply or the ground, contrary to (1). However, if an open failure has occurred in the first test transistor, the potential of the decode signal output line becomes a potential divided by the first test resistance element and the second test resistance element. Open defects can be detected. Therefore, by adding a second test resistance element and a transistor, it is possible to detect a short circuit failure and an open failure of the first test transistor.

(First embodiment)
A first embodiment in which the present invention is applied to a NOR type decoder circuit will be described below with reference to FIG. 4 that are the same as those in FIG. 4 are denoted by the same reference numerals and description thereof is omitted. The decoder (decoder circuit) 21 of this embodiment is different from the decoder 9 shown in FIG. 4A in that another p-channel MOS transistor 22 for test (first test) between the transistor 8 and the decode signal output line 10. Transistor). Other configurations are the same as those shown in FIG.

Next, the operation of this embodiment will be described. By setting ON and OFF states of the transistor 22 and the transistor 11 (second test transistor), a test can be performed as follows. Note that the former gate signal is T2, and the latter gate signal is T1.
(1) Transistor 22: ON, Transistor 11: OFF (T2: L, T1: H)
→ Transistor 22: Open defect detection This is the same setting as that in the case where the decoder 21 performs a normal decoder operation. However, if the transistor 22 is in the ON state, the transistor 22 and the transistors 5 to 8 (first When an input signal is supplied to turn on all the transistor groups including the transistor), the decode signal output line 10 changes to the level (high) of the power supply Vcc connected to the other end side of the transistor group. However, if the transistor 22 is open failure, the level of the decode signal output line 10 does not change at all, so that the open failure of the transistor 22 can be detected.

(2) Transistor 22: OFF, Transistor 11: ON (T2: H, T1: L)
-> (A) Transistor 11: Open failure detection-> (b) Transistors 1-4: Open failure detection (a) That is, if the transistor 11 is in the ON state, the transistors 1 to 4 which are the transistor groups on the parallel connection side When all the (second transistors) are in the OFF state, the decode signal output line 10 should be at the power supply Vcc level connected to the source side of the transistor 11. That is, as shown in the timing chart of FIG. 1B, this corresponds to the case where all of A0 to A3 are set to the low level.
At this time, if an open failure occurs in the transistor 11, the level of the decode signal output line 10 is maintained at the ground level when all the transistors 1 to 4 are turned on before that. An open defect is detected (indicated by a broken line in the timing chart of FIG. 1B).
(B) When the transistor 11 is normal and any one of the transistors 1 to 4 is turned on, the level of the decode signal output line 10 changes to the ground level. Therefore, if the level of the decode signal output line 10 does not change even when any one of the input signals to turn on is applied, it is detected that the transistor is in an open defect.

(3) Transistors 22, 11: OFF (T2: H, T1: H)
→ Transistors 22 and 11: Short circuit failure detection In this case, since the two test transistors 22 and 11 are both OFF, the decode signal output line 10 becomes high impedance when the transistors 1 to 4 are all OFF. In the same manner as described above, the ground level when any one of them is turned on should be maintained. Therefore, when all of the transistors 1 to 4 are in the OFF state, if the decode signal output line 10 is at a level opposite to the above level, it is detected that at least one of the transistors 22 and 11 has a short circuit failure.

  As described above, according to this embodiment, the decoder 21 is provided with the transistor 22 on the side of the transistors 5 to 8 connected in series among the transistors 1 to 4 and 5 to 8 serving as a normal decoder. Since the transistor 11 is connected in parallel to the transistor group including the transistor 22, the open failure of the transistors 1 to 4 is detected by the combination of the ON and OFF states of the transistors 22 and 11, and the transistor 11 It becomes possible to detect open and short-circuit defects as well as short-circuit defects of the transistor 22.

(Second embodiment)
FIG. 2 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. In the decoder 23 of the second embodiment, the transistor 11 of the decoder 21 in the first embodiment is replaced with a test resistance element 24. The resistance value of the resistance element 24 is set to a high value similar to the ON resistance of the transistor 11. A series circuit of a test n-channel MOS transistor 25 and a test resistance element 26 is connected between the decode signal output line 10 and the ground. The resistance values of the resistance elements 24 and 26 are set to substantially the same value as an example. Note that the gate signal of the transistor 25 is T3.

Next, the operation of the second embodiment will be described.
(1) Transistors 22 and 25: OFF (T2: H, T3: H)
→ (a) Resistive element 24: Open defect detection → (b) Transistors 1-4: Open defect detection (a) This is the same setting as in the normal operation of the decoder 23. That is, if the resistor element 24 is normally connected, the decode signal output line 10 should be at the power supply Vcc level connected to the other end side of the resistor element 24 when all of the transistors 1 to 4 are OFF. It is. In this case, if the resistance element 24 is in an open state, the decode signal output line 10 becomes high impedance, and the level is maintained at the low level when any one of the transistors 1 to 4 is turned on before that. Therefore, an open failure of the resistance element 24 is detected.
(B) Further, if any one of the transistors 1 to 4 is turned on when the resistance element 24 is normally connected, the level of the decode signal output line 10 changes to the ground level. Therefore, if the level of the decode signal output line 10 does not change even when any one of the input signals to turn on is applied, it is detected that the transistor is in an open defect.

(2) Transistor 22: OFF, Transistor 25: ON (T2: H, T3: L)
→ Transistor 22: Detection of short circuit failure In this case, if the transistor 22 is OFF, the potential of the decode signal output line 10 should be the potential divided by the resistance elements 24 and 26, that is, Vcc / 2. If a short circuit failure has occurred, the potential of the decode signal output line 10 becomes the power supply Vcc level, and therefore a short circuit failure can be detected.

(3) Transistors 22 and 25: ON (T2: L, T3: H)
→ Transistor 22: Open defect detection In this case, if the transistor 22 is ON, contrary to (2), the potential of the decode signal output line 10 should be the power supply Vcc level, but an open defect occurs in the transistor 22. Then, the potential of the decode signal output line 10 becomes the potential Vcc / 2 divided by the resistance elements 24 and 26, so that an open failure can be detected.
The function test of the transistor 25 can be performed by checking the level change of the decode signal output line 10 by switching the transistor 25 from ON to OFF or vice versa during the test of (1).

  As described above, according to the second embodiment, since the test resistance element 24 is connected in parallel to the series transistor group including the test transistor 22, the transistors 1 to 4 are opened by turning off the transistor 22. In addition to the defect detection, it is possible to detect an open defect of the resistance element 24. In addition, since the series circuit of the test transistor 25 and the test resistance element 26 is connected between the decode signal output line 10 and the ground, by combining the ON and OFF states of the two test transistors 22 and 25, It is possible to detect a short circuit failure or an open failure of the transistor 22.

(Third embodiment)
FIG. 3 shows a third embodiment of the present invention. Although the first and second embodiments are examples applied to a NOR type decoder, the third embodiment shows a case where the present invention is applied to a NAND type decoder 31.
That is, the decoder 31 includes four p-channel MOS transistors (second transistors) 33 to 36 connected in parallel so that the source is connected to the power supply Vcc and the drain is connected to the decode signal output line 32, and the drain Are basically connected to four n-channel MOS transistors (first transistors) 37 to 40 connected to the decode signal output line 32 side and connected in series so that the source is connected to the ground side. Then, a test n-channel MOS transistor 41 (first test transistor) is inserted between the transistor 40 and the ground, and an n-channel MOS transistor 42 (first transistor) is connected between the decode signal output line 32 and the ground. 2 test transistors) are connected.
According to the decoder 31 configured as described above, the same test as in the first embodiment can be performed by switching between the ON and OFF states of the two test transistors 41 and 42.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
The relationship between the p-channel and n-channel of the first and second transistors may be reversed.
The insertion positions of the test transistors 22 and 41 inserted into the series transistor group may be anywhere in the transistor group.
In the second embodiment, when only the test (1) is required, the series circuit of the transistor 25 and the resistor 26 is unnecessary.
For the NAND decoder 31 of the third embodiment, if the transistor 42 is replaced with a test resistance element, and a series circuit of the test transistor and the test resistance element is added between the power supply Vcc and the decode signal output line 32, A test can be performed as in the second embodiment.

1 is a first embodiment when the present invention is applied to a NOR type decoder circuit, where (a) is a diagram showing the configuration of the decoder, and (b) is a timing chart showing the circuit operation of the decoder. FIG. 1 (a) equivalent view showing a second embodiment of the present invention. FIG. 2 equivalent diagram showing a third embodiment when the present invention is applied to a NAND type decoder. 1 equivalent diagram showing the prior art

Explanation of symbols

  In the figure, 1-4 are n-channel MOS transistors (second transistors), 5-8 are p-channel MOS transistors (first transistor), 10 is a decode signal output line, and 11 is a p-channel MOS transistor 11 (first transistor). 2 test transistor), 21 is a decoder (decoder circuit), 22 is a p-channel MOS transistor (first test transistor), 23 is a decoder (decoder circuit), 24 is a test resistance element, and 25 is an n-channel MOS transistor. Transistor (test transistor), 26 is a test resistance element, 31 is a decoder (decoder circuit), 32 is a decode signal output line, 33 to 36 are p-channel MOS transistors (second transistors), and 37 to 40 are n-channels Type MOS transistor (first transistor), 41 is n-channel MOS transistor (first test transistor), 42 denotes an n-channel type MOS transistor (second test transistor).

Claims (3)

A plurality of first transistors connected in series or in parallel between the power supply and the decode signal output line, and a transistor complementary to the first transistor, and in parallel or in series between the decode signal output line and the ground In a decoder circuit composed of the same number of second transistors connected to the first transistor,
A first test transistor inserted in the transistor connected in series among the first and second transistors;
A decoder circuit comprising: a second test transistor connected in parallel to a transistor group including the first test transistor. A plurality of first transistors connected in series or in parallel between the power supply and the decode signal output line, and a transistor complementary to the first transistor, and in parallel or in series between the decode signal output line and the ground In a decoder circuit composed of the same number of second transistors connected to the first transistor,
A test transistor inserted on the transistor side connected in series among the first and second transistors;
A decoder circuit comprising: a test resistance element connected in parallel to a transistor group including the test transistor. 3. The decoder circuit according to claim 2, wherein a series circuit of a test transistor and a test resistance element is connected between the decode signal output line and a ground or a power source.

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