JP2007035171A - Semiconductor storage device and its testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem in a function test of semiconductor storage device that an operation margin can not be detected with respect to a defective write-in of data to a storage cell or a defective holding of data storage of the storage cell. <P>SOLUTION: By a simple constitution that a word line driving pulse generating circuit 13 capable of changing a word line driving pulse width is provided in the semiconductor storage device for changing a usual word line driving pulse width, the tests of the data write-in margin and the data holding margin of the semiconductor storage device can be carried out. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, in particular, an SRAM type semiconductor memory device and a method for testing an operation margin thereof.

  FIG. 6 is a basic configuration diagram of a conventional semiconductor memory device, and FIG. 5 is a circuit diagram of a semiconductor memory element (cell) of an SRAM type semiconductor memory device.

  As shown in FIG. 6, the basic configuration of the semiconductor memory device is an X decoder circuit 1 that decodes an X address signal to select one of a plurality of word lines WL1 to WLm, and a bit line that decodes a Y address signal. One storage element (cell) 4 in the memory matrix 3 is selected by the Y decode circuit 2 that selects one of the pairs BL1, BLX1 to BLn, BLXn. The input / output control circuit 5 transfers the storage data of the storage cell to the output terminal during the read operation, and transfers the input data to the storage cell during the write operation.

  As shown in FIG. 5, each memory cell 4 is composed of a total of six elements including NMOS access transistors 6 and 7, driver transistors 8 and 9, and PMOS load transistors 10 and 11. The NMOS transistor 8 and the PMOS transistor 10 constitute a first inverter, and the NMOS transistor 9 and the PMOS transistor 11 constitute a second inverter. A flip-flop circuit is configured by cross-connecting the input and output of the two inverters.

  In the read operation, a word line driving pulse having an optimum pulse width is generated and transmitted to the selected word line based on a clock signal from the word line driving pulse generation circuit 12. With this word line drive pulse, access transistors 6 and 7 become conductive, and the potential at point A of memory cell 4 is read to bit line BL1 and the potential at point B is read to bit line BLX1. A potential difference generated between bit line BL1 and bit line BLX1 is amplified by a sense amplifier (not shown) and read as stored information.

  In the write operation, a word line drive pulse having an optimum pulse width is generated and transmitted to the selected word line from the word line drive pulse generation circuit 12 based on a clock signal. With this word line drive pulse, the access transistors 6 and 7 become conductive, the point A of the memory cell 4 is connected to the bit line BL1, the point B is connected to the bit line BLX1, and data is written to the memory cell 4.

  As a test of these semiconductor memory devices, a so-called function (FN) test is performed in which various test patterns are normally written in all the memory cells and the test is repeated many times to determine whether or not they can be normally read out.

  Further, as a method for testing the operation margin (operation margin) of the semiconductor memory device, for example, as described in Patent Document 1, the time from sending the word line drive pulse to activating the sense amplifier is advanced. It has been proposed to detect a memory cell with a small margin by reducing the voltage difference between the bit line pair and bringing it close to the minimum potential difference that can be sensed.

Further, as described in Patent Document 2, it is possible to detect a memory cell with a small margin by lowering the voltage level of the word line drive pulse to make the memory information read / write condition of the memory cell strict. Proposed.
Japanese Patent Laid-Open No. 11-39899 Japanese Patent Laid-Open No. 3-156792

  However, the test method described in the above-mentioned patent document can detect an insufficient drive current of the memory cell, but cannot detect an operation margin for a data write failure to the memory cell or a data storage failure of the memory cell. Further, the test method described in Patent Document 2 has a problem that a circuit for changing the voltage level of the word line driving pulse is required.

  In order to solve the above problems, according to one aspect of the present invention, in a semiconductor memory device in which memory cells are arranged at positions where a plurality of word lines and a plurality of bit lines intersect, the driving pulse width of the word lines can be varied. It has a word line drive pulse generation circuit. Further, in a test method of a semiconductor memory device in which a memory cell is arranged at a position where a plurality of word lines and a plurality of bit lines intersect, a data retention margin of the memory cell or a memory cell Tested for writing margin.

  According to the present invention, the word line drive pulse width is made wider than usual to test the data retention margin of the memory cell, and the word line drive pulse width is made narrower than usual so as to store the data. The cell write margin test can be performed with a relatively simple configuration.

  FIG. 1 is a circuit diagram of a word line drive pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a time chart when testing a semiconductor memory device according to the embodiment of the present invention, and FIG. The flowchart and FIG. 4 are graphs showing the tendency of the operation lower limit voltage of the SRAM type semiconductor memory device to depend on the word line drive pulse width.

  The word line drive pulse generation circuit 13 in the present invention is a chopper circuit composed of inverters 14 to 17 and 20 and NAND circuits 18 and 19 as shown in FIG.

  The word line drive pulse generation circuit 13 replaces the word line drive pulse generation circuit 12 that outputs a fixed word line drive pulse shown in FIG. 6, and can change the word line drive pulse width.

  An output pulse from the word line drive pulse generation circuit 13 is applied to all the word lines WL1 to WLm through a gate circuit (not shown) in the X decoder circuit 1, but only to the word line selected by the X address signal. It is output as the word line drive pulse signal WLP.

  When the test mode terminal T is at the H level, the clock signal is delayed by the inverters 14 to 17 and the NAND circuit 18, and the word line drive pulse generation circuit 13 outputs a pulse having a normal width. As shown in A), a normal word line drive pulse width signal WLP is output to the word line WL.

  On the other hand, when the test mode terminal is at the L level, the clock signal is not delayed by the inverters 14 to 17 and the NAND circuit 18, and the word line drive pulse generation circuit 13 outputs a word line drive pulse wider than usual. As shown in (B) of 2, the word line drive pulse signal WLP having a width wider than usual is output to the word line WL.

  Next, a test flow of the semiconductor memory device according to the embodiment of the present invention will be described with reference to FIG.

When the test of the semiconductor memory device is started (step S1), the test mode terminal T is set to the H level, various test patterns are written to all the memory cells, and a normal function (FN) test for reading them is performed. (Step S2)
In this normal function test, a normal word line drive pulse is generated from the clock signal and applied to the word line WL of the memory cell 4 as the word line drive pulse signal WLP as shown in FIG. , 7 are conducted. Next, a sense enable signal (SAen) for driving a sense amplifier that reads information stored in the memory cell 4 is output. The stored data is read by driving the sense amplifier. (Dout)
As a result of the normal function test, if it is defective, it is selected as a defective product in the normal function test. (Step 3)
Up to this point, the normal function test has been performed so far. However, in the present invention, the test mode terminal T is further set to the L level and the function (FN) operation margin test is performed on the non-defective product. (Step 4)
In the function operation margin test, as shown in FIG. 2B, a word line driving pulse signal WLP wider than the word line driving pulse WLP shown in FIG. Therefore, the memory cell 4 is connected to the bit line pair BL1, BLX1 for a longer time than usual.

  FIG. 4 is a graph showing the dependence of the operation lower limit voltage on the word line drive pulse width of the SRAM type semiconductor memory device in which the horizontal axis represents the word line drive pulse width and the vertical axis represents the operation lower limit voltage of the memory cell.

  As is apparent from FIG. 4, as the word line drive pulse width increases from the optimum pulse width range P, the lower limit operating voltage of the memory cell increases, and the memory cell is in a state of being difficult to hold the stored information. Therefore, in this function operation margin test, a memory cell having a small data retention margin can be detected.

As a result of this function operation margin test, if it is defective, it is selected as a cell characteristic defective product. (Step 5)
The above function operation margin test detects the data retention margin of the storage information of the memory cell by performing the function test with the word line drive pulse width wider than usual, but conversely the word line drive pulse width Can be made narrower than usual to test the write margin of the memory cell.

  When the word line drive pulse is narrower than usual, the memory cell is connected to the bit line pair BL1, BLX1 only for a shorter time than usual when data is written to the memory cell. As apparent from FIG. 4, as the word line drive pulse width decreases from the optimum pulse width range P, the lower limit voltage of the operation of the memory cell 4 increases, and it is difficult to write the memory information to the memory cell. Become. Therefore, in this case, a memory cell having a small data write margin can be detected.

  In order to generate a word line drive pulse narrower than usual, a method of further increasing the number of stages of inverters 14 to 17 in the word line drive pulse generation circuit 13 of FIG. 1 or a clock signal (Clock) pulse may be used. You may make it switch to a narrow thing.

  As a test flow of the semiconductor memory device, instead of the combination of the above-mentioned normal function test and the operation margin test that applies a word line drive pulse wider than normal, the normal function test and word line drive narrower than normal You may combine with the operation | movement margin test which applies a pulse.

  Alternatively, the normal function test, the operation margin test that applies a word line drive pulse wider than normal, and the operation margin test that applies a word line drive pulse narrower than normal may be combined. That is, in step 5 of the test flow of FIG. 3, an operation margin test for applying a word line driving pulse narrower than usual is added to those selected as non-defective products. As a result, it is possible to select memory cells having a small data holding margin and data writing margin.

  According to the present invention, the test of the data retention margin and the data write margin of the semiconductor memory cell can be realized with a simple configuration in which the normal word line drive pulse width is wider or narrower than usual as described above.

  The present invention can test the data retention margin and data write margin of a semiconductor memory device with a simple configuration in which the normal word line drive pulse width is changed.

FIG. 5 is a circuit diagram of a word line driving pulse generator according to an embodiment of the present invention. Time chart at the time of test of a semiconductor memory device according to an embodiment of the present invention Semiconductor memory device test flowchart according to an embodiment of the present invention The graph which shows the tendency of the word line drive pulse width dependence of the operation | movement minimum voltage of SRAM type semiconductor memory device Circuit diagram example of semiconductor memory cell of SRAM type semiconductor memory device Configuration diagram of semiconductor memory device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 X decoder circuit 2 Y decoder circuit 3 Memory matrix 4 Memory cell 5 Input / output control circuit 6, 7 Access transistor 8, 9 Driver transistor 10, 11 Load transistor 12, 13 Word line drive pulse generation circuit 14-17, 20 Inverter 18 , 19 NAND circuit

Claims (5)

  A semiconductor memory device in which a memory cell is arranged at a position where a plurality of word lines and a plurality of bit lines intersect, and a semiconductor memory device having a word line driving pulse generating circuit capable of varying a driving pulse width of the word line .   2. The semiconductor memory device according to claim 1, wherein the drive pulse width is varied by varying the number of stages of the chopper circuit.   3. The semiconductor memory device according to claim 1, wherein the memory cell is an SRAM cell.   In a test method of a semiconductor memory device in which a memory cell is arranged at a position where a plurality of word lines and a plurality of bit lines intersect, testing the data retention margin of the semiconductor memory cell by changing the drive pulse width of the word line A method for testing a semiconductor memory device. In a test method of a semiconductor memory device in which memory cells are arranged at positions where a plurality of word lines and a plurality of bit lines intersect, the write margin of the semiconductor memory cells is tested by changing the drive pulse width of the word lines. A method for testing a semiconductor memory device.

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