JP2008016080A - Address decoder and its inspection apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address decoder capable of easily detecting a malfunction of multi-selection caused by a defect of an open system, and to provide its inspection apparatus. <P>SOLUTION: In the address decoder 10, resistors R10-R13 are interposed between the ground E and a decode output terminal Po on at least one side of drain side or source side of MOS transistors N11-N14 as to respective MOS transistors, and the decode output terminal Po is connected to a power source voltage Vdd through a resistor R21 and further connected to a non-inverted input. Also, a comparator Cp10 capable of detecting that potential higher than a division voltage of the power source voltage Vdd formed by a parallel combining resistor with the resistors R10-R13 and the resistor R21 at the time when the MOS transistors N11-N14 are all in on-states, is inputted to this non-inverted input is included. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an address decoder built in a ROM (Read Only Memory) and an inspection device thereof.

  The ROM has a built-in address decoder that decodes the address information of the memory cell when the stored data is read. As a failure mode of the address decoder, for example, the same memory cell is selected at a different address. There is a problem of so-called “multiple selection” (sometimes referred to as “multiple selection”). This defect is caused by an open-system failure that occurs when a transistor that constitutes the address decoder does not switch from an off state to an on state or a wiring pattern is disconnected.

  In general, the presence or absence of such multiple selection cannot be detected by simply reading the data stored in the memory cell, so by reading the value of the memory cell based on a test pattern that takes into account the combination of address and data The detection method has been conventionally employed. However, in such a conventional detection method, since it is necessary to create a test pattern corresponding to the content of data stored in accordance with the storage content of the ROM, it is difficult to create and manage the test pattern. It was happening.

  Thus, as prior art that can facilitate such detection, there are techniques disclosed in, for example, the following Patent Documents 1 to 3. In the “decoder circuit” disclosed in Patent Document 1 and the “test circuit” disclosed in Patent Document 2, transistors whose decoder lines are gate inputs are provided (Patent Document 1; NCH-TR405 to 475, Patent Document 2). T4 to T11), when multiple transistors are selected, the current change that flows through the transistors at that time is changed to a current sense amplifier or the like (Patent Document 1; Current Sense Amplifier 700, Patent Document 2). Detection by a sense amplifier 3) makes it possible to detect a change in the state of a transistor or the like (Patent Document 1; pages 3 to 5, FIGS. 1 and 2, Patent Document 2; paragraphs 0010 to 0013, FIG. 1,3).

In addition, in the “semiconductor memory” disclosed in Patent Document 3, a plurality of transistors each having a gate connected to each node capable of determining selection / non-selection of a plurality of row decoders are provided (Patent Document 3; Tr. 2). By detecting the potential change of the common node that collects the outputs of these transistors, it is possible to detect whether the row decoder is good or bad (Patent Document 3; paragraphs 0104 to 0106, 0115 to 0119). In each of the disclosed technologies disclosed in Patent Documents 1 to 3, it is possible to detect a malfunction of multiple selection caused by an open system failure of the decoder circuit without reading the value of the memory cell.
JP-A 64-69124 JP-A-6-201792 JP 2002-133898 A

  However, according to the prior arts disclosed in these Patent Documents 1 to 3, although it is not necessary to read the value of the memory cell, it is necessary to inspect the address decoder in consideration of an address combination that may cause multiple selection. For this reason, the trouble of creating such address data remains as it is, so that creation and management thereof are required, and there is a problem that it is not possible to easily detect a problem of multiple selection caused by an open system failure.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an address decoder capable of easily detecting a failure of multiple selection caused by an open system failure and an inspection device therefor There is to do.

  In order to achieve the above object, in the address decoder according to claim 1, on / off control is possible in the address decoder built in the ROM according to the signal level from the input terminal connected to the address line of the ROM. An address decoder comprising a plurality of semiconductor switching elements, each input / output connected in parallel and interposed between a reference potential and an output terminal, between the reference potential and the output terminal A plurality of resistors of 10 kΩ or more and 100 kΩ or less intervening at least one of the input side or output side of the plurality of semiconductor switching elements, a predetermined resistor connecting the output terminal to a predetermined potential, and connecting the output terminal to an input When the plurality of semiconductor switching elements are all in the on state, the parallel combined resistor by the plurality of resistors is used. And a voltage detector capable of detecting that a potential higher than the predetermined potential divided by the resistance and the predetermined resistance is input to the input.

  The address decoder according to claim 2, wherein the address decoder according to claim 1 further comprises switching means that can be externally controlled so as to be short-circuited between the reference potential and the output terminal. Characteristic.

  In the address decoder according to claim 3, the on-resistance of each of the plurality of semiconductor switching elements is 10 kΩ or more and 100 kΩ in place of the plurality of resistors in the address decoder according to claim 1 or 2. A technical feature is that the resistors having the following resistance values are used as the plurality of resistors. “On-resistance” refers to the resistance value between the input and output of the semiconductor switching element in the on-state of the semiconductor switching element.

  5. The address decoder detecting device according to claim 4, wherein the plurality of semiconductors are controlled to be turned on / off by an address decoder built in the ROM according to a signal level from an input terminal connected to an address line of the ROM. Address decoder for inspecting an address decoder having a switching element having an on-resistance of 10 kΩ or more and 100 kΩ or less, each input / output being connected in parallel and interposed between a reference potential and an output terminal A parallel combination of a plurality of resistors when the output terminals are connected to an input and the plurality of semiconductor switching elements are all in an ON state. A potential higher than the divided voltage of the predetermined potential by the resistor and the predetermined resistance is input to this input. And a voltage detector capable of detection.

  According to the first aspect of the present invention, a resistance (10 kΩ or more and 100 kΩ or less) is interposed between the reference potential and the output terminal on at least one of the input side and the output side of each of the semiconductor switching elements. The output terminal is connected to a predetermined potential via a predetermined resistor, and the output terminal is further connected to the input, and the predetermined combined potential of the parallel combined resistor and the predetermined resistor when the plurality of semiconductor switching elements are all in the ON state. A voltage detector capable of detecting that a potential higher than the divided voltage is input to this input. As a result, even though a signal of a signal level capable of turning on all of the plurality of semiconductor switching elements is input from the input terminal, the one that does not normally shift to the on state is the plurality of semiconductor switching elements. , The combined resistance value increases because the number of resistors constituting the parallel combined resistance is reduced accordingly. Therefore, in such a case, the voltage detector has a potential higher than the divided voltage of the predetermined potential generated by the parallel combined resistance of the plurality of resistors and the predetermined resistance when all of the plurality of semiconductor switching elements are in the ON state. Since the voltage is input, it is possible to detect the presence of the semiconductor switching element that does not normally shift to the on state by the voltage detector. Therefore, it becomes unnecessary to create and manage address data in consideration of a combination of addresses that can cause multiple selection, and it is possible to easily detect a malfunction of multiple selection due to an open system failure.

  According to a second aspect of the present invention, switching means that can be externally controlled so as to be short-circuited between the reference potential and the output terminal is provided. As a result, even if a resistance of 10 kΩ or more and 100 kΩ or less is present on at least one of the input side or the output side of the plurality of semiconductor switching elements, the switching means can short-circuit between the reference potential and the output terminal. Thus, the potential of the output terminal can be quickly discharged to the reference potential side.

  In the invention of claim 3, instead of the plurality of resistors, the on-resistance of each of the plurality of semiconductor switching elements having a resistance value of 10 kΩ or more and 100 kΩ or less is used as the plurality of resistors. This eliminates the need to provide a plurality of resistors between the reference potential and the output terminal, thereby reducing the number of parts, thereby reducing the cost and failure rate, and reducing the size and weight. Become.

  In a fourth aspect of the invention, a predetermined potential is connected to an output terminal of an address decoder having a plurality of semiconductor switching elements each having an on-resistance of 10 kΩ or more and 100 kΩ or less via a predetermined resistor, and the output terminal is input to the output terminal. And a voltage capable of detecting that a potential higher than the divided potential of the predetermined potential by the parallel combined resistance and the predetermined resistance when the plurality of semiconductor switching elements are all in the ON state is input to this input. A detector is provided. As a result, even though a signal of a signal level capable of turning on all of the plurality of semiconductor switching elements is input from the input terminal, the one that does not normally shift to the on state is the plurality of semiconductor switching elements. , The combined resistance value increases because the number of on-resistances constituting the parallel combined resistance is reduced accordingly. Therefore, in such a case, the voltage detector has a potential higher than the divided voltage of the predetermined potential by the parallel combined resistance by the plurality of ON resistances and the predetermined resistance when all of the plurality of semiconductor switching elements are in the ON state. Therefore, it is possible to detect the presence of the semiconductor switching element that does not normally shift to the on state by the voltage detector. Therefore, for address decoders composed of semiconductor switching elements having such a high on-resistance, it is not necessary to create and manage address data in consideration of address combinations that can cause multiple selection. Thus, it is possible to easily detect a malfunction of multiple selection caused by an open system failure.

  Embodiments of an address decoder and its detection apparatus according to the present invention will be described below with reference to the drawings. An embodiment in which the address decoder of the present invention is applied to an address decoder built in a mask ROM will be described with reference to FIGS. FIG. 1 is a block diagram showing a part of a ROM incorporating the address decoder 10 according to this embodiment, and FIG. 2 is a circuit diagram showing the configuration of the address decoder 10. ing. Further, FIG. 3 shows a timing chart showing the operation of the address decoder 10, which shows a decoding operation (FIG. 3A) and a test operation (FIG. 3B).

  As shown in FIG. 1, the address decoder 10 according to the present embodiment has lower 4 bits of address information (for example, 13 bits A0 to A12 when the mask ROM has an 8 kbit configuration) input to the mask ROM. Is mainly composed of a decoder circuit 10a, an additional circuit 10b, and a detection circuit 10c.

  The decoder circuit 10a is input from address buses A0, A1, A2, and A3 (hereinafter referred to as “A0 to A3”) connected to address input terminals Pa0, Pa1, Pa2, and Pa3 (hereinafter referred to as “Pa0 to Pa3”). It has a function of decoding address information and outputting it to a decode output terminal Po. For example, in the case of the address decoder 10 in which the output Out_0 is connected to xxx0 of the memory cell matrix 50, all four bits of the address information input from the address buses A0 to A3 are logical level L level (hereinafter simply referred to as “L level”). The logic value H level (hereinafter simply referred to as “H level”) can be output only when

  In the case of the address decoder 10 in which the output Out_1 is connected to xxx1 of the memory cell matrix 50, the least significant bit of the address information from the address buses A0 to A3 is H level and the other 3 bits are all L level. In the case of the address decoder 10 that outputs the H level only when the output Out_f is similarly connected to the xxxf of the memory cell matrix 50, all four bits of the address information from the address buses A0 to A3 are at the H level. Each is configured to output an H level only. Note that “f” in xxxf means a hexadecimal number of 15. In this embodiment, 16 sets of such address decoders 10 are connected as X decoders (or Y decoders) of the mask ROM.

  Such a decoder circuit 10a is configured as a NOR type decoder, for example, and a specific circuit example is shown in FIG. Here, the case of the address decoder 10 in which the output Out_0 is connected to xxx0 of the memory cell matrix 50 will be described as an example.

  As shown in FIG. 2, the decoder circuit 10a includes P-channel type MOS transistors P10, P11, P12, P13, P14 (hereinafter referred to as "P10 to P14") and N-channel type MOS transistors N10, N11, N12, N13. , N14 (hereinafter referred to as “N10 to N14”), an inverting amplifier INV1, and resistors R10, R11, R12, and R13 (hereinafter referred to as “R10 to R13”).

  The MOS transistors P10 to P13 are semiconductor switching elements that can be controlled to be turned on and off according to the signal level of the address information input to the gate (on state at the signal level L and off state at the signal level H), and correspond to the least significant bit of the address information. The input / output is connected in series in order from the MOS transistor P10 to the upper bit direction.

  That is, the gate of the MOS transistor P10 is connected to the address input terminal Pa0, the gate of the MOS transistor P11 is connected to the address input terminal Pa1, the gate of the MOS transistor P12 is connected to the address input terminal Pa2, and the gate of the MOS transistor P13 is connected to the address input terminal Pa3. The source of the MOS transistor P10 is connected to the power supply voltage Vdd, the drain of the MOS transistor P10 is the source of the MOS transistor P11, the drain of the MOS transistor P11 is the source of the MOS transistor P12, and this The drain of the MOS transistor P12 is the source of the MOS transistor P13, the drain of the MOS transistor P13 is the source of the MOS transistor P14, and the drain of the MOS transistor P14 is the decode output terminal. The Po, are connected.

  The MOS transistor P14 is a semiconductor switching element having a function that can be controlled from the outside so that the decode output terminal Po and the drain of the MOS transistor P13 can be short-circuited. In this embodiment, the gate is connected to the inverting amplifier from the system clock input terminal Pc. The decode output terminal Po is connected to the drain via the INV1, and the drain of the MOS transistor P13 is connected to the source. The inverting amplifier INV1 is an inverting circuit that can invert the input signal level L to the signal level H and the input signal level H to the signal level L, and is also referred to as an inverter.

  The MOS transistors N11 to N14 are also semiconductor switching elements that can be controlled to be turned on and off according to the signal level of the address information input to the gate. However, contrary to the MOS transistors P10 to P13, the MOS transistors N11 to N14 are turned on at the signal level H, The MOS transistor N11 corresponding to the least significant bit of the address information and the MOS transistor N14 corresponding to the upper bit are both connected in parallel to each other and are controlled to be turned off. The MOS transistors N11 to N14 can correspond to “a plurality of semiconductor switching elements” recited in the claims.

  That is, the gate of the MOS transistor N11 is the address input terminal Pa0, the gate of the MOS transistor N12 is the address input terminal Pa1, the gate of the MOS transistor N13 is the address input terminal Pa2, and the gate of the MOS transistor N14 is the address input terminal Pa3. The drains of the MOS transistors N11 to N14 are connected to the decode output terminal Po, respectively. The source of the MOS transistor N11 is connected through the resistor R10, the source of the MOS transistor N12 is connected through the resistor R11, the source of the MOS transistor N13 is connected through the resistor R12, and the source of the MOS transistor N14 is connected through the resistor R13. Each is connected to ground E.

The resistors R10 to R13 are connected so as to be interposed between the sources of the MOS transistors N11 to N14 and the ground E as described above to constitute the additional circuit 10b. These are, for example, 10 kΩ or more and 100 kΩ or less. The same resistance value (for example, 10 kΩ) is set. This resistance value corresponds to 10 ⁴ times to 10 ⁸ times the on-resistance (several mΩ to several Ω) of a normal MOS transistor, and thus can be said to be high resistance in this sense. In the present embodiment, these resistors R10 to R13 are connected so as to be interposed between the sources of the MOS transistors N11 to N14 and the ground E. However, the present invention is not limited to this. For example, the decode output terminal and the PoMOS transistor You may connect so that it may interpose with the drain of N11-N14. Further, the MOS transistors N11 to N14 may be connected so as to be interposed on both the drain side and the source side. The resistors R10 to R13 may correspond to “a plurality of resistors” recited in the claims.

  The MOS transistor N10 is a semiconductor switching element having a function that can be controlled from the outside so that the decode output terminal Po and the ground E can be short-circuited. In this embodiment, the system clock input terminal Pc is the gate and the drain is the decode. The output terminal Po is connected to the source, and the ground E is connected to the source. The MOS transistor N10 can correspond to "switching means" described in the claims.

  The MOS transistor N10 constitutes the additional circuit 10b together with the resistors R10 to R13 described above, and the decode output terminal Po and the ground E are synchronized with the system clock input from the clock bus CLK via the system clock input terminal Pc. It can be turned on and off. Thus, even if the resistors R10 to R13 are interposed on the source side of the MOS transistors N11 to N14, the MOS transistor N10 can short-circuit between the ground E and the decode output terminal Po. Therefore, the resistors R10 to R13 Thus, the potential (charge) of the decode output terminal Po, which prevents rapid discharge, can be quickly discharged to the ground E side. Therefore, by performing such discharge every system clock, even if the resistors R10 to R13 are interposed in series with the MOS transistors N11 to N14, the operating speed of the MOS transistors N11 to N14 due to these resistors R10 to R13 can be reduced. A decrease can be prevented.

  By configuring the decoder circuit 10a in this way, the address decoder 10 during decoding operates according to the timing chart shown in FIG. As shown in FIG. 3A, for example, all four bits of the address information input from the address buses A0 to A3 via the address input terminals Pa0 to Pa3 are at L level, and via the system clock input terminal Pc. When the clock input from the clock bus CLK to the MOS transistor N10 is at L level, the MOS transistors P10 to P13 are turned on and the MOS transistors N10 to N14 are turned off. Therefore, in this case, the H level output Out_0 is output from the decode output terminal Po (the gray portion timing shown in FIG. 3A).

  On the other hand, when at least one of the 4 bits of the address information input from the address buses A0 to A3 is at H level, or when the clock input to the MOS transistor N10 is at H level, the MOS Since any of the transistors N11 to N14 or the MOS transistor N10 is turned on, the potential of the decode output terminal Po is pulled to the ground E side. Therefore, in this case, an L level output Out_0 is output from the decode output terminal Po (timing other than the gray portion shown in FIG. 3A). Thus, only when the address information input to the decoder circuit 10a is 0h (h indicates hexadecimal notation), the H level output Out_0 is output from the decode output terminal Po. Address decoding is possible.

  The decoder circuit 10a is configured in this manner and enables a decoding operation, while the address decoder 10 according to the present embodiment includes a detection circuit 10c. Here, the configuration of the detection circuit 10c will be described with reference to FIGS. In this embodiment, the detection circuit 10c and the decode output terminal Po are directly connected. For example, a switching means such as a CMOS switch is provided between the detection circuit 10c and the decoding output terminal Po. The control input for turning off the switching means during other decoding operations or the like may be input from the outside.

  As shown in FIG. 1, the detection circuit 10c includes a comparator Cp10, resistors R21, R22, R23, a sampling circuit S10, and a switch SW1. The comparator Cp10 and the resistors R22 and R23 can correspond to the “voltage detector” recited in the claims, and the resistor R21 can correspond to the “predetermined resistor” recited in the claims. Is.

  The comparator Cp10 has a function of comparing the voltage input to the inverting input with the voltage input to the non-inverting input and outputting the comparison result by the H level or L level output signal Cout_0. The main functions of In the case of the present embodiment, the reference voltage Vref is connected to the inverting input of the comparator Cp10, while the potential of the decode output terminal Po described above is input to the non-inverting input as an input voltage to be compared with the reference voltage Vref. A decode output terminal Po is connected to enable input, and a resistor R21 is connected to the power supply voltage Vdd. When the inverting input is larger (higher) than the non-inverting input, the L-level output signal Cout_0 is output. When the inverting input is smaller (lower) than the non-inverting input, the H-level output signal Cout_0 is output. The input of the sampling circuit S10 is connected to the output of the comparator Cp10.

  The switch SW1 can turn on / off the conduction between the decoding output (decoding output terminal Po) of the decoder circuit 10a and the comparator Cp10 of the detection circuit 10c according to a control input inputted from the outside. For example, a CMOS analog switch is used. It is done. In the case of the present embodiment, as will be described later, the decoder circuit 10a can be tested by turning on the switch SW1 when the address decoder 10 is tested.

  As the reference voltage Vref, a voltage taken out as a divided voltage by resistors R22 and R23 connected in series between the power supply voltage Vdd and the ground E is used. The resistor R22 is set to a value (for example, 10 kΩ) that is substantially the same as the value of the resistor R21 connected between the non-inverting input of the comparator Cp10 and the power supply voltage Vdd, and the resistor R23 is, for example, any of the resistors R10 to R13 described above. Is approximately equal to 10 kΩ, it is set to 1 / 3.5, that is, 2.86 kΩ (≈10 kΩ / 3.5). Thus, since the reference voltage Vref is obtained by the power supply voltage Vdd × R23 / (R22 + R23), for example, when the power supply voltage Vdd is 5 V, the reference voltage Vref is 5 V × 2.86 kΩ / (10 kΩ + 2.86 kΩ). = 1.1V.

  Here, in determining the resistance value of the resistor R23, the value obtained by dividing the resistance values of the resistors R10 to R13 by 3.5 (2.86 kΩ≈10 kΩ / 3.5) will be described later. Thus, when all the MOS transistors N11 to N14 are normally turned on, the parallel combined resistance (R10 // R11 // R12 // R13) formed between the decode output terminal Po and the ground E is It is based on the fact that it is composed of four resistors of 10 kΩ (“//” is a symbol meaning parallel connection, and the same applies hereinafter).

  That is, when all of the MOS transistors N11 to N14 are normally turned on without any open system failure, the parallel combined resistance formed between the decode output terminal Po and the ground E is R10 // R11 // R12 // R13 and, as described above, since these resistors are almost the same value, the value of the parallel combined resistance is 1/4 of one resistance value. On the other hand, when at least one of the MOS transistors N11 to N14 has an open-system failure, the parallel combined resistance formed between the decode output terminal Po and the ground E is the resistance R10 to Since at least one of R13 is a parallel combined resistance, at least the value of the parallel combined resistance is 1/3 or less of one resistance value, that is, smaller (lower) than 1 / 3.5.

  Therefore, by dividing the resistance values of the resistors R10 to R13 by 3.5 to the resistance value of the resistor R23, the resistance value of the resistor R23 is composed of four resistors having the same value to form a parallel combined resistor. The resistance value is larger (higher) than the resistance value in this case, and smaller (lower) than the resistance value in the case where the parallel combined resistance is configured with three resistors having the same value. For this reason, in this embodiment, the resistance values of the resistors R10 to R13 are divided by 3.5. For example, when the circuit configuration of the decoder circuit 10a corresponds to the one that decodes the address information of the 8-bit configuration. Since there are eight resistors constituting such a parallel combined resistor, a value obtained by dividing these resistance values by 7.5 is set as the resistance value of the resistor R23. That is, when the circuit configuration of the decoder circuit 10a corresponds to the one that decodes address information of n (n is an integer of 1 or more) bit configuration, the resistance value of one resistor constituting the parallel combined resistor is obtained. A value obtained by dividing by (n−0.5) is set to the resistance value of the resistor R23.

  Therefore, in the case of the present embodiment, the voltage input to the non-inverting input is obtained by using the voltage divided by the resistor R23 set to such a value and the resistor R22 described above as the inverting input of the comparator Cp10 as the reference voltage Vref. Is a divided voltage by the parallel combined resistor composed of four resistors and the resistor R21 (= R22), or the parallel combined resistor and resistor R21 (= R22) composed of three or less resistors It can be determined from the output result of the comparator Cp10 whether the partial pressure is due to the above.

  The sampling circuit S10 has a function capable of holding the output signal Cout_0 of the input comparator Cp10 at a predetermined timing and outputting it as a flag signal Fsg. For example, a latch circuit or a sample hold circuit corresponds to this. In the present embodiment, a latch circuit capable of holding and outputting the input output signal Cout_0 at the timing when the sampling clock Sck is input is applied. For this reason, the output of the comparator Cp10 is connected to the input, and the sampling clock input terminal Ps is connected to the clock input. A flag output terminal Pf is connected to the output of the flag signal Fsg. As a result, the output signal Cout_0 of the comparator Cp10 input at the rising timing of the sampling clock Sck can be sampled and output as the flag signal Fsg.

  By configuring the detection circuit 10c as described above, the address decoder 10 at the time of the test operates according to the timing chart shown in FIG. Specifically, after inputting a control input for turning on the switch SW1 of the detection circuit 10c, a test operation described below is performed.

  That is, when testing the address decoder 10, all four bits of the address information input from the address buses A0 to A3 are set to the H level, and the system clock input from the clock bus CLK is set to the L level. As a result, when all the MOS transistors N11 to N14 are normally turned on, the resistors R10 to R13 are all connected in parallel between the decode output terminal Po and the ground E. For this reason, the divided voltage (= Vdd × (R10 // R11 // R12 // R13) / (R21 + R10 // R11 // R12 // R13)) of the combined resistance of the resistors R10 to R13 and the resistor R21 is a comparator. Since it is input to the non-inverting input of Cp10, for example, when the power supply voltage Vdd is 5V, 5V × 2.5 kΩ / (10 kΩ + 2.5 kΩ) = 1.0 V is input to the non-inverting input of the comparator Cp10. Therefore, compared with 1.1 V of the reference voltage Vref input to the inverting input, there is a relationship of non-inverting input (1.0 V) <inverting input (Vref = 1.1 V). When the output signal Cout_0 is output and the L level output signal Cout_0 is sampled by the sampling circuit S10 at the rising timing of the sampling clock Sck, the L level flag signal Fsg is output from the sampling circuit S10 (FIG. 3 ( B) Normal on the left side of the paper.

  On the other hand, when one of the MOS transistors N11 to N14 does not shift to the on state, the MOS transistor is maintained in the off state, so that the parallel combined resistor is connected to the resistor R10 between the decode output terminal Po and the ground E. It is comprised by three of ~ R13. For example, when the MOS transistor N12 does not shift to the ON state due to an open system failure, the resistor R11 connected to the source does not form a parallel resistor with the other resistor R10 and the like, and therefore between the power supply voltage Vdd and the ground E. The parallel combined resistance at is R10 // R12 // R13. For this reason, the divided voltage (= Vdd × (R10 // R12 // R13) / (R21 + R10 // R12 // R13)) of the parallel combined resistance of the resistors R10, R12, and R13 and the resistor R21 is non-inverted by the comparator Cp10. When the power supply voltage Vdd is 5V, 5V × 3.3 kΩ / (10 kΩ + 3.3 kΩ) = 1.2 V is input to the non-inverting input of the comparator Cp10. Therefore, when compared with 1.1 V of the reference voltage Vref input to the inverting input, there is a relationship of non-inverting input (1.2 V)> inverting input (Vref = 1.1 V). When the output signal Cout_0 is output, and when the H level output signal Cout_0 is sampled at the rising timing of the sampling clock Sck by the sampling circuit S10, the H level flag signal Fsg is output from the sampling circuit S10 (FIG. 3 ( B) on the right side of the paper).

  Further, when two of the MOS transistors N11 to N14 do not shift to the on state, the parallel combined resistance between the decode output terminal Po and the ground E is constituted by two of the resistors R10 to R13. Therefore, for example, when the MOS transistors N12 and N14 do not shift to the ON state due to an open system failure, the resistors R11 and R13 connected to their sources do not constitute a parallel resistor with the other resistors R10 and the like. Therefore, the divided voltage (= Vdd × (R10 // R12) / (R21 + R10 // R12)) of the parallel combined resistance of the resistors R10 and R12 and the resistor R21 is input to the non-inverting input of the comparator Cp10, and the power supply voltage Vdd 5V × 5 kΩ / (10 kΩ + 5 kΩ) = 1.7 V is input to the non-inverting input of the comparator Cp10. Also in this case, since there is a relationship of non-inverting input (1.7 V)> inverting input (Vref = 1.1 V), an output signal Cout_0 of H level is output from the comparator Cp10, and the sampling clock is output by the sampling circuit S10. When the H level output signal Cout_0 is sampled at the rise timing of Sck, the sampling circuit S10 outputs the H level flag signal Fsg (at the time of failure on the right side of FIG. 3B).

  When three of the MOS transistors N11 to N14 do not shift to the on state, the resistance between the decode output terminal Po and the ground E no longer constitutes a parallel composite resistor, so the MOS that has shifted to the on state. Only the resistor connected to the source of the transistor. In this case, since any one of the resistors R10 to R13 and the resistor R21 are divided between the power supply voltage Vdd and the ground E, the power supply voltage Vdd can be obtained if both resistors are substantially equal. 1/2 of (= Vdd / 2) is input to the non-inverting input of the comparator Cp10. That is, when the power supply voltage Vdd is 5V, 5V / 2 = 2.5V is input to the non-inverting input of the comparator Cp10. Also in this case, since there is a relationship of non-inverting input (2.5 V)> inverting input (Vref = 1.1 V), an output signal Cout_0 of H level is output from the comparator Cp10, and the sampling clock is output by the sampling circuit S10. When the H level output signal Cout_0 is sampled at the rise timing of Sck, the sampling circuit S10 outputs the H level flag signal Fsg (at the time of failure on the right side of FIG. 3B).

  If none of the MOS transistors N11 to N14 is turned on, that is, if all of the MOS transistors N11 to N14 have an open fault, there is no resistance between the decode output terminal Po and the ground E. Therefore, the non-inverting input of the comparator Cp10 connected to the decode output terminal Po is kept pulled up to the power supply voltage Vdd side by the resistor R21. Therefore, in such a case, since the potential of the power supply voltage Vdd is almost input to the comparator Cp10, for example, when the power supply voltage Vdd is 5V, the non-inverting input 5V is input. Also in this case, since the relationship of non-inverting input (5V)> inverting input (Vref = 1.1V) is established, the comparator Cp10 outputs an H level output signal Cout_0, and the sampling circuit S10 outputs the sampling clock Sck. When the H level output signal Cout_0 is sampled at the rising timing, the H level flag signal Fsg is output from the sampling circuit S10 (at the time of failure on the right side of FIG. 3B).

  As described above, in the address decoder 10 according to the present embodiment, when there is an open-system failure including wiring in any one or more of the MOS transistors N11 to N14, both voltages input to the comparator Cp10 of the detection circuit 10c are detected. Since the relationship is non-inverted input (1.2V to 5V)> inverted input (Vref = 1.1V), the comparator Cp10 outputs an output signal Cout_0 of H level. Therefore, by sampling this at the timing of the predetermined sampling clock Sck by the sampling circuit S10, it is possible to easily detect that an open system failure has occurred in the decoder circuit 10a.

  If the accuracy of the resistors R10 to R13 connected to the sources of the MOS transistors N11 to N14 is not high, the decoder circuit 10a has an open fault as described above by adopting the following configuration and test method. Can be easily detected.

  For example, any two MOS transistors of the MOS transistors N11 to N14 can be inspected as a set, and the test is divided into a plurality of times. In this case, the resistance value of the resistor R23 is set to a value obtained by dividing the resistance values of the resistors R10 to R13 by 1.5, so that the resistance value of the resistor R23 is approximately equal to two resistors. The resistance value is larger (higher) than that in the case where the parallel combined resistor is configured, and is smaller (lower) than the resistance value in the case where the parallel combined resistor is configured with one resistor having substantially the same value.

  Thus, when the address decoder 10 is tested, first, among the 4 bits of the address information input from the address buses A0 to A3, the address buses A0 and A1 are set to H level, A2 and A3 are set to L level, and the clock The system clock input from the bus CLK is set to L level. In this setting, if the MOS transistors N11 and N12 are normal among the MOS transistors N11 to N14, they are turned on, and the remaining MOS transistors N13 and N14 are kept off, so that the decode output terminal Po and A parallel combined resistor is formed between the ground E and the resistors R10 and R11. Therefore, the divided voltage (= Vdd × (R10 // R11) / (R21 + R10 // R11)) between the parallel combined resistance of the resistors R10 and R11 and the resistor R21 is input to the non-inverting input of the comparator Cp10 and is input to the inverting input. The input voltage is compared with the divided voltage (= Vdd × R23 / (R22 + R23)) of the resistor R22 and the resistor R23, and the result is output from the comparator Cp10 as the output signal Cout_0.

  Next, out of the 4 bits of the address information input from the address buses A0 to A3, the address buses A0 and A1 are set to L level, A2 and A3 are set to H level, and the system clock input from the clock bus CLK is set. Set to L level. In this setting, if the MOS transistors N13 and N14 are normal among the MOS transistors N11 to N14, they are turned on, and the remaining MOS transistors N11 and N12 are kept off, so that the decode output terminal Po and A parallel combined resistor is formed between the ground E and the resistors R12 and R13. For this reason, the divided voltage (= Vdd × (R12 // R13) / (R21 + R12 // R13)) of the parallel combined resistance of the resistors R12 and R13 and the resistor R21 is input to the non-inverting input of the comparator Cp10 and is input to the inverting input. The input voltage is compared with the divided voltage (= Vdd × R23 / (R22 + R23)) of the resistor R22 and the resistor R23, and the result is output from the comparator Cp10 as the output signal Cout_0.

  The output signal Cout_0 output from the comparator Cp10 is at the L level if it is normal, and is at the H level if there is an open system failure or the like, and is sampled and output by the sampling circuit S10 as described above. It can be easily detected from the signal level of the flag signal Fsg that an open-system failure has occurred in the decoder circuit 10a.

  As described above, according to the address decoder 10 according to the present embodiment, for each of the MOS transistors N11 to N14, at least one of the drain side and the source side of the MOS transistors N11 to N14 is connected between the ground E and the decode output terminal Po. And the decode output terminal Po is connected to the power supply voltage Vdd via the resistor R21, the decode output terminal Po is connected to the non-inverting input, and the MOS transistors N11 to N14 are all turned on. A comparator Cp10 capable of detecting that a potential higher than the divided voltage of the power supply voltage Vdd by the resistor R21 and the parallel combined resistor by the resistors R10 to R13 is input to this non-inverting input.

  As a result, even though an H level signal capable of turning on all of these MOS transistors N11 to N14 is inputted from the address input terminals Pa0 to Pa3, those which do not normally shift to the on state are those MOSs. When the transistors N11 to N14 are present, the number of resistors R10 to R13 constituting the parallel combined resistor is reduced correspondingly, so that the combined resistance value is increased. Therefore, in such a case, the comparator Cp10 has a voltage higher than the divided voltage of the power supply voltage Vdd by the parallel combined resistance of the resistors R10 to R13 and the resistor R21 when the MOS transistors N11 to N14 are all on. Since the potential is input, it is possible to detect the presence of the MOS transistor that does not normally shift to the on state by the comparator Cp10. Therefore, it becomes unnecessary to create and manage address data in consideration of a combination of addresses that can cause multiple selection, and it is possible to easily detect a malfunction of multiple selection due to an open system failure.

  Further, the address decoder 10 according to the present embodiment includes a MOS transistor N10 that can be controlled from the outside so as to be short-circuited between the ground E and the decode output terminal Po. As a result, even if the resistances R10 to R13 of 10 kΩ are interposed in at least one of the drain side or the source side of the MOS transistors N11 to N14, the MOS transistor N10 shorts between the ground E and the decode output terminal Po. Therefore, the potential of the decode output terminal Po can be quickly discharged to the ground E side. Therefore, by performing such discharge every system clock, even if the resistors R10 to R13 are interposed in series with the MOS transistors N11 to N14, the operating speed of the MOS transistors N11 to N14 due to these resistors R10 to R13 can be reduced. A decrease can be prevented.

In the above-described embodiment, the resistors R10 to R13 are connected in series to the MOS transistors N11 to N14. For example, instead of the resistors R10 to R13, the on-resistance R _ON included in the MOS transistor is used. 10, R _ON 11, R _ON 12, R _ON 13 (hereinafter referred to as “R _ON 10 to R _ON 13”) may be used. That is, by applying a MOS transistor having a resistance value of 10 kΩ or more and 100 kΩ or less as the _ON resistances R _ON 10 to R _ON 13 to the MOS transistors N11 to N14, the resistors R10 to R10 are connected between the ground E and the decode output terminal Po. There is no need to provide R13. As a result, the number of parts can be reduced, and accordingly, the cost and the failure rate can be reduced, and further, the size and weight can be reduced.

  Next, another embodiment in which an inspection apparatus for an address decoder according to the present invention is built in a mask ROM will be described with reference to FIGS. The detection device 20 according to the other embodiment is configured around the detection circuit 10c of the address decoder 10 according to the above-described embodiment. For this reason, substantially the same components as those of the address decoder 10 according to the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 4 is a block diagram showing a part of a ROM incorporating the address decoder inspection device 20 according to the other embodiment.

As shown in FIG. 4, the detection device 20 includes a detection circuit 10c and a selection circuit 10d, and is connected to the decode output terminal Po of each address decoder 10 ′ and is output from these decode output terminals Po. The output Out_0 (Out_1 ... Out_f) can be input.
The detection circuit 10c is configured substantially the same as the detection circuit 10c shown in FIG. 1, and is configured so that the output of the selection circuit 10d can be input to the non-inverting input of the comparator Cp10.

  The selection circuit 10d is a signal selector having a function of selecting and outputting the output Out_0 (Out_1... Out_f) input from each address decoder 10 ′ according to the selection signal Sel input from the outside. There are 16 input ports and 1 output port. The selection circuit 10d is composed of, for example, a plurality of CMOS switches.

Note that the address decoder 10 ', a structure excluding the detection circuit 10c from the address decoder 10 shown in FIG. 1, the resistor R10~R13 the on-resistance _{R ON 10~R ON} 13 of the MOS transistor N11～N14, also MOS transistors It has a decoder circuit 10a 'having a configuration excluding N10. In other words, a decoder circuit 10a 'corresponds to a normal NOR-type decoder MOS transistor having a high on-resistance (10 kΩ to 100 kΩ).

'By adding relative address decoder 10' such address decoder 10 to the formed detecting device 20 using a MOS transistor having a high on-resistance R _ON 10~R _ON 13 so in the test of the test The input port connected to the decode output terminal Po of the address decoder 10 ′ is selected by the selection signal Sel. Then, the detection circuit 10c of the detection device 20 is operated by the timing chart shown in FIG. 3B with respect to the address decoder 10 ′ thus selected, as in the case of the above-described embodiment. Thereby, when there is an open-system failure including wiring in any one or more of the MOS transistors N11 to N14, the relationship between the two voltages input to the comparator Cp10 of the detection circuit 10c is the non-inverted input (1 .2V-5V)> inverted input (Vref = 1.1V), the comparator Cp10 outputs an H level output signal Cout_0, which is sampled by the sampling circuit S10 at the timing of a predetermined sampling clock Sck. Thus, it is possible to easily detect that an open system failure has occurred in the address decoder 10 '.

As described above, in the detection device 20 according to the other embodiment, the decode outputs of the address decoder 10 ′ including the MOS transistors N11 to N14 whose on-resistances R _ON 10 to R _ON 13 have resistance values of 10 kΩ or more and 100 kΩ or less. The power supply voltage Vdd is connected to the terminal Po via the resistor R21, and the decode output terminal Po is connected to the non-inverting input, and the on-resistances R _ON 10 to R when the MOS transistors N11 to N14 are all in the on state. comprises a detectable comparator Cp10 that a potential higher than the partial pressure of the power supply voltage Vdd by a parallel combined resistance and the resistance R21 due to _oN 13 is input to the input.

As a result, even though an H level signal capable of turning on all of these MOS transistors N11 to N14 is inputted from the address input terminals Pa0 to Pa3, those which do not normally shift to the on state are those MOSs. if present in the transistor N11~N14 is that amount, the combined resistance value is increased the number of on-resistance R _oN 10~R _oN 13 constituting a parallel combined resistance decreases. Therefore, in such a case, the comparator Cp10, the power supply voltage Vdd by a parallel combined resistance with the resistor R21 by a plurality of the on-resistance R _ON 10~R _ON 13 when MOS transistor N11~N14 are all in the on state Since a potential higher than the divided voltage is input, it is possible to detect the presence of a MOS transistor that does not normally shift to the ON state by the comparator Cp10. Thus, for such high on-resistance R _ON 10~R _ON 13 constructed address decoder 10 in MOS transistors having a 'create address data multiplexing selection considering combinations of addresses, such as may occur Since no management is required, it is possible to easily detect a problem of multiple selection caused by an open system failure.

In this example, the detection device 20 is inspected by adopting a configuration in which the detection circuit 10c and the MOS transistor N10 are removed from the address decoder 10 shown in FIG. 1, and the resistors R10 to R13 are turned on by turning on the MOS transistors N11 to N14. resistance R _oN 10~R has been illustrated and described the 'address decoder 10 having a' decoder circuit 10a configured as _oN 13, never Kagireru thereto, only the detection circuit 10c from the address decoder 10 shown in FIG. 1 The address decoder 10 having a decoder circuit having a configuration excluding the above can be a target to be inspected by the detection device 20 according to the other embodiment. In this case, the same explanation can be made by replacing the above-mentioned “on resistances R _ON 10 to R _ON 13” with “resistances R 10 to R 13”.

  In each of the embodiments described above, the case of the mask ROM has been described as an example. However, in the address decoder and the inspection device of the present invention, the input and output of a plurality of semiconductor switching elements are connected in parallel to output the reference potential and the output. Any decoder that employs a configuration intervening between the terminals can be applied to various semiconductor memory devices such as EPROM that mainly read data, and the same operations and effects as described above can be obtained.

  In each of the embodiments described above, a NOR-type decoder has been described as the address data. However, the decoding on the NAND side also includes “a plurality of semiconductor switching elements that can be controlled on and off according to the signal level from the input terminal”. If the address decoder has an input / output connected in parallel and interposed between the reference potential and the output terminal, the same operation and effect can be obtained by configuring in the same manner as described above. it can.

It is a block diagram which shows a part of ROM which incorporated the address decoder based on one Embodiment of this invention. It is a circuit diagram which shows the structure of the address decoder which concerns on this embodiment. 3A and 3B are timing charts showing the operation of the address decoder according to the present embodiment. FIG. 3A shows a decoding operation and FIG. 3B shows a test operation. It is a block diagram which shows a part of ROM incorporating the test | inspection apparatus of the address decoder which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10 '... Address decoder 10a ... Decoder circuit 10b ... Additional circuit 10c ... Detection circuit 10d ... Selection circuit 20 ... Detection apparatus 50 ... Memory cell matrix A0, A1, A2, A3 ... Address bus (address line)
CLK: Clock bus Cp10: Comparator (voltage detector)
E ... Earth (reference potential)
Fsg: Flag signal INV1: Inverting amplifier N10: MOS transistor (switching means)
N11, N12, N13, N14 ... MOS transistors (multiple semiconductor switching elements)
P10, P11, P12, P13, P14 ... MOS transistors Pa0, Pa1, Pa2, Pa3 ... Address input terminals (input terminals)
Pc: System clock input terminal Pf: Flag output terminal Po: Decode output terminal (output terminal)
Ps: Sampling clock input terminal R10, R11, R12, R13 ... Resistor R (multiple resistors)
R21: Resistance (predetermined resistance)
R22, R23 ... resistance (voltage detector)
R _ON 10, R _ON 11, R _ON 12, R _ON 13 ... ON resistance S10 ... Sampling circuit Sck ... Sampling clock Sel ... Selection signal SW1 ... Switch Vdd ... Power supply voltage (predetermined potential)

Claims (4)

In the address decoder built in the ROM, a plurality of semiconductor switching elements that can be controlled to be turned on and off according to the signal level from the input terminal connected to the address line of the ROM. An address decoder provided with an intervening terminal,
A plurality of resistors of 10 kΩ or more and 100 kΩ or less interposed between at least one of the input side and the output side of the plurality of semiconductor switching elements between the reference potential and the output terminal;
A predetermined resistor for connecting the output terminal to a predetermined potential;
When the output terminal is connected to the input, a potential higher than a divided voltage of the predetermined potential by the parallel combined resistance by the plurality of resistors and the predetermined resistance when the plurality of semiconductor switching elements are all in the ON state is input to the input terminal. A voltage detector capable of detecting the input to
An address decoder comprising:   2. The address decoder according to claim 1, further comprising switching means that can be controlled from the outside so as to be short-circuited between the reference potential and the output terminal.   3. The on-resistance of each of the plurality of semiconductor switching elements that has a resistance value of 10 kΩ or more and 100 kΩ or less is used as the plurality of resistors instead of the plurality of resistors. Address decoder. A plurality of semiconductor switching elements that are on / off controlled by signal levels from input terminals connected to the address lines of the ROM, which are built-in address decoders in the ROM, and have on-resistances of 10 kΩ or more and 100 kΩ or less, respectively. An address decoder inspection device for inspecting an address decoder having an input / output connected in parallel and interposed between a reference potential and an output terminal,
A predetermined resistor for connecting the output terminal to a predetermined potential;
When the output terminal is connected to the input, a potential higher than a divided voltage of the predetermined potential by the parallel combined resistance by the plurality of resistors and the predetermined resistance when the plurality of semiconductor switching elements are all in the ON state is input to the input terminal. A voltage detector capable of detecting the input to
An inspection apparatus for an address decoder, comprising:

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