JP2006344959A - 半導体集積回路装置およびその製造方法 - Google Patents

半導体集積回路装置およびその製造方法 Download PDF

Info

Publication number
JP2006344959A
JP2006344959A JP2006156335A JP2006156335A JP2006344959A JP 2006344959 A JP2006344959 A JP 2006344959A JP 2006156335 A JP2006156335 A JP 2006156335A JP 2006156335 A JP2006156335 A JP 2006156335A JP 2006344959 A JP2006344959 A JP 2006344959A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
circuit device
semiconductor integrated
metal pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006156335A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006344959A5 (https=
Inventor
Dong-Ryul Jang
張　東烈
Soo-Cheol Lee
李　受哲
Tae-Jung Lee
李　泰政
Hyeon-Cheol Kim
▲ヒョン▼鐵 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006344959A publication Critical patent/JP2006344959A/ja
Publication of JP2006344959A5 publication Critical patent/JP2006344959A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006156335A 2005-06-08 2006-06-05 半導体集積回路装置およびその製造方法 Withdrawn JP2006344959A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050049018A KR100678631B1 (ko) 2005-06-08 2005-06-08 반도체 집적 회로 소자 및 그 제조 방법

Publications (2)

Publication Number Publication Date
JP2006344959A true JP2006344959A (ja) 2006-12-21
JP2006344959A5 JP2006344959A5 (https=) 2009-07-23

Family

ID=37572546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006156335A Withdrawn JP2006344959A (ja) 2005-06-08 2006-06-05 半導体集積回路装置およびその製造方法

Country Status (3)

Country Link
US (1) US20060284219A1 (https=)
JP (1) JP2006344959A (https=)
KR (1) KR100678631B1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100751698B1 (ko) * 2006-07-12 2007-08-23 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 구조물 및 이의 제조 방법
KR100796506B1 (ko) * 2006-12-29 2008-01-21 동부일렉트로닉스 주식회사 저유전율 층간 절연막의 형성 방법 및 그 구조
US8785997B2 (en) 2012-05-16 2014-07-22 Infineon Technologies Ag Semiconductor device including a silicate glass structure and method of manufacturing a semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162262A (en) * 1989-03-14 1992-11-10 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
JP2797994B2 (ja) * 1995-02-17 1998-09-17 ヤマハ株式会社 半導体装置
JPH0955425A (ja) * 1995-08-10 1997-02-25 Mitsubishi Electric Corp 多層Ａｌ配線構造を有する半導体装置およびその製造方法
US6242299B1 (en) * 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
JP2002064190A (ja) * 2000-08-18 2002-02-28 Mitsubishi Electric Corp 半導体装置
US6475857B1 (en) * 2001-06-21 2002-11-05 Samsung Electronics Co., Ltd. Method of making a scalable two transistor memory device
US6706594B2 (en) * 2001-07-13 2004-03-16 Micron Technology, Inc. Optimized flash memory cell
KR100457843B1 (ko) * 2002-09-18 2004-11-18 삼성전자주식회사 반도체 장치에서 콘택 형성 방법
JP4799148B2 (ja) * 2005-11-28 2011-10-26 株式会社東芝 不揮発性半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
KR100678631B1 (ko) 2007-02-05
KR20060127688A (ko) 2006-12-13
US20060284219A1 (en) 2006-12-21

Similar Documents

Publication Publication Date Title
US7898037B2 (en) Contact scheme for MOSFETs
US8058185B2 (en) Method of fabricating semiconductor integrated circuit device
US8253217B2 (en) Seal ring structure in semiconductor devices
US7651939B2 (en) Method of blocking a void during contact formation
US7842577B2 (en) Two-step STI formation process
US6498089B2 (en) Semiconductor integrated circuit device with moisture-proof ring and its manufacture method
KR100874524B1 (ko) 반도체 장치 및 그 제조 방법
US8067807B2 (en) Semiconductor integrated circuit device
US8217472B2 (en) Semiconductor device with isolation trench liner
US7741205B2 (en) Integrated circuit having a top side wafer contact and a method of manufacture therefor
US9875928B2 (en) Metal interconnect structure and method for fabricating the same
US20090121322A1 (en) Semiconductor chip and semiconductor device
US7230270B2 (en) Self-aligned double gate device and method for forming same
US11437272B2 (en) Semiconductor device and method for fabricating the same
TW202002114A (zh) 半導體裝置
KR100678631B1 (ko) 반도체 집적 회로 소자 및 그 제조 방법
JPH09312331A (ja) 半導体装置及びその製造方法
JP4533873B2 (ja) 半導体装置およびその製造方法
JP3125929B2 (ja) 半導体装置の製造方法
CN110364564B (zh) 半导体器件及其制作方法
US11456207B2 (en) Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same
KR100815798B1 (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090605

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090605

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20090818