JP2006344710A - Semiconductor light emitting element, its manufacturing method, semiconductor light emitting device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element capable of reducing light circulating in the light emitting element or leaking toward a sidewall for improving light extraction efficiency from a light extraction surface and its manufacturing method, and to provide a semiconductor light emitting device and its manufacturing method. <P>SOLUTION: In the semiconductor light emitting element made of a group III-V compound semiconductor layer, the light extraction surface 20 is formed on a (001) plane of an n-type semiconductor layer 1 for example, and inclined reflection surfaces 24 and 25 each constituted of a (111) plane and a (11-1) plane and not reaching an active layer 3 are formed on p-type semiconductor layers 4 and 5 present oppositely to the surface 20 across the active layer 3. The surfaces 24 and 25 are formed by wet etching with a low-temperature hydrochloric acid as an etchant together with element separation surfaces 21 and 22 each similarly made of a (111) plane and a (11-1) plane. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting element and a method for manufacturing the same, a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a light extraction structure.

  2. Description of the Related Art Conventionally, a compound semiconductor light emitting element formed by stacking a plurality of compound semiconductor layers on a substrate is known. For example, gallium arsenide (GaAs) -based or indium-phosphorus (InP) formed by epitaxial growth on a substrate such as a red light emitting diode or an infrared laser diode used for 1.3-1.5 μm optical communication. ) -Based III-V group compound semiconductor layers.

  In the production of these compound semiconductor light emitting devices, after a plurality of compound semiconductor layers are stacked on a substrate, each compound semiconductor layer is selectively removed by wet etching, so that the light emitting region of each light emitting device has a mesa structure. Often, a method of forming a light emitting element or separating elements between light emitting elements is used. The etchant used for etching is appropriately selected according to the constituent elements of the compound semiconductor layer to be removed.

  For example, in Patent Document 1 described later, an n-type InP buffer layer, a non-InGaAsP active layer, a p-type InP clad layer, and a p-type InGaAsP etching dummy are formed on an n-type InP substrate having a (100) plane as a main surface. A method of manufacturing a semiconductor light emitting device is shown in which a layered active layer is formed by sequentially forming layers and then performing wet etching using an etching mask made of silicon oxide to extend in a [011] direction. .

At this time, an etchant containing bromine and hydrogen bromide (HBr—Br ₂ —H ₂ O) is used, and while controlling the etching time, a p-type InGaAs etching dummy layer, a p-type InP cladding layer, a non-InGaAsP active layer, The n-type InP buffer layer and a part of the n-type InP substrate are etched to form a mesa structure including the stripe-shaped active layer.

  In Patent Document 2 described later, a DBR (Distributed Bragg Reflector) layer, an n-type AlInP lower cladding layer, an AlGaInP active layer, a p-type AlInP upper cladding layer, a p-type GaAs layer, a p-type AlGaAs window on a GaAs substrate. A method of manufacturing a semiconductor light emitting device is shown in which a layer, an insulating film, and an electrode are sequentially stacked and formed, and then device isolation is performed by wet etching using a photoresist as an etching mask.

  In this example, the p-type AlGaAs window layer is first etched using an iodine-based etchant (for example, an etchant prepared by mixing 150 g of iodine, 1500 g of ammonium iodide, 450 ml of ethanol and 3000 ml of water), and then Etching of the p-type GaAs layer using a sulfuric acid etchant (for example, a mixture of sulfuric acid, hydrogen peroxide and water mixed at a ratio of sulfuric acid: hydrogen peroxide: water = 1: 2: 50), Etching is performed on the p-type AlInP upper cladding layer using a phosphoric acid-based etchant (hot phosphoric acid at 60 ° C.).

  In Patent Document 2, a suitable mesa shape can be formed by properly using an appropriate etchant as described above, and a hydrogen chloride etchant (hydrogen chloride: acetic acid: hydrogen peroxide) can be used instead of a phosphate etchant. A mixture of hydrogen chloride, acetic acid and hydrogen peroxide mixed at a ratio of 31: 62: 7 may be used, and a hydrofluoric acid-based etchant (for example, hydrogen fluoride: water) instead of an iodine-based etchant = Mixture of hydrogen fluoride and water mixed in a ratio of 1: 4.

  In Patent Document 3 described later, an InGaAsP / InGaAsP multiple quantum well active layer, a p-type InP cladding layer, and a p-type InGaAs contact layer are sequentially stacked on an n-type InP substrate, and extend in the [011] direction. A method of manufacturing a semiconductor device is shown in which after forming a striped active layer mesa stripe by dry etching, an Fe-doped InP buried layer is formed around it and the surface thereof is planarized by wet etching.

  In this example, it is said that a mixture of hydrogen chloride and acetic acid is used as an etchant, and water or hydrogen peroxide may be contained in addition. In Patent Document 3, when such an etchant is used, the etching in the [0-11] direction of the InP buried layer occurs more rapidly than the etching in the [100] direction or the [011] direction. It is described that the surface of the buried layer can be flattened to a (100) plane.

  By the way, a light-emitting element made of a III-V group compound semiconductor such as GaAs or GaInP having P or As as a constituent element and having a zinc blende type crystal structure has a high refractive index of the material. ), The light inside the LED is often reflected to the LED side at the interface between the LED and the outside air. For this reason, the light generated in the light emitting layer often circulates inside the LED or leaks to the side wall, and it is difficult to efficiently extract the generated light from the light extraction surface to the outside of the LED. There is.

  Therefore, in Non-Patent Document 1 and Patent Document 4 to be described later, a reflection surface that diverges the path of light is formed on the light extraction surface, or, for example, a truncated pyramid-shaped embedded light reflector (on the opposite surface side of the light extraction surface ( There has been proposed an LED that improves light extraction efficiency from the light extraction surface by reducing light that circulates inside the LED or leaks to the side wall by forming BMR (buried micro-reflectors). .

  However, when the inventors tried using the above-mentioned various etchants, there was a problem that the resist deteriorated in the acetic acid-based etchant. In the etching using these etchants, the controllability is deteriorated because the etching rate is significantly different between GaInP and AlGaInP. For this reason, when the surface roughness of the light extraction surface is increased, the shape lacks uniformity. Moreover, it has been difficult to form irregularities having a certain uniformity on the opposite surface side of the light extraction surface. As a result, it was not possible to dramatically increase the light extraction efficiency.

JP-A-10-321944 (pages 4 and 5, FIG. 1-10) Japanese Patent Laid-Open No. 2003-31843 (pages 5 and 6, FIG. 1-3) JP 2002-198616 A (11th and 12th pages, FIG. 6-9) Japanese translation of PCT publication No. 2004-506331 (page 7-9, FIG. 1-3) S.Illek et al., Buried micro-reflectors boost performance of AlGaInP LEDs, Compound Semiconductor, p.39-42, (2002) (FIGS. 2, 4 and 5)

  As described above, it has been found that it is difficult to improve the light extraction efficiency of the LED by forming regular irregularities on the surface facing the light extraction surface of the LED only by selecting the etchant. In particular, for a fine compound semiconductor light emitting device such as a micro LED, it is difficult to produce surface texture and surface roughness.

  The present invention has been made in view of such a situation, and an object of the present invention is to reduce the light that circulates inside the semiconductor light emitting element or leaks to the side wall, and the light extraction efficiency from the light extraction surface. It is an object to provide a semiconductor light emitting device and a method for manufacturing the same, a semiconductor light emitting device and a method for manufacturing the same.

That is, the present invention relates to a semiconductor light emitting device comprising a III-V compound semiconductor layer,
A light extraction surface is formed on the (001) surface of the first conductivity type semiconductor layer;
An inclined reflective surface composed of a (111) surface and a (11-1) surface that does not reach the active layer is formed in the second conductive type semiconductor layer existing on the opposite side of the light extraction surface with the active layer interposed therebetween. A plurality of the semiconductor light emitting elements are formed in an array on the same substrate consisting of at least the lowermost layer of the first conductivity type semiconductor layer; The present invention relates to a semiconductor light emitting device.

  Further, in the method for manufacturing the semiconductor light emitting element or the semiconductor light emitting device, the inclined reflecting surface composed of the (111) plane and the (11-1) plane is formed by wet etching using low temperature hydrochloric acid as an etchant. The present invention relates to a method for manufacturing a semiconductor light emitting element or a semiconductor light emitting device.

  The semiconductor light emitting device of the present invention is a semiconductor light emitting device comprising a III-V group compound semiconductor layer having a zinc blende type crystal structure, and a light extraction surface is formed on the (001) plane of the first conductivity type semiconductor layer. In addition, an inclined reflecting surface composed of a (111) surface and a (11-1) surface that does not reach the active layer is formed in the second conductive type semiconductor layer existing on the opposite side of the light extraction surface with the active layer interposed therebetween. Has been. The inclined reflecting surface composed of the (111) surface and the inclined reflecting surface composed of the (11-1) surface are respectively compared with the light extraction surface which is the (001) surface, regardless of the production conditions such as the etching rate. Since it has a certain inclination (about 55 degrees), the light that circulates inside the semiconductor light emitting element or leaks to the side wall side due to the reflection by the regularly formed inclined reflecting surfaces. The light extraction efficiency from the light extraction surface can be improved.

  In the semiconductor light emitting device of the present invention, since the plurality of semiconductor light emitting elements are formed in an array on the same substrate composed of at least the lowermost layer of the first conductivity type semiconductor layer, the light extraction efficiency is improved. Using the semiconductor light emitting element, not only light sources having various shapes such as a line shape or a surface can be formed, but also a self-luminous display device can be formed.

  Further, according to the method for manufacturing the semiconductor light emitting element or the semiconductor light emitting device, the inclined reflective surface composed of the (111) plane and the (11-1) plane is formed by wet etching using low temperature hydrochloric acid as an etchant. In this manufacturing method, in etching with hydrochloric acid, etching in a direction parallel to the (111) plane and the (11-1) plane is compared with etching in a direction intersecting the (111) plane and the (11-1) plane. Since the fact that it travels much faster is used, it is possible to reliably form an inclined reflecting surface composed of the (111) plane and the (11-1) plane. In addition, since the etching reaction is performed at a low temperature, the reaction rate is slow, the etching can be performed over a long time at a small etching rate, and the removal amount of each semiconductor layer by etching is controlled easily and satisfactorily. be able to.

  The zinc blende crystal structure belongs to a cubic system, and the a-axis direction, b-axis direction, and c-axis direction of the crystal orientation are equivalent to each other. There are no restrictions on the exchange of directions. For example, the present invention includes the case where the light extraction surface is formed not on the (001) plane but on the (100) plane or the (010) plane.

  In the semiconductor light emitting element or the semiconductor light emitting device of the present invention, the inclined reflective surface composed of the (111) plane and the inclined reflective surface composed of the (11-1) plane have a cross-section V on the surface of the second conductivity type semiconductor layer. It is preferable to form a letter-shaped groove. As described in detail in the first embodiment, the inclined reflection surface composed of the (111) plane whose surface is masked intersects with the inclined reflection surface composed of the (11-1) surface, and the groove having a V-shaped cross section. After that, the subsequent etching is much slower, and these inclined reflecting surfaces work close to an effective etching stop surface. For this reason, the amount of side etching is reduced, and the depth of the groove is almost automatically determined by the mask interval. Therefore, even if the second conductivity type semiconductor layer is a multilayer film having a different etching rate, Alternatively, the groove having a predetermined depth can be formed with good controllability without controlling the etching rate. In addition, the groove can be formed at the same time as the deep element isolation groove for element isolation without causing excessive etching.

  At this time, it is preferable that the grooves extend in a linear pattern along the [1-10] direction, and a plurality of the linear patterns are arranged in parallel. By adopting such a shape, the inclined reflection surface composed of the (111) plane and the (11-1) plane can be effectively arranged in a wide region on the second conductive semiconductor layer. . In addition, current diffusion in the second conductive semiconductor layer is suppressed by the groove, and current is concentrated in the second conductive semiconductor layer sandwiched between the grooves, so that current density is improved and luminous efficiency is increased.

  Further, it is preferable that an electrode is provided on a part of the second conductivity type semiconductor layer, and at least a part of the groove is present in a region where the electrode is not provided. As an electrode capable of realizing adhesion and ohmic contact with the underlying semiconductor layer, for example, when an electrode having a three-layer structure in which titanium, platinum and gold are stacked is provided, the titanium layer absorbs part of the emitted light. Therefore, it is preferable that the electrode is provided not on the entire surface of the second conductivity type semiconductor layer but on a part thereof. In this case, it is preferable to provide the groove also in a region where the electrode is not provided so that light propagating through the region is reflected on the light extraction surface.

  The second conductive semiconductor layer preferably contains phosphorus as a constituent element. The III-V compound semiconductor layer containing phosphorus is etched in a direction parallel to the (111) plane and the (11-1) plane in the etching using hydrochloric acid as an etchant, and the (111) plane and (11-1) It proceeds much faster than etching in the direction that intersects the surface. Therefore, the present invention can be applied most effectively.

  Further, at least part of the second conductivity type semiconductor layer, the active layer, and the first conductivity type semiconductor layer by an inclined surface that is a (111) plane and / or an inclined surface that is a (11-1) plane. Are preferably formed in a mesa shape. The inclined surface formed of the (111) plane and / or the inclined surface formed of the (11-1) plane has the above-described characteristics, that is, even when the inclined surface is formed over a plurality of semiconductor layers having different etching rates. It is formed with a certain inclination (about 55 degrees) with respect to the light extraction surface which is the (001) plane, and the side etching is performed in a direction intersecting with the inclined surface, so that the amount of side etching is reduced. ing. Therefore, the inclined surface is suitable as a side surface when forming the second conductive semiconductor layer, the active layer, and at least a part of the first conductive semiconductor layer in a mesa shape. Further, the inclined surface can be used as a part of the inclined reflecting surface. The inclined surface can be formed simultaneously with the inclined reflecting surface, and the manufacturing process can be simplified.

  At this time, in order to form the inclined surface in at least a part of the first conductive semiconductor layer, the first conductive semiconductor layer contains phosphorus as a constituent element, as in the second conductive semiconductor layer. It is good to be.

  In the semiconductor light emitting device of the present invention, it is preferable that the semiconductor light emitting elements are separated from each other by the inclined surface. This semiconductor light emitting device has an advantage that the process can be simplified if the inclined surface forming the mesa of the semiconductor light emitting element is used as the element isolation surface. In addition, damage to the semiconductor light emitting element can be reduced as compared with applying physical external force such as dicing or cleavage, and the deterioration of the characteristics of the semiconductor light emitting element can be prevented.

  Moreover, it is preferable that a light reflecting means is provided on the second conductive semiconductor layer. The light reflecting means is made of a light reflecting metal deposited on the second conductive type semiconductor layer, or a concave mirror spaced apart above the second conductive type semiconductor layer. It is good. An application as an omnidirectional reflector (ODR) is also possible by molding a low refractive index material into the groove having a V-shaped cross section and depositing a light reflecting metal thereon.

  In the method for manufacturing a semiconductor light emitting element or semiconductor light emitting device of the present invention, the second conductive semiconductor layer, the active layer, and at least a part of the second conductive semiconductor layer are made to be low temperature hydrochloric acid as an etchant. Etching by wet etching is preferable to form into a mesa shape having an inclined surface composed of (111) plane and / or (11-1) plane as a side surface. The mesa shape may be formed simultaneously with the inclined reflecting surface. As described above, the inclined surface formed of the (111) plane and / or the inclined surface formed of the (11-1) plane is suitable as the side surface of the mesa and can be formed simultaneously with the inclined reflecting surface. The manufacturing process can be simplified.

  Next, a preferred embodiment of the present invention will be described specifically and in detail with reference to the drawings.

Embodiment 1
In the first embodiment, a micro light emitting diode (hereinafter abbreviated as a micro LED) is given as an example related to the semiconductor light emitting device described in claims 1 to 9 and the method for manufacturing the semiconductor light emitting device described in claims 15 to 17. And the manufacturing method thereof.

  FIG. 1 is a plan view (A) of a micro LED 10 based on Embodiment 1, and a cross-sectional view (B) at the position indicated by the line 1B-1B in the plan view (A). However, the cross-sectional view (B) is slightly enlarged as compared with the plan view (A). The micro LED 10 has a substantially rectangular planar shape, and is formed in a mesa shape having a substantially trapezoidal cross section taken along line 1B-1B.

  An example of the micro LED 10 is a red light emitting diode, and as shown in the enlarged view of FIG. 1B, an n-type gallium arsenide (GaAs) layer 1, n-type aluminum gallium indium phosphorus (AlGaInP) clad layer 2, multiple thin aluminum gallium indium phosphorus (AlGaInP) layers and gallium indium phosphide (GaInP) layers alternately stacked to form multiple quantum wells (MQW: Multi Quantum Well) active layer 3, p-type aluminum gallium indium phosphorus (AlGaInP) cladding layer 4, p-type gallium indium phosphorus (GaInP) buffer layer 5, and p-type gallium Arsenic (GaAs) contact layer 6 is laminated. The semiconductor layers 1 and 2 correspond to the first conductivity type semiconductor layer, and the semiconductor layers 4 to 6 correspond to the second conductivity type semiconductor layer. The semiconductor layer 5 is a three-element material semiconductor layer that is sandwiched as a buffer layer when the stacked semiconductor layer is transferred from the four-element material semiconductor layer 4 to the two-element material semiconductor layer 6.

  The micro LED 10 has, for example, a long side of 25 μm, a short side of 20 μm, a thickness (height) of 2.5 μm, and the total thickness of the p-type semiconductor layers 4 and 5 is about 1 μm.

  In this embodiment, first, each semiconductor constituent material layer corresponding to the semiconductor layers 1 to 6 is stacked on the substrate by an epitaxial growth method using a metal organic chemical vapor deposition method (MOCVD method) or the like, Next, by selectively removing each semiconductor constituent material layer by wet etching and patterning, a large number of micro LEDs 10 having semiconductor layers 1 to 6 are formed on the substrate, and element separation is performed between the micro LEDs 10. To do.

  In FIG. 1A, the directions indicated by the arrows a and b are the a-axis direction and the b-axis direction of the crystal orientation, and the direction rising vertically from the paper surface is the c-axis direction of the crystal orientation. As shown in FIG. 1B, the micro LED 10 has a (001) plane as a main surface, a light extraction surface 20 is formed on the (001) plane, and light is extracted mainly in the [00-1] direction. As shown in FIG. 1A, the long side of the micro LED 10 is formed in the [1-10] direction.

  Of the semiconductor layers constituting the micro LED 10, the semiconductor layers 2 to 5 contain phosphorus. When the constituent material layers of the semiconductor layers 2 to 5 are wet-etched using hydrochloric acid as an etchant, the (111) plane and the (11 -1) Etching in a direction parallel to the plane proceeds much faster than etching in a direction intersecting the (111) plane and the (11-1) plane. Therefore, when a rectangular resist mask having a long side in the [1-10] direction is provided, and the constituent material layers of the semiconductor layers 2 to 5 are wet-etched using hydrochloric acid as an etchant, the (111) plane and ( 11-1) Mesa-shaped semiconductor layers 2 to 5 having inclined surfaces (hereinafter referred to as element isolation surfaces 21 and 22 respectively) are formed. The element isolation surfaces 21 and 22 composed of the (111) plane and the (11-1) plane are formed with a certain inclination (about 55 degrees) with respect to the light extraction surface 20 that is the (001) plane regardless of the etching conditions. The

  At this time, if an elongated rectangular opening having a long side in the [1-10] direction is provided in the resist mask, the semiconductor constituent material layer below the opening is also subjected to anisotropic etching similar to the above, A V-shaped groove 26 is formed below the opening, with the (111) plane and the (11-1) plane being inclined surfaces (hereinafter, these surfaces are referred to as inclined reflecting surfaces 24 and 25, respectively). In the V-shaped groove 26, since the short side of the rectangular opening is short, the (111) plane and the (11-1) plane grown from the end portions of the resist mask adjacent to the left and right long sides of the opening are active. Intersection before reaching layer 3 and no further etching under appropriate etching conditions. Similar to the element isolation surfaces 21 and 22, the inclined reflecting surfaces 24 and 25 forming the inclined wall surface of the V-shaped groove 26 have a certain inclination (about 55) with respect to the light extraction surface 20 which is the (001) surface, regardless of the etching conditions. Degree).

  The opening is preferably in the form of a single long stripe. If the opening is divided into a plurality of rectangles, pattern breakage is likely to occur due to etching from the end.

  A feature of the micro LED 10 of the present embodiment is that a V-shaped groove 26 having inclined reflecting surfaces 24 and 25 is formed on the opposite surface side of the light extraction surface 20, and the regularly formed inclined reflecting surfaces 24 and 25 are provided. The reflection by the element isolation surfaces 21 and 22 reduces the light that circulates inside the LED 10 or leaks to the side wall, and improves the light extraction efficiency from the light extraction surface 20.

  On the p-type semiconductor layers 4 to 6, for example, a p-electrode 7 having a three-layer structure of Ti / Pt / Au in which titanium, platinum, and gold are stacked in this order is formed. Adhesion and ohmic contact with the underlying semiconductor layer can be realized by forming the electrode in such a laminated structure.

  However, since the titanium layer absorbs part of the light emitted from the micro LED 10, the p-electrode 7 is not provided on the entire surface of the p-type semiconductor layers 4 to 6, but the semiconductor layers 4 to 6 as shown in FIG. It is good to provide in the upper part. Light that is about to leak from the region where the p-electrode 7 is not formed is preferably reflected by the inclined reflecting surfaces 24 and 25 or another light reflecting means to improve the total amount of emitted light.

  2 and 3 are a plan view (A) and a cross-sectional view (B) showing a flow of manufacturing the micro LED 10 based on the first embodiment. Note that these cross-sectional views are cross-sectional views at the same position as the cross-sectional view of FIG. 1B, and are slightly enlarged as compared with the plan view (A), as in FIG. 1B.

  First, as shown in FIG. 2A, an n-type gallium arsenide (GaAs) constituent material layer 11, an n-type aluminum gallium indium phosphide (AlGaInP) are formed on a substrate by an epitaxial growth method using an MOCVD method or the like. ) Constituent material layer 12, active layer constituent material layer 13 in which a number of thin aluminum gallium indium phosphide (AlGaInP) layers and gallium indium phosphide (GaInP) layers are alternately stacked, p-type aluminum gallium gallium The indium phosphorus (AlGaInP) constituent material layer 14, the p-type gallium indium phosphorus (GaInP) constituent material layer 15, and the p-type gallium arsenide (GaAs) constituent material layer 16 are stacked.

  A resist mask 51 corresponding to the shape of the micro LED 10 to be formed is formed thereon by patterning by photolithography. At this time, the resist mask 51 is formed so that the direction of the long side of the micro LED 10 is the [1-10] direction. The resist mask 51 has a plurality of elongated rectangular openings 52 corresponding to the V-shaped grooves 26 formed in the p-type semiconductor layers 4 and 5 of the micro LED 10, and the long side is in the [1-10] direction. To form.

  Subsequently, the semiconductor constituent material layers 12 to 16 are selectively removed by wet etching and patterned, thereby forming a large number of micro LEDs 10 having the semiconductor layers 2 to 6 and element separation between the micro LEDs 10. The processing in the steps detailed below is summarized as follows.

  First, for example, a phosphoric acid mixed solution in which phosphoric acid, hydrogen peroxide water, and water are mixed at a volume ratio of 6: 2: 100 is prepared as an etchant, and the semiconductor constituent material layers 11 to 16 and the resist mask 51 are formed. The obtained substrate is immersed in this etchant for about 90 seconds. Thus, as shown in FIG. 2B, the p-type gallium arsenide constituting material layer 16 at the position corresponding to the opening 52 formed in the resist mask 51 is removed by etching, and the p-type gallium arsenide contact layer 6 is formed. . Thereafter, the surface is washed with running water and then blown with nitrogen gas for about 2 minutes to dry.

  Next, for example, an etching solution prepared by cooling hydrochloric acid having a concentration of 35% by mass or more to −10 ° C. or less is prepared as an etchant. The hydrochloric acid may contain a small amount of other etchant such as phosphoric acid within a range not to impair the etching anisotropy described later. The substrate on which the semiconductor constituent material layers 11 to 15, the p-type gallium arsenide contact layer 6 and the resist mask 51 are formed is immersed in this etchant for about 120 seconds, and then the surface is washed with running water, followed by nitrogen gas for about 2 minutes. Blow to dry. Then, the substrate is again immersed in this etchant for about 180 seconds, and then the surface is washed with running water and then blown with nitrogen gas for about 2 minutes to dry. Strictly speaking, this etching is performed using the p-type gallium arsenide contact layer 6 formed under the resist mask 51 as a substantial etching mask, but the resist mask 51 and the p-type gallium arsenide contact layer 6 are particularly used. When there is no need to distinguish between them, it is abbreviated as “etching using the resist mask 51 as a mask”.

  In this etching with hydrochloric acid, since the etching reaction is performed at a low temperature, the reaction rate is slow, and etching can be performed over a long time at a low etching rate, and the amount of each semiconductor layer removed by etching can be reduced. It becomes easy to control well. It is not necessary to perform operations such as swinging the substrate in the etchant during etching.

  In addition, bubbles that appear to be hydrogen due to the etching reaction may adhere to the etching surface. If the etching reaction is continued with this being left as it is, the etching reaction does not proceed in the region where the bubbles are attached, and etching unevenness such as the generation of etching residues may occur, resulting in disturbance of the surface. As a countermeasure, the etching is performed in two steps, the substrate 1 is lifted from the etchant between the first etching and the second etching, washed with running water, and the bubbles are removed. As a result, even when bubbles are generated by the etching reaction, it is possible to suppress the occurrence of etching unevenness due to the influence of the bubbles and form a uniform etching surface.

  As described above, in the semiconductor constituent material layers 12 to 15 containing phosphorus, when etching is performed using hydrochloric acid as an etchant, etching in a direction parallel to the (111) plane and the (11-1) plane is ( It proceeds much faster than etching in the direction that intersects the (111) plane and the (11-1) plane. For this reason, when the anisotropic etching of the semiconductor constituent material layers 12 to 15 is performed using the rectangular resist mask 51 whose long side is formed in the [1-10] direction, the (111) plane and the (11−) plane are formed. 1) Etched surfaces are formed in the surface direction, and finally mesa-shaped semiconductor layers 2 to 5 having these surfaces as inclined surfaces (element isolation surfaces 21 and 22) are formed.

  Etching also proceeds from a plurality of elongated rectangular openings 52 provided in the resist mask 51, and anisotropic etching similar to the above is performed on the semiconductor constituent material layer below the openings 52. The V-shaped groove 26 having the (111) plane and the (11-1) plane as inclined surfaces (inclined reflecting surfaces 24 and 25) is formed.

  This anisotropic etching process will be described in more detail as follows.

  Etching of the semiconductor constituent material layers 12 to 15 starts from the surface of the p-type gallium indium phosphorus constituent material layer 15 which is the uppermost layer. At this time, all the particles forming the surface of the p-type gallium-indium-phosphorus constituent material layer 15 not covered with the resist mask 51 and the p-type gallium arsenide contact layer 6 can be the starting point of etching. Then, the subsequent etching mainly proceeds in the (111) plane or (11-1) plane direction.

  For this reason, in the region not covered with the resist mask 51, the fine (111) plane or the (11-1) plane, or the fine plane having these as an inclined plane, in the entire etching process immediately after the start of etching. An infinite number of V-shaped grooves are formed. However, since the upper portions of these inclined surfaces are not covered with the resist mask 51, the particles constituting these inclined surfaces are soon removed by rapid etching that proceeds in the (111) plane direction or the (11-1) plane direction. These inclined surfaces are not preserved for a long time. As described above, the etching as a whole proceeds downward ([00-1] direction) through the semiconductor constituent material layers 11 to 15 while repeating generation and disappearance of the fine (111) plane and (11-1) plane. As a result, the element isolation groove 23 is formed. Since the n-type gallium arsenide constituent material layer 11 does not react with the etchant made of hydrochloric acid, the n-type gallium arsenide constituent material layer 11 functions as an etching stop layer, and the downward etching stops when it reaches the surface of the n-type gallium arsenide constituent material layer 11.

  When etching proceeds downward in the region not covered with the resist mask 51 as described above, a p-type gallium arsenide contact which is a substantial mask is formed in the vicinity of the boundary with the region covered with the resist mask 51. The etched surface reaches the (111) plane or the (11-1) plane whose upper part is covered with the layer 6. Since these (111) and (11-1) planes are covered with the upper part, fast etching that proceeds in the (111) plane direction or the (11-1) plane direction is impossible, and (111) Etching in the direction intersecting the surface or the (11-1) surface is slow and is difficult to etch. On the other hand, these particles on the etchant side of the (111) plane and the (11-1) plane are immediately removed by fast etching that proceeds in the (111) plane direction or the (11-1) plane direction. Therefore, these (111) plane and (11-1) plane are effective etching stop planes in the lateral direction. As a result, a mesa-shaped semiconductor whose uppermost portion is covered with the p-type gallium arsenide contact layer 6 in the vicinity of the boundary and whose (111) plane and (11-1) plane are inclined planes (element isolation planes 21 and 22). Layers 2-5 are formed.

  Although the progress of etching in the direction intersecting with the (111) plane and the (11-1) plane forming the element isolation surfaces 21 and 22 is slow, it is not impossible. When such etching occurs and some of the particles constituting the (111) plane or the (11-1) plane are removed, the (111) plane direction or (11-1) ) Fast etching progresses in the plane direction, and the (111) plane or the entire (11-1) plane where the missing portion is generated is quickly removed. The (111) plane or (11-1) plane of the layer next to the (111) plane or (11-1) plane becomes a new inclined plane (element isolation plane 21 or 22) of the mesa structure. In this way, the lateral etching gradually proceeds.

  Thus, utilizing the fact that the etching rate varies depending on the plane orientation, the shape of the mesa composed of the semiconductor layers 2 to 5 is etched into a shape conforming to the plane orientation. That is, after the element isolation is completed, inclined surfaces (element isolation surfaces 21 and 22) composed of the (111) plane and the (11-1) plane are formed on the long side of the micro LED 10. This inclined surface is not only formed with a certain inclination (about 55 degrees) with respect to the light extraction surface 20 which is the (001) plane, but is formed as a flat surface without any disturbance such as a missing portion, regardless of the etching conditions. Is done. This is particularly effective when the element isolation surfaces 21 and 22 are formed across a plurality of semiconductor layers having different etching rates.

  On the other hand, on the short side of the resist mask 51, even if it is a crystallographically equivalent plane, the ratio of atoms constituting the plane differs depending on the orientation in the mixed crystal. 1) An etching stop surface corresponding to the surface is not formed, etching proceeds to the short side position of the resist mask 51, and an etching surface perpendicular to the light extraction surface 20 is formed.

  On the other hand, etching also proceeds from a plurality of elongated rectangular openings 52 provided in the resist mask 51, and the semiconductor constituent material layer below the openings 52 also undergoes anisotropic etching similar to the above. As a result, the inclined reflecting surface 24 composed of a (111) surface whose surface is covered with a resist mask 51 (strictly, the p-type gallium arsenide contact layer 6 below the left and right long sides of the opening 52) and An inclined reflection surface 25 made of a (11-1) surface is formed as an effective etching stop surface, and a V-shaped groove 26 having these as inclined surfaces is formed below the opening 52.

  As described above, since the etching in the direction intersecting the (111) plane or the (11-1) plane is slow, the V-shaped groove 26 is less likely to be etched. Therefore, the amount of side etching is reduced, and the depth of the V-shaped groove 26 is almost automatically determined by the length of the short side of the resist mask 51. Therefore, the V-shaped groove 26 is formed across the p-type aluminum gallium indium phosphorus (AlGaInP) constituent material layer 14 and the p-type gallium indium phosphorus (GaInP) constituent material layer 15 having different etching rates. Even in this case, the V-shaped groove 26 having a predetermined depth can be formed with good controllability without controlling the etching rate. Further, even if formed at the same time as the deep element isolation groove 23 for element isolation, the V-shaped groove 26 can be formed without causing excessive etching, so that the number of manufacturing steps can be reduced.

  The formation mechanism of the element isolation groove 23 and the V-shaped groove 26 is the same, but the main purpose of the element isolation groove 23 is to isolate the elements between the micro LEDs 10. The (111) plane and the (11-1) plane of the separation groove 23 are prevented from intersecting before reaching the surface of the n-type gallium arsenide constituting material layer 11. On the other hand, the V-shaped groove 26 has an opening portion so that the V-shaped groove 26 active layer 3 is not damaged and the electrode provided in the V-shaped groove 26 is not short-circuited with the n-type semiconductor layers 1 and 2. The length of the short side of 52 is made sufficiently short, and the (111) plane and the (11-1) plane grown from the end portions of the resist mask 51 adjacent to the left and right long sides of the opening 52 are the active layer 3. Make sure to cross before reaching.

  The progress of etching in the direction intersecting the inclined reflecting surfaces 24 and 25 forming the inclined surface of the V-shaped groove 26 is slow, but this is not impossible. When such etching occurs and some of the particles constituting the (111) plane or the (11-1) plane are removed, the (111) plane direction or (11-1) ) Fast etching progresses in the plane direction, and the (111) plane or the entire (11-1) plane where the missing portion is generated is quickly removed. Then, the (111) plane or the (11-1) plane of the layer next to the (111) plane or the (11-1) plane becomes the new inclined reflecting surface 24 or 25 of the V-shaped groove 26. In this way, the etching for enlarging the V-shaped groove 26 gradually proceeds, but the inclined reflecting surfaces 24 and 25 forming the inclined surface of the V-shaped groove 26 take out light that is a (001) plane regardless of the etching conditions. It is formed as a flat surface having a constant inclination (about 55 degrees) with respect to the surface 20 and having no disturbance such as a missing portion.

  FIG. 4 shows a scanning electron microscope (SEM) showing a V-shaped groove 26 having a groove width of 1.5 μm and a depth of 1.1 μm formed by etching an aluminum, gallium, indium, and phosphorus (AlGaInP) layer as described above. ) Is an SEM image observed. 4A shows an image after etching for 60 seconds, and FIG. 4B shows an image after etching for 120 seconds. Comparing the two, according to the etching method of the present embodiment, after the V-shaped groove 26 is formed, the groove and depth of the V-shaped groove 26 do not change even if the etching time is added, which is useless. It can be seen that no etching occurs.

  As described above, the element isolation surfaces 21 and 22 and the inclined reflection surfaces 24 and 25 are formed. Thereafter, the p-electrode 7 is formed in a predetermined region on the p-type semiconductor layers 4 to 6 by a lift-off method.

  First, as shown in FIG. 3D, patterning is performed by photolithography to form a resist mask 53 having an opening in the p electrode formation region 54.

  Next, as shown in FIG. 3 (5), an electrode material layer 17 having a three-layer structure of Ti / Pt / Au in which, for example, titanium, platinum and gold are laminated in this order on the entire surface by vacuum deposition or sputtering. Form. Adhesion and ohmic contact with the underlying semiconductor layer can be realized by forming the electrode in such a laminated structure.

  Next, as shown in FIG. 3 (6), by removing the photoresist 53, the electrode material layer 17 deposited thereon is removed, leaving only the electrode material layer 17 that becomes the p-electrode 7. Subsequently, the unnecessary p-type gallium arsenide contact layer 6 around the p-electrode 7 is removed.

  Thereafter, the semiconductor layers 2 to 6 formed on the substrate are separated from each other by cutting the substrate, and the post-process such as the formation of the n-electrode and the formation of the protective film is performed to manufacture the individualized micro LED 10. To do. On the other hand, in the second embodiment, each of the semiconductor layers 2 to 6 formed on the substrate is not separated into individual pieces, and includes a plurality of micro LEDs 10 having at least an n-type gallium arsenide (GaAs) constituent material layer 11 as a common substrate. A semiconductor light emitting device is formed.

  FIG. 5 is a cross-sectional view for explaining that the light extraction efficiency from the light extraction surface 20 is improved in the micro LED 10 based on the first embodiment. However, the hatching of the semiconductor layers 2, 4 and 5 is omitted so that the path of light can be easily understood.

FIG. 5 shows the paths of light d and e emitted upward from the light emitting point L ₁ and light f and g emitted downward from the light emitting point L ₂ as an example. If the opposing surface of the light extraction surface 20 is a plane parallel to the light extraction surface 20, these lights d to g proceed in the lateral direction while repeating reflection between the two, and circulate inside the micro LED 10, The possibility of being extracted from the light extraction surface 20 is low only by leaking to the side wall side. On the other hand, in the present embodiment, a large number of inclined reflecting surfaces 24 and 25 intersecting the light extraction surface 20 at a certain angle (about 55 degrees) are formed on the opposite surface side of the light extraction surface 20. The path of d to g is largely redirected by reflection from the inclined reflecting surfaces 24 and 25, and the probability of being extracted from the light extraction surface 20 is greatly enhanced.

  At this time, as can be seen from FIG. 5, the element separation surfaces 21 and 22 that form the inclined surface of the mesa of the micro LED 10 also function as a part of the reflecting surface, and the path of light traveling in the lateral direction inside the micro LED 10 is a light extraction surface. It has the effect of improving the efficiency of extracting light from the light extraction surface 20 by reflecting in the direction of 20.

  FIG. 6 is a cross-sectional view for comparing and explaining the result of calculating the light extraction efficiency by the ray tracing method in the micro LED based on the first embodiment and the comparative example. The position of the cross section is the same as the position of the cross section in FIG.

  FIG. 6A shows the case of Comparative Example 1 in which the surface facing the light extraction surface 20 is a plane parallel to the light extraction surface 20 and the p-type gallium arsenide contact layer 6 is completely left below the p-electrode 7. The light extraction efficiency of this micro LED is 11.0%.

  In FIG. 6B, the opposite surface of the light extraction surface 20 is a plane parallel to the light extraction surface 20, but the p-type gallium arsenide contact layer 6 is formed only on a part of the lower portion of the p electrode 7 corresponding to the micro LED 10. In the case of Comparative Example 2 in which the line and space type is left, the light extraction efficiency of this micro LED is 17.6%. Compared with the light extraction efficiency in Comparative Example 1, the light extraction efficiency is improved by 6.6% (corresponding to 60% of the light extraction efficiency of Comparative Example 2), and the presence of the p-type gallium arsenide contact layer 6 is light. It turns out that it becomes the obstacle of the improvement of extraction efficiency.

  FIG. 6C shows the case of the micro LED 10 according to the present embodiment in which the inclined reflection surface is provided facing the light extraction surface 20, and the light extraction efficiency in the micro LED 10 is 22.8%. Compared with the light extraction efficiency in Comparative Example 2, it can be seen that the light extraction efficiency is improved by 5.2% (corresponding to 30% of the light extraction efficiency of Comparative Example 2). This is an effect of providing the inclined reflection surfaces 24 and 25 facing the light extraction surface 20 with the active layer 3 interposed between the p-type semiconductor layers 4 and 5.

  FIG. 6D shows a modification of the micro LED 10 in which the p-type gallium arsenide contact layer 6 is removed from the micro LED 10, and the light extraction efficiency of this micro LED is 40.6%. Compared to the light extraction efficiency of the micro LED 10 shown in FIG. 6D, it can be seen that there is an improvement of 17.8%. This indicates that in the micro LED 10 provided with the inclined reflecting surfaces 24 and 25, the effect of removing the p-type gallium arsenide contact layer 6 is extremely large in improving the light extraction efficiency.

  6 (E) to 6 (G) show other modified examples of the micro LED 10 based on the present embodiment. In the micro LEDs shown in FIGS. 6E and 6F, a metal reflecting mirror 27 is provided on the back side of the micro LED shown in FIGS. Are 28.5% and 51.9%, respectively. The light extraction efficiency of the micro LED shown in FIG. 6E is 5.7% higher than that of the micro LED shown in FIG. 6C, whereas the micro LED shown in FIG. The light extraction efficiency is improved by 11.3% as compared with the micro LED of FIG. The micro LED shown in FIG. 6D is more effective in providing the metal reflector 27 than the micro LED shown in FIG. 6D because the p-type gallium arsenide contact layer 6 is omitted and light extraction is performed. This is because more light leaks to the back side as a result of improved efficiency.

  The micro LED shown in FIG. 6 (G) is an example in which a V-shaped groove 28 is also formed on the light extraction surface 20 of the micro LED shown in FIG. The light extraction efficiency is 54.6%. Compared with the micro LED of FIG. 6F, the light extraction efficiency is improved by 2.7% by the V-shaped groove 28 in the micro LED of FIG. 6G.

  As described above, the light extraction efficiency can be significantly improved by combining various improvement measures.

  In the micro LED 10, the V-shaped groove 26 extends in a linear pattern along the [1-10] direction, and a plurality of the V-shaped grooves 26 are arranged in parallel. By adopting such a shape, the inclined reflecting surface 24 made of the (111) plane and the inclined reflecting surface 25 made of the (11-1) surface are effectively provided in a wide area on the p-type semiconductor layers 4 and 5. Can be arranged. The V-shaped groove 26 not only reflects light but also suppresses current diffusion in the p-type semiconductor layers 5 and 4, concentrates current in a limited region of the active layer 3, and current density in the active layer 3. As a result, the luminous efficiency is increased. Hereinafter, this operation will be described.

  FIG. 7A shows the relationship between the current density and the current diffusion distance in the p-type semiconductor layers 5 and 4 in the comparative micro LED having the same material layer as the micro LED 10 but without the V-shaped groove 26. It is a graph which shows the result calculated | required by calculation, FIG.7 (b) is sectional drawing explaining a current diffusion distance. However, the hatching of the semiconductor layers 4 and 5 is omitted so that the path of light can be easily understood. As shown in FIG. 7B, the current diffusion distance in the p-type semiconductor layers 5 and 4 is the position of the end of the electrode for injecting current into the p-type semiconductor layers 5 and 4 and the active layer 3. This is a shift in the position of the end of the current spread, and is the distance that the current injected from the electrode spreads in the horizontal direction in the figure while flowing through the p-type semiconductor layers 5 and 4 in the downward direction in the figure. It is.

According to the graph of FIG. 7A, for example, at 44 (A / cm ² ) which is the rated current density of the micro LED 10, the current diffusion distance is 3.7 μm. This is because when the current density is 44 (A / cm ² ), the current injected from the electrode flows through the p-type semiconductor layers 5 and 4 to a position away from the end of the electrode by 3.7 μm. It shows spreading in the horizontal direction of the figure.

  FIG. 8 is a cross-sectional view for explaining the current confinement action by the V-shaped groove 26, and FIG. 8B is an enlarged cross-sectional view of a portion surrounded by a dotted line in FIG. However, the hatching of the semiconductor layers 4 and 5 is omitted so that the path of light can be easily understood. Since current cannot flow through the region where the V-shaped groove 26 is formed, the current diffusion is prevented by the presence of the V-shaped groove 26, as is apparent from a comparison between FIG. 8B and FIG. It is suppressed. For example, if the current spreads to a position in contact with the side wall of the V-shaped groove 26, the current diffusion distance is substantially equal to the width of the side wall portion of the V-shaped groove 26 and is approximately the same as the depth of the V-shaped groove 26 of about 1 μm. Yes, it is much smaller than the comparative example of 3.7 μm. In this way, the current spread is suppressed by the V-shaped mesa groove 26 and the current is confined in a limited region of the active layer 3, so that the current flows in a region where non-radiative recombination is dominant, such as an element end face. Spreading can be prevented, and as a result, the luminous efficiency can be increased.

Embodiment 2
In the second embodiment, as an example relating to the semiconductor light-emitting device described in claims 10 to 14 and the method for manufacturing the semiconductor light-emitting device described in claims 15 to 17, a semiconductor light-emitting device including a plurality of micro light-emitting diodes is provided. The manufacturing method thereof will be described.

  In this semiconductor light emitting device 40, a plurality of micro light emitting diodes 30 are formed in an array on the same substrate composed of at least an n-type gallium arsenide (GaAs) layer 1, and have various shapes such as a linear shape or a surface. In addition to forming a light source, a self-luminous display device can be formed.

  FIG. 9 is a cross-sectional view showing a mounting state of micro LED 30 in semiconductor light emitting device 40 based on the second embodiment. The position of the cross section is the same as the cross section position of FIG.

  As shown in FIG. 9, in the semiconductor light emitting device 40, a concave portion is formed in a transparent electrode 31 made of ITO (Indium Tin Oxide) or the like, and two layers of AuGe / Au in which, for example, gold germanium and gold are laminated in the concave portion. After the n-electrode 32 having the structure is embedded, the surface is planarized by a CMP method (chemical mechanical polishing method) or the like. A large number of micro light emitting diodes 30 having the same layer configuration as the micro LED 10 described in the first embodiment are formed on the substrate made of at least the n-type gallium arsenide (GaAs) layer 1. An array is formed. The method of manufacturing the array of micro light emitting diodes 30 is as mentioned in the description of the method of manufacturing the micro light emitting diode 10 in the first embodiment.

Compared with the micro LED 10, the micro LED 30 constituting the semiconductor light emitting device 40 is further provided with means for increasing the amount of emitted light. Of the upper surface of the p-type semiconductor layer 5 (or 4) of the micro LED 30, in a region where the p-electrode 7 is not formed, a low-refractive index film 33 made of a low-refractive index material such as silicon oxide SiO ₂ is formed into a V-shaped groove. 26, a light reflecting metal 34 made of silver Ag or the like is provided as the light reflecting means.

  The micro LED 30 provided with the light reflecting metal 34 is sealed with a protective mold resin 33 made of a silicone resin or the like except for the n-type gallium arsenide (GaAs) layer 1, and penetrates the mold resin 33 to form the p electrode 7. A lead electrode 36 is provided for connection to the. And in order to reflect the light leaked behind the micro LED 10 forward, the concave mirror 37 having a large curvature radius common to the plurality of micro LEDs 30 is separated from the plurality of micro LEDs 30 as another light reflecting means. Is provided.

  FIG. 10 is a plan view showing a state of the micro LED 30 during the manufacturing process of the semiconductor light emitting device 40. FIG. 10A shows a state in which a light reflecting metal 34 made of silver Ag or the like is formed on the p-type semiconductor layer 5 (or 4) of the micro LED 30 by vapor deposition or the like. FIG. 10B shows a state in which the micro LED 30 shown in FIG. 10A is sealed with a protective molding resin 33 and an opening 38 for forming the extraction electrode 36 is formed.

It is also possible to apply as an omni-directional reflector (ODR) by molding a low refractive index material into the groove having a V-shaped cross section and depositing a light reflecting metal thereon. LEDs with omnidirectional reflectors can improve light extraction efficiency without depending on direction (T. Gessmann, EF Schubert, JW Graff, K. Streubel and C. Karnutsch, Omnidirectional Reflective Contacts for Light- Emitting Diodes, IEEE Electron Device Letters, 24, 683-685 (2003), Jong Kyu Kim, Thomas Gessmann, Hong Luo and E. Fred Schubert, GaInN light-emitting diodes with RuO ₂ / SiO ₂ / Ag omni-directional reflector, APPLIED PHYSICS LETTERS, 84, 4508-4510 (2004)).

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  The semiconductor light emitting device and the method for manufacturing the same according to the present invention can contribute to an improvement in the amount of light emitted from a semiconductor light emitting device such as a micro light emitting diode. A plurality of micro light-emitting diodes are formed in an array on the same substrate, so that a light source having various shapes such as a line shape or a surface can be formed, and a self-luminous display device can also be provided. The present invention can be applied to a semiconductor light emitting device that can be used and a manufacturing method thereof, and can contribute to an improvement in the amount of emitted light.

They are a top view (A) of micro LED based on Embodiment 1 of this invention, and sectional drawing (B) in the position shown by the 1B-1B line | wire in the top view (A). It is sectional drawing which shows the flow of the manufacturing process of micro LED same as the above. It is sectional drawing which shows the flow of the manufacturing process of micro LED same as the above. It is the SEM image which observed the V-shaped groove | channel 26 with the scanning electron microscope (SEM). FIG. 6 is a cross-sectional view for explaining that light extraction efficiency from the light extraction surface is improved in the micro LED. It is sectional drawing for comparing and explaining the result of having calculated the light extraction efficiency by the ray tracing method in micro LED based on Embodiment 1, and a comparative example. The graph (a) which shows the relationship between a current density and a current diffusion distance in the micro LED of the comparative example without a V-shaped groove | channel, and sectional drawing (b) explaining a current diffusion distance. It is sectional drawing explaining the electric current constriction effect | action in micro LED similarly. FIG. 6 is a cross-sectional view showing a mounting state of a micro LED in a semiconductor light emitting device according to a second embodiment. It is a top view which shows the state of micro LED in the middle of the manufacturing process of a semiconductor light-emitting device.

Explanation of symbols

1 ... n-type gallium arsenide (GaAs) layer,
2 ... n-type aluminum, gallium, indium, phosphorus (AlGaInP) cladding layer,
3. MQW active layer in which a number of AlGaInP layers and GaInP layers are alternately laminated,
4 ... p-type aluminum, gallium, indium, phosphorus (AlGaInP) cladding layer,
5... P-type gallium indium phosphorus (GaInP) buffer layer,
6 ... p-type gallium arsenide (GaAs) contact layer, 7 ... p-electrode,
10 ... micro light emitting diode, 11 ... n-type gallium arsenide constituent material layer,
12 ... n-type aluminum, gallium, indium, phosphorus constituent material layer,
13 ... MQW active layer constituting material layer,
14 ... p-type aluminum, gallium, indium, phosphorus constituent material layer,
15 ... p-type gallium / indium / phosphorus constituent material layer,
16 ... p-type gallium arsenide constituent material layer, 17 ... p electrode material layer, 20 ... light extraction surface,
21, 22 ... element isolation surface, 23 ... element isolation groove, 24, 25 ... inclined reflection surface,
26 ... V-shaped groove, 27 ... Metal reflector, 28 ... V-shaped groove, 30 ... Micro LED,
31 ... Transparent electrode (ITO etc.), 32 ... n electrode, 33 ... low refractive index film,
34 ... Light reflecting metal, 35 ... Mold resin, 36 ... Lead electrode,
37 ... concave mirror with a large radius of curvature, 38 ... opening for forming extraction electrode,
40 ... Semiconductor light emitting device, 51, 53 ... Photoresist, 52 ... Opening,
54... P electrode formation region, L ₁ and L ₂ ... Emission point, d to g.

Claims (17)

In a semiconductor light emitting device comprising a III-V compound semiconductor layer,
A light extraction surface is formed on the (001) surface of the first conductivity type semiconductor layer;
An inclined reflective surface composed of a (111) surface and a (11-1) surface that does not reach the active layer is formed in the second conductive type semiconductor layer existing on the opposite side of the light extraction surface with the active layer interposed therebetween. A semiconductor light emitting device characterized by being made.   2. The inclined reflection surface composed of the (111) plane and the inclined reflection surface composed of the (11-1) plane form a V-shaped groove on the surface of the second conductive semiconductor layer. The semiconductor light emitting device described in 1.   The semiconductor light emitting element according to claim 2, wherein the groove extends in a linear pattern along the [1-10] direction.   The semiconductor light emitting element according to claim 3, wherein a plurality of the linear patterns are arranged side by side.   The semiconductor light emitting element according to claim 1, wherein an electrode is provided on a part of the second conductivity type semiconductor layer.   The semiconductor light emitting element according to claim 5, wherein at least a part of the groove is present in a region where the electrode is not provided.   The semiconductor light emitting element according to claim 1, wherein the second conductivity type semiconductor layer contains phosphorus as a constituent element.   Due to the inclined surface being the (111) plane and / or the inclined surface being the (11-1) plane, the second conductive semiconductor layer, the active layer, and at least a part of the first conductive semiconductor layer are formed. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is formed in a mesa shape.   The semiconductor light emitting element according to claim 7, wherein the first conductivity type semiconductor layer contains phosphorus as a constituent element.   A semiconductor light-emitting device, wherein a plurality of semiconductor light-emitting elements according to claim 1 are formed in an array on the same substrate comprising at least the lowermost layer of the first conductivity type semiconductor layer.   The semiconductor light emitting device according to claim 10, wherein the semiconductor light emitting elements are separated from each other by the inclined surface according to claim 8.   The semiconductor semiconductor light-emitting device according to claim 10, wherein light reflecting means is provided on the second conductivity type semiconductor layer.   13. The semiconductor semiconductor light emitting device according to claim 12, wherein the light reflecting means is made of a light reflecting metal deposited on the second conductive type semiconductor layer.   The semiconductor semiconductor light-emitting device according to claim 12, wherein the light reflecting means is a concave mirror disposed apart from the second conductive semiconductor layer.   It is a manufacturing method of the semiconductor light-emitting device or semiconductor light-emitting device of any one of Claims 1-12, Comprising: The inclined reflective surface which consists of said (111) surface and said (11-1) surface is made into low temperature. A method for manufacturing a semiconductor light-emitting element or a semiconductor light-emitting device, which is formed by wet etching using hydrochloric acid as an etchant.   The second conductive type semiconductor layer, the active layer, and at least a part of the second conductive type semiconductor layer are etched by wet etching using low temperature hydrochloric acid as an etchant to obtain a (111) plane and / or ( The manufacturing method of the semiconductor light-emitting element or the semiconductor light-emitting device according to claim 15, wherein the semiconductor light-emitting element or the semiconductor light-emitting device is formed into a mesa shape having an inclined surface formed of a surface as a side.   The method of manufacturing a semiconductor light emitting element or a semiconductor light emitting device according to claim 16, wherein the mesa shape is formed simultaneously with the formation of the inclined reflecting surface.