JPH05299781A - Semiconductor light-emitting device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which is capable of reducing a drive current without increasing a drive voltage and being manufactured with a minimum process. CONSTITUTION:Amphoteric impurities are doped on a semiconductor layer formed on both sides of a mesa stripe section of a p-type clad layer 4. As a crystal surface of a mixed crystal differs on the side surfaces 10 of a mesa stripe section and other surfaces 11 excluding the mesa stripe section in the p-type clad layer, semiconductor laminated layers 6 and 7 formed on the p-type clad layer 4 are turned into p-type semiconductor layers 6a and 7b on the both side surfaces and n-type semiconductor layers 6a and 7a on the surfaces except for the mesa stripe section by impurities. Therefore, the width of the bottom of the mesa stripe section is limited by the n type semiconductor layers 6a and 7a so that a current injection width may be narrowed. Although this reduction in the current injection width reduces the injection current as well, an opening area in the upper part of the mesa stripe section is widened substantially. It is, therefore, possible to prevent an increase in the drive voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor laser device or the like made of an AlGaInP mixed crystal lattice-matched with a GaAs substrate.

[0002]

2. Description of the Related Art In recent years, semiconductor light emitting devices have been widely used in the fields of optical communication, optical measurement control, etc., including light sources of information recording / reproducing devices. In an information recording / reproducing apparatus such as an optical disk and a video disk, it is preferable that the oscillation wavelength of the light source is short and the light spot is narrowed down because high-density recording can be performed. A semiconductor laser device using an AlGaInP mixed crystal lattice-matched with a GaAs substrate is particularly attracting attention as the above-mentioned light source because it can obtain visible light having a short wavelength of 600 nm band. The該混crystal lattice-matched to GaAs _{substrate, (Al y Ga 1-y} ) x In
_1-x P (y is 0 or more and 1 or less, and x is approximately 0.5).

Hitherto, various structures of semiconductor light emitting devices using AlGaInP mixed crystals have been proposed. FIG. 3 is a cross-sectional view of an essential part showing an example of such an AlGaInP-based semiconductor laser device. The semiconductor laser device shown in FIG. 3 is an SBR (Serectively Buried Ridge).
This is called a “waveguide” structure, and is formed by three crystal growth steps by a metal organic chemical vapor deposition (MOCVD) method as described below.

First, in the first growth step, n-type Ga is used.
N-type Al is formed on the As substrate 31 by the low pressure MOCVD method.
GaInP clad layer (hereinafter referred to as n-type clad layer)
32, GaInP active layer 33, p-type AlGaInP clad (hereinafter referred to as p-type clad layer) layer 34, p-type Ga
The InP intermediate layer 35 and the p-type GaAs layer 36 are sequentially grown.

After completion of the first growth step, p-type GaIn
The P intermediate layer 35, the p-type GaAs layer 36, and the p-type cladding 34 are etched by an appropriate etching method,
A mesa-shaped stripe portion is formed.

Then, in the second growth step, the n-type GaAs current blocking layer 37 is selectively grown on the portion other than the upper surface of the mesa stripe portion. Further, in the third growth step, p-type G is formed on the entire surface including the upper surface of the mesa stripe portion.
The aAs contact layer 38 is laminated and formed, and then electrodes (not shown) are formed on the substrate 31 side and the contact layer 38 side, respectively, to fabricate a double hetero type semiconductor laser device.

In this structure, the p-type cladding layer 3
4. Since the junction portion of the n-type GaAs current blocking layer 37 and the p-type GaAs contact layer 38 has a pnp structure, no current flows in this portion, and the current injection region to the active layer 33 is limited to only the mesa stripe portion. It n-type GaAs
The current blocking layer 37 also functions as a light absorption layer, thereby forming an optical waveguide.

In addition, GaInP forming the intermediate layer 35
Is the valence band energy of the p-type cladding layer 34 and the p-type G
The valence band energy has an intermediate value between the valence band energies of the aAs layer 36. Therefore, this p-type GaIn
The presence of the P intermediate layer 35 causes the p-type cladding layer 34 and the p-type GaA that act as a barrier against the injection of holes.
Since the discontinuity of the band structure on the valence band side with the s layer 36 is reduced, current easily flows in this portion.
Other than GaInP, the intermediate layer 35 has a valence band energy of AlGa forming the p-type cladding layer 34.
A mixed crystal having a value between the valence band energy of InP and the valence band energy of GaAs forming the p-type GaAs layer 36, that is, Al mixed crystal ratio lower than that of AlGaAs or AlGaInP forming the p-type cladding layer 34. AlGa
It may be formed of InP.

By the way, as one of the highly functional semiconductor laser devices, there is a reduction in the drive current of the device. This reduction of the drive current suppresses power consumption, which is very effective especially for making the system portable. One method for reducing the drive current in the semiconductor laser device shown in FIG. 3 is to reduce the width of the mesa stripe portion.

However, if an attempt is made to reduce the width of the mesa stripe portion, the opening area of the mesa stripe portion with respect to the p-type GaAs contact layer 38 becomes extremely narrow, so that the resistance in this portion becomes large and the driving voltage of the element is increased. It had the drawback of increasing. Further, when the width of the mesa stripe portion is narrowed, it becomes difficult to process the mesa etching and the selective growth, and it becomes difficult to manufacture a product with high accuracy, so that there is a drawback that the yield is reduced.

In order to solve these drawbacks, for example,
A semiconductor laser device having the structure disclosed in JP-A-4-10685 has been proposed. FIG. 4 shows the main structure of this semiconductor laser device. In this semiconductor laser device, as in the semiconductor laser shown in FIG.
On the substrate 41, an n-type AlGaInP clad layer (hereinafter,
42, a GaInP active layer 43,
A p-type AlGaInP layer (hereinafter referred to as a p-type clad layer) 44 having a mesa stripe portion, p-type GaInP
The intermediate layer 45 and the p-type GaAs layer 46 are laminated and formed. Except for the upper surface of the mesa stripe portion of the p-type cladding layer 44, p-type GaI was formed by the second growth step.
An nP layer 411, a p-type GaAs layer 412, and an n-type GaAs current blocking layer 47 are laminated and formed. After that, in the third growth step, a p-type GaAs contact layer 48 is formed on the entire surface including the upper portion of the mesa stripe portion, and electrodes (not shown) are formed on the substrate 41 side and the contact layer 48 side, respectively. Thus, a double hetero type semiconductor laser device is manufactured. In this semiconductor laser, the p-type GaInP layer 411 covering both side surfaces of the mesa stripe portion is formed.
Since a current can also flow in the p-type GaAs layer 412, the substantial opening area of the mesa stripe portion corresponding to the contact layer 48 is increased, and the increase in resistance can be suppressed.

[0012]

However, in the semiconductor laser device shown in FIG. 4, the p-type GaInP layer 411 and the p-type GaAs layer 412 are formed not only on the inclined side surface of the mesa stripe portion but also on the p-type cladding layer 44. Since it is also laminated on the flat surface 413 other than the mesa stripe portion of,
These p-type GaInP layer 411 and p-type GaAs layer 412
At, the current spreads not only to the inclined part covering the side surface of the mesa stripe part but also to the flat part,
There is a problem that the width of current injection into the active layer 43 becomes too wide. In order to solve this, after the p-type GaAs layer 412 is laminated and formed in the second crystal growth step,
p-type Ga on the flat surface 413 of the p-type cladding layer 44
The InP layer 411 and the p-type GaAs layer 412 are removed, and the third
The n-type GaAs current blocking layer 47 may be laminated in the growth step of the fourth time, and then the contact layer 48 may be formed in the fourth crystal step. However, in this case, since the crystal growth process is required four times as described above, there is a drawback that the manufacturing process becomes complicated.

The present invention is intended to solve the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor light emitting device in which the driving current is reduced without increasing the driving voltage and which can be manufactured in a small number of steps. To do.

[0014]

A semiconductor light emitting device of the present invention comprises an n-type GaAs substrate on which Al is lattice-matched.
What is claimed is: 1. A semiconductor light emitting device having a double hetero-type laminated structure formed by using a GaInP-based mixed crystal, comprising n-type (Al _t G
a _1-t ) _s In _1-s P (t is greater than 0 and 1 or less, s
Is greater than 0 and less than 1), (A
_{l u Ga 1-u) v} In 1-v P (u is 0 to less than 1, v
Is greater than 0 and less than 1), and a p-type (Al _t Ga _1-t ) _s In _1-s having a mesa stripe portion.
A cladding layer made of P is laminated in this order, and an AlGa doped with amphoteric impurities is formed on both sides of the mesa stripe portion of the p-type (Al _t Ga _1-t ) _s In _1-s P cladding layer.
As layer and, the p-type _{(Al t Ga 1-t)} s In 1-s P cladding layer smaller Al mole fraction than, and amphoteric impurity-doped _{(Al p Ga 1-p)} q In 1 _At least one layer of _-q P (p is 0 or more and less than 1 and q is more than 0 and less than 1) is laminated, and thereby the above object is achieved.

[0015]

In the present invention, the semiconductor layers formed on both sides of the mesa stripe portion of the p-type cladding layer are doped with amphoteric impurities. In the p-type cladding layer, the crystal plane of the mixed crystal is different between the side surface of the mesa stripe portion and the surface other than the mesa stripe portion, so that the semiconductor layer laminated on the p-type cladding layer is affected by the amphoteric impurity. A p-type semiconductor layer is formed on the side surface, and an n-type semiconductor layer is formed on the surface other than the mesa stripe portion. Therefore, the width of the bottom of the mesa stripe portion is limited by the n-type semiconductor layer and the current injection width is narrowed, so that the injection current is reduced, but the substantial opening area of the upper portion of the mesa stripe portion is widened and the drive voltage is increased. do not do.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a main part of a first embodiment of the present invention.

On the n-type GaAs substrate 1, n-type (Al _t Ga _1-t ) _s In _1-s P (t is larger than 0) stacked by the low pressure MOCVD method in the first crystal growth step. 1
Below, s is greater than 0 and less than 1) clad layer (hereinafter referred to as n-type clad layer) 2, undoped (Al
_u Ga _1-u ) _v In _1-v P (u is 0 or more and less than 1 and v is greater than 0 and less than 1) active layer 3, p-type (Al _t Ga)
_{A 1-t} ) _s In _1-s P clad layer (hereinafter referred to as a p-type clad layer) 4 and a p-type GaInP intermediate layer 5 are formed in this order. The upper surface 9 of the n-type GaAs substrate 1 is GaA.
It is the (100) plane of s crystal.

The intermediate layer 5 is laminated on the p-type cladding layer 4 and then etched together with the p-type cladding layer 4 by photolithography and wet etching to form a mesa stripe. At this time, the mixed crystal (111) plane appears on the side surface 10 of the mesa stripe portion, and the mixed crystal (100) plane is present on the flat surface 11 of the p-type cladding layer 4 other than the mesa stripe portion. Is appearing.

On the p-type clad layer 4, except for the upper surface of the mesa stripe portion, Al laminated by MBE (Molecular Beam Epitaxy) method in the second growth step.
A GaAs layer 6 and a GaAs layer 7 are formed, and these two layers are doped with amphoteric impurities. Therefore, the AlGaAs layer 6 and the GaAs layer 7 are p at the portion stacked on the inclined side surface 10 of the mesa stripe portion, that is, at the portion inside the broken line shown in FIG.
Type AlGaAs layer 6b and p type GaAs layer 7b,
In the portion of the mold cladding layer 4 stacked on the flat surface 11, that is, the portion outside the broken line, n
Type AlGaAs layer 6a and n type GaAs layer 7a.

Further, on the above structure, a p-type Ga layer is formed by MOCVD in the third crystal growth step.
The As contact layer 8 is formed.

As described above, the n-type cladding layer 2 is formed on the substrate 1.
After the contact layer 8 is formed, the electrodes (not shown) are respectively formed on the substrate side 1 and the contact layer 8 side by a usual method, and the semiconductor light emitting device is manufactured.

The above-mentioned amphoteric impurity is an impurity that can serve as an acceptor or a donor because the lattice positions occupied by the impurity atoms differ depending on the plane orientation of the crystal planes to be stacked.
Examples of such amphoteric impurities include Group IV elements, and Si is used in the first embodiment and the second embodiment described later. A group IV atom is usually doped as a donor in a group III-V semiconductor, but in the present invention, since the side surface 10 of the mesa stripe portion is a (m11) plane, the group V atom has a low sticking coefficient and a group IV atom. Atoms become incorporated into the lattice position of the group V atom in the group III-V semiconductor. Therefore, the side surface 10
In the portion laminated on the top, the amphoteric impurity acts as an acceptor, and the crystal grown in this portion becomes a p-type crystal. Further, since the flat surface 11 of the p-type cladding layer 4 is the (100) plane, amphoteric impurities are taken into the lattice position of the group III atom, and the amphoteric impurity acts as a donor, so that the flat surface 11 is formed on the flat surface 11. The grown portion becomes an n-type crystal. The use of the MBE method is particularly preferable because this impurity effectively acts as an amphoteric impurity.

The composition of each layer laminated on the substrate is set so as to be lattice-matched with the substrate. Therefore, the AlGaInP forming the n-type clad layer 2, the active layer 3 and the p-type clad layer 4 is formed as described above. The mixed crystal ratios s and v are preferably about 0.5. In the first embodiment, the contact layer 8 was formed from the substrate 1 using the following mixed crystal.

Substrate 1: GaAs (Si: 2 × 10 ¹⁸ cm
^-3 ), n-type cladding layer 2: n-type (Al _0.7 Ga _0.3 ) _0.5
In _0.5 P (Se: 1 × 10 ¹⁸ cm ⁻³ ), active layer 3: non-doped Ga _0.5 In _0.5 P, p-type clad layer 4: p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P (Zn: 6 × 10 5). ¹⁷ c
m ⁻³ ), intermediate layer 5: p-type Ga _0.5 In _0.5 P (Zn: 1 ×
10 ¹⁸ cm ^-3 ), AlGaAs layer 6: Al _0.5 Ga _0.5 A
s (Si: 1 × 10 ¹⁸ cm ^-3 ), GaAs layer 7: GaA
s (Si: 2 × 10 ¹⁸ cm ⁻³ ), contact layer 8: Ga
As (Zn: 2 × 10 ¹⁸ cm ⁻³ ).

In the first embodiment, the n-type AlGaA is used.
The s layer 6a and the n-type GaAs layer 7a function as a current blocking layer. The injection current flows from the contact layer 8 to the p-type clad layer 4 as well as from the contact layer 8 to the p-type cladding layer 4.
The GaAs layer 7 b, the p-type AlGaAs layer 6 b, and the p-type clad layer 4 flow through the path and are injected into the active layer 3. Therefore, the width of injection of the current into the active layer 3 (width of the bottom of the mesa stripe portion) is narrow, so that the drive current can be reduced, and the opening area of the mesa stripe portion with respect to the contact layer 8 is increased, so that the drive voltage is increased. Can be suppressed.

The valence band energy of the AlGaAs layer 6 is equal to the valence band energy of the p-type cladding layer 4 and p.
Since it is an intermediate value with the valence band energy of the type GaAs contact layer 8, the discontinuity of the band structure between the p-type cladding layer 4 and the p-type GaAs contact layer 8 is relaxed. As a result, current easily flows in this portion.

FIG. 2 is a vertical sectional view showing a second embodiment of the present invention. In the second example, crystal growth was performed only by the MBE method.

On the n-type GaAs substrate 21, the n-type clad layer 22 and the non-doped active layer 2 are formed as in the first embodiment.
3, a p-type clad layer 24 having a mesa stripe portion, and a p-type intermediate layer 25 are laminated, and a p-type GaAs layer 29 is laminated on the intermediate layer 25. A mixed crystal (111) plane appears on the side surface 212 of the mesa stripe portion, and a (100) plane of the mixed crystal appears on a flat surface 213 of the p-type cladding layer 24 other than the mesa stripe portion. There is.

In the region except the upper surface of the mesa stripe portion, the Al mixed crystal ratio is smaller than that of the p-type cladding layer 24 (A
l _p Ga _1-p ) _q In _1-q P (p is 0 or more and less than 1, and q
Layer 210, AlGaAs layer 26 and GaAs layer 27 are laminated, and these three layers are doped with amphoteric impurities. Therefore, as in the first embodiment, in the portion inside the broken line shown in FIG. 2, the three layers are p-type (Al _p Ga).
_1-p ) _q In _1-q P layer 210b, p-type AlGaAs layer 26
b and p-type GaAs layer 27b, and n-type (Al _p Ga _{1 -p} ) _q is formed in the portions outside the broken line.
It becomes the In _1-q P layer 210a, the n-type AlGaAs layer 6a, and the n-type GaAs layer 7a.

Further, on the above structure, a p-type GaAs contact layer 28 is formed by MOCVD in the third crystal growth step, and thereafter, electrodes (FIG. (Not shown) is formed, and a semiconductor light emitting device is manufactured.

In the second embodiment, the contact layer 28 was formed from the substrate 21 using the following mixed crystal. In addition, (Al _p G
In the a _1-p ) _q In _1-q P layer 210 as well, the mixed crystal ratio q is preferably about 0.5 in order to make the lattice match with the substrate 21.

Substrate 21: GaAs (Si: 2 × 10 ¹⁸ c
m ⁻³ ), n-type cladding layer 22: n-type (Al _0.7 Ga _0.3 ).
_0.5 In _0.5 P (Si: 1 × 10 ¹⁸ cm ^-3 ), active layer 2
3: Non-doped Ga _0.5 In _0.5 P, p-type cladding layer 2
4: p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P (Be: 1 ×
10 ¹⁸ cm ^-3 ), the intermediate layer 25: p-type Ga _0.5 In _0.5 P
(Be: 1 × 10 ¹⁸ cm ⁻³ ), p-type GaAs layer 29: G
aAs (Be: 1 × 10 ¹⁸ cm ⁻³ ), (Al _p Ga _{1 -p} ).
_q In _1-q P layer 210: Ga _0.6 InP _0.4 (Si: 1 × 1
0 ¹⁸ cm ^-3 ), AlGaAs layer 26: Al _0.5 Ga _0.5 A
s (Si: 1 × 10 ¹⁸ cm ^-3 ), GaAs layer 27: Ga
As (Si: 2 × 10 ¹⁸ cm ⁻³ ), contact layer 28:
GaAs (Be: 2 × 10 ¹⁸ cm ⁻³ ).

In the semiconductor light emitting device of the second embodiment, the n-type (Al _p Ga _1-p ) _q In _1-q P layer 210a, the n-type A
The lGaAs layer 26a and the n-type GaAs layer 27a function as a current blocking layer. The injected current is from the contact layer 28 to the p-type GaAs layer 29, the intermediate layer 25, and the p-type cladding layer 24.
From the contact layer 28 to p-type GaAs
Layer 27b, p-type AlGaAs layer 26b, p-type (Al _p G
a _1-p ) _q In _1-q P layer 210 b and the p-type clad layer 24, and is injected into the active layer 33. Also in the second embodiment, the injection width of the current to the active layer 23 is narrow, so that the drive current can be reduced, and the opening area of the mesa stripe portion with respect to the contact layer 28 is increased, so that the increase of the drive voltage is suppressed. ..

In the second embodiment, p-type AlGaAs is used.
There is a p-type (Al _p Ga _1-p ) _q In _1-q P layer 210b having a valence band energy intermediate between the valence band energy of the layer 26a and the valence band energy of the p-type cladding layer 24. The p-type cladding layer 24 and the p-type GaA
The discontinuity of the band structure between the s contact layers 28 is the first.
Since it is further relaxed as compared with the embodiment, the current can flow more easily in this portion.

Further, in the second embodiment, the contact layer 28 is omitted and the p-type GaAs layer 29 and p-type GaA are used.
It is also possible to directly form the electrode on the s layer 27b. In this case, since the third growth step can be omitted, the number of steps can be further reduced.

The present invention can also be applied to a semiconductor light emitting device having a structure such as a quantum well structure, a structure having an optical guide layer, and a structure having a buffer layer for improving crystallinity.

[0038]

According to the present invention, the drive current of the semiconductor light emitting element can be reduced without increasing the drive voltage thereof.

The semiconductor light emitting device of the present invention can be easily manufactured by a crystal growth step of three times or less without providing a special device.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a second embodiment of the present invention.

FIG. 3 is a vertical sectional view showing a main part of a conventional semiconductor laser device.

FIG. 4 is a vertical cross-sectional view showing a main part of another conventional semiconductor laser device.

[Explanation of symbols]

1 n-type GaAs substrate 2 n-type (Al _t Ga _1-t ) _s In _1-s P clad layer 3 (Al _u Ga _1-u ) _v In _1-v P active layer 4 p-type (Al _t Ga _{1- t} ) _s In _1-s P clad layer 6 AlGaAs layer 10 side surface of mesa stripe 21 n-type GaAs substrate 22 n-type (Al _t Ga _1-t ) _s In _1-s P clad layer 23 (Al _u Ga _1-u ) _V In _1-v P active layer 24 p-type (Al _t Ga _1-t ) _s In _1-s P clad layer 26 AlGaAs layer 210 (Al _p Ga _1-p ) _q In _1-q P layer 212 mesa stripe Part side

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Suga 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor ▲ Takahashi Musei 22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka No.22 Sharp Co., Ltd.

Claims (1)

[Claims] 1. A semiconductor light emitting device having a double hetero-type laminated structure formed on an n-type GaAs substrate by using an AlGaInP-based mixed crystal lattice-matched to the substrate, which is an n-type (Al _t Ga _1-t ) _S In _1-s P (t is greater than 0 and less than or equal to 1 and s is greater than 0 and less than 1), (Al _u Ga _1-u ) _v In _1-v P ( u is 0 or more and less than 1 and v is more than 0 and less than 1),
And p-type (Al _t Ga _1-t ) having a mesa stripe portion
_A cladding layer made of _s In _1-s P was formed in this order, and amphoteric impurities were doped on both sides of the mesa stripe portion of the p-type (Al _t Ga _1-t ) _s In _1-s P cladding layer. AlGaAs layer and the p-type (Al _t Ga _1-t ) _s I
The Al mixed crystal ratio is smaller than that of the n _1-s P clad layer and is doped with amphoteric impurities (Al _p Ga _1-p ) _q In _1-q
A semiconductor light-emitting device in which at least one layer of P (p is 0 or more and less than 1 and q is more than 0 and less than 1) layers is laminated.